A heterogeneous integration method and structure of a thin-film lithium niobate and transparent substrate waveguide system

Abstract

This invention relates to the field of photonic computing technology, and more particularly to a heterogeneous integration method and structure of a thin-film lithium niobate and a transparent substrate waveguide system. The heterogeneous integration method includes the following steps: S101, depositing a masking layer on a first surface of the transparent substrate, the masking layer protecting the transparent substrate during subsequent etching and simultaneously improving the optical coupling between the transparent substrate and light; S102, depositing a first waveguide layer on a second surface of the masking layer; S103, depositing a capping layer around the first waveguide layer, the capping layer being flush with the upper surface of the first waveguide layer; S104, depositing a second waveguide layer on the first waveguide layer and the capping layer; wherein the second waveguide layer is a thin-film lithium niobate layer.

Description

Technical Field

[0001] This invention relates to the field of photonic computing technology, and in particular to a heterogeneous integration method and structure of a thin-film lithium niobate and a transparent substrate waveguide system. Background Technology

[0002] The increasing demand for AI chip computing power, driven by the need for high-density computing, machine learning, parallel computing, and HPC applications in fields such as AI, places higher demands on chips. For example, AMD's new generation EPYC processors support up to 384 threads and up to 192 cores, including 16 "Zen 5" CCDs (core composite chips). These CCD chips utilize TSMC's 3nm process, while the central I / O chip (IOD) employs a 4nm process, demonstrating the demand for higher process technologies in the AI ​​era. As AI computing power demands continue to rise and hardware circuits become increasingly complex, traditional PCB organic substrates and TSV technology may become bottlenecks restricting the production of high-performance computing chips like AI chips in the future.

[0003] Glass substrates possess high surface flatness and low roughness, which is beneficial for high-density RDL wiring. They exhibit excellent chemical stability, effectively resisting environmental corrosion from moisture, acids, and alkalis. Glass substrates effectively combat warping issues during the packaging process. Simultaneously, they possess superior electrical properties; high resistivity and low dielectric constant reduce transmission losses, ensuring interconnect density and signal integrity. Furthermore, the size variation of glass substrate packaging brings significant cost benefits. The mismatch between rectangular chips and circular silicon interposers leads to waste at wafer edges and further degrades efficiency as chip size increases. Using large-format rectangular glass as a carrier or ultimately as an interposer allows for accommodating more chips within a single carrier or interposer, significantly improving the efficiency of advanced packaging. Therefore, GCP (Glass Circuit Board), as a new substrate material for the iterative upgrade of organic substrates, has gained worldwide attention due to its advantages such as low CTE value, low dielectric loss, high Young's modulus, high surface flatness, and large-size (510mm*515mm) fabrication capabilities, making it more suitable for realizing large-size, low-power AI computing chips. Based on this, existing technologies have proposed using glass substrates as carriers to fabricate various optical devices, such as optical waveguides.

[0004] Furthermore, lithium niobate is a multifunctional material with electro-optic effects, nonlinear optics, piezoelectricity, and ferroelectricity, and has been widely used in optical communication and integrated optoelectronic devices. Compared to bulk lithium niobate, thin-film lithium niobate possesses both excellent electro-optic properties and on-chip integration capabilities, gradually becoming a potential solution for next-generation photonic integrated devices. The development of modulators, optical microcavities, mode converters, and other devices based on the thin-film lithium niobate platform offers possibilities for addressing current optical communication and signal processing needs. To realize optoelectronic devices based on thin-film lithium niobate, various integrated optical waveguide structures need to be designed. Achieving high-precision, low-loss optical waveguide structures through fabrication processes is of great significance for the fabrication of large-scale thin-film lithium niobate optoelectronic devices and for effectively improving device performance.

[0005] However, fabricating low-loss thin-film lithium niobate waveguides remains an international challenge. Fabricating waveguides on thin-film lithium niobate wafers using photolithography and etching processes has been a research hotspot in recent years. Traditional methods for fabricating thin-film lithium niobate waveguides involve etching the thin film using hard masks such as metal or silicon dioxide. For example, patents CN114755761A and CN110764185A use metal hard masks for etching. Because this method uses fluorine-based gases, byproducts such as lithium fluoride inevitably adhere to the waveguide surface during etching, increasing the roughness of the waveguide sidewalls and thus increasing transmission loss. Furthermore, hard masks reduce the dimensional accuracy of the waveguide fabrication, hindering fine processing.

[0006] Nanoimprint lithography (NIL) is a method that directly uses mechanical contact extrusion to redistribute the imprinted material between a template and a substrate. It has advantages such as simple process, low cost, high yield, and large-scale production capability, making it the most promising patterning technology. Its accuracy is not limited by the physical limitations of optical diffraction limit, and it also eliminates the cost of optical lithography masks and optical imaging equipment. It has wide applications in display, semiconductor and other fields.

[0007] For example, patent application CN119535884A discloses a nanoimprint master and an optical waveguide, as well as a method for manufacturing the same, which can solve the defects of poor edge quality and uneven residual adhesive in the grating structure region during nanoimprinting. The steps for preparing the optical waveguide include: first preparing a master plate; then using the master plate to imprint a sub-plate substrate to form a nanoimprint sub-plate after curing; and using the nanoimprint sub-plate to imprint a waveguide substrate to form an optical waveguide after curing.

[0008] For example, patent application CN118363259A discloses a method for preparing a nanoimprint template and a method for preparing an optical waveguide. The nanoimprint template preparation method includes the following steps: providing a substrate with a silicon oxide layer formed on its surface; patterning the silicon oxide layer to form a patterned structure with micro- and nano-scale dimensions; and heat-treating the substrate with the patterned structure to prepare the nanoimprint template. Simultaneously, a method for preparing an optical waveguide is also provided, specifically including the steps of: using the nanoimprint template for nanoimprinting and etching to transfer the micro- and nano-scale patterned structure onto a composite waveguide substrate composed of silicon and silicon oxide, thereby obtaining an optical waveguide with the micro- and nano-scale patterned structure.

[0009] However, the above-mentioned scheme involves depositing waveguides on traditional SOI substrates, which is not suitable for fabricating optical waveguides with large-area patterned structures on large-area transparent substrates, such as glass substrates, especially for fabricating thin-film lithium niobate optical waveguides with large-area patterned structures. Summary of the Invention

[0010] The purpose of this invention is to provide a heterogeneous integration method and structure for a thin-film lithium niobate and a transparent substrate waveguide system, which partially solves or alleviates the above-mentioned deficiencies in the prior art. When fabricating optical waveguides and / or thin-film lithium niobate waveguides on a large-area transparent substrate, it can improve the uniformity of the waveguide obtained by etching to a certain extent (i.e., improve device performance). At the same time, it can protect the structure under the transparent substrate and / or the thin-film lithium niobate layer, thereby preventing damage to the transparent substrate and other components during the etching process, and thus improving the yield of the optical waveguide.

[0011] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution:

[0012] A first aspect of the present invention provides a method for heterogeneous integration of a thin-film lithium niobate and a transparent substrate waveguide system, comprising the steps of: S101, depositing a first masking layer on a first surface of a transparent substrate, the first masking layer being used to protect the transparent substrate during a subsequent etching process; S102, depositing a first waveguide layer on a second surface of the first masking layer; S103, depositing a first capping layer around the first waveguide layer, the upper surface of the first capping layer being flush with the upper surface of the first waveguide layer; S104, depositing a second masking layer on the upper surface of the first waveguide layer and the upper surface of the first capping layer; S105, depositing a second waveguide layer on the second masking layer; wherein the second waveguide layer is a thin-film lithium niobate layer.

[0013] In some embodiments, the light-transmitting substrate is a glass substrate.

[0014] In some embodiments, in step S102, a patterned first waveguide layer is fabricated on the first masking layer using nanoimprint lithography. In some embodiments, in step S105, a patterned second waveguide layer is fabricated on the second masking layer using nanoimprint lithography.

[0015] In some embodiments, step S101 specifically includes: S1011, depositing a silicon dioxide layer with a thickness of H1 and a first morphology on the first surface using a first deposition process as a first protective layer; the first deposition process includes HDP-CVD, SACVD, or FCVD; S1012, depositing a silicon dioxide layer with a thickness of H2 and a second morphology on the upper surface of the first protective layer using a second deposition process as a second protective layer; the second deposition process includes PECVD; wherein the sum of the thickness H2 of the second protective layer and the thickness H1 of the first protective layer is greater than or equal to 1 μm; and the first protective layer with the first morphology and the second protective layer with the second morphology complement each other to form a flat first protective layer.

[0016] In some embodiments, step S104 specifically includes the following steps: S1041, depositing a third protective layer with a first morphology on the upper surface of the first waveguide layer and the upper surface of the first cover layer using a first deposition process; S1042, depositing a fourth protective layer with a second morphology on the third protective layer using a second deposition process; wherein the sum of the thickness H3 of the fourth protective layer and the thickness H4 of the third protective layer is greater than or equal to 5 μm; and the third protective layer with the first morphology and the fourth protective layer with the second morphology complement each other to form a flat second shielding layer.

[0017] In some embodiments, before fabricating the patterned first waveguide layer and / or the patterned second waveguide layer using nanoimprint lithography, the method further includes the following steps: S401, pre-obtaining the width of the graphic structure corresponding to the waveguide structure in the first waveguide layer and / or the width of the graphic structure corresponding to the waveguide structure in the second waveguide layer on the imprint soft template; S402, for the first waveguide layer, dividing the first waveguide layer into regions with a specified graphic structure as the center point and a first preset side length R1 to obtain multiple regions, and calculating the graphic duty cycle of each region, and executing step S403; and / or, for the second waveguide layer, dividing the second waveguide layer into regions with a specified graphic structure as the center and a second preset side length R2 to obtain multiple regions, and calculating the image duty cycle of each region, and executing step S403; S403, for the first waveguide layer, determining whether the graphic duty cycle of each region is greater than or equal to a first preset duty cycle threshold; if the graphic duty cycle is greater than or equal to the first preset duty cycle threshold, marking the corresponding region as a dense region; if the graphic duty cycle is less than the first preset duty cycle threshold, determining whether the graphic duty cycle of each region is greater than or equal to a first preset duty cycle threshold ... A duty cycle threshold is set, and the corresponding region is marked as a sparse region; and / or, for the second waveguide layer, it is determined whether the pattern duty cycle of each region is greater than or equal to a second preset duty cycle threshold. If the pattern duty cycle is greater than or equal to the second preset duty cycle threshold, the corresponding region is marked as a dense region; if the pattern duty cycle is less than the second preset duty cycle threshold, the corresponding region is marked as a sparse region. Accordingly, during etching in step S102, for sparse regions, over-etching is performed based on a first preset etching parameter; while for dense regions, over-etching is performed based on a second preset parameter. Etching parameters are used for over-etching; wherein, the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power; and / or, during etching in step S105, for sparse regions, over-etching is performed based on a seventh preset etching parameter; while for dense regions, over-etching is performed based on an eighth preset etching parameter; wherein, the seventh preset etching parameter includes a seventh ICP power, the eighth preset etching parameter includes an eighth ICP power, and the eighth ICP power is greater than the seventh ICP power.

[0018] In some embodiments, before fabricating the patterned second waveguide layer using nanoimprint lithography, the method further includes the following steps: S601, obtaining the width and height of each pattern structure corresponding to the waveguide structure in the second waveguide layer on the imprint soft template; S602, dividing the second waveguide layer into regions with any specified pattern structure as the center and a second preset side length R2 to obtain multiple regions, and calculating the average height and average width of the pattern structure in each region; S603, determining whether the average height of each region is greater than or equal to a tenth preset height threshold and whether the average width is greater than or equal to a first preset width threshold; if the average height is less than or equal to the tenth preset height threshold and the average width is less than the first preset width threshold, marking the region as a Level I shallow etching region; if the average height is less than or equal to the tenth preset height threshold and the average width is greater than or equal to the first preset width threshold, marking the region as a Level II region. Shallow etched areas; if the average height is greater than the tenth preset height threshold and the average width is less than the first preset width threshold, the area is marked as a Level I deep etched area; if the average height is greater than the tenth preset height threshold and the average width is greater than or equal to the first preset threshold, the area is marked as a Level II deep etched area; correspondingly, step S105 specifically includes: for the Level I shallow etched areas, over-etching is performed based on the ninth preset etch parameters; for the Level II shallow etched areas, over-etching is performed based on the tenth preset etch parameters; for the Level I deep etched areas, over-etching is performed based on the eleventh preset etch parameters; for the Level II deep etched areas, over-etching is performed based on the twelfth preset etch parameters; wherein, the ninth preset etch parameters include the ninth ICP power, the tenth preset etch parameters include the tenth ICP power, the eleventh preset etch parameters include the eleventh ICP power; and the twelfth preset etch parameters include the twelfth ICP power.

[0019] A second aspect of the present invention provides a heterogeneous integrated structure of a thin-film lithium niobate and a transparent substrate waveguide system, which is prepared using any of the heterogeneous integration methods for a thin-film lithium niobate and transparent substrate waveguide system described above. The structure includes: a transparent substrate; a first masking layer on the transparent substrate; a patterned first waveguide layer on the first masking layer; a first capping layer surrounding the first waveguide layer; a second masking layer on the upper surface of the first capping layer and the upper surface of the first waveguide layer; and a second waveguide layer on the second masking layer. The upper surface of the first capping layer is flush with the upper surface of the first waveguide layer. Both the first masking layer and the second masking layer are deposited using pure silicon dioxide material, and both have a thickness greater than or equal to 1 μm.

[0020] In some embodiments, the first shielding layer includes: a first protective layer with a thickness of H1 located on a first surface of the light-transmitting substrate; and a second protective layer with a thickness of H2 located on the upper surface of the first protective layer; H1+H2≥1µm; and / or, the second shielding layer includes: a third protective layer with a thickness of H3 located on the first cover layer and the first waveguide layer; and a fourth protective layer with a thickness of H4 located on the upper surface of the third protective layer; H3+H4≥5µm.

[0021] In some embodiments, the first protective layer or the third protective layer is a silicon dioxide layer with a first morphology deposited using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD; the second protective layer or the fourth protective layer is a silicon dioxide layer with a second morphology deposited using a second deposition process; the second deposition process includes PECVD; wherein the first protective layer with the first morphology and the second protective layer with the second morphology complement each other to form a flat first protective layer, or the third protective layer with the first morphology and the fourth protective layer with the second morphology complement each other to form a flat second protective layer.

[0022] Beneficial Effects: Traditional photolithography cannot fabricate large-scale waveguide structures on large-area substrates, while nanoimprint lithography enables large-scale patterned replication. Furthermore, the pre-defined patterns guide the etching process, significantly reducing the high defect rate caused by "blind etching" in traditional photolithography. However, when fabricating large-area patterned waveguide structures on transparent substrates, especially when using micron- or even meter-sized transparent substrates as the base to integrate numerous patterned waveguide structures for large-scale optical computer matrices, two issues arise: firstly, the large-area patterned structures on the nanoimprint stencil may exhibit inhomogeneity and varying density; secondly, the large area makes it impossible to guarantee a uniform etching ratio across the entire transparent substrate. Therefore, to ensure complete isolation between waveguide structures (or patterned structures) and prevent light leakage to adjacent waveguide structures, this application involves over-etching the waveguide layer. Simultaneously, placing a masking layer between the transparent substrate and the waveguide layer significantly relaxes the requirements for the etching process. It eliminates the need for precise calculations of the "just enough" etching time to prevent over-etching; only the waveguide layer needs to be etched through. This results in a very wide process window. Furthermore, it avoids the formation of non-volatile etching products during over-etching, which can affect the performance of the silicon waveguide. For example, it can significantly increase the scattering loss of light propagating in the waveguide, thereby reducing the optical coupling between the light and the transparent substrate and lowering the waveguide yield. Since this masking layer is deposited using pure silicon dioxide (e.g., 99.9999% purity), it not only protects the transparent substrate but also improves the optical coupling between the transparent substrate and the waveguide (e.g., by wrapping the waveguide layer together with the capping layer), thus improving the waveguide yield. Furthermore, using two different deposition processes to obtain a double-layered masking layer not only protects the transparent substrate but also ensures the flatness of the deposited waveguide plane due to the complementary physical morphologies between the two protective layers. This eliminates the need for additional planarization layers or other special treatments, reducing process complexity and improving device performance to some extent. Additionally, because of the significant differences between the transparent substrate and the waveguide system, the masking layer also acts as an "adhesive" to increase the adhesion between the transparent substrate and the waveguide layer, preventing easy detachment.

[0023] Furthermore, this application incorporates a buffer layer between the mask layer and the waveguide layer. This ensures that even if some areas of the waveguide layer remain unetched (e.g., 10nm) due to poor process parameter control, the subsequent etching steps will almost instantly remove these residues due to the extremely high etching rate of the buffer layer, quickly exposing the underlying pure silicon dioxide mask layer. This significantly reduces the uniformity requirements for the "etching through the waveguide layer" step, making the process easier to control and resulting in a higher yield. Moreover, this buffer layer, together with the pure silicon dioxide protective layer, can be directly used as the lower cladding layer for "in-situ encapsulation" of the waveguide layer. The minimum thickness requirement (e.g., 1µm) for the silicon dioxide mask layer as the final protective layer is sufficient, eliminating the need to reserve additional thickness for over-etching.

[0024] In summary, this application maximizes the process window and accuracy by precisely controlling the etching selectivity between different layers, thereby reducing the difficulty of etching depth control and ensuring the uniformity and consistency of waveguides etched on large-area transparent substrates as much as possible.

[0025] Furthermore, because the etching rates differ across different regions of the pattern—for example, denser regions have slower etching rates while sparser regions have faster etching rates—the waveguide in the sparse region may be completely etched through or even over-etched within the same etching time, while the waveguide in the dense region may not yet be etched through. This directly leads to inconsistent performance across different functional areas of the chip. Therefore, to avoid this problem, this application increases the ion concentration for etching in dense regions, thereby accelerating the etching rate in these regions and avoiding excessively long over-etching times.

[0026] Compared to other waveguide layers, thin-film lithium niobate waveguide layers are more fragile. Therefore, very dense waveguide structures are not typically placed on thin-film lithium niobate waveguide layers. In addition, since the thin-film lithium niobate waveguide layer is directly placed on the first waveguide layer, when patterning the thin-film lithium niobate waveguide layer using nanoimprint lithography, it is necessary to consider not only the brittleness of the thin-film lithium niobate waveguide layer itself but also its impact on the underlying waveguide layer. Therefore, in this application, a second shielding layer is placed on the first waveguide layer, and then the second waveguide layer is placed, so that the first waveguide layer is protected by the second shielding layer during the over-etching process of the second waveguide layer. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0028] Figure 1A This is a flowchart of the heterogeneous integration method of thin-film lithium niobate and transparent substrate waveguide system in Embodiment 1 of the present invention; Figure 1B This is a flowchart illustrating the fabrication process of the double-layer shielding layer in the heterogeneous integration method of the thin-film lithium niobate and transparent substrate waveguide system in Embodiment 2 of the present invention. Figure 2 This is a flowchart of the process for preparing the embossing soft template in this invention; Figure 3 A schematic diagram illustrating the varying density of waveguide structures on the first waveguide layer; Figure 4 To reflect the corresponding Figure 3 A schematic diagram of the graphic structure of a mid-waveguide; Figure 5A This is a flowchart of the heterogeneous integration method of thin-film lithium niobate and transparent substrate waveguide system in Embodiment 1 of the present invention; Figure 5B This is a flowchart of the heterogeneous integration method of thin-film lithium niobate and transparent substrate waveguide system in Embodiment 2 of the present invention; Figure 6 This is a flowchart illustrating the patterning of the first waveguide layer using nanoimprint lithography in Embodiment 1 or 2 of the present invention. Figure 7 This is a flowchart of the heterogeneous integration method of thin-film lithium niobate and transparent substrate waveguide system in Embodiment 3 of the present invention; Figure 8 This is a flowchart illustrating the process of partitioning deep etching regions and shallow etching regions based on a patterned structure in the heterogeneous integration method of thin-film lithium niobate and transparent substrate waveguide system in Embodiment 4 of the present invention.

[0029] Reference numerals: Transparent substrate 100, first masking layer 200-1, second masking layer 200-2, second surface 201, first protective layer 202, second protective layer 203, third protective layer 204, fourth protective layer 205, first waveguide layer 300, imprinting adhesive layer (i.e., mask layer) 400, imprinting flexible template 500, first adhesive layer 5001, flexible film layer 5002, base layer 600, electron beam adhesive layer 700, first cover layer 800-1, second waveguide layer 300B, second cover layer 800-2; pattern structure 120, waveguide structure 110. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" can be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In this document, unless otherwise expressly specified and limited, terms such as "installed," "equipped with," and "connected" should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "and / or" includes any and all combinations of one or more of the listed related items. "Multiple" in this document means two or more, i.e., it includes two, three, four, five, etc. In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, a range description should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within that range. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0032] Optical AI chip: A photonic computing chip, also known as a photonic chip or optical computing chip, is a chip specifically designed for processing optical data and performing artificial intelligence (AI) inference. Based on optical principles, it takes optical signals as input and performs computational operations through a series of optical elements and devices. These optical elements can be components such as lasers, optical fibers, and optical modulators, used to process and transmit optical signals. For example, a photonic computing chip converts the optical signal into a weak photocurrent signal using a light-emitting diode (LED). This photocurrent signal is then converted into a voltage signal U by a transimpedance amplifier (TIA), and finally converted into a digital signal by an analog-to-digital converter (ADC). The digital signal is then output to an FPGA for processing. Simultaneously, the FPGA outputs the processed digital signal to a digital-to-analog converter (DAC) to convert the FPGA's digital signal back into an analog signal and input it back to the photonic computing chip.

[0033] Computational unit: A single computational unit used to perform a calculation. For example, using Mach... A single computational unit for photonic computing can be implemented using a Zeidel interferometer (MZI) or a microring structure (MMR). Other examples include photonic computing units utilizing carrier light absorption effects and photonic computing units based on the absorption effects of phase change materials. Specifically, computational units can be categorized into photonic computing units and hybrid computing units.

[0034] Computational Array: An N*N computational array is constructed based on the above computational units. Each intersection of the input row waveguide and the output column waveguide in this array contains a computational unit. If the computational units are photonic computational units, the computational array can also be called a photonic computational array; if the computational units are optoelectronic hybrid computational units, the computational array can also be called an optoelectronic hybrid computational array.

[0035] Transparent substrate: In this document, a transparent substrate refers to a base substrate with a flat, smooth surface and specific geometric dimensions (such as a disc, square, or panel), and exhibits extremely high transmittance, for example, >99.999%, within the target wavelength range (such as the visible light region 380nm-2µm). It is commonly used as a "foundation" or "canvas" for various functional devices (such as circuits, sensors, and waveguides), providing a support platform for subsequent micro / nano fabrication and functional layer deposition. Examples include interposers or redistribution substrates for system-in-package (SIIP), and the fabrication of electrical interconnect vias and optical waveguide structures (such as gratings) within glass. Preferably, the transparent substrate can be a glass substrate, etc.

[0036] Masking layer: In this paper, the masking layer refers to a layer that protects the next material layer during the etching process, preventing it from being etched during the etching process. It does not need to be removed in subsequent processes. Its refractive index is similar to that of the light-transmitting substrate, thus ensuring the coupling between light and the substrate. Furthermore, it can co-encapsulate the waveguide layer with the capping layer on the waveguide layer. Preferably, the masking layer can be deposited using materials such as pure silicon dioxide. For example, the first masking layer 200-1 and the second masking layer 200-2 in subsequent embodiments.

[0037] Over-etching: In this article, over-etching refers to continuing etching for an additional period of time after the preset time for "just etching to the target depth" has emulsified. For example, ideally, the etching time required to just etch through a waveguide layer of a certain depth is T1 (e.g., 10s), but in actual engineering applications, it is necessary to continue etching for T2 (20s) to ensure that the corresponding area on a large-area waveguide layer is completely etched through the waveguide layer.

[0038] Fabricating a large number of optical waveguides on a large-area transparent substrate to create a large-scale computing matrix is ​​challenging due to the etching process. It's impossible to guarantee uniform etching ratios across all structures, and the uniformity of the structures after nanoimprint lithography cannot be guaranteed. This makes controlling the etching depth / time difficult, consequently compromising the uniformity and consistency of the etched waveguide structures. Therefore, this application employs nanoimprint lithography, over-etching, and a multi-layered structure. By controlling the etching selectivity ratio between different layers, the process window and precision are maximized, reducing the difficulty of controlling etching depth / time and ensuring uniformity among the waveguides etched on the large-area transparent substrate. For example, a masking layer, such as a double-layered masking layer, is placed between the transparent substrate and the waveguide layers. By controlling the etching ratio between the upper and lower layers, the process window is maximized, allowing for a longer etching time without damaging the transparent substrate. Furthermore, the masking layer can be directly integrated with the subsequently deposited capping layer to perform in-situ encapsulation of the etched waveguide structures. In addition, the number of layers in the structure affects the miniaturization and integration of the device. Therefore, in order to avoid introducing too many multilayer materials, the etching process parameters are adjusted based on the dense and sparse regions of the patterned waveguide structure in the imprinting process. This reduces the difference in etching time or etching depth caused by non-uniformity to a certain extent, and then works in synergy with the multilayer structure to ensure the uniformity of the waveguide structure.

[0039] Example 1: See Figure 1A and Figure 5A This is a flowchart of an embodiment of a heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system according to the present invention. Specifically, the method includes the following steps:

[0040] S101, a first protective layer 200-1 is deposited on the first surface 101 of the light-transmitting substrate 100. In this embodiment, the first protective layer 200-1 is used to protect the light-transmitting substrate 100 during subsequent etching processes to prevent etching of the light-transmitting substrate 100 and to ensure that the optical coupling between the light and the light-transmitting substrate 100 is not significantly reduced. In some embodiments, the first protective layer 200-1 may be deposited using a transparent material that does not absorb light, and the higher its etching selectivity ratio with the waveguide layer material, the better (i.e., the etching rate of the waveguide layer is much greater than the etching rate of the protective layer). Preferably, the first protective layer 200-1 is made of pure SiO2. More preferably, the refractive index n1 of the first protective layer 200-1 and the refractive index n2 of the light-transmitting substrate 100 satisfy the relationship: n2 - Δn0 ≤ n1 ≤ n2 = Δn0. Preferably, Δn0 = ±0.01. Furthermore, the thickness of the first masking layer 200-1 is greater than or equal to 1 μm. Specifically, the first masking layer 200-1 can be deposited on the light-transmitting substrate 100 using methods such as PECVD or HDP CVD.

[0041] S102, a first waveguide layer 300 is deposited on the second surface 201 of the first shielding layer 200-1. In some embodiments, the first waveguide layer 300 is deposited using waveguide materials commonly used in the art, such as SiN material.

[0042] S103, a first capping layer 800-1 is deposited around the first waveguide layer 300, with the upper surface of the first capping layer 800-1 flush with the upper surface of the first waveguide layer 300. In some embodiments, the first capping layer 800-1 is deposited on the first waveguide layer 300, such that the first capping layer 800-1 and the first shielding layer 200-1 encapsulate the first waveguide layer 300. In this embodiment, the first capping layer 800-1 and the first shielding layer 200-1 together form an almost symmetrical "sandwich" structure, encapsulating the high-refractive-index first waveguide layer 300 in the middle. Since the first waveguide layer 300 is directly deposited on the first shielding layer 200-1, no separate process is needed to encapsulate the waveguide layer, thereby achieving "in-situ encapsulation" and reducing the risk of waveguide contamination or exposure. In this embodiment, the first capping layer 800-1 and the first shielding layer 200-1 are made of the same material, for example, pure SiO2. Preferably, the first cover layer 800-1 is prepared using the same deposition process as the first shielding layer 200-1.

[0043] S104, deposit a second shielding layer 200-2 on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1.

[0044] S105, a second waveguide layer 300B is deposited on the second shielding layer 200-2. In this embodiment, the second waveguide layer 300B is formed by thin-film lithium niobate deposition, and correspondingly, the thickness of the second shielding layer 200-2 is greater than or equal to 5 μm. That is, compared to the first shielding layer 200-1 between the first waveguide layer 300 and the light-transmitting substrate 100, which is made of other materials, the thickness of the second shielding layer 200-2 is more than 5 times the thickness of the first shielding layer 200-1.

[0045] Of course, a second capping layer 800-2 can be deposited on the second waveguide layer 300B.

[0046] The over-etching process for waveguide layers made of thin-film lithium niobate (this is existing technology and will not be elaborated here) differs from the etching process for waveguide layers made of other materials. Because it is difficult or impossible to clean up solid waste from the etched product in a timely manner during the etching process, the risk of etching into the transparent substrate is greater. Therefore, to ensure the uniformity of the waveguide structure and reduce the risk of etching into underlying structures, such as the first waveguide layer 300, a second shielding layer 200-2 of a specific thickness is provided. This provides sufficient space for over-etching without significantly reducing the longitudinal transmission of light.

[0047] Preferably, the width of the second waveguide layer 300B is greater than the width of the first waveguide layer 300, thereby forming a T-shaped heterostructure waveguide to fabricate an active modulator. Accordingly, when fabricating the active modulator, external electrodes are also connected through shallow etched regions, thus introducing electrodes while controlling the spot size to the greatest extent.

[0048] Preferably, in other embodiments, the first waveguide layer 300 in step S102 and the second waveguide layer 300B in step S105 are both waveguide layers patterned using nanoimprint lithography. Specifically, see... Figure 6 First, an imprinting adhesive layer 400 is deposited on the first waveguide layer 300 / second waveguide layer 300B. Then, a pre-prepared imprinting soft template 500 is used to imprint the imprinting adhesive layer 400, forming an imprinted pattern on the imprinting adhesive layer 400. Next, based on the imprinted pattern, the residual layer in the imprinted groove is etched. After removing the residual layer, the first waveguide layer 300 / second waveguide layer 300B is etched again based on the imprinted pattern, thereby obtaining a patterned first waveguide layer 300 / second waveguide layer 300B. Finally, the imprinting adhesive layer 400 is removed.

[0049] Specifically, after the pattern transfer is completed, all remaining imprinting adhesive is removed using a wet method (such as solvents or acids) or a dry method (such as O2 plasma ashing) to leave a clean, patterned waveguide structure.

[0050] In some embodiments, the etching process must have a high selectivity, i.e., it rapidly etches only the imprinting resist while barely etching the underlying first waveguide layer 300 / second waveguide layer 300B. For example, reactive ion etching (RIE) is used to etch the imprinting resist layer. Other processes can also be used to remove this residual layer. In specific implementations, based on the imprinted pattern, the first waveguide layer 300 is over-etched using an etching gas (such as CF4, CHF3 for SiN) with a preset etching selectivity (e.g., an empirical value) to obtain a patterned first waveguide layer 300.

[0051] In this embodiment, over-etching refers to the process where, after etching the waveguide layer (e.g., the first waveguide layer 300 or the second waveguide layer 300B) for a preset etching time (e.g., 20s), the waveguide layer (e.g., the first waveguide layer 300 at 15s) is etched through, resulting in slight etching of the underlying masking layer (e.g., the first masking layer 200-1 below the first waveguide layer 300, or the second masking layer 200-2 below the second waveguide layer 300B). Since the waveguide layer is over-etched, the resulting masking layer (e.g., the first masking layer 200-1 or the second masking layer 200-2) also has a corresponding pattern. Furthermore, because the preset etching selection is relatively large, the process will not completely etch the masking layer, meaning it will not etch the light-transmitting substrate 100 below the first waveguide layer 300, or the first waveguide layer 300 and the first capping layer 800-1 below the second waveguide layer 300B.

[0052] Preferably, over-etching the first waveguide layer 300 using an etching gas with a preset etching selectivity means that the etching rate of the etching gas on the first waveguide layer 300 is much greater than the etching rate of the etching gas on the first shielding layer 200-1. Therefore, after the first waveguide layer 300 is etched through, micro-etching will continue on the first shielding layer 200-1. However, since the etching rate of the first shielding layer 200-1 is low and it has a certain thickness (e.g., greater than or equal to 1 μm), the etching will stop on the first shielding layer 200-1 when the preset etching time (e.g., 20 s) is reached, thereby protecting the light-transmitting substrate 100 from damage.

[0053] As mentioned earlier, since the second waveguide layer 300B needs to be patterned, if the second waveguide layer 300B formed by the thin-film lithium niobate directly contacts the first waveguide layer 300, the first waveguide layer 300 may be damaged during the patterning process. Therefore, when the second waveguide layer 300B needs to be over-etched for patterning to fabricate different functional devices, a second shielding layer 200-2 needs to be set on the first waveguide layer 300 and the first capping layer 800-1 to prevent damage to the first waveguide layer 300 and the first capping layer 800-1 during the over-etching process of the second waveguide layer 300B. Specifically, the same principle is adopted, and the second shielding layer 200-2 deposited on the first waveguide layer 300 and the first capping layer 800-1 is also made of pure SiO2. Based on the imprinted pattern, the second waveguide layer 300B is over-etched using an etching gas (such as CF4 or CHF3 for SiN) with a preset etching selectivity ratio (e.g., an empirical value of 1:5) to obtain the patterned second waveguide layer 300B.

[0054] In this embodiment, over-etching the second waveguide layer 300B using an etching gas with a preset etching selectivity means that the etching rate of the etching gas on the second waveguide layer 300B is much greater than the etching rate of the etching gas on the underlying second shielding layer 200-2. Therefore, after the second waveguide layer 300B is etched through, micro-etching will continue on the second shielding layer 200-2. However, since the etching rate of the second shielding layer 200-2 is low and it has a certain thickness (e.g., greater than or equal to 5 μm), the etching will stop on the second shielding layer 200-2 when the preset etching time (e.g., 25 s) is reached, thereby protecting the first waveguide layer 300 and the first cover layer 800-1 from damage. Similarly, when the second waveguide layer 300B is etched according to the preset etching time (e.g., 25s), since the second waveguide layer 300B is etched through (e.g., at 20s), the second masking layer 200-2 will be slightly etched. Therefore, the final second masking layer 200-2 also has the corresponding pattern. Furthermore, since the etching selectivity is greater than the fourth preset threshold, the process will not completely etch the second masking layer 200-2, that is, it will not etch the first waveguide layer 300 and the first capping layer 800-1. Moreover, since the second masking layer 200-2 is made of pure silicon dioxide, it will not significantly affect the optical coupling between the second waveguide layer and the first waveguide layer.

[0055] In some embodiments, the preparation step of the imprinting soft template in the above steps specifically includes: S301, depositing an electron beam resist layer 700 on a substrate layer 600, and exposing a designated area in the electron beam resist layer 700. S302, developing the exposed electron beam resist layer 700 to obtain a patterned electron beam resist layer 700. In some embodiments, the electron beam resist layer 700 is a positive resist layer or a negative resist layer; correspondingly, if there is no positive resist layer, the electron beam resist layer in the exposed area is removed during the developing process in step S302, see [reference]. Figure 2 If there is no negative resist layer, in step S302, when developing the electron beam resist layer, the electron beam resist layer outside the exposure area is removed (not shown in the figure). S303, the substrate layer 600 is etched based on the patterned electron beam resist layer 700 to obtain the patterned substrate layer 600. S304, a first resist layer 5001 and a soft film layer 5002 are sequentially deposited on the patterned substrate layer 600. S305, the substrate layer 600 is removed to obtain the patterned imprinting soft template 500.

[0056] During nanoimprinting, uneven height of the pattern on the template or uneven thickness of the residual layer in the grooves of the imprinting adhesive may occur, increasing the difficulty of controlling the etching depth / etching time of the subsequent optical waveguide. Although a high-performance imprinting film can be designed in advance using high-precision algorithms to ensure the uniformity of the imprinting thickness, redesigning and manufacturing a new high-performance template for existing imprinting films would significantly increase costs, and the waiting process for a new template may result in production stoppages and losses. On the other hand, even with a template with high uniformity, different areas of the imprinting film will experience varying degrees of wear after long-term use, leading to different imprinting thicknesses and consequently, different residual layer thicknesses in the grooves. Therefore, to reduce the risk of unevenness in the etched optical waveguide caused by uneven pattern or residual layer thickness, this embodiment uses over-etching combined with a masking layer to ensure the uniformity of the optical waveguide while protecting the transparent substrate 100 and / or the first waveguide layer 300, thereby improving the yield of the waveguide device.

[0057] Example 2: This invention also provides another heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system, which includes the steps of Example 1 above, except that, see [link to example]. Figure 1B and Figure 5BIn the preparation method of this embodiment, the first shielding layer 200-1 between the light-transmitting substrate 100 and the first waveguide layer 300, and / or the second shielding layer 200-2 between the first waveguide layer 300 and the second waveguide layer 300B formed by the thin film lithium niobate, are not single-layer shielding layers, but rather double-layer shielding layers. For example, pure silicon dioxide double-layer structures with different properties (including etching rate and etching resistance, morphology) are deposited through two different deposition processes. For example, in the first masking layer 200-1 between the light-transmitting substrate 100 and the first waveguide layer 300, the lower layer near the light-transmitting substrate 100 has a dense structure, while the upper layer near the first waveguide layer 300 has a sparser structure (i.e., the lower layer is more resistant to etching than the upper layer). This allows the two layers to have different morphologies and complement each other to form a flat first masking layer, ensuring waveguide uniformity while maintaining the stability of the connection between the multilayer structures. Specifically, step S101 includes: S1011, using a first deposition process, such as HDP-CVD technology, depositing a silicon dioxide layer with a thickness of H1 and a first morphology on the first surface 101 of the light-transmitting substrate 100 as a first protective layer 202. S1012, using a second deposition process, such as PECVD technology, depositing a silicon dioxide layer with a thickness of H2 and a second morphology on the upper surface of the first protective layer 202 as a second protective layer 203.

[0058] In this embodiment, the first morphology refers to the first protective layer 202 comprising: a smooth and flat lower surface in contact with the light-transmitting substrate 100, and an upper surface for depositing the second protective layer 203 and disposed opposite to its lower surface. The second morphology refers to the second protective layer 203 comprising: a third surface in contact with the upper surface of the first protective layer 202, and a fourth surface for depositing the first waveguide layer 300 and disposed opposite to the third surface. Since the first protective layer 202 is deposited directly on the light-transmitting substrate 100, its upper surface is almost flat, while its lower surface has an uneven morphology due to limitations in the deposition process. Correspondingly, since the second protective layer 203 is deposited directly on the upper surface of the first protective layer 202, the morphology of the third surface is complementary to the upper surface, while the fourth surface is almost flat due to the maturity of the deposition process. This results in the first masking layer 200-1 of the double-layer structure having two flat upper and lower surfaces (i.e., the fourth surface and the lower surface of the first protective layer 202), and the stress integration effect of the double-layer structure can reduce the risk of warping.

[0059] In this embodiment, a dense, hard silicon dioxide layer with high image stability is prepared using HDP-VCD. Compared to the sparser silicon dioxide layer prepared using PECVD, its etching rate is slower. Therefore, even if the thinner second protective layer 203 is etched through during the over-etching process, the etching process will eventually stop on the highly etch-resistant first protective layer 202.

[0060] Generally, to ensure sufficient safety, a sufficiently thick silicon dioxide layer can be used as a first protective layer 200-1. However, a thicker layer would affect the subsequent vertical stacking, thus impacting the device size. Therefore, to ensure that the first waveguide layer 300 is etched through during over-etching without etching through the first protective layer 202 and damaging the light-transmitting substrate 100, the second protective layer 203 near the first waveguide layer 300 is made thinner. During over-etching, only the first protective layer 202 is etched, not the light-transmitting substrate 100. Compared to simply increasing the thickness of the silicon dioxide layer, for example, by providing a very thick silicon dioxide layer (e.g., 2µm), it is more beneficial for device miniaturization and integration. Preferably, H1 < H2. More preferably, H1 + H2 ≥ 1µm. Preferably, a 0.1-0.2 μm PE-CVD SiO2 layer is deposited as the second protective layer 203, and a 0.8-0.9 μm HDP-CVDSiO2 layer is deposited as the first protective layer 202. Of course, in other embodiments, other deposition techniques can be used to deposit a denser first protective layer 202, such as SACVD technology, FCVD technology, etc.

[0061] Of course, similarly, the same process described above can be used to prepare the second shielding layer 200-2 located between the first waveguide layer 300, the first capping layer 800-1, and the second waveguide layer 300B, thereby obtaining a pure SiO2 double-layer structure. That is, firstly, a third protective layer 204 (i.e., S1041) of a certain thickness H3 is deposited on the first waveguide layer 300 and the first capping layer 800-1 using a first deposition process, and then a fourth protective layer 205 (i.e., S1042) of a certain thickness H4 is deposited on the third protective layer 204 using a second deposition process. Preferably, the thickness H4 of the fourth protective layer 205 is less than the thickness H3 of the third protective layer 204, and H3+H4≥1um, more preferably, H3+H4≥5um; and the third protective layer 204 with the first morphology and the fourth protective layer 205 with the second morphology complement each other to form a flat second shielding layer 200-2.

[0062] Example 3: This invention also provides another heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system, which includes the steps of Example 1 or 2 above, except that, see [link to example]. Figure 7In this embodiment, before over-etching the first waveguide layer 300, the method further includes the step: S401, obtaining the width of the pattern structure 120 (i.e., the spacing between waveguide structures 110) based on the pattern structure 120 corresponding to the waveguide structure 110 on the imprinted soft template 500. In some embodiments, different patterns are set on the first waveguide layer 300 and the second waveguide layer 300B. Therefore, different imprinted soft templates can be provided for the two waveguide layers in advance. Then, the imprinted pattern on the imprinted soft template is captured by an image acquisition device, such as a high-definition camera, and image analysis is performed to obtain the spacing L1 or L2 between the waveguide structure 110 and the corresponding pattern structure 120. See [link to relevant documentation]. Figure 3 That is, the width L1 or L2 of the raised graphic structure 120 on the embossing soft template 500, such as Figure 4 Of course, in other embodiments, the width (or spacing) of the graphic structure 120 can also be obtained directly from the design drawings (such as the GDSII layout) of the imprinted soft template 500, thereby obtaining the spacing between the waveguide structures.

[0063] S402, using the specified graphic structure 120 as the center point, the second waveguide layer 300B is divided into regions by a first preset side length R1 (actually, the region is divided according to the side of the design drawing where the graphic structure 120 is set on the imprinted soft template), resulting in multiple regions; and the graphic duty cycle and the average width of the graphic structure in each region are calculated; if the graphic duty cycle is greater than or equal to the first preset duty cycle threshold (e.g., 55%), and the average width of the graphic structure in the corresponding region is less than the first preset width threshold, then the region is marked as a Level I dense region; if the graphic duty cycle is greater than the first preset duty cycle threshold, and the average width of the graphic structure in the corresponding region is greater than the first preset width threshold, then the region is marked as a Level II dense region; if the graphic duty cycle is less than the first preset duty cycle threshold (e.g., 55%), and the average width of the graphic structure is less than the first preset width threshold, then the corresponding region is marked as a Level I sparse region; if the graphic duty cycle is less than the first preset duty cycle threshold, and the average width of the graphic structure is greater than the first preset width value, then the corresponding region is marked as a Level II sparse region. First, the image is divided into sparse and dense regions based on its duty cycle. Then, the sparse and dense regions are further divided based on the width, resulting in sparse regions and dense regions of different levels.

[0064] Of course, in other embodiments, the division of dense and sparse regions can also be based solely on the graphic duty cycle. For example, if the graphic duty cycle is greater than or equal to a first preset duty cycle threshold, it is classified as a dense region; if it is less than the first preset duty cycle threshold, it is classified as a sparse region. Accordingly, step S103 specifically includes: for sparse regions, over-etching is performed based on a first preset etching parameter; while for dense regions, over-etching is performed based on a second preset etching parameter; wherein, the first preset etching parameter includes a first particle concentration or a first etching time, and the second preset etching parameter includes a second ion concentration or a second etching time, wherein the second ion concentration is greater than the first particle concentration, or the second etching time is greater than the second etching time. Of course, different preset etching parameters can be preset for different levels of sparse regions and different levels of dense regions. The higher the level of the same type of region, the smaller its corresponding preset etching parameter. For example, the preset etching parameter for a level I dense region is greater than the preset etching parameter for a level II dense region.

[0065] In a specific example, taking the etching of a silicon carbide waveguide layer as an example, the initial etching parameters preset according to actual needs include: ICP power: 1000W (to control plasma ion concentration); etching mixed gas: CHF3 / CF4 / O2; etching time: 20s. When the duty cycle of a certain region is 70%, which is greater than the first preset threshold of 55%, the ICP power of that dense region is increased to 1200W (i.e., the second preset etching parameter) to increase the ion concentration. When the duty cycle of a certain region is 35%, which is less than 55%, the ICP power of that sparse region is kept at 1000W.

[0066] In another specific example, if the duty cycle of a certain region on the first waveguide layer 300 is 70%, which is greater than the first preset threshold of 55%, and the average width of the pattern structure is less than or equal to the preset width threshold, the region is marked as a Class I dense region, and the ICP power in the initial preset etching parameters of 1000W is adjusted to 1200W (i.e., the second preset etching parameter). If the average width of the pattern structure is greater than or equal to the preset width threshold, the region is marked as a Class II dense region, and the ICP power in the initial preset etching parameters of 1000W is adjusted to 1100W (i.e., the fourth preset etching parameter). Similarly, when the image duty cycle of a certain region on the first waveguide layer 300 is less than 55% (35%), and the average width of the pattern structure 120 is less than a preset width threshold, the ICP power of this Class I sparse region is maintained at 1000W (i.e., the first preset etching parameter). If the average width of the pattern structure 120 is greater than or equal to the preset width threshold, the ICP power of the Class II sparse region is maintained at 900W (i.e., instead of maintaining the first preset etching parameter, the first preset etching parameter is reduced to obtain the third preset etching parameter). In other words, the difference in global waveguide etching time is minimized by adjusting the ion concentration during etching. This means different preset etching parameters are set for different levels of dense regions.

[0067] Preferably, when adjusting the ion concentration, a high-end etching machine supporting zone control can be used to set corresponding etching parameters, such as ICP power, for each region, and then the high-end etching machine can be used to over-etch all regions (i.e., the etching time for all regions is the same). When adjusting the etching time, traditional occlusion-based occlusion etching can be used, i.e., etching sparse and dense regions separately. Specifically, when etching sparse regions, dense regions are occluded, and vice versa. Similarly, the waveguide structure on the second waveguide layer 300B also has sparse and dense sections. Therefore, based on the same principle, before over-etching the second waveguide layer 300B, steps S401-S402 are also used to partition the structure, obtaining the duty cycle and average width of the pattern structure for each region. The difference is that the preset side lengths for dividing the regions are different. For example, taking the specified pattern structure 120 as the center point, the second preset side length R2 divides the second waveguide layer 300B into multiple regions; and calculates the pattern duty cycle and the average width of the pattern structure in each region; wherein the second preset side length R2 is greater than the first preset side length R1. Since the thin-film lithium niobate waveguide layer is brittle, the density of the waveguide structure on the thin-film lithium niobate is less than that of the first waveguide layer 300 made of other materials. Therefore, the scale of the preset side length can be appropriately enlarged.

[0068] Accordingly, if the duty cycle of the pattern is greater than or equal to the second preset duty cycle threshold (e.g., 60%), the corresponding region is marked as a dense region; if the duty cycle of the pattern is less than the second preset duty cycle threshold, the corresponding region is marked as a sparse region; the second preset duty cycle threshold is greater than the first preset duty cycle threshold. Accordingly, step S105 specifically includes: for sparse regions, over-etching is performed based on a seventh preset etching parameter; while for dense regions, over-etching is performed based on an eighth preset etching parameter; wherein, the seventh preset etching parameter includes a seventh ICP power, the eighth preset etching parameter includes an eighth ICP power, and the eighth ICP power is greater than the seventh ICP power.

[0069] Of course, further classification can be made based on the average width of each region. For example, if the graphic duty cycle is greater than or equal to a second preset duty cycle threshold, and the average width of the graphic structure within the corresponding region is less than a second preset width threshold, then the region is marked as a Level I dense region; if the graphic duty cycle is greater than the second preset duty cycle threshold, and the average width of the graphic structure within the corresponding region is greater than a second preset width threshold, then the region is marked as a Level II dense region; if the graphic duty cycle is less than the second preset duty cycle threshold, and the average width of the graphic structure is less than a second preset width threshold, then the corresponding region is marked as a Level I sparse region; if the graphic duty cycle is less than the second preset duty cycle threshold, and the average width of the graphic structure is greater than a second preset width value, then the corresponding region is marked as a Level II sparse region.

[0070] Accordingly, based on the same principle, for the same type of region, the higher its level, the smaller its corresponding preset etching parameter. Specifically, step S105 includes: for level I sparse regions, over-etching is performed based on the seventh preset etching parameter; for level II sparse regions, over-etching is performed after reducing the seventh preset etching parameter according to the preset reduction; for level I dense regions, over-etching is performed based on the eighth preset etching parameter; for level II dense regions, over-etching is performed after reducing the eighth preset etching parameter according to the preset reduction.

[0071] In other embodiments, since the distribution of waveguide structures on the first waveguide layer 300 is not only dense and sparse in the two-dimensional plane, but also has a height in the three-dimensional direction, which determines the etching depth, the method further includes the step of: S501, obtaining the height of each pattern structure in the dense region (preferably obtained from the GDSII layout; this height actually maps the etching depth of the grooves between the waveguide structures 110), and further dividing it into regions; specifically, for each dense region, taking any specified pattern structure as the center, the dense region is divided into regions by a third preset side length R3 (R3 < R1) to obtain at least two sub-regions (i.e., rectangular regions), and the pattern structure in each sub-region is calculated. The average height of the structure 120 is determined. If the average height is less than or equal to a first preset height threshold and greater than or equal to a second preset height threshold, the second etching parameters corresponding to the corresponding sub-region are adjusted, such as increasing the initial etching time or increasing the initial ICP power according to a first preset increment, thereby increasing the ion concentration. If the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, the second etching parameters corresponding to the corresponding sub-region are adjusted, such as increasing the initial etching time or increasing the initial ICP power according to a second preset increment, thereby increasing the ion concentration. The second preset increment is less than the first preset increment. If the average height is less than the third preset height threshold, the current second etching parameters are maintained. Furthermore, if the ion concentration is increased, the thickness of the second protective layer 203 is correspondingly increased.

[0072] In a specific example, following the example above, when the average height of any sub-region in any dense region is equal to or less than a first preset height threshold (preferably, the first preset height threshold is the largest of the average heights in all sub-regions), and greater than or equal to a second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1250W. If the average height is less than the second preset height threshold, and greater than or equal to a third preset height threshold, the ICP power in the corresponding sub-region's second etching parameters is adjusted from 1200W to 1230W. If the average height is less than the third preset height threshold, the current second etching parameters are maintained.

[0073] Of course, in other embodiments, the aforementioned preset increments differ for each level of dense region. That is, the level of the dense region is first identified, and then the corresponding preset increments are adjusted based on the average height. For example, when the average height of any sub-region in any Level I dense region is equal to or less than a first preset height threshold and greater than or equal to a second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1250W. When the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, the ICP power in the second etching parameters corresponding to the sub-region is adjusted from 1200W to 1230W. Similarly, when the average height of any sub-region in any Level II dense region is equal to or less than the first preset height threshold and greater than or equal to the second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1240W. When the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, the ICP power in the second etching parameters corresponding to the sub-region is adjusted from 1200W to 1220W.

[0074] Of course, to further reduce the difference, in some other embodiments, each sparse region can also be further divided into sub-regions based on the height of the graphic structure 120, and the division principle is the same as that of the dense region. For example, for each dense region, with any specified graphic structure 120 as the center, the dense region is divided into regions by a fourth preset side length R4 (R4 is greater than R2) to obtain at least two sub-regions (i.e., rectangular regions), and the average height of the graphic structure 120 in each sub-region is calculated; if the average height is less than or equal to a fourth preset height threshold (the fourth preset height threshold is greater than a first preset height threshold), and greater than or equal to a fifth preset height threshold (the fifth preset height threshold is less than a second preset height threshold), the first etching parameter corresponding to the corresponding sub-region is adjusted, such as increasing the ion concentration according to the corresponding preset increment; if the average height is less than a fifth preset height threshold, and greater than or equal to a sixth preset height threshold (the sixth preset height threshold is greater than a third preset height threshold), the first etching parameter corresponding to the corresponding sub-region is adjusted, such as increasing the ICP power according to the corresponding preset increment, thereby increasing the ion concentration; if the average height is less than a sixth preset height threshold, the current first etching parameter is maintained.

[0075] Compared to complex multilayer structures that are more suitable for the experimental stage (e.g., optical waveguides with double waveguide layers and double shielding layers), in this embodiment, the ion concentration in the etching parameters is set based on the sparse and dense regions of the waveguide structure 110 and the average height of the waveguide structure within the region. This reduces the difficulty of controlling the etching depth / etching time of the first waveguide layer 300 due to uneven imprinted structure, uneven residual layer thickness, and etching ratio differences (and even the large difference in etching time between different waveguide structures can lead to some waveguide structures being unsmooth or experiencing severe lateral etching, thus affecting the optical waveguide performance). It eliminates the need for covering deposition and etching processes, which not only reduces costs but also lowers the complexity of the entire optical waveguide fabrication process, and facilitates industrialization.

[0076] This embodiment analyzes the graphic information of the imprint template to predict the non-uniformity (micro-load effect and depth effect) during the etching process, and applies different process parameters to different areas during etching for dynamic compensation, so as to ensure global uniform etching over a large area as much as possible.

[0077] Of course, in other embodiments, the same principle can be used when patterning the second waveguide layer 300B using nanoimprint lithography. That is, based on the width of the pattern structure 120 corresponding to the waveguide structure 110 on the imprint soft template 500 pre-prepared for the second waveguide layer 300B, sparse and dense regions are divided, and then different etching parameters are set for the sparse and dense regions respectively. For example, for the sparse regions, over-etching is performed based on a seventh preset etching parameter; while for the dense regions, over-etching is performed based on an eighth preset etching parameter; wherein the seventh preset etching parameter includes a seventh particle concentration (or a seventh ICP power) or a seventh etching time, and the eighth preset etching parameter includes an eighth ion concentration (or an eighth ICP power) or an eighth etching time, where the eighth ion concentration is greater than the seventh particle concentration, or the eighth etching time is greater than the seventh etching time. Of course, going further, based on the same principle, the height of each graphic structure in the dense region can also be obtained (preferably from the GDSII layout; this height actually maps to the etching depth of the grooves between the waveguide structures 110), and further partitioned; specifically, for each dense region, with any specified graphic structure as the center, the dense region is divided into regions by a fifth preset side length R5 (R5 is less than R2), resulting in at least two sub-regions (i.e., rectangular regions), and the average height of the graphic structure 120 in each sub-region is calculated; if the average height is less than or equal to a seventh preset height threshold, and greater than or equal to... At the eighth preset height threshold, the eighth etching parameters corresponding to the corresponding sub-region are adjusted, such as increasing the initial etching time or increasing the initial ICP power according to the third preset increment, thereby increasing the ion concentration. If the average height is less than the eighth preset height threshold but greater than or equal to the ninth preset height threshold, the eighth etching parameters corresponding to the corresponding sub-region are adjusted, such as increasing the initial etching time or increasing the initial ICP power according to the fourth preset increment, thereby increasing the ion concentration; wherein the fourth preset increment is less than the third preset increment. If the average height is less than the ninth preset height threshold, the current eighth etching parameters are maintained. Furthermore, if the ion concentration is increased, the thickness of the third protective layer 204 is increased accordingly.

[0078] Example 4: The present invention also provides another heterogeneous integration method for thin-film lithium niobate and transparent substrate waveguide system, which includes the steps of Example 3 above. The difference is that, since the second waveguide layer 300B is made of thin-film lithium niobate material, considering the properties of thin-film lithium niobate itself, sometimes a relatively dense waveguide structure 110 is not designed on the second waveguide layer 300B, but a waveguide structure 110 with a large height difference may be designed. Therefore, in this example, the etching parameters are configured from two angles: the width and height (related to the etching depth) of the waveguide structure 110. That is, the first waveguide layer 300 still uses the duty cycle-based division of dense and sparse regions as described in Embodiment 3 above, and then adjusts the etching parameters based on width and height. However, unlike the etching parameter configuration method of the first waveguide layer 300, the etching parameters of the second waveguide layer 300B in this embodiment are not based on the duty cycle to distinguish between dense and sparse regions, but rather on the height or depth of the patterned structure 120 to distinguish between deep and shallow etched regions (here, deep and shallow etched refer to the different etching depths corresponding to different waveguide structures 110 when the second waveguide layer 300B is etched through; depths greater than or equal to a preset height threshold are considered deep etched, while depths less than the preset height threshold are considered shallow etched). Then, the average width of the patterned structure 120 or waveguide structure 110 in each region is used for classification, and corresponding process parameters are configured for each level of region. See Figure 8Specifically, the steps include: S601, obtaining the width and height of each graphic structure 120 (preferably obtained from the GDSII layout; the height actually maps the etching depth of the grooves between waveguide structures 110); S602, dividing the second waveguide layer 300B into regions with any specified graphic structure as the center and a second preset side length R2 (actually dividing the regions according to the side of the embossed soft template in the design drawing where the graphic structure is set), obtaining multiple regions (i.e., rectangular regions), and calculating the average height and average width of the graphic structure 120 in each region; S603, determining whether the average height of each region is greater than or equal to a tenth preset height threshold, and whether the average width is greater than or equal to a tenth preset height threshold. The system checks whether the average height is greater than or equal to a first preset width threshold. If the average height is less than or equal to a tenth preset height threshold, the corresponding area is marked as a shallow etched area. If the average height is greater than the tenth preset height threshold, the corresponding area is marked as a deep etched area. If the average width of any shallow etched area is less than the first preset width threshold, the area is marked as a Class I shallow etched area. If the average width is greater than or equal to the first preset width threshold, the area is marked as a Class II shallow etched area. If the average width of any deep etched area is less than the first preset width threshold, the area is marked as a Class I deep etched area. If the average width is greater than or equal to the first preset threshold, the area is marked as a Class II deep etched area. The higher the height and the wider the width of the pattern structure within a certain area, the deeper the waveguide structure is etched, but the larger the spacing. Conversely, the higher the height and the smaller the width of the pattern structure within a certain area, the deeper the waveguide structure is etched, and the smaller the spacing. Therefore, compared to the former area, if the same etching parameters are used, the etching rate of the latter area is slower. Therefore, to reduce the difference in etching time and thus reduce the overall over-etching time, the etching parameters of the latter area can be greater than those of the former area.

[0079] Accordingly, step S105 specifically includes: for the Class I shallow etched region, over-etching is performed based on the ninth preset etching parameter; for the Class II shallow etched region, over-etching is performed based on the tenth preset etching parameter; for the Class I deep etched region, over-etching is performed based on the eleventh preset etching parameter; and for the Class II deep etched region, over-etching is performed based on the twelfth preset etching parameter. Wherein, the ninth preset etching parameter includes the ninth ICP power, the tenth preset etching parameter includes the tenth ICP power, the eleventh preset etching parameter includes the eleventh ICP power, and the twelfth preset etching parameter includes the twelfth ICP power. Preferably, the twelfth ICP power < the eleventh ICP power, the ninth ICP power < the twelfth ICP power, and the tenth ICP power < the ninth ICP power.

[0080] Example 5: Referring to Figure 1, this is a schematic diagram of an embodiment of the heterogeneous integrated structure of a thin-film lithium niobate and transparent substrate waveguide system according to the present invention. This heterogeneous integrated structure is prepared based on the method of Example 1, Example 3, or Example 4 above. Specifically, the heterogeneous integrated structure includes: a transparent substrate 100, a first masking layer 200-1 located on the transparent substrate 100, a first waveguide layer 300 located on the first masking layer 200-1, a first cover layer 800-1 surrounding the first waveguide layer 300, a second masking layer 200-2 located on the first masking layer 800-1 covering the upper surface of the first waveguide layer 300, and a second waveguide layer 300B located on the second masking layer 200-2; wherein, the upper surface of the first cover layer 800-1 is flush with the upper surface of the first waveguide layer 300.

[0081] Furthermore, both the first masking layer 200-1 and the second masking layer 200-2 are patterned. Specifically, as described in Embodiment 1, since the first waveguide layer 300 and the second waveguide 300B have been etched respectively, the first masking layer 200-1 located on the light-transmitting substrate 100 is also patterned; similarly, the second masking layer 200-2 is also patterned.

[0082] In some other embodiments, the first protective layer 200-1 has a double-layer structure, specifically comprising: a first protective layer 202 located on the first surface 101 of the light-transmitting substrate 100, and a second protective layer 203 located between the first protective layer 202 and the first waveguide layer 300. The first protective layer 202 is obtained by depositing a silicon dioxide layer of thickness H1 on the first surface 101 of the light-transmitting substrate 100 using a first deposition process such as HDP-CVD technology, and has a first morphology. The second protective layer 203 is obtained by depositing a silicon dioxide layer of thickness H2 on the upper surface of the first protective layer 202 using a second deposition process such as PECVD technology, and has a second morphology. The first morphology and the second morphology are complementary, thereby forming a first protective layer with flat upper and lower surfaces.

[0083] In other embodiments, the second shielding layer 200-2 also adopts a double-layer structure. Specifically, it includes a third protective layer 204 located on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1, and a fourth protective layer 205 located between the third protective layer 204 and the second waveguide layer 300B. The third protective layer 204 is obtained by depositing a silicon dioxide layer with a thickness of H3 on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1 using a first deposition process such as HDP-CVD technology, and it has a first morphology. The fourth protective layer 205 is obtained by depositing a silicon dioxide layer with a thickness of H4 on the upper surface of the third protective layer 204 using a second deposition process such as PECVD technology, and it has a second morphology. The first morphology and the second morphology are complementary, thereby forming a second shielding layer 200-2 with flat upper and lower surfaces. Specifically, the first protective layer 200-1 and the second protective layer 200-2 of the double-layer structure are both prepared using the method described in Example 2 above. Correspondingly, the second protective layer 203 and the fourth protective layer 205 are both patterned.

[0084] Preferably, the thickness H2 of the second protective layer 203 is less than the thickness H1 of the first protective layer 202. Preferably, H1 + H2 ≥ 1 μm (i.e., the thickness of the protective layer 200 is greater than or equal to 1 μm). Preferably, the thickness H4 of the fourth protective layer 205 is less than the thickness H3 of the third protective layer 204. Preferably, H3 + H4 ≥ 5 μm (i.e., the thickness of the second protective layer 200-2 is greater than or equal to 5 μm).

[0085] In other embodiments, the heterogeneous integrated structure further includes a second cladding layer 800-2 covering the second waveguide layer 300B.

[0086] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0087] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for heterogeneous integration of a thin-film lithium niobate and a transparent substrate waveguide system, characterized in that, Including the following steps: S101, a first masking layer (200-1) is deposited on the first surface (101) of the light-transmitting substrate (100), the first masking layer (200-1) being used to protect the light-transmitting substrate (100) during subsequent etching. S102, deposit a first waveguide layer (300) on the second surface (201) of the first shielding layer (200-1). S103, a first capping layer (800-1) is deposited around the first waveguide layer (300), the upper surface of the first capping layer (800-1) being flush with the upper surface of the first waveguide layer (300); S104, deposit a second shielding layer (200-2) on the upper surface of the first waveguide layer (300) and the upper surface of the first cover layer (800-1). S105, deposit a second waveguide layer (300B) on the second shielding layer (200-2); wherein the second waveguide layer (300B) is a thin film lithium niobate layer; Step S101 specifically includes: S1011, a first protective layer (202) with a thickness of H1 and a first morphology is deposited on the first surface (101) using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD. S1012, a second deposition process is used to deposit a silicon dioxide layer (203) with a thickness of H2 and a second morphology on the upper surface of the first protective layer (202); the second deposition process includes PECVD; Wherein, the sum of the thickness H2 of the second protective layer (203) and the thickness H1 of the first protective layer (202) is greater than or equal to 1 μm; and the first protective layer (202) of the first morphology and the second protective layer (203) of the second morphology complement each other to form a flat first protective layer (200-1).

2. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 1, characterized in that, The light-transmitting substrate (100) is a glass substrate.

3. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 1 or 2, characterized in that, In step S102, a patterned first waveguide layer (300) is fabricated on the first masking layer (200-1) using nanoimprint lithography. And / or, in step S105, a patterned second waveguide layer (300B) is fabricated on the second masking layer (200-2) using nanoimprint lithography.

4. A heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system according to claim 1 or 2, characterized in that, Step S104 specifically includes the following steps: S1041, a third protective layer (204) with a first morphology is deposited on the upper surface of the first waveguide layer (300) and the upper surface of the first cover layer (800-1) using a first deposition process. S1042, a fourth protective layer (205) with a second morphology is deposited on the third protective layer (204) using a second deposition process. Wherein, the sum of the thickness H3 of the fourth protective layer (205) and the thickness H4 of the third protective layer (204) is greater than or equal to 5 μm; and the third protective layer (204) of the first morphology and the fourth protective layer (205) of the second morphology complement each other to form a flat second protective layer (200-2).

5. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 3, characterized in that, Before fabricating the patterned first waveguide layer (300) and / or the patterned second waveguide layer (300B) using nanoimprint lithography, the following steps are also included: S401, the width of the graphic structure (120) on the imprinting soft template (500) corresponding to the waveguide structure (110) in the first waveguide layer (300) and / or the width of the graphic structure (120) corresponding to the waveguide structure (110) in the second waveguide layer (300B) is obtained in advance; S402, for the first waveguide layer (300), with the specified graphic structure as the center point, the first waveguide layer (300) is divided into regions by a first preset side length R1 to obtain multiple regions, and the graphic duty cycle of each region is calculated, and step S403 is executed; and / or, for the second waveguide layer (300B), with the specified graphic structure as the center, the second waveguide layer (300B) is divided into regions by a second preset side length R2 to obtain multiple regions, and the image duty cycle of each region is calculated, and step S403 is executed; S403, for the first waveguide layer (300), determine whether the pattern duty cycle of each region is greater than or equal to the first preset duty cycle threshold. If the pattern duty cycle is greater than or equal to the first preset duty cycle threshold, mark the corresponding region as a dense region. If the duty cycle of the graphic is less than the first preset duty cycle threshold, the corresponding region will be marked as a sparse region. And / or, for the second waveguide layer (300B), determine whether the pattern duty cycle of each region is greater than or equal to a second preset duty cycle threshold. If the pattern duty cycle is greater than or equal to the second preset duty cycle threshold, mark the corresponding region as a dense region. If the duty cycle of the graphic is less than the second preset duty cycle threshold, the corresponding region will be marked as a sparse region. Accordingly, during etching in step S102, sparse regions are over-etched based on a first preset etching parameter; while dense regions are over-etched based on a second preset etching parameter; wherein the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power; and / or, during etching in step S105, sparse regions are over-etched based on a seventh preset etching parameter; while dense regions are over-etched based on an eighth preset etching parameter; wherein the seventh preset etching parameter includes a seventh ICP power, the eighth preset etching parameter includes an eighth ICP power, and the eighth ICP power is greater than the seventh ICP power.

6. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 3, characterized in that, Before fabricating the patterned second waveguide layer (300B) using nanoimprint lithography, the following steps are also included: S601, obtain the width and height of each graphic structure (120) on the imprinted soft template (500) corresponding to the waveguide structure (110) in the second waveguide layer (300B); S602, with any specified graphic structure as the center, the second waveguide layer (300B) is divided into regions by the second preset side length R2 to obtain multiple regions, and the average height and average width of the graphic structure (120) in each region are calculated; S603, determine whether the average height of each region is greater than or equal to the tenth preset height threshold, and whether the average width is greater than or equal to the first preset width threshold; If the average height is less than or equal to the tenth preset height threshold and the average width is less than the first preset width threshold, the area is marked as a Class I shallow etching area. If the average height is less than or equal to the tenth preset height threshold and the average width is greater than or equal to the first preset width threshold, the area is marked as a Level II shallow etching area. If the average height is greater than the tenth preset height threshold and the average width is less than the first preset width threshold, the area is marked as a Level I deep area. If the average height is greater than the tenth preset height threshold and the average width is greater than or equal to the first preset threshold, the area is marked as a Class II deep erosion area. Accordingly, step S105 specifically includes: for the Class I shallow etched area, over-etching is performed based on the ninth preset etch parameter; for the Class II shallow etched area, over-etching is performed based on the tenth preset etch parameter; for the Class I deep etched area, over-etching is performed based on the eleventh preset etch parameter; for the Class II deep etched area, over-etching is performed based on the twelfth preset etch parameter; wherein, the ninth preset etch parameter includes the ninth ICP power, the tenth preset etch parameter includes the tenth ICP power, the eleventh preset etch parameter includes the eleventh ICP power, and the twelfth preset etch parameter includes the twelfth ICP power.

7. A heterogeneous integrated structure of a thin-film lithium niobate and a transparent substrate waveguide system, characterized in that, It is prepared using a heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system as described in any one of claims 1 to 6, comprising: A light-transmitting substrate (100), a first masking layer (200-1) on the light-transmitting substrate (100), and a patterned first waveguide layer (300) on the first masking layer (200-1); a first cover layer (800-1) surrounding the first waveguide layer (300), and a second masking layer (200-2) on the upper surface of the first cover layer (800-1) and the upper surface of the first waveguide layer (300), and a second waveguide layer (300B) on the second masking layer (200-2); the upper surface of the first cover layer (800-1) is flush with the upper surface of the first waveguide layer (300); The first shielding layer (200-1) and the second shielding layer (200-2) are both deposited using pure silicon dioxide material, and the thickness of the first shielding layer (200-1) and the second shielding layer (200-2) is greater than or equal to 1 μm. The first shielding layer (200-1) includes: a first protective layer (202) with a thickness of H1 on a first surface (101) of the light-transmitting substrate (100); and a second protective layer (203) with a thickness of H2 deposited on the upper surface of the first protective layer (202); H1+H2≥1um; and / or, the second shielding layer (200-2) includes: a third protective layer (204) with a thickness of H3 on the first cover layer (800-1) and the first waveguide layer (300); and a fourth protective layer (205) with a thickness of H4 on the upper surface of the third protective layer (204); H3+H4≥5um.

8. The heterogeneous integrated structure of a thin-film lithium niobate and transparent substrate waveguide system according to claim 7, characterized in that, The first protective layer (202) or the third protective layer (204) is a silicon dioxide layer with a first morphology deposited using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD. The second protective layer (203) or the fourth protective layer (205) is a silicon dioxide layer with a second morphology deposited using a second deposition process; the second deposition process includes PECVD; wherein the first protective layer (202) of the first morphology and the second protective layer (203) of the second morphology complement each other to form a flat first protective layer (200-1), or the third protective layer (204) of the first morphology and the fourth protective layer (205) of the second morphology complement each other to form a flat second protective layer (200-2).

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