Memory chip packaging method and system based on hipi protocol

Abstract

The application provides a memory particle packaging method and system based on a HIPI protocol, which packages memory particles through the HIPI protocol, and the memory particle packaging method comprises the following steps: receiving all signals sent by a DRAMC through a DRAM interface module, analyzing the signals through semantics, and then packaging the signals to a HIPI channel; synchronizing the bandwidth of the HIPI and the DRAM particle through a read-write buffer module to complete the HIPI packaging; generating a DQS signal and a Clock signal of the DRAM particle based on the access protocol of the DRAM through a DRAM clock signal generation module; and writing data into the DRAM particle or reading data out of the DRAM based on the DQS signal and the Clock signal. In the memory particle packaging process, the DRAMC and the memory particle do not need any modification, and the application is friendly to the development of hardware manufacturers.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and in particular relates to a method and system for packaging memory chips based on the HIPI protocol. Background Technology

[0002] This invention addresses a technical need: how to enable devices such as CPUs / NPUs to access memory devices through a chiplet interconnect scheme.

[0003] In existing technologies, if customers need to co-package their self-developed chips with memory chips, they need to define their own communication methods and packaging methods, and ensure link signal quality. Using the HIPI protocol of the memory chip allows direct use of the memory chip via the HIPI protocol, reducing development costs. Chip manufacturers need to package their self-developed IP with memory to achieve high density, high memory bandwidth, and low power consumption. Commonly used memory chips include high-performance HBM memory and low-cost DDR / DDR2 / DDR3 memory. The significant differences in memory chips and the lack of a unified standard result in different manufacturers having different co-packaging solutions, leading to high development costs and long development cycles.

[0004] This invention defines a data encapsulation strategy and proposes a method for encapsulating memory data based on the HIPI protocol. Summary of the Invention

[0005] To address this, the present invention provides a memory chip packaging method based on the HIPI protocol. The method encapsulates memory chips using the HIPI protocol, comprising: receiving all signals emitted by the DRAMC through a DRAM interface module, performing semantic analysis, and then encapsulating them into the HIPI path; synchronizing the bandwidth of the HIPI and DRAM chips through a read / write buffer module to complete the HIPI encapsulation; generating DQS and Clock signals for the DRAM chips based on the DRAM access protocol through a DRAM clock signal generation module; and writing data to or reading data from the DRAM chips based on the DQS and Clock signals.

[0006] Furthermore, preferably, in the memory chip packaging method of the present invention, the DRAMC sends memory operation behaviors to the memory chip through pins, so that the DRAM chip can perform corresponding operations. The memory operation behaviors include: reading data, writing data, activating a memory page, closing a memory page, refreshing a bank or all banks, reading and writing general-purpose registers, process initialization, etc.

[0007] Furthermore, preferably, in the memory chip packaging method of the present invention, the memory operation behavior includes a memory refresh operation, and when a refresh request from the memory controller is detected, the address of the refresh operation is obtained.

[0008] Furthermore, preferably, in the memory chip packaging method of the present invention, when the CS_n, RAS_n, and CAS_n signals are low, and the ACT_n and WE_n signals are high, and the CKE signals of the previous cycle and the current cycle are high, it indicates that the memory controller requests a refresh operation on the memory chip. After recognizing this request, the address of the refresh operation is obtained through the BG, BA, and CA signal lines. Any combination of signals that recognizes the refresh request from the memory controller is acceptable, and other combinations besides those mentioned above are also possible.

[0009] Furthermore, preferably, in the memory chip packaging method of the present invention, the signals emitted by the DRAMC for a certain operation have a specific timing sequence among multiple commands, and the packaging module identifies the timing sequence to obtain the semantics of the operation.

[0010] Furthermore, preferably, in the memory chip packaging method of the present invention, when packaging the read data, the read request of the memory controller is identified. In one state, the memory controller first sends a READ command, and then receives a DQS signal after a specific N cycles allowed by the memory chip. As the DQS signal samples the DQ signal line, the data content is obtained.

[0011] Furthermore, preferably, in the memory chip packaging method of the present invention, when packaging data read continuously from multiple addresses, the DRAMC sends a READ command for address Addr1, sends a READ command for address Addr2 within m cycles allowed by the memory chip, and receives a DQS signal after m+n cycles, where m and n are positive integers greater than or equal to 1.

[0012] Furthermore, preferably, in the memory chip packaging method of the present invention, different memory banks are DRAMC sending the READ command at address Addr1, sending the READ command at address Addr2 after p cycles allowed by the memory chip, and receiving the DQS signal and DQ data after p+q cycles, where p and q are positive integers greater than or equal to 1.

[0013] Furthermore, preferably, in the memory chip packaging method of the present invention, after obtaining the content of the command and data, the DRAM interface, after understanding the semantics of the request, saves the operation command word and data into the read / write buffer, and waits for the HIPI controller to package the data and command and send them to the DRAM side of the chip.

[0014] Furthermore, preferably, in the memory chip packaging method of the present invention, during the interaction between the DRAM Interface and the DRAMC, the latency of DRAM operation is increased by modifying the memory operation parameters of the DRAMC.

[0015] Furthermore, preferably, in the memory chip packaging method of the present invention, when delay jitter occurs during the HIPI link transmission process, the impact of the jitter is accommodated by an internal buffer. When the jitter exceeds the buffer's capacity, an ECC error is used to notify the memory controller, causing it to retransmit the data.

[0016] Furthermore, preferably, the present invention also provides a memory chip packaging system based on any of the above-described memory chip packaging methods.

[0017] The beneficial effects of the present invention include at least one of the following:

[0018] 1) The HIPI controller is positioned between the DRAMC and the memory chip. Neither the DRAMC nor the memory chip requires any modifications, making it more user-friendly for hardware manufacturers.

[0019] 2) DRAMC requires adjustment of the latency parameters of the memory chips.

[0020] 3) The HIPI controller module includes a buffer on the DRAMC side, a buffer on the DRAM chip side, a data command parameter packing module, and a timing and semantic recognition module.

[0021] 4) The HIPI controller is located on the DRAM chip side, and the timing of memory operations needs to be analyzed and adjusted.

[0022] 5) The HIPI channel is divided, and each channel is assigned an independent I / O to meet the requirements of minimum latency and constant latency.

[0023] 6) For link anomalies and occasional delays caused by error retransmissions, notify the memory controller via ECC error to retransmit the data. Attached Figure Description

[0024] Figure 1 Different NPU interface locations are shown in several memory packaging methods according to one embodiment of the present invention.

[0025] Figure 2 The diagram illustrates a memory packaging system structure according to one embodiment of the present invention.

[0026] Figure 3 This illustrates a packaging format in a memory packaging system architecture according to an embodiment of the present invention, in which a HIPI controller packages data and commands captured from a DRAM interface. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0028] To provide high-bandwidth memory access for compute-intensive IPs (such as NPUs, GPUs, and codecs), one approach is to encapsulate memory granules using the HIPI protocol. This provides a simplified memory solution leveraging HIPI's high throughput, offering bandwidth close to that of HBM.

[0029] There are various methods for encapsulating memory; the essential difference lies in the location of the interface provided to the NPU. Specific details are as follows: Figure 1 As shown. That is to say, Figure 1 Different NPU interface locations are shown in several memory packaging methods according to one embodiment of the present invention.

[0030] (a) indicates that the communication between the memory controller (DRAMC) and the memory chip (or die) is encapsulated by the HIPI protocol, and the NPU interconnects with the memory chip.

[0031] (b) indicates that the communication between the NPU and DRAMC is packaged by HIPI, and the NPU interconnects with the "DRAM chip with memory controller".

[0032] (c) indicates that a custom DRAMC is designed for high-performance memory scenarios, and a portion of the communication data is encapsulated in HIPI within the DRAMC.

[0033] The advantages and disadvantages of the three methods are compared in Table 1.

[0034] Table 1. Advantages and disadvantages of three memory packaging methods

[0035]

[0036] In this invention, a HIPI communication protocol for scheme (a) was designed.

[0037] A memory packaging system structure diagram according to an embodiment of the present invention is shown below. Figure 2 As shown.

[0038] Figure 2 The design scheme is shown in the dashed box, and its main modules are shown in Table 2.

[0039] Table 2. Description of the main modules in the design scheme of the memory packaging system structure.

[0040]

[0041] Module behavior

[0042] 1) DRAMC

[0043] DRAMC is IP provided by the NPU developers themselves. DRAMC may be specially optimized and customized IP for the NPU's memory read / write modes.

[0044] If no chip interconnect solution is used, the DRAMC connects directly to the DRAM chip. The DRAM provides pins for clock signals, DQS signals, command lines, address lines, and data lines.

[0045] The DRAMC sends memory operation commands to the memory chips via pins. These commands include: reading data, writing data, activating memory pages, precharging memory pages, refreshing a specific or all memory libraries, reading and writing general-purpose registers, and initialization procedures. These commands are issued by the DRAMC and communicated to the DRAM chips via combinations of signals on its pins, instructing the DRAM chips to perform the corresponding operations.

[0046] For example, when the CS_n, RAS_n, and CAS_n signals are low, and the ACT_n and WE_n signals are high, and the CKE signal of the previous cycle and the current cycle is high, the memory chip performs a REFRESH operation, and the address of the operation is obtained through the BG, BA, C, and A signal lines.

[0047] The signals emitted by the DRAMC have very strict timing characteristics, which are reflected in several aspects.

[0048] ① An operation often consists of a combination of multiple commands, and these commands have a strict order of delay. For example, for a read operation (NPU reading DRAM), in one state, the DRAMC first sends a READ command (represented by a combination of signal lines), and then receives the DQS signal after 11 cycles. With the DQS signal, the DQ signal line is sampled to obtain the data content. In another state, after sending the READ command, it is necessary to wait 21 cycles to receive the DQS signal.

[0049] ② To optimize read / write operations, READ commands may be sent between different addresses. For example, the DRAMC might send a READ command for address Addr1, then send a READ command for address Addr2 in the 4th cycle, and receive the DQS signal in the 11th cycle. The returned data is the data for Addr1 immediately following the data for Addr2, with no gap between the two data entries. If Addr1 and Addr2 are in different libraries, the scenario might be that the DRAMC sends a READ command for Addr1, sends a READ command for address Addr2 in the 6th cycle, and receives the DQS signal and DQ data in the 11th cycle.

[0050] In summary, there are specific delay requirements between sending a command and receiving data. A DQS signal must be responded to after a preset time. The delay requirements for sending multiple commands are related to the addresses of these commands; different addresses may correspond to different delays.

[0051] In the method of this invention, the DRAMC does not need to be modified; it can simply emit signals according to its normal behavior.

[0052] 2) DRAM Interface

[0053] The DRAM interface (also known as the DRAM interface) simulates the signal lines of the DDR chip. From the perspective of the DRAMC, when the DRAM chip is not in use, the DRAMC is connected to the memory chip; when the DRAM chip is in use, it is connected to the DRAM interface. However, the pin signals of the DRAM interface are completely identical to the signals of the memory chip in terms of function and behavior.

[0054] The DRAM Interface captures the command signals and address of the read command issued by the DRAMC, and after a specific time, sends the data to be read to the DRAMC through the DQS pin and the DQ pin.

[0055] For write commands sent by DRAMC, capture the command signals, address, and data.

[0056] For the Refresh, active, and precharge commands, capture the command signals and addresses.

[0057] For other commands, capture command signals and data signals.

[0058] After obtaining the command and data content, the DRAM Interface can understand the semantics of this request. It saves the operation command word and data to the Read / Write Buffer, waiting for the HIPI controller to package the data and command before sending them to the DRAM side of the chip.

[0059] The interaction between the DRAM Interface and DRAMC increases the latency of DRAM operations, thus requiring modification of the DRAMC's memory operation parameters.

[0060] For ease of description, HIPI has a minimum delay from the transmitter to the receiver, called N. That is, when the transmitter sends a signal to the receiver, if there is no retransmission due to a check failure, the delay is between N and N+ε, where ε is generally 0, 1, or 2. This is due to the random delay caused by crossing clock domains. If a check failure occurs, the delay may be greater than 3N, but the delay will not be less than N.

[0061] It's important to note that delay parameters have three characteristics: ① For general read / write commands, the reasonable use of delay parameters is to improve performance and avoid wasting bus bandwidth. Minor deviations in delay will not cause data errors, so the aforementioned ε is not considered in the correction. ② For refresh commands, delay parameters need to be relatively accurate, but minor errors have little impact. ③ For write commands, after sending the WRITE command, data will be sent after a delay of tWCL. For the HIPI controller, this data can be buffered to hide the disturbances caused by ε. Accumulated errors can be eliminated using read commands. However, if write commands are continuously sent without read commands to eliminate errors, the buffer may overflow. In this case, the DRAM interface can generate a CRC error signal to notify the DRAMC that the data needs to be retransmitted.

[0062] The latency correction introduced by the DRAM interface is intended to reduce the throughput performance loss caused by latency in the HIPI link.

[0063] Specifically, for the Read command, the important timing parameters are shown in Table 3.

[0064] Table 3 explains the important timing parameters for the Read command.

[0065]

[0066]

[0067] As shown in Table 3 above, the delay parameters for read and write commands need to be modified, while other commands remain basically unchanged.

[0068] 3) HIPI controller

[0069] There is a HIPI controller on both the NPU side and the DRAM side.

[0070] On the NPU side, the HIPI controller encapsulates the contents of the buffer, adds verification information, performs flow control, and then sends it to the HIPI controller on the DRAM side.

[0071] Each channel has a dedicated number of I / O operations, and therefore a fixed bit width. For HBM3e memory, in one configuration, there are 16 channels, each with a 64-bit width. The I / O frequency is 9.6 GHz. For the HIPI protocol, in one configuration, each I / O provides a throughput of 32 Gbps.

[0072] Each channel has its own set of I / O operations. The specific method for estimating the number of I / O operations is as follows:

[0073] 64 * 9.6G / 32 = 20

[0074] Because data lines, address lines, and command lines are independent in DRAM memory, the number of I / Os is greater than calculated using the above method. Assume that N I / Os are dedicated to one channel.

[0075] The HIPI controller packages the data and commands captured by the DRAM Interface and sends them to the HIPI controller on the DRAM side through the IO channel.

[0076] The packaging method is briefly introduced below:

[0077] The input consists of a combination of a command word (CMD), parameters (param), and data (data). Depending on the type of CMD, it may contain parameters of varying lengths. Some CMDs may send or receive data in subsequent cycles.

[0078] The rules for the packaging method are as follows:

[0079] ① It needs to include information such as CMD, Param, and data.

[0080] ② It is necessary to ensure the order and transmission quality.

[0081] ③ Make the most of the I / O bandwidth.

[0082] ④ Minimize the transmission delay, and keep the delay close to a constant.

[0083] ⑤ Facilitates hardware parsing of message formats.

[0084] Packaging format as follows Figure 3 As shown.

[0085] CMD uses a fixed-length field. According to the current design, it uses 5 bits, that is, power(2,5) = 32 command words.

[0086] Different CMDs have different lengths of Param. You can look up the format of the current Param by referring to the table for each CMD.

[0087] If it is data, it is identified using a special CMD type. For a memory configuration, DRAMC sends 64 bits of data per clock cycle. Because the HIPI I / O frequency is higher than that of DRAMC, the data in one clock cycle may be sent in several HIPI data packets.

[0088] 4) Channel segmentation

[0089] Each channel has its own set of I / O to achieve minimal latency and near-constant latency.

[0090] For example, if a DRAMC has 16 channels, and each channel occupies N IOs, then a total of 16*N IOs are needed to carry out all data transmission.

[0091] 5) DRAM-side HIPI controller

[0092] Similar to the controller on the NPU side, the HIPI controller on the DRAM side also includes protocol parsing, buffer, and DRAM interface.

[0093] The protocol parsing section analyzes the data sent by the NPU. If it's a read / write command, it's sent directly to the DRAM chip. If it's data to be written, a timing check is performed at the receiving end. In principle, the HIPI controller's transmission time is close to constant, but cross-clock domain data transmission may introduce jitter of about one cycle (ε). Forcibly adding this ε jitter time to the DRAMC can ensure the correct timing of data transmission to the DRAM chip, but it will degrade memory performance parameters. Therefore, checking the latency at the HIPI receiver can improve performance.

[0094] For read commands, data sent by the DRAM chip needs to be received after a specific time. Therefore, a buffer is needed to store this data before sending it to the NPU. It's important to note that during the read process, after issuing the read command, a CL time is required before receiving the DQ and DQS signals from the DRAM chip. However, on the DRAMC side (i.e., the NPU side), the CL time is modified to CL+2N, while on the DRAM side, the time remains CL. This is because CL is an inherent characteristic of the memory chip, while CL+2N is the characteristic of the memory chip after adding the HIPI delay. The delay characteristics observed by the DRMAC and HIPI controllers differ.

[0095] The DRAM interface also needs to provide DQS and CLK signals that meet the phase requirements according to the needs of the DRAM chip.

[0096] 6) Exception handling

[0097] From the perspective of DRAMC, for read commands, after issuing the command, you just need to wait for the data to arrive. If there is abnormal delay due to the link delay of the HIPI controller or the retransmission of errors, it will affect the performance, but it will not cause data errors.

[0098] There may be risks associated with write commands. Specifically, DRAMC may send write requests to the DRAM chip continuously. For burst requests, the HIPI controller's buffer will temporarily store the data, waiting for the timing to be correct before writing the data to the DRAM chip. If writes are continuous, the amount of data written can be accommodated according to the aforementioned CWL delay, provided there are no link error retransmissions.

[0099] If a link error occurs, causing a retransmission, excessive write data may accumulate in the buffer. If the DRAMC sends the write again, it will cause the buffer to malfunction.

[0100] Currently, DRAM chips lack a handshake mechanism; the DRAM controller does not check the DRAM's receive status to decide whether to send the next data. However, DRAM has an Alert_n signal, typically used for DRAM CRC checks. If the DRAM chip's CRC check fails, the Alert_n signal is triggered, notifying the DRAM controller to retransmit the data. Therefore, when a link error occurs in the HIPI controller, causing excessive delays and the buffer nearing overflow, this method can be used to notify the DRAM controller, delaying subsequent write operations.

[0101] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0102] The various embodiments in this specification are described in a related manner. For the same or similar parts between the various embodiments, please refer to each other. Each embodiment focuses on describing the differences from other embodiments.

[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0104] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A memory chip packaging method based on the HIPI protocol, wherein the memory chip is packaged using the HIPI protocol, characterized in that... The memory chip packaging method includes: The DRAM interface module receives all signals from the DRAMC, performs semantic analysis, and then encapsulates them into the HIPI path. The HIPI packaging is completed by synchronizing the bandwidth of the HIPI and DRAM chips through the read / write buffer module. The DRAM clock signal generation module generates the DQS and Clock signals of the DRAM chips based on the DRAM access protocol. Data is written to or read from DRAM based on DQS and Clock signals.

2. The memory chip packaging method according to claim 1, characterized in that, DRAMC sends memory operation requests to the memory chips via pins, allowing the DRAM chips to perform corresponding operations. These memory operation requests include: reading data, writing data, activating memory pages, closing memory pages, refreshing a specific library or all libraries, reading and writing general-purpose registers, and process initialization.

3. The memory chip packaging method according to claim 2, characterized in that, Memory operations include memory refresh operations. When a refresh request from the memory controller is detected, the address of the refresh operation is obtained.

4. The memory chip packaging method according to claim 3, characterized in that, When CS_n, RAS_n, and CAS_n signals are low, and ACT_n and WE_n are high, and the CKE signal of the previous cycle and the current cycle is high, it indicates that the memory controller requests a refresh operation on the memory chip. After recognizing this request, the address of the refresh operation is obtained through the BG, BA, and CA signal lines.

5. The memory chip packaging method according to claim 3, characterized in that, The signals emitted by the DRAMC contain multiple commands for a certain operation with a specific timing sequence. The packaging module identifies this timing sequence to obtain the semantics of the operation.

6. The memory chip packaging method according to claim 5, characterized in that, When encapsulating the read data, the read request from the memory controller is identified. In one state, the memory controller first sends a READ command, and then receives the DQS signal after a specific N cycles allowed by the memory chip. The DQ signal line is sampled along with the DQS signal to obtain the data content.

7. The memory chip packaging method according to claim 6, characterized in that, When encapsulating data read from multiple addresses consecutively, the DRAMC sends a READ command for address Addr1, sends a READ command for address Addr2 within m cycles allowed by the memory chip, and receives a DQS signal after m+n cycles, where m and n are positive integers greater than or equal to 1.

8. The memory chip packaging method according to claim 7, characterized in that, When encapsulating data from multiple different bank addresses, if Addr1 and Addr2 are in different memory banks, the DRAMC sends a READ command for address Addr1, sends a READ command for address Addr2 after p cycles allowed by the memory chip, and receives the DQS signal and DQ data after p+q cycles, where p and q are positive integers greater than or equal to 1.

9. The memory chip packaging method according to claim 2, characterized in that, After obtaining the command and data content, the DRAM interface, after understanding the semantics of the request, saves the operation command word and data into the read / write buffer, and waits for the HIPI controller to package the data and command and send them to the DRAM side of the chip.

10. The memory chip packaging method according to claim 9, characterized in that, During the interaction between the DRAM Interface and the DRAMC, the latency of DRAM operations is increased by modifying the memory operation parameters of the DRAMC.

11. The memory chip packaging method according to claim 1, characterized in that, When delay jitter occurs during HIPI link transmission, the internal buffer absorbs the jitter. When the jitter exceeds the buffer's capacity, an ECC error is used to notify the memory controller, causing it to retransmit the data.

12. A memory chip packaging system implemented based on the memory chip packaging method according to any one of claims 1 to 11.

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