Fuse detection circuit, fuse detection method and semiconductor memory

Abstract

Embodiments of this disclosure provide a fuse detection circuit, a fuse detection method, and a semiconductor memory, including a matching circuit and a conversion circuit. The matching circuit can receive reference values ​​transmitted by multiple address lines and fuse group output values ​​output by multiple fuse groups. It matches the multiple reference values ​​with the multiple fuse output values ​​in each fuse group output value, and determines the status indication signal of each fuse group based on the multiple matching results of each fuse group. The conversion circuit can receive the multiple status indication signals output simultaneously by the matching circuit and convert the parallel multiple status indication signals into a serial target indication signal to indicate the available fuse groups among the multiple fuse groups, thereby detecting the available fuse groups.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of semiconductor device technology, and more particularly to a fuse detection circuit, a fuse detection method, and a semiconductor memory. Background Technology

[0002] Double Data Rate (DDR) memory is an advanced Dynamic Random Access Memory (DRAM) technology. DDR memory can transfer data twice within a single clock cycle, making data transfer twice as fast as traditional single-data-rate memory. It is widely used in computers, servers, mobile devices, consumer electronics, and embedded systems, covering almost all application scenarios requiring fast data storage. With continuous technological advancements, DDR memory has become one of the key technological components for improving device performance.

[0003] In DRAM, a fuse is a one-time programmable element. Its main function is to repair defects, configure parameters, and adjust functions during chip manufacturing and testing. Its core principle is to permanently change the circuit state by physically breaking metal connections. Typically, each memory module in a DRAM contains a certain number of fuses. These fuses can repair damaged word lines, etc. Therefore, it is essential to understand whether there are usable fuses in each memory module of the chip. Summary of the Invention

[0004] This disclosure provides a fuse detection circuit, a fuse detection method, and a semiconductor memory capable of detecting available fuse groups.

[0005] In a first aspect, this disclosure provides a fuse detection circuit, comprising: a matching circuit and a conversion circuit; a first input terminal of the matching circuit is connected to the output terminal of a fuse group, a second input terminal of the matching circuit is connected to an address line, and the output terminal of the matching circuit is connected to the conversion circuit.

[0006] The matching circuit is configured to receive reference values ​​transmitted by multiple address lines and fuse group output values ​​output by multiple fuse groups; match the multiple reference values ​​with multiple fuse output values ​​in each fuse group output value; and determine the status indication signal of each of the multiple fuse groups based on the multiple matching results of each of the multiple fuse groups.

[0007] The conversion circuit is configured to receive multiple status indication signals simultaneously output by the matching circuit, and convert the parallel multiple status indication signals into a serial target indication signal to indicate the available fuse group among the multiple fuse groups.

[0008] In some embodiments of this disclosure, the matching circuit includes a plurality of logic circuits, each of which corresponds one-to-one with a plurality of fuse groups; a plurality of first input terminals of each logic circuit are connected one-to-one with the output terminals of a plurality of fuses in a fuse group, a plurality of second input terminals of each logic circuit are connected one-to-one with the plurality of address lines, and the output terminal of each logic circuit is connected to an input terminal of the conversion circuit.

[0009] The logic circuit is configured to receive the plurality of reference values ​​and the plurality of fuse output values, match each of the plurality of reference values ​​with the corresponding output value of the plurality of fuse output values ​​to obtain the matching result of each of the plurality of fuses, and determine the status indication signal of the corresponding fuse group based on the matching result of each of the plurality of fuses.

[0010] In some embodiments of this disclosure, the logic circuit includes a plurality of comparison units and a state determination unit. Each comparison unit corresponds one-to-one with a plurality of fuses, and the number of comparison units in a single logic circuit is equal to the number of address lines. The first input terminal of each comparison unit is connected to the output terminal of a fuse, the second input terminal of each comparison unit is connected to an address line, the output terminal of each comparison unit is connected to an input terminal of the state determination unit, and the output terminal of the state determination unit is connected to an input terminal of the conversion circuit.

[0011] The comparison unit is configured to receive a reference value and a fuse output value, and when the reference value is equal to the fuse output value, determine the matching result of the corresponding fuse as a first level, and when the reference value is not equal to the fuse output value, determine the matching result of the corresponding fuse as a second level.

[0012] The state determination unit is configured to determine that the state indication signal of the corresponding fuse group is high when the matching results of each of the plurality of fuses are all at the first level, and to determine that the state indication signal of the corresponding fuse group is low when at least one of the matching results of the plurality of fuses is at the second level.

[0013] In some embodiments of this disclosure, the reference value is 0, the first level is the low level, the second level is the high level, the comparison unit includes an OR gate, and the state determination unit includes a NOR gate. The first input of the OR gate is connected to the output of the fuse, the second input of the OR gate is connected to the address line, the output of the OR gate is connected to the input of the NOR gate, and the output of the NOR gate is connected to one input of the conversion circuit.

[0014] In some embodiments of this disclosure, the conversion circuit includes multiple cascaded conversion modules. The first input terminals of each conversion module are connected one-to-one with the multiple output terminals of the matching circuit. The control terminals of each conversion module are connected to a read signal, and the enable terminals are connected to a clock signal. The second input terminal of the subsequent conversion module in a pair of adjacent conversion modules is connected to the output terminal of the preceding conversion module. The second input terminal of the first-stage conversion module is connected to a low-level signal. The output terminal of the last-stage conversion module is used to output the target indication signal.

[0015] The conversion module is configured to output the signal received at the first input terminal when the read signal and the clock signal are valid, output the signal received at the second input terminal when the read signal is invalid and the clock signal is valid, and maintain the output of the clock signal before it flips to an invalid signal when the clock signal is invalid.

[0016] In some embodiments of this disclosure, the conversion module includes a multiplexer, a first inverter, a second inverter, a third inverter, a fourth inverter, and a latch.

[0017] The output of the matching circuit is connected to the first input of the multiplexer via the first inverter. The read signal is connected to the selector of the multiplexer via the third inverter. The output of the multiplexer is connected to the input of the latch. The clock signal is connected to the enable of the latch via the fourth inverter. The second input of the multiplexer in the first-stage conversion module is connected to the low-level signal. The output of the latch in the previous-stage conversion module is connected to the second input of the multiplexer in the next-stage conversion module via the second inverter. The output of the latch in the last-stage conversion module is connected to the output of the conversion module.

[0018] Secondly, this disclosure provides a fuse detection method, applied to any fuse detection circuit provided in the first aspect, the fuse detection method comprising:

[0019] The system receives reference values ​​transmitted from multiple address lines and fuse group output values ​​from multiple fuse groups; it matches the multiple reference values ​​with the multiple fuse output values ​​in each fuse group; it determines the status indication signal of each fuse group based on the multiple matching results of each fuse group; and it converts the multiple parallel status indication signals into a serial target indication signal to indicate the available fuse groups among the multiple fuse groups.

[0020] In some embodiments of this disclosure, a fuse group includes multiple fuses.

[0021] The step of matching multiple reference values ​​with multiple fuse output values ​​in each fuse group includes:

[0022] Each of the plurality of reference values ​​is matched with the corresponding output value among the plurality of fuse output values ​​to obtain the matching result of each of the plurality of fuses.

[0023] The determination of the status indication signal for each of the multiple fuse groups based on the multiple matching results of each of the multiple fuse groups includes:

[0024] The status indication signal of the corresponding fuse group is determined based on the matching results of each of the plurality of fuses.

[0025] In some embodiments of this disclosure, matching each of the plurality of reference values ​​with the corresponding output value among the plurality of fuse output values ​​to obtain the matching result for each of the plurality of fuses includes:

[0026] When a reference value is equal to the output value of a fuse, the matching result of the corresponding fuse is determined to be a first level; when the reference value is not equal to the output value of the fuse, the matching result of the corresponding fuse is determined to be a second level.

[0027] The determination of the status indication signal for the corresponding fuse group based on the matching results of the plurality of fuses includes:

[0028] When the matching results of each of the plurality of fuses are all at the first level, the status indication signal of the corresponding fuse group is determined to be at a high level; when at least one of the matching results of the plurality of fuses is at the second level, the status indication signal of the corresponding fuse group is determined to be at a low level.

[0029] Thirdly, this disclosure provides a semiconductor memory including a fuse bank, address lines, and any of the fuse detection circuits provided in the first aspect.

[0030] In the technical solution of this disclosure embodiment, the fuse detection circuit includes a matching circuit and a conversion circuit. The matching circuit can receive reference values ​​transmitted by multiple address lines and fuse group output values ​​output by multiple fuse groups. It matches the multiple reference values ​​with the multiple fuse output values ​​in each fuse group output value, and determines the status indication signal of each fuse group based on the multiple matching results of each fuse group. The conversion circuit can receive the multiple status indication signals output by the matching circuit at the same time, and convert the multiple parallel status indication signals into a serial target indication signal to indicate the available fuse groups among the multiple fuse groups, thereby detecting the available fuse groups. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present disclosure.

[0033] Figure 2 This is a schematic diagram of a fuse detection circuit provided in an embodiment of the present disclosure.

[0034] Figure 3 This is a circuit diagram of a fuse detection circuit provided in an embodiment of the present disclosure.

[0035] Figure 4 This is a schematic diagram of the working timing of a fuse detection circuit provided in an embodiment of the present disclosure.

[0036] Figure 5 This is a schematic flowchart of a fuse detection method provided in an embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0039] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0040] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0041] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0042] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present disclosure, such as... Figure 1 The semiconductor memory 100 includes a fuse group 110, an address line 120, and a fuse detection circuit 200. The first input terminal of the fuse detection circuit 200 is connected to the output terminal of the fuse group 110, and the second input terminal of the fuse detection circuit 200 is connected to the address line 120.

[0045] See also Figure 1 The fuse detection circuit 200 includes a matching circuit 210 and a conversion circuit 220. The first input terminal of the matching circuit 210 is connected to the output terminal of the fuse group 110, the second input terminal of the matching circuit 210 is connected to the address line 120, the output terminal of the matching circuit 210 is connected to the input terminal of the conversion circuit 220, and the output terminal of the conversion circuit 220 is connected to the output terminal of the fuse detection circuit 200.

[0046] The matching circuit 210 is configured to receive reference values ​​transmitted by each of the multiple address lines 120 and fuse group output values ​​output by each of the multiple fuse groups 110, match the multiple reference values ​​with the multiple fuse output values ​​in each fuse group output value, and determine the status indication signal of each of the multiple fuse groups 110 based on the multiple matching results of each of the multiple fuse groups 110.

[0047] The conversion circuit 220 is configured to receive multiple status indication signals simultaneously output by the matching circuit 210, and convert the multiple parallel status indication signals into a serial target indication signal to indicate the available fuse group 110 among the multiple fuse groups 110.

[0048] For example, Figure 2 This is a schematic diagram of the structure of a fuse detection circuit provided in an embodiment of the present disclosure, combined with... Figure 1 and Figure 2 As shown, the matching circuit 210 includes multiple logic circuits 211, and each of the multiple logic circuits 211 corresponds to a multiple fuse group 110.

[0049] Each logic circuit 211 has multiple first input terminals connected one-to-one with the output terminals of multiple fuses in a fuse group 110 to receive multiple fuse output values ​​from the output values ​​of a fuse group. Each logic circuit 211 has multiple second input terminals connected one-to-one with multiple address lines 120 to receive multiple reference values. Each logic circuit 211 has an output terminal connected to an input terminal of a conversion circuit 220 to output a status indication signal for a fuse group 110.

[0050] See also Figure 2 The logic circuit 211 includes multiple comparison units 212 and a state determination unit 213. The multiple comparison units 212 correspond one-to-one with multiple fuses. The number of comparison units 212 in a single logic circuit 211 is equal to the number of address lines 120.

[0051] The first input terminal of each comparison unit 212 is connected to the output terminal of a fuse to receive a fuse input value. The second input terminal of each comparison unit 212 is connected to an address line 120 to receive a reference value. The output terminal of each comparison unit 212 is connected to an input terminal of a status determination unit 213 to output a fuse matching result. The output terminal of the status determination unit 213 is connected to an input terminal of a conversion circuit 220 to output a status indication signal of the fuse group 110.

[0052] For example, the fuse output value can indicate whether the corresponding fuse is available. When the fuse is in use, the corresponding fuse output value is 1, and when the fuse is not in use, the corresponding fuse output value is the default value of 0.

[0053] Figure 3 A circuit diagram of a fuse detection circuit provided in an embodiment of this disclosure is shown below. Figure 3 As shown, the matching circuit 210 includes two logic circuits 211, namely the first logic circuit 2111 and the second logic circuit 2112.

[0054] The four first input terminals of the first logic circuit 2111 are respectively connected to the first fuse, the second fuse, the third fuse and the fourth fuse to simultaneously receive the output values ​​of the first fuse, the second fuse, the third fuse and the fourth fuse, wherein the first fuse, the second fuse, the third fuse and the fourth fuse constitute the first fuse group.

[0055] The four second input terminals of the first logic circuit 2111 are respectively connected to the first address line, the second address line, the third address line and the fourth address line to simultaneously receive the first reference value transmitted by the first address line, the second reference value transmitted by the second address line, the third reference value transmitted by the third address line and the fourth reference value transmitted by the fourth address line. The output terminal of the first logic circuit 2111 is connected to the first input terminal of the conversion circuit 220 to output the status indication signal of the first fuse group, that is, the first status indication signal.

[0056] The four first input terminals of the second logic circuit 2112 are respectively connected to the fifth fuse, the sixth fuse, the seventh fuse and the eighth fuse to simultaneously receive the output values ​​of the fifth fuse, the sixth fuse, the seventh fuse and the eighth fuse, wherein the fifth fuse, the sixth fuse, the seventh fuse and the eighth fuse constitute the second fuse group.

[0057] The four second input terminals of the second logic circuit 2112 are respectively connected to the first address line, the second address line, the third address line and the fourth address line to simultaneously receive the first reference value, the second reference value, the third reference value and the fourth reference value. The output terminal of the second logic circuit 2112 is connected to the second input terminal of the conversion circuit 220 to output the status indication signal of the second fuse group, that is, the second status indication signal.

[0058] See also Figure 3 Each logic circuit 211 includes four comparison units and one state determination unit. The first logic circuit 2111 includes a first comparison unit, a second comparison unit, a third comparison unit, a fourth comparison unit, and a first state determination unit. The second logic circuit 2112 includes a fifth comparison unit, a sixth comparison unit, a seventh comparison unit, an eighth comparison unit, and a second state determination unit.

[0059] The first input terminal of the first comparison unit is connected to the output terminal of the first fuse, the second input terminal of the first comparison unit is connected to the first address line, and the output terminal of the first comparison unit is connected to the first input terminal of the first state determination unit. The first comparison unit can receive the output value of the first fuse and a first reference value. When the output value of the first fuse is equal to the first reference value, the matching result of the first fuse is determined, i.e., the first matching result is a first level. When the output value of the first fuse is not equal to the first reference value, the first matching result is determined to be a second level.

[0060] The first input terminal of the second comparison unit is connected to the output terminal of the second fuse, the second input terminal of the second comparison unit is connected to the second address line, and the output terminal of the second comparison unit is connected to the second input terminal of the first state determination unit. The second comparison unit can receive the output value of the second fuse and the second reference value. When the output value of the second fuse is equal to the second reference value, the matching result of the second fuse is determined, i.e., the second matching result is a first level. When the output value of the second fuse is not equal to the second reference value, the second matching result is determined to be a second level.

[0061] The first input terminal of the third comparison unit is connected to the output terminal of the third fuse, the second input terminal of the third comparison unit is connected to the third address line, and the output terminal of the third comparison unit is connected to the third input terminal of the first state determination unit. The third comparison unit can receive the output value of the third fuse and the third reference value. When the output value of the third fuse is equal to the third reference value, the matching result of the third fuse is determined, i.e., the third matching result is the first level. When the output value of the third fuse is not equal to the third reference value, the third matching result is determined to be the second level.

[0062] The first input terminal of the fourth comparator is connected to the output terminal of the fourth fuse, the second input terminal of the fourth comparator is connected to the fourth address line, and the output terminal of the fourth comparator is connected to the fourth input terminal of the first state determination unit. The fourth comparator can receive the output value of the fourth fuse and a fourth reference value. When the output value of the fourth fuse is equal to the fourth reference value, the matching result of the fourth fuse is determined, i.e., the fourth matching result is a first level. When the output value of the fourth fuse is not equal to the fourth reference value, the fourth matching result is determined to be a second level.

[0063] The first state determination unit can receive the first matching result, the second matching result, the third matching result, and the fourth matching result. When all of the first matching result, the second matching result, the third matching result, and the fourth matching result are at the first level, the first state indication signal is determined to be at the high level. When at least one of the first matching result, the second matching result, the third matching result, and the fourth matching result is at the second level, the first state indication signal is determined to be at the low level.

[0064] The first input terminal of the fifth comparator is connected to the output terminal of the fifth fuse, the second input terminal of the fifth comparator is connected to the first address line, and the output terminal of the fifth comparator is connected to the first input terminal of the second state determination unit. The fifth comparator can receive the output value of the fifth fuse and the first reference value. When the output value of the fifth fuse is equal to the first reference value, the matching result of the fifth fuse is determined, i.e., the fifth matching result is a first level. When the output value of the fifth fuse is not equal to the first reference value, the fifth matching result is determined to be a second level.

[0065] The first input terminal of the sixth comparator is connected to the output terminal of the sixth fuse, the second input terminal of the sixth comparator is connected to the second address line, and the output terminal of the sixth comparator is connected to the second input terminal of the second state determination unit. The sixth comparator can receive the output value of the sixth fuse and the second reference value. When the output value of the sixth fuse is equal to the second reference value, the matching result of the sixth fuse is determined, i.e., the sixth matching result is the first level. When the output value of the sixth fuse is not equal to the second reference value, the sixth matching result is determined to be the second level.

[0066] The first input terminal of the seventh comparator is connected to the output terminal of the seventh fuse, the second input terminal of the seventh comparator is connected to the third address line, and the output terminal of the seventh comparator is connected to the third input terminal of the second state determination unit. The seventh comparator can receive the output value of the seventh fuse and the third reference value. When the output value of the seventh fuse is equal to the third reference value, the matching result of the seventh fuse is determined, i.e., the seventh matching result is the first level. When the output value of the seventh fuse is not equal to the third reference value, the seventh matching result is determined to be the second level.

[0067] The first input terminal of the eighth comparator is connected to the output terminal of the eighth fuse, the second input terminal of the eighth comparator is connected to the fourth address line, and the output terminal of the eighth comparator is connected to the fourth input terminal of the second state determination unit. The eighth comparator can receive the output value of the eighth fuse and the fourth reference value. When the output value of the eighth fuse is equal to the fourth reference value, the matching result of the eighth fuse is determined, i.e., the eighth matching result is the first level. When the output value of the fourth fuse is not equal to the eighth reference value, the eighth matching result is determined to be the second level.

[0068] The second state determination unit can receive the fifth matching result, the sixth matching result, the seventh matching result, and the eighth matching result. When all five matching results are at the first level, the second state indication signal is determined to be at the high level. When at least one of the five matching results is at the second level, the second state indication signal is determined to be at the low level.

[0069] For example, the reference value can be 0, that is, the first reference value, the second reference value, the third reference value and the fourth reference value are all 0, the first level is low level, the second level is high level and low level, the comparison unit 212 includes an OR gate, and the state determination unit 213 includes a NOR gate.

[0070] Based on the above embodiments, such as Figure 3 As shown, the first comparison unit includes a first OR gate OR1, the second comparison unit includes a second OR gate OR2, the third comparison unit includes a third OR gate OR3, the fourth comparison unit includes a fourth OR gate OR4, and the first state determination unit includes a first NOR gate NOR1.

[0071] In this configuration, the first input of the first OR gate (OR1) is connected to the output of the first fuse to receive the fuse's output value. The second input of the first OR gate (OR1) is connected to the first address line to receive the first reference value. The output of the first OR gate (OR1) is connected to the first input of the first NOR gate (NOR1) to output the first matching result. When the first fuse output value is 0, the first matching result is 0 (low level); when the first fuse output value is 1, the first matching result is 1 (high level).

[0072] The first input of the second OR gate OR2 is connected to the output of the first fuse to receive the output value of the second fuse. The second input of the second OR gate OR2 is connected to the second address line to receive the second reference value. The output of the second OR gate OR2 is connected to the second input of the first NOR gate NOR1 to output the second matching result. When the output value of the second fuse is 0, the second matching result is 0, i.e., low level; when the output value of the second fuse is 1, the second matching result is 1, i.e., high level.

[0073] The first input of the third OR gate (OR3) is connected to the output of the third fuse to receive the fuse's output value. The second input of the third OR gate (OR3) is connected to the third address line to receive the third reference value. The output of the third OR gate (OR3) is connected to the third input of the first NOR gate (NOR1) to output the third matching result. When the third fuse output value is 0, the third matching result is 0 (low level); when the third fuse output value is 1, the third matching result is 1 (high level).

[0074] The first input of the fourth OR gate (OR4) is connected to the output of the fourth fuse to receive its output value. The second input of the fourth OR gate (OR4) is connected to the fourth address line to receive the fourth reference value. The output of the fourth OR gate (OR4) is connected to the fourth input of the first NOR gate (NOR1) to output the fourth matching result. When the output value of the fourth fuse is 0, the fourth matching result is 0 (low level); when the output value of the fourth fuse is 1, the fourth matching result is 1 (high level).

[0075] When the first matching result, the second matching result, the third matching result, and the fourth matching result are all 0, the first NOR gate NOR1 outputs 1, that is, the first state indicator signal is high. When there is at least one 1 among the first matching result, the second matching result, the third matching result, and the fourth matching result, the first NOR gate NOR1 outputs 0, that is, the first state indicator signal is low.

[0076] The fifth comparison unit includes the fifth OR gate OR5, the sixth comparison unit includes the sixth OR gate OR6, the seventh comparison unit includes the seventh OR gate OR7, the eighth comparison unit includes the eighth OR gate OR8, and the second state determination unit includes the second NOR gate NOR2.

[0077] In this configuration, the first input of the fifth OR gate (OR5) is connected to the output of the fifth fuse to receive its output value. The second input of the fifth OR gate (OR5) is connected to the first address line to receive the first reference value. The output of the fifth OR gate (OR5) is connected to the first input of the second NOR gate (NOR2) to output the fifth matching result. When the output value of the fifth fuse is 0, the fifth matching result is 0 (low level); when the output value of the fifth fuse is 1, the fifth matching result is 1 (high level).

[0078] The first input of the sixth OR gate (OR6) is connected to the output of the sixth fuse to receive the fuse's output value. The second input of the sixth OR gate (OR6) is connected to the second address line to receive the second reference value. The output of the sixth OR gate (OR6) is connected to the second input of the second NOR gate (NOR2) to output the sixth matching result. When the sixth fuse output value is 0, the sixth matching result is 0 (low level); when the sixth fuse output value is 1, the sixth matching result is 1 (high level).

[0079] The first input of the seventh OR gate (OR7) is connected to the output of the seventh fuse to receive its output value. The second input of the seventh OR gate (OR7) is connected to the third address line to receive the third reference value. The output of the seventh OR gate (OR7) is connected to the third input of the second NOR gate (NOR2) to output the seventh match result. When the output value of the seventh fuse is 0, the seventh match result is 0 (low level); when the output value of the seventh fuse is 1, the seventh match result is 1 (high level).

[0080] The first input of the eighth OR gate (OR8) is connected to the output of the eighth fuse to receive its output value. The second input of the eighth OR gate (OR8) is connected to the fourth address line to receive the fourth reference value. The output of the eighth OR gate (OR8) is connected to the fourth input of the second NOR gate (NOR2) to output the eighth matching result. When the output value of the eighth fuse is 0, the eighth matching result is 0 (low level); when the output value of the eighth fuse is 1, the eighth matching result is 1 (high level).

[0081] In other embodiments, the reference value is 1, the first level is a low level, the second level is a high level, the comparison unit 212 includes an AND gate, and the state determination unit 213 includes a NOR gate; or, the reference value is 0, the first level is a high level, the second level is a low level, the comparison unit 212 includes a NOR gate, and the state determination unit 213 includes an AND gate; or, the reference value is 1, the first level is a high level, the second level is a low level, the comparison unit 212 includes a NAND gate, and the state determination unit 213 includes an AND gate.

[0082] It should be noted that Figure 2 and Figure 3 only for exemplary display, the matching circuit 210 includes two logic circuits 211, and the logic circuit 211 includes four comparison units 212. In practical applications, the number of logic circuits 211 in the matching circuit 210 can also be three or more, specifically depending on the number of fuse groups 110, and the number of comparison units 212 in a single logic circuit 211 can also be two, three or more, specifically depending on the number of address lines 120.

[0083] In this way, the logic circuit 211 can receive multiple reference values and multiple fuse output values, match each reference value in the multiple reference values with the corresponding output value in the multiple fuse output values to obtain the matching results of each fuse, and determine the status indication signal of the corresponding fuse group 110 based on the matching results of each fuse.

[0084] Continue to refer to Figure 2 and Figure 3 , the conversion circuit 220 includes a plurality of cascaded conversion modules 221. The first input ends of the plurality of conversion modules 221 are respectively and correspondingly connected to the plurality of output ends of the matching circuit 210. The control ends of the plurality of conversion modules 221 are connected to the read signal, and the enable ends of the plurality of conversion modules 221 are connected to the clock signal.

[0085] The second input end of the subsequent conversion module 221_i+1 in two adjacent conversion modules 221 is connected to the output end of the previous conversion module 221_i. The second input end of the first-level conversion module 221_1 is connected to the low-level signal Vss, and the output end of the last-level conversion module 221_n is used to output the target indication signal. Wherein, 1≤i<n, n is the number of conversion modules 221 in the conversion circuit 220, and i is an integer.

[0086] The conversion module 221 includes a multiplexer (Mux), a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4), and a latch. The output of the matching circuit 210 is connected to the first input of the multiplexer (Mux) via the first inverter (INV1). The read signal is connected to the selector of the multiplexer (Mux) via the third inverter (INV3). The output of the multiplexer (Mux) is connected to the input of the latch. The clock signal is connected to the enable of the latch via the fourth inverter (INV4).

[0087] The second input of the multiplexer Mux in the first-stage conversion module 221_1 is connected to the low-level signal Vss. The output of the latch in the previous-stage conversion module 221_i is connected to the second input of the multiplexer Mux in the next-stage conversion module 221_i+1 through the second inverter INV2. The output of the latch in the last-stage conversion module 221_n is connected to the output of the conversion module 220.

[0088] For example, based on the above embodiments, the conversion circuit 220 includes two cascaded conversion modules 221, such as... Figure 3 As shown, these are the first-stage conversion module 221_1 and the second-stage conversion module 221_2, respectively. The output of the latch in the first-stage conversion module 221_1 is connected to the second input of the multiplexer in the second-stage conversion module 221_2 via the second inverter INV2. The output of the latch in the second-stage conversion module 221_2 is connected to the output of the conversion module 220.

[0089] The first output of the matching circuit 210 is connected to the first input of the multiplexer Mux in the first-stage conversion module 221_1 via the first inverter INV1 in the first-stage conversion module 221_1 to output a first state indication signal. The second output of the matching circuit 210 is connected to the first input of the multiplexer Mux in the second-stage conversion module 221_2 via the first inverter INV1 in the second-stage conversion module 221_2 to output a second state indication signal.

[0090] Figure 4 A timing diagram of a fuse detection circuit provided in an embodiment of this disclosure is shown below. Figure 4As shown, for the first-stage conversion module 221_1, when the read signal is valid (high level), the strobe signal of the multiplexer Mux is low level, and the output signal out of the multiplexer Mux is... <1> The signal received at the first input terminal is the output signal OUT. <1> This is the inverted signal of the first state indication signal. When the read signal is invalid (low level), the strobe signal of the multiplexer Mux is high, and the output signal of the multiplexer Mux is out. <1> The signal received at the second input terminal is the output signal OUT. <1> It is the inverted signal of the low-level signal Vss.

[0091] When the clock signal is valid (high level), the output of the latch follows the output of the multiplexer (Mux). If the read signal is valid (high level) at this time, the output signal of the latch is out'. <1> This is the inverted signal of the first state indication signal. If the read signal is invalid (low level), the output signal of the latch, 'out', will be... <1> It is the inverted signal of the low-level signal Vss.

[0092] When the clock signal is invalid (low level), the latch output retains the output before the clock signal toggled to low level. If the read signal before the clock signal toggled to low level is valid (high level), the latch output signal out' <1> This is the inverted signal of the first state indicator. If the read signal before the clock signal toggles to low is invalid (low level), the output signal of the latch, out', will be used. <1> The output signal is the inverted signal of the low-level signal Vss, i.e., the output signal out'. <1> It includes a first state indication signal.

[0093] The output signal of the latch is 'out' <1> The second input terminal of the second-stage conversion module 221_2 is provided. For the second-stage conversion module 221_2, when the read signal is valid (high level), the output signal out of the multiplexer Mux is... <2> This is the inverted signal of the second state indication signal. When the read signal is invalid (low level), the output signal of the multiplexer Mux is out. <2> For the output signal out' <1> The inverted signal, when the clock signal is valid (high level), the output of the latch synchronizes with the output of the multiplexer (Mux). When the clock signal is invalid (low level), the output of the latch remains the same as before the clock signal toggled low. Therefore, the output signal is out. <2> It includes a second state indication signal and an output signal 'out'. <1> That is, it includes the first state indication signal and the second state indication signal.

[0094] At this time, the signal output by the latch in the second-level conversion module 221_2 is the target status indication signal. The target status indication signal includes both the first status indication signal and the second status indication signal. The number of clock cycles corresponding to the time difference between the time when the target status indication signal flips to a valid signal and the time when the read signal flips to a valid signal can be used to indicate the available fuse group 110.

[0095] It should be noted that, Figure 2 and Figure 3 The example shown is of conversion circuit 220 including two cascaded conversion modules 221. In practical applications, the number of conversion modules 221 can be three or more, depending on the number of logic circuits 211.

[0096] Thus, when the read signal and the clock signal are valid, the conversion module 221 can output the signal received at the first input terminal. When the read signal is invalid and the clock signal is valid, the conversion module 221 can output the signal received at the second input terminal. When the clock signal is invalid, the conversion module 221 maintains the output before the clock signal flips to an invalid signal.

[0097] In some embodiments, address lines A<12:3> in the DRAM can be used as multiple address lines connected to the second input terminal of the matching circuit 210. If all address signals of address lines A<12:3> are 0, the matching circuit 210 receives ten parallel reference values, all of which are 0. The DRAM includes 16 fuse groups 110, and each fuse group 110 includes ten fuses.

[0098] In this embodiment of the present disclosure, the fuse detection circuit includes a matching circuit and a conversion circuit. The matching circuit can receive reference values ​​transmitted by multiple address lines and fuse group output values ​​output by multiple fuse groups. It matches the multiple reference values ​​with the multiple fuse output values ​​in each fuse group output value, and determines the status indication signal of each fuse group based on the multiple matching results of each fuse group. The conversion circuit can receive the multiple status indication signals output by the matching circuit at the same time, and convert the multiple parallel status indication signals into a serial target indication signal to indicate the available fuse groups among the multiple fuse groups, thereby detecting the available fuse groups.

[0099] This disclosure also provides a fuse detection method, which is applied to the fuse detection circuit 200 provided in any of the above embodiments.

[0100] Figure 5 This is a flowchart illustrating a fuse detection method provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the specific steps of the fuse testing method include:

[0101] S101 receives the reference values ​​transmitted by each of the multiple address lines, as well as the fuse group output values ​​output by each of the multiple fuse groups.

[0102] S102, matching multiple reference values ​​with multiple fuse output values ​​in each fuse group output value respectively.

[0103] For example, each of the plurality of reference values ​​is matched with the corresponding output value of the plurality of fuse output values ​​to obtain the matching result of each fuse. Specifically, when a reference value is equal to a fuse output value, the matching result of the corresponding fuse is determined to be a first level; when a reference value is not equal to a fuse output value, the matching result of the corresponding fuse is determined to be a second level.

[0104] S103, determine the status indication signal of each of the multiple fuse groups based on the multiple matching results of each of the multiple fuse groups.

[0105] For example, the status indication signal of the corresponding fuse group is determined based on the matching results of each of the multiple fuses. Specifically, when the matching results of each of the multiple fuses are all at the first level, the status indication signal of the corresponding fuse group is determined to be at the high level; when at least one of the matching results of the multiple fuses is at the second level, the status indication signal of the corresponding fuse group is determined to be at the low level.

[0106] S104 converts multiple parallel status indication signals into a single serial target indication signal to indicate the available fuse group among multiple fuse groups.

[0107] In this embodiment of the present disclosure, by receiving reference values ​​transmitted by multiple address lines and fuse group output values ​​output by multiple fuse groups, the multiple reference values ​​are matched with multiple fuse output values ​​in each fuse group output value. Based on the multiple matching results of the multiple fuse groups, the status indication signals of the multiple fuse groups are determined. The multiple parallel status indication signals are converted into a serial target indication signal to indicate the available fuse groups among the multiple fuse groups, thereby enabling the detection of available fuse groups.

[0108] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0109] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0110] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A fuse detection circuit, characterized by, The application relates to a matching circuit and a conversion circuit. A first input end of the matching circuit is connected with an output end of a fuse group, a second input end of the matching circuit is connected with an address line, and an output end of the matching circuit is connected with the conversion circuit. The matching circuit is configured to receive reference values transmitted by a plurality of address lines respectively and fuse group output values output by a plurality of fuse groups respectively. The plurality of reference values are matched with a plurality of fuse output values in each fuse group output value respectively, and a state indication signal of each fuse group is determined based on a plurality of matching results of the plurality of fuse groups respectively. The conversion circuit is configured to receive a plurality of state indication signals output by the matching circuit simultaneously, and convert the plurality of state indication signals in parallel into a serial target indication signal to indicate a usable fuse group in the plurality of fuse groups. The conversion circuit comprises a plurality of conversion modules connected in cascade, a first input end of the plurality of conversion modules is connected with a plurality of output ends of the matching circuit one by one, a control end of the plurality of conversion modules is connected with a read signal, and an enable end of the plurality of conversion modules is connected with a clock signal. A second input end of a next-stage conversion module in two adjacent conversion modules is connected with an output end of a previous-stage conversion module, a second input end of a first-stage conversion module is connected with a low-level signal, and an output end of a last-stage conversion module is used for outputting the target indication signal. The conversion module is configured to output a signal received by the first input end when the read signal and the clock signal are valid, output a signal received by the second input end when the read signal is invalid and the clock signal is valid, and keep the output before the clock signal is inverted into an invalid signal when the clock signal is invalid. The matching circuit comprises a plurality of logic circuits corresponding to the plurality of fuse groups one by one.

2. The fuse detection circuit of claim 1, wherein, A plurality of first input ends of each logic circuit are connected with output ends of a plurality of fuses in a fuse group one by one, a plurality of second input ends of each logic circuit are connected with the plurality of address lines one by one, and an output end of each logic circuit is connected with an input end of the conversion circuit. The logic circuit is configured to receive the plurality of reference values and the plurality of fuse output values, match each reference value in the plurality of reference values with a corresponding output value in the plurality of fuse output values, obtain a matching result of each fuse, and determine the state indication signal of the corresponding fuse group based on the matching result of each fuse. The logic circuit comprises a plurality of comparison units and a state determination unit, the plurality of comparison units correspond to the plurality of fuses one by one, and the number of comparison units in a single logic circuit is equal to the number of address lines.

3. The fuse detection circuit of claim 2, wherein, A first input end of each comparison unit is connected with an output end of a fuse, a second input end of each comparison unit is connected with an address line, an output end of each comparison unit is connected with an input end of the state determination unit, and an output end of the state determination unit is connected with an input end of the conversion circuit. ​ The comparison unit is configured to receive one reference value and one fuse output value, and determine that the matching result of the corresponding fuse is a first level when the one reference value is equal to the one fuse output value, and determine that the matching result of the corresponding fuse is a second level when the one reference value is not equal to the one fuse output value; The state determination unit is configured to determine that the state indication signal of the corresponding fuse group is a high level when the matching result of each of the plurality of fuses is the first level, and determine that the state indication signal of the corresponding fuse group is a low level when there is at least one second level in the matching result of each of the plurality of fuses.

4. The fuse detection circuit of claim 3, wherein, The reference value is 0, the first level is the low level, the second level is the high level, the comparison unit includes an OR gate, and the state determination unit includes an NOR gate; A first input end of the OR gate is connected to an output end of a fuse, a second input end of the OR gate is connected to the address line, an output end of the OR gate is connected to an input end of the NOR gate, and an output end of the NOR gate is connected to one input end of the conversion circuit.

5. The fuse detection circuit of claim 1, wherein, The conversion module includes a multiplexer, a first inverter, a second inverter, a third inverter, a fourth inverter, and a latch; An output end of the matching circuit is connected to a first input end of the multiplexer through the first inverter, a read signal is connected to a gating end of the multiplexer through the third inverter, an output end of the multiplexer is connected to an input end of the latch, and a clock signal is connected to an enable end of the latch through the fourth inverter; a second input end of the multiplexer in the first-stage conversion module is connected to the low-level signal, an output end of the latch in the previous-stage conversion module is connected to a second input end of the multiplexer in the next-stage conversion module through the second inverter, and an output end of the latch in the last-stage conversion module is connected to an output end of the conversion module.

6. A method of detecting a fuse, characterized by, The method is applied to the fuse detection circuit of any one of claims 1-5, and the method comprises: receiving reference values transmitted by a plurality of address lines respectively and fuse group output values output by a plurality of fuse groups respectively; matching the plurality of reference values with a plurality of fuse output values in each fuse group output value respectively; determining state indication signals of the plurality of fuse groups based on a plurality of matching results of the plurality of fuse groups respectively; converting a plurality of state indication signals in parallel into a serial target indication signal to indicate available fuse groups in the plurality of fuse groups.

7. The fuse detection method of claim 6, wherein, One fuse group includes a plurality of fuses; The matching the plurality of reference values with the plurality of fuse output values in each fuse group output value respectively comprises: matching each reference value in the plurality of reference values with a corresponding output value in the plurality of fuse output values to obtain a matching result of each of the plurality of fuses; The determining the state indication signals of the plurality of fuse groups based on the plurality of matching results of the plurality of fuse groups respectively comprises: The state indication signal of a corresponding fuse group is determined based on the matching result of each of the plurality of fuses.

8. The fuse detection method of claim 7, wherein, The matching of each of the plurality of reference values with a corresponding output value in the plurality of fuse output values to obtain the matching result of each of the plurality of fuses comprises: When one reference value is equal to one fuse output value, the matching result of the corresponding fuse is determined as a first level; When the one reference value is not equal to the one fuse output value, the matching result of the corresponding fuse is determined as a second level; The determination of the state indication signal of the corresponding fuse group based on the matching result of each of the plurality of fuses comprises: When the matching result of each of the plurality of fuses is the first level, the state indication signal of the corresponding fuse group is determined as a high level; When there is at least one second level in the matching result of each of the plurality of fuses, the state indication signal of the corresponding fuse group is determined as a low level.

9. A semiconductor memory, characterized by comprising: A fuse detection circuit according to any one of claims 1-5, a fuse group, an address line.

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