Radiation-proof SRAM (Static Random Access Memory) unit and integrated circuit board

Abstract

The invention relates to the technical field of integrated circuit design, discloses an anti-radiation SRAM (Static Random Access Memory) storage unit and an integrated circuit board, and aims to solve the problems that the SRAM storage unit in the prior art has many sensitive nodes and cannot realize multi-node overturning self-recovery. When any one main storage node is at a low level, due to the characteristics of the NMOS tube, the main storage node cannot become a sensitive node when the node is bombarded by radiation particles. And the other main storage node is matched with the pull-down tube through the logic retainer and is recovered to the original state through the action of the pull-up tube after single event upset. The width-to-length ratios of the pull-down tubes in the two groups of cross-coupled inverters are greater than those of the pull-up tubes, and when a single event upset event occurs in the redundant storage node, the logic of the main storage node corresponding to the redundant storage node can be kept unchanged through the setting that the width-to-length ratios of the pull-down tubes are greater than those of the pull-up tubes, so that the upset self-recovery of multiple nodes is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, in particular to an SRAM memory cell. BACKGROUND

[0002] Modern civil aircraft flight control, avionics and other systems are highly complex, and a large number of complex electronic devices based on static random access memory (SRAM) are used, such as microprocessors, field programmable gate arrays (FPGA) and the like. With the continuous reduction of integrated circuit process size, especially at 28nm and below, the feature size of the SRAM cell is reduced and the operating voltage is lowered, making it more sensitive to single event effects caused by high-energy particles (such as cosmic rays, alpha particles, etc.), and single event upset (SEU) is extremely likely to occur. Single event upset (SEU) is a phenomenon in which a single high-energy particle in space strikes the sensitive area of a semiconductor device, causing the logic state of the device to flip. In aerospace, military and other high-reliability application scenarios, soft errors caused by single event upset may even cause system crashes, so key circuits must be hardened.

[0003] In the current technology, the anti-radiation capability of the memory cell is usually improved by increasing a plurality of redundant storage nodes. This method achieves a certain degree of single-node flip recovery, but the structure contains a plurality of sensitive nodes, and when subjected to multiple high-energy particle strikes at the same time, multiple-node flips may occur, exceeding the fault tolerance range and failing to achieve self-recovery.

[0004] Therefore, how to harden the storage nodes in the SRAM memory cell to achieve flip recovery after single-node or even multiple-node SEU and improve the anti-radiation capability of the memory cell is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] The purpose of the present application is to solve the problem of multiple sensitive nodes in the SRAM memory cell in the current technology and the inability to achieve multiple-node flip recovery. Therefore, the present application provides an anti-radiation SRAM memory cell and an integrated circuit board to harden the storage nodes in the SRAM memory cell, achieve flip recovery after single-node or even multiple-node SEU, and improve the anti-radiation capability of the memory cell.

[0006] To solve the above technical problems, the present application provides an anti-radiation SRAM memory cell, comprising: a first cross-coupled inverter, a second cross-coupled inverter, a logic keeper and a transmitter.

[0007] The first cross-coupled inverter comprises four PMOS tubes, two pull-up tubes and two pull-down tubes; the second cross-coupled inverter comprises four NMOS tubes, two pull-up tubes and two pull-down tubes; the width-length ratio of the conductive channel of the pull-down tube is greater than the width-length ratio of the conductive channel of the pull-up tube;

[0008] The gates and the drains of the two pull-up tubes in the first cross-coupled inverter are cross-coupled to form a first storage node and a second storage node;

[0009] The gates and the drains of the two pull-down tubes in the second cross-coupled inverter are cross-coupled to form a third storage node and a fourth storage node;

[0010] The pull-up tubes in the second cross-coupled inverter are connected to the first storage node and the second storage node in the first cross-coupled inverter, respectively;

[0011] The logic keeper comprises two NMOS tubes, which are connected to the two pull-down tubes in the first cross-coupled inverter and are connected to the third storage node and the fourth storage node in the second cross-coupled inverter, for keeping the logic of the first storage node and the third storage node consistent and the logic of the second storage node and the fourth storage node consistent;

[0012] The transmitter comprises two NMOS tubes, which are used to connect the second cross-coupled inverter to the connection line of the word line and the bit line.

[0013] Preferably, the pull-up tubes in the first cross-coupled inverter are the first PMOS tube P1 and the second PMOS tube P2, and the pull-down tubes are the third PMOS tube P3 and the fourth PMOS tube P4;

[0014] The pull-up tubes in the second cross-coupled inverter are the first NMOS tube N1 and the second NMOS tube N2, and the pull-down tubes are the third NMOS tube N3 and the fourth NMOS tube N4;

[0015] The two NMOS tubes of the logic keeper are the fifth NMOS tube N5 and the sixth NMOS tube N6;

[0016] The two NMOS tubes of the transmitter are the seventh NMOS tube N7 and the eighth NMOS tube N8;

[0017] The drain of the first PMOS tube P1 is connected to the first storage node, the gate is connected to the second storage node, the source is connected to the power supply, and the substrate is connected to the power supply;

[0018] The drain of the second PMOS tube P2 is connected to the second storage node, the gate is connected to the first storage node, the source is connected to the power supply, and the substrate is connected to the power supply;

[0019] the drain of the third PMOS transistor P3 is connected to ground, the gate is connected to the source of the fifth NMOS transistor N5, the source is connected to the first storage node, and the substrate is connected to ground;

[0020] the drain of the fourth PMOS transistor P4 is connected to ground, the gate is connected to the source of the sixth NMOS transistor N6, the source is connected to the second storage node, and the substrate is connected to ground;

[0021] the drain of the first NMOS transistor N1 is connected to a power supply, the gate is connected to the first storage node, the source is connected to the third storage node, and the substrate is connected to the power supply;

[0022] the drain of the second NMOS transistor N2 is connected to the power supply, the gate is connected to the second storage node, the source is connected to the fourth storage node, and the substrate is connected to the power supply;

[0023] the drain of the third NMOS transistor N3 is connected to the third storage node, the gate is connected to the fourth storage node, the source is connected to ground, and the substrate is connected to ground;

[0024] the drain of the fourth NMOS transistor N4 is connected to the fourth storage node, the gate is connected to the third storage node, the source is connected to ground, and the substrate is connected to ground;

[0025] the drain of the fifth NMOS transistor N5 is connected to the third storage node, the gate is connected to the fourth storage node, and the substrate is connected to the gate of the third PMOS transistor P3;

[0026] the drain of the sixth NMOS transistor N6 is connected to the fourth storage node, the gate is connected to the third storage node, and the substrate is connected to the gate of the fourth PMOS transistor P4;

[0027] the drain of the seventh NMOS transistor N7 is connected to the third storage node, the gate is connected to a word line WL, the source is connected to a bit line BL, and the substrate is connected to the bit line BL;

[0028] the drain of the eighth NMOS transistor N8 is connected to a complementary bit line BLB, the gate is connected to the word line WL, the source is connected to the fourth storage node, and the substrate is connected to the complementary bit line BLB.

[0029] Preferably, the width-length ratios of the conductive channels of the first PMOS transistor P1 and the second PMOS transistor P2 are the same, and the width-length ratios of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 are the same;

[0030] the width-length ratios of the conductive channels of the first NMOS transistor N1 and the second NMOS transistor N2 are the same, and the width-length ratios of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 are the same.

[0031] Preferably, each pull-up tube is a single fin fin field effect transistor.

[0032] Preferably, the width-length ratio of the conductive channel of the third PMOS tube P3 and the fourth PMOS tube P4 is 2 times of the first PMOS tube P1 and the second PMOS tube P2.

[0033] The width-length ratio of the conductive channel of the third NMOS tube N3 and the fourth NMOS tube N4 is 2 times of the first NMOS tube N1 and the second NMOS tube N2.

[0034] The width-length ratio of the conductive channel of the seventh NMOS tube N7 and the eighth NMOS tube N8 is 2 times of the third NMOS tube N3 and the fourth NMOS tube N4.

[0035] Preferably, when performing a read operation, the bit line BL and the complementary bit line BLB are both pre-charged to high level, when the word line WL is high, a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, and the storage unit outputs the stored logic data.

[0036] Preferably, when performing a write operation, the bit line BL is pre-set to high level, and the complementary bit line BLB is pre-set to low level, when the word line WL is high, the first storage node and the third storage node are written to high level, and the second storage node and the fourth storage node are written to low level.

[0037] Preferably, when performing a write operation, the bit line BL is pre-set to low level, and the complementary bit line BLB is pre-set to high level, when the word line WL is high, the first storage node and the third storage node are written to low level, and the second storage node and the fourth storage node are written to high level.

[0038] Preferably, the bit line BL and the complementary bit line BLB are both pre-charged to high level, and when the word line WL is low, the storage unit maintains the initial state.

[0039] In order to solve the above technical problems, the application further provides an integrated circuit board comprising the above anti-radiation SRAM storage unit, and further comprising a differential amplifier, two input ends of the differential amplifier are connected with the bit line BL and BLB respectively, and the differential amplifier is used for reading the differential signal between the bit line BL and BLB.

[0040] The application provides an anti-radiation SRAM memory unit, relative to the problem that a plurality of sensitive nodes of the SRAM memory unit in the prior art cannot realize multi-node flip recovery, two groups of cross-coupled inverters are used to form a main storage node, a third storage node and a fourth storage node, and corresponding redundant storage nodes, a first storage node and a second storage node.

[0041] The integrated circuit board provided by the application has the beneficial effects corresponding to the anti-radiation SRAM memory unit, and thus the beneficial effects are not described here. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0043] Figure 1 A circuit diagram of the anti-radiation SRAM memory unit provided by the embodiments of the application;

[0044] Figure 2 A read-write operation simulation waveform diagram of the anti-radiation SRAM memory unit provided by the embodiments of the application;

[0045] Figure 3 A single-particle incidence simulation waveform diagram of the anti-radiation SRAM memory unit provided by the embodiments of the application;

[0046] Figure 4 Another single-particle incidence simulation waveform diagram of the anti-radiation SRAM memory unit provided by the embodiments of the application;

[0047] The signs in the drawings are as follows: a first storage node S0, a second storage node S1, a third storage node Q, and a fourth storage node QN. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0049] The core of the present application is to provide an anti-radiation SRAM memory cell and an integrated circuit board, which are used to reinforce the storage node in the SRAM memory cell, realize the flip self-recovery after the SEU of a single node or multiple nodes, and improve the anti-radiation capability of the memory cell.

[0050] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0051] Figure 1 A circuit diagram of an anti-radiation SRAM memory cell provided by the present application is shown in FIG. 1, which includes a first cross-coupled inverter, a second cross-coupled inverter, a logic keeper and a transmitter. Figure 1 The first cross-coupled inverter includes four PMOS tubes, which are two pull-up tubes and two pull-down tubes; the second cross-coupled inverter includes four NMOS tubes, which are two pull-up tubes and two pull-down tubes; the width-length ratio of the conductive channel of the pull-down tube is greater than that of the pull-up tube.

[0052] The gates and drains of the two pull-up tubes in the first cross-coupled inverter are cross-coupled to form a first storage node S0 and a second storage node S1.

[0053] The gates and drains of the two pull-down tubes in the second cross-coupled inverter are cross-coupled to form a third storage node Q and a fourth storage node QN.

[0054] The gates and drains of the two pull-down tubes in the second cross-coupled inverter are cross-coupled to form a third storage node Q and a fourth storage node QN.

[0055] The pull-up tubes in the second cross-coupled inverter are connected with the first storage node S0 and the second storage node S1 in the first cross-coupled inverter, respectively.

[0056] The logic keeper includes two NMOS tubes, which are connected with the two pull-down tubes in the first cross-coupled inverter and are connected with the third storage node Q and the fourth storage node QN in the second cross-coupled inverter, so as to keep the logic of the first storage node S0 and the third storage node Q consistent and the logic of the second storage node S1 and the fourth storage node QN consistent.

[0057] The transmitter includes two NMOS transistors for connecting the second cross-coupled inverter with the connection lines of the word line and the bit line.

[0058] The anti-radiation SRAM memory cell provided in the application is based on the extension of the conventional 6T SRAM structure, and the memory cell is designed by using a double-layer cross-coupled structure. The circuit is composed of 12 transistors, including 4 PMOS transistors and 8 NMOS transistors. From the structure, the memory cell can be divided into two symmetrical parts: the upper part is composed of two pull-up PMOS transistors and two pull-down PMOS transistors to form a first cross-coupled inverter, forming two complementary storage nodes of a first storage node S0 and a second storage node S1; the lower part is composed of two pull-up NMOS transistors and two pull-down NMOS transistors to form a second cross-coupled structure, forming two complementary storage nodes of a third storage node Q and a fourth storage node QN. The two groups of cross-coupled inverters are connected through a logic keeper, so that the logic of the first storage node S0 and the third storage node Q is kept consistent, and the logic of the second storage node S1 and the fourth storage node QN is kept consistent. The pull-up transistor in the second cross-coupled inverter is connected with the first storage node S0 and the second storage node S1 in the first cross-coupled inverter, respectively, and the circuit can realize the flip recovery of the storage node when the single event upset occurs. The width-length ratio of the conductive channel of the pull-down transistor in the two groups of cross-coupled inverters is greater than that of the pull-up transistor, so that the storage node is not easy to be changed by the change of the on-off state of the transistor connected to the node, and the anti-radiation capability is improved. The transmitter is two NMOS transistors for connecting the second cross-coupled inverter with the connection lines of the word line and the bit line, realizing the read-write function.

[0059] The embodiment provides a specific circuit connection mode, specifically, the pull-up tube in the first cross-coupled inverter is a first PMOS tube P1 and a second PMOS tube P2, and the pull-down tube is a third PMOS tube P3 and a fourth PMOS tube P4; the pull-up tube in the second cross-coupled inverter is a first NMOS tube N1 and a second NMOS tube N2, and the pull-down tube is a third NMOS tube N3 and a fourth NMOS tube N4; the two NMOS tubes of the logic keeper are a fifth NMOS tube N5 and a sixth NMOS tube N6; and the two NMOS tubes of the transmitter are a seventh NMOS tube N7 and an eighth NMOS tube N8. Wherein, the drain of the tube P1 is connected with a first storage node S0, the gate is connected with a second storage node S1, the source is connected with a power supply VDD, and the substrate is connected with the power supply VDD; the drain of the second PMOS tube P2 is connected with the second storage node S1, the gate is connected with the first storage node S0, the source is connected with the power supply VDD, and the substrate is connected with the power supply VDD; the drain of the third PMOS tube P3 is connected with the ground, the gate is connected with the source of the fifth NMOS tube N5, the source is connected with the first storage node S0, and the substrate is connected with the ground; the drain of the fourth PMOS tube P4 is connected with the ground, the gate is connected with the source of the sixth NMOS tube N6, the source is connected with the second storage node S1, and the substrate is connected with the ground; the drain of the first NMOS tube N1 is connected with the power supply VDD, the gate is connected with the first storage node S0, the source is connected with a third storage node Q, and the substrate is connected with the power supply VDD; the drain of the second NMOS tube N2 is connected with the power supply VDD, the gate is connected with the second storage node S1, the source is connected with a fourth storage node QN, and the substrate is connected with the power supply VDD; the drain of the third NMOS tube N3 is connected with the third storage node Q, the gate is connected with the fourth storage node QN, the source is connected with the ground, and the substrate is connected with the ground; the drain of the fourth NMOS tube N4 is connected with the fourth storage node QN, the gate is connected with the third storage node Q, the source is connected with the ground, and the substrate is connected with the ground; the drain of the fifth NMOS tube N5 is connected with the third storage node Q, the gate is connected with the fourth storage node QN, and the substrate is connected with the gate of the third PMOS tube P3; the drain of the sixth NMOS tube N6 is connected with the fourth storage node QN, the gate is connected with the third storage node Q, and the substrate is connected with the gate of the fourth PMOS tube P4; the drain of the seventh NMOS tube N7 is connected with the third storage node Q, the gate is connected with a word line WL, the source is connected with a bit line BL, and the substrate is connected with the bit line BL; the drain of the eighth NMOS tube N8 is connected with a complementary bit line BLB, the gate is connected with the word line WL, the source is connected with the fourth storage node QN, and the substrate is connected with the complementary bit line BLB.

[0060] Based on the above structure, the working principle of the storage unit is as follows: in the holding stage, the bit line BL and the complementary bit line BLB are both pre-charged to high level, and the storage unit remains in the initial state and does not work when the word line WL is low. When performing a read operation, the bit line BL and the complementary bit line BLB are both pre-charged to high level, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on when the word line WL is high. If the logic data stored in the storage unit is "0", S0=Q=0 and S1=QN=1, the bit line BL is discharged to ground through the seventh NMOS transistor N7 and the third NMOS transistor N3, and a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, which can be read by a differential amplifier outside the storage unit. Similarly, if the logic data stored in the storage unit is "1", S0=Q=1 and S1=QN=0, the complementary bit line BLB is discharged to ground through the eighth NMOS transistor N8 and the fourth NMOS transistor N4, and a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, which can be read by a differential amplifier outside the storage unit.

[0061] When performing a write operation, when performing a write "0" operation, the bit line BL is pre-set to low level and the complementary bit line BLB is pre-set to high level, and the first storage node S0 and the third storage node Q are written to low level and the second storage node S1 and the fourth storage node QN are written to high level when the word line WL is high. When performing a write "1" operation, the bit line BL is pre-set to high level and the complementary bit line BLB is pre-set to low level, and the first storage node S0 and the third storage node Q are written to high level and the second storage node S1 and the fourth storage node QN are written to low level when the word line WL is high.

[0062] In specific implementation, in order to facilitate the production of the storage unit, the width-length ratio of the conductive channel of the first PMOS transistor P1 and the second PMOS transistor P2 is the same, and the width-length ratio of the conductive channel of the third PMOS transistor P3 and the fourth PMOS transistor P4 is the same; the width-length ratio of the conductive channel of the first NMOS transistor N1 and the second NMOS transistor N2 is the same, and the width-length ratio of the conductive channel of the third NMOS transistor N3 and the fourth NMOS transistor N4 is the same.

[0063] In order to enhance the anti-radiation capability of the anti-radiation SRAM memory cell, each pull-up tube can adopt a single fin fin field effect transistor. When the conductive channel width-length ratio of the pull-down tube is greater than that of the pull-up tube, the width-length ratio of the conductive channel of the third PMOS tube P3 and the fourth PMOS tube P4 is twice that of the first PMOS tube P1 and the second PMOS tube P2; the width-length ratio of the conductive channel of the third NMOS tube N3 and the fourth NMOS tube N4 is twice that of the first NMOS tube N1 and the second NMOS tube N2. And for the transmitter, the width-length ratio of the conductive channel of the seventh NMOS tube N7 and the eighth NMOS tube N8 is twice that of the third NMOS tube N3 and the fourth NMOS tube N4.

[0064] The anti-radiation SRAM memory cell provided by the application can solve the problems of multiple sensitive nodes and the inability to realize multi-node flip self-recovery of the SRAM memory cell in the prior art. The application forms the main storage nodes, the third storage node Q and the fourth storage node QN, and the corresponding redundant storage nodes, the first storage node S0 and the second storage node S1, by two groups of cross-coupled inverters. The application forms a polarity reinforcement device by four NMOS tubes to reinforce the main storage nodes. When any one of the main storage nodes is at a low level, the NMOS tube will not become a sensitive node due to its characteristics when it is bombarded by radiation particles, thereby improving the anti-radiation capability of the node. Another main storage node is restored to the original state by the cooperation of the logic keeper and the pull-down tube after a single event upset occurs. When a single event upset occurs in the redundant storage node, the logic of the corresponding main storage node of the redundant storage node is kept unchanged by setting the conductive channel width-length ratio of the pull-down tube to be greater than that of the pull-up tube, thereby realizing the flip self-recovery of the redundant storage node. The conductive channel width-length ratio of the pull-down tube in the two groups of cross-coupled inverters is greater than that of the pull-up tube, which can realize the flip self-recovery of multiple nodes and improve the multi-node anti-radiation capability of the memory cell.

[0065] In order to verify the correctness of the anti-radiation SRAM memory cell provided by the application, timing analysis of read-write operation is performed on the Hspice simulation platform, Figure 2 The read-write operation simulation waveform diagram of the anti-radiation SRAM memory cell provided by the embodiment of the application is as follows, Figure 2As shown, when performing a data write operation, the bit line is first pre-set: the bit line BL is pre-set to a high level, and the complementary bit line BLB is pre-set to a low level. When the simulation time reaches 50 ns, the word line WL signal is pulled high, triggering the write process of the storage unit, realizing data conversion from logic "0" to logic "1". At this time, the internal state of the storage unit is: the third storage node Q outputs a high level, the fourth storage node QN outputs a low level, and the redundant storage nodes, the first storage node S0 and the second storage node S1, remain in high and low level states, respectively. After the word line WL signal returns to a low level, the storage unit is electrically isolated from the external bit line system, ensuring the stable retention of internal data. In the verification process of the data read operation, the bit line BL is pre-charged to a high level before reading, and the complementary bit line BLB is pre-charged to a high level. At 80 ns, the read timing is started by pulling up the word line WL signal, at which time a differential voltage signal is generated between the bit lines BL and BLB. After the differential signal is processed by the differential amplifier in the peripheral readout circuit, the stored logic "1" data is successfully output. Using the same verification method, the storage unit successfully completes the write operation of logic "0" at 110 ns, and completes the read verification of logic "0" at 160 ns. The entire simulation process fully demonstrates the working timing characteristics of the anti-radiation SRAM storage unit provided by the present application, and fully proves the reliability and correctness of the present application in the three core functions of data storage, reading and writing.

[0066] In order to verify the ability of the anti-radiation SRAM storage unit provided by the present application in the face of SEU events, the SEU of each storage node in the storage unit is analyzed and verified by simulation, and the specific circumstances include:

[0067] I. When Q=S0=1, QN=S1=0, the behavior of single event upset of the storage nodes Q, QN, S0 and S1 after being hit by a single particle is analyzed:

[0068] 1) When the fourth storage node QN is hit by a radiation particle, only one "0->0" transient pulse can be generated at the node QN, and this will not change the logic value of the node QN, so the node QN is not a sensitive node at this time.

[0069] 2) When the third storage node Q occurs SEU, Q changes from logic "1" to logic "0", at this time the sixth NMOS tube N6 and the fourth NMOS tube N4 will be temporarily closed, but QN will not change, and Q will recover to 1 through the first NMOS tube N1.

[0070] 3) When SEU occurs in the first storage node S0, S0 changes from logic "1" to logic "0", which makes the first NMOS transistor N1 temporarily close and the second PMOS transistor P2 open. At this time, P2 and P4 are open at the same time, but the width-length ratio of the conductive channel of P4 is greater than that of P2. The potential of S1 node does not change, and the temporary closing of N1 does not change the potential of Q node. The value of Q node remains "1" unchanged. Since S1 node remains "0" unchanged, S0 is finally restored by the turned-on P1.

[0071] 4) When SEU occurs in the second storage node S1, S1 changes from logic "0" to logic "1", which makes N2 open and P1 close. At this time, N2 and N4 are turned on, and since the width-length ratio of the conductive channel of N4 is greater than that of N2, the logic value of QN does not change. Since P4 is turned on and P2 is cut off, the potential of S1 is restored to 0.

[0072] 5) When SEU occurs in S0 and S1 at the same time, since the width-length ratio of the conductive channel of the pull-down transistor is greater than that of the pull-up transistor, the QN node does not change. Finally, S0 and S1 nodes are restored to normal potential through P4.

[0073] Figure 3 A simulation waveform diagram of the anti-radiation SRAM storage unit provided by the embodiment of the present application is shown in Figure 3 The anti-radiation SRAM storage unit has three sensitive nodes for different storage conditions. The current injection method is used to simulate the response of the sensitive nodes to high-energy particles. The node recovery simulation result is shown in Figure 3 Specifically, the simulation process first sets the anti-radiation SRAM storage unit to complete the write "1", read "1", write "0" and read "0" process. The current source is selected to inject the sensitive node. Under the condition of LET=0.8PC / um, the storage unit circuit is affected. As shown in Figure 3As shown, the anti-radiation SRAM memory unit completes the data write "1" operation at 50 ns, and then, at 60 ns, a single particle pulse is injected to the sensitive node S1 to simulate the single particle bombardment response of the node to high energy particles, and the process of the voltage of the node S1 rapidly rising above the high level and then recovering to the original low level, indicating that the node S1 has complete self-recovery capability under the bombardment of this energy. At the same time, the simulation results also show that the bombardment of the node S1 does not cause the other three nodes to flip. Similarly, at 120 ns and 150 ns, pulse injection is performed on the nodes QN and S0 respectively, and the memory unit also exhibits good self-recovery performance and can recover to the original logic state. The anti-radiation SRAM memory unit completes the data write "0" operation at 110 ns, and the storage state of the internal nodes of the memory unit can still normally flip. In summary, the simulation results show that, in the case where Q is at a low potential, the sensitive nodes QN, S0 and S1 can recover to the original logic level from the flip, and the recovery process is consistent with the analysis of the behavior of the single event upset of the storage nodes, so the anti-radiation SRAM memory unit has the flip self-recovery capability of the sensitive nodes QN, S0 and S1.

[0074] II. When Q=S0=0, QN=S1=1, the behavior of the single event upset of the storage nodes Q, QN, S0 and S1 after being bombarded by a single particle is analyzed.

[0075] 1) When the third storage node Q is bombarded by a radiation particle, only one "0->0" transient pulse can be generated at Q, which does not change the logic value of the node Q, so the node Q is not a sensitive node.

[0076] 2) When the node QN has an SEU, the node QN changes from logic "1" to logic "0", at this time N3 and N5 will be temporarily closed, but Q will not change and will recover to 1 through N2.

[0077] 3) When the node S0 has an SEU, the node S0 changes from logic "0" to logic "1", which makes N1 open and P2 close. At this time, N1 and N3 are conductive, and since the width-to-length ratio of the conductive channel of N3 is greater than that of N1, the logic value of the node Q does not change; and since P3 is conductive and P1 is cut off, the S0 potential recovers to 0.

[0078] 4) When the node S1 has an SEU, S1 changes from logic "1" to logic "0", which will temporarily close N2 and open P1, at this time P1 and P3 are both open, but the width-to-length ratio of the conductive channel of P3 is greater than that of P1, the S0 node potential does not change, and the temporary closing of N2 does not change the potential of QN, the value of QN node remains "1" unchanged, and the node S0 remains "0" unchanged, finally S1 is recovered by the conductive transistor P2.

[0079] 5) When SEU occurs in nodes S0 and S1 simultaneously, since the width-length ratio of the conduction channel of the pull-down tube is greater than that of the pull-up tube, the node Q will not change, and finally S0 and S1 nodes are restored to normal potential through P3.

[0080] Figure 4 Another anti-radiation SRAM storage unit provided by the embodiment of the present application has a single particle incidence simulation waveform diagram, which is similar to Figure 3 In the case that the initial potential of the node Q and S0 is high level and the logic state of the node QN and S1 is low level, the anti-radiation SRAM storage unit can also ensure the sensitive nodes Q, S0 and S1 have the flip-flop self-recovery ability while ensuring normal read and write operations, and the recovery process is completely consistent with the behavior analysis of the single particle flip-flop of the storage node.

[0081] As can be seen from the above, the anti-radiation SRAM storage unit provided by the present application shows high symmetry and consistency in two complementary storage states. Whether storing "0" or "1", the storage unit can ensure the sensitive node has a fast flip-flop self-recovery ability while ensuring normal read and write operations, and the recovery process and analysis results are completely consistent. The symmetrical anti-radiation performance design eliminates the dependence of the storage state, ensures reliable SEU protection in any data mode, and further confirms the effectiveness and robustness of the anti-radiation SRAM storage unit.

[0082] Finally, the present application also provides an integrated circuit board, which includes the anti-radiation SRAM storage unit mentioned in the above embodiment, and also includes a differential amplifier, two input ends of the differential amplifier are connected to the bit line BL and BLB respectively, for reading the differential signal between the bit lines BL and BLB.

[0083] In specific implementation, the integrated circuit board can be an FPGA, a processor or a storage controller, and the like, which has high reliability requirements, and the effect is similar to the above-mentioned embodiments, which will not be described here.

[0084] The anti-radiation SRAM storage unit and the integrated circuit board provided by the present application are described in detail above. The embodiments in the specification are described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other. It should be pointed out that, for those skilled in the art, without departing from the principle of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A radiation-resistant SRAM memory cell, characterized in that, include: First cross-coupled inverter, second cross-coupled inverter, logic hold, and transmitter; The first cross-coupled inverter includes four PMOS transistors, namely two pull-up transistors and two pull-down transistors; the second cross-coupled inverter includes four NMOS transistors, namely two pull-up transistors and two pull-down transistors; the aspect ratio of the conductive channel of each pull-down transistor is greater than the aspect ratio of the conductive channel of each pull-up transistor. In the first cross-coupled inverter, the gates and drains of the two pull-up transistors are cross-coupled to form the first memory node and the second memory node. In the second cross-coupled inverter, the gates and drains of the two pull-down transistors are cross-coupled to form the third and fourth memory nodes; The pull-up transistors in the second cross-coupled inverter are connected to the first storage node and the second storage node in the first cross-coupled inverter, respectively. The logic hold includes two NMOS transistors, which are respectively connected to two pull-down transistors in the first cross-coupled inverter, and are also connected to the third and fourth memory nodes in the second cross-coupled inverter, in order to maintain the logic consistency between the first memory node and the third memory node, and the logic consistency between the second memory node and the fourth memory node. The transmitter includes two NMOS transistors for connecting the second cross-coupled inverter to the word line and bit line connection lines.

2. The radiation-resistant SRAM memory cell according to claim 1, characterized in that, The pull-up transistors in the first cross-coupled inverter are the first PMOS transistor P1 and the second PMOS transistor P2, and the pull-down transistors are the third PMOS transistor P3 and the fourth PMOS transistor P4. The pull-up transistors in the second cross-coupled inverter are the first NMOS transistor N1 and the second NMOS transistor N2, and the pull-down transistors are the third NMOS transistor N3 and the fourth NMOS transistor N4; The two NMOS transistors of the logic hold are the fifth NMOS transistor N5 and the sixth NMOS transistor N6; The two NMOS transistors of the transmitter are the seventh NMOS transistor N7 and the eighth NMOS transistor N8; The drain of the first PMOS transistor P1 is connected to the first memory node, the gate is connected to the second memory node, the source is connected to the power supply, and the substrate is connected to the power supply. The drain of the second PMOS transistor P2 is connected to the second memory node, the gate is connected to the first memory node, the source is connected to the power supply, and the substrate is connected to the power supply. The drain of the third PMOS transistor P3 is grounded, the gate is connected to the source of the fifth NMOS transistor N5, the source is connected to the first memory node, and the substrate is grounded. The drain of the fourth PMOS transistor P4 is grounded, its gate is connected to the source of the sixth NMOS transistor N6, the source is connected to the second memory node, and the substrate is grounded. The drain of the first NMOS transistor N1 is connected to the power supply, the gate is connected to the first memory node, the source is connected to the third memory node, and the substrate is connected to the power supply. The drain of the second NMOS transistor N2 is connected to the power supply, the gate is connected to the second memory node, the source is connected to the fourth memory node, and the substrate is connected to the power supply. The drain of the third NMOS transistor N3 is connected to the third memory node, the gate is connected to the fourth memory node, the source is grounded, and the substrate is grounded. The drain of the fourth NMOS transistor N4 is connected to the fourth memory node, the gate is connected to the third memory node, the source is grounded, and the substrate is grounded. The drain of the fifth NMOS transistor N5 is connected to the third memory node, the gate is connected to the fourth memory node, and the substrate is connected to the gate of the third PMOS transistor P3. The drain of the sixth NMOS transistor N6 is connected to the fourth memory node, the gate is connected to the third memory node, and the substrate is connected to the gate of the fourth PMOS transistor P4. The drain of the seventh NMOS transistor N7 is connected to the third memory node, the gate is connected to the word line WL, the source is connected to the bit line BL, and the substrate is connected to the bit line BL. The drain of the eighth NMOS transistor N8 is connected to the complementary bit line BLB, the gate is connected to the word line WL, the source is connected to the fourth memory node, and the substrate is connected to the complementary bit line BLB.

3. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, The first PMOS transistor P1 and the second PMOS transistor P2 have the same width-to-length ratio of their conductive channels, and the third PMOS transistor P3 and the fourth PMOS transistor P4 have the same width-to-length ratio of their conductive channels. The first NMOS transistor N1 and the second NMOS transistor N2 have the same width-to-length ratio of their conductive channels, and the third NMOS transistor N3 and the fourth NMOS transistor N4 have the same width-to-length ratio of their conductive channels.

4. The radiation-resistant SRAM memory cell according to claim 3, characterized in that, Each pull-up transistor is a single-fin field-effect transistor.

5. The radiation-resistant SRAM memory cell according to claim 4, characterized in that, The width-to-length ratio of the conductive channels of the third PMOS transistor P3 and the fourth PMOS transistor P4 is twice that of the first PMOS transistor P1 and the second PMOS transistor P2. The width-to-length ratio of the conductive channels of the third NMOS transistor N3 and the fourth NMOS transistor N4 is twice that of the first NMOS transistor N1 and the second NMOS transistor N2; The width-to-length ratio of the conductive channels of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 is twice that of the third NMOS transistor N3 and the fourth NMOS transistor N4.

6. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, During a read operation, both the bit line BL and the complementary bit line BLB are precharged to a high level. When the word line WL is high, a differential voltage signal is generated between the bit line BL and the complementary bit line BLB, and the storage unit outputs the stored logic data.

7. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, During a write operation, the bit line BL is preset to a high level, the complementary bit line BLB is preset to a low level, and when the word line WL is high, the first storage node and the third storage node are written with a high level, while the second storage node and the fourth storage node are written with a low level.

8. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, During a write operation, the bit line BL is preset to low level, the complementary bit line BLB is preset to high level, and when the word line WL is high level, the first storage node and the third storage node are written to low level, while the second storage node and the fourth storage node are written to high level.

9. The radiation-resistant SRAM memory cell according to claim 2, characterized in that, Both the bit line BL and the complementary bit line BLB are precharged to a high level, and the memory cell remains in its initial state when the word line WL is at a low level.

10. An integrated circuit board, characterized in that, The device includes the radiation-resistant SRAM memory cell according to any one of claims 1 to 9, and further includes a differential amplifier, wherein the two input terminals of the differential amplifier are respectively connected to bit lines BL and BLB for reading the differential signal between bit lines BL and BLB.

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