Radiation-hardened structure for one-time programmable memory sense logic

Abstract

The application discloses an anti-radiation reinforcing structure of a one-time programmable memory readout logic, and belongs to the field of semiconductor devices, comprising a state machine, a one-time programmable memory and an error correction module. The application reduces the influence of storage data in a readout process caused by a single particle effect by means of redundant reading of one-time programmable memory data and error detection and correction of readout storage data by means of an error correction module composed of a voter. Since the memory is read out redundantly for five times in the application, the two data errors caused by the single particle in the readout process of the memory data can be corrected at most, and the error correction module has a small area, so that the application has the characteristics of high reliability and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a radiation-hardened structure for one-time programmable memory readout logic. Background Technology

[0002] Numerous radiation effects exist in the space environment, including TID (Total Ionizing Dose) and SEE (Single Event Effect). The unique characteristics of the space environment place extremely high demands on the radiation resistance of aerospace electronic equipment.

[0003] One-time programmable memory (IPM), a core component of aerospace electronic systems, is primarily used for long-term storage of mission data, scientific exploration data, and critical configuration parameters. It must possess a certain degree of radiation resistance to meet performance requirements in space applications. Since IPM cannot be hardened against radiation through data refresh, Triple Modular Redundancy (TMR) and Error Detection and Correction (ECC) are currently effective methods for hardening IPM against radiation. However, TMR cannot correct errors and consumes significant resources when the user circuitry is large. Summary of the Invention

[0004] The purpose of this invention is to provide a radiation-hardened structure for the read logic of a one-time programmable memory, so as to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a radiation-hardened structure for the readout logic of a one-time programmable memory, comprising: a state machine, a one-time programmable memory, and an error correction module;

[0006] The output of the state machine is connected to the input control terminal of the one-time programmable memory, and is used to control the one-time programmable memory to repeatedly perform a read operation on the same address 5 times.

[0007] The output of the one-time programmable memory is connected to the error correction module, and each bit of the output Y... n_m Each error correction module's data input terminal is connected to one of the error correction modules; the other four outputs of the state machine are connected to the inputs of each error correction module, and are used to control the error correction modules to correct the outputs of the one-time programmable memory.

[0008] The error correction module ultimately outputs the data Q0~Q after the one-time programmable memory data has been processed by the irradiation-hardened structure. n Two errors are allowed during the five read operations;

[0009] The error correction module includes: a three-input NAND gate, a three-input OR gate, a three-input AND gate, a full adder, a first asynchronous reset register, a second asynchronous reset register, a two-input AND gate, and a third asynchronous reset register;

[0010] The inputs of the three-input NAND gate include: the OE signal and the SUM output from the Q terminal of the first asynchronous reset register. n_m The Q output of the second asynchronous reset register is CO. n_m The inputs of the three-input OR gate include: the Q-terminal output SUM of the first asynchronous reset register. n_m The Q output of the second asynchronous reset register is CO. n_m The inverted signal of the OE signal; the inputs of the three-input AND gate include: Y n_m The output of the three-input NAND gate and the output of the three-input OR gate; the two addends of the three-input input in the full adder are the Q output of the first asynchronous reset register and the B output of the three-input AND gate. n_m The carry input is the Q output of the second asynchronous reset register; the D input of the first asynchronous reset register is the SUM output of the full adder, the Clk input of the first asynchronous reset register is the CP1 input port (rising edge triggered), and the Reset input of the first asynchronous reset register is the RST input port; the D input of the second asynchronous reset register is the CO output of the full adder, the Clk input of the second asynchronous reset register is the CP1 input port (rising edge triggered), and the Reset input of the second asynchronous reset register is the RST input port; the input of the two-input AND gate includes: the SUM output signal of the Q output of the first asynchronous reset register. n_m The Q output signal CO of the second asynchronous reset register n_m The D input of the third asynchronous reset register is the output of the two-input AND gate; the Clk input of the third asynchronous reset register is the CP2 input port, triggered on the rising edge; the Reset input of the third asynchronous reset register is the RST input port; and the Q output is Q. n ;in,

[0011] Y n_m The terminal signal represents the nth bit of data output after the one-time programmable memory repeatedly reads a certain address for the mth time, where m ranges from 1 to 5, and the range of n is determined according to the output bit width of the one-time programmable memory;

[0012] The OE input signal is set high when the one-time programmable memory reads data from a certain address for the fourth time, to determine Y. n_m Whether the terminal signal is input to the full adder;

[0013] CP1 signal in each Y n_m After the signal is input to the error correction module, a high pulse is triggered to latch the output of the full adder;

[0014] The RST signal triggers a low pulse before the first reading of a certain address, which is used to reset the output of the first asynchronous reset register, the second asynchronous reset register, and the third asynchronous reset register to 0. The RST signal is triggered once before the address of the one-time programmable memory is changed.

[0015] Y of CP2 signal at m=5 n_5 After the signal input to the voting unit and the CP1 signal high-pulse latch register are input, a high pulse is generated to latch the final output Q of the error correction logic. n ;

[0016] B n_m The signal is the output signal of the three-input AND gate.

[0017] In one implementation, the three-input NAND gate, the three-input OR gate, and the three-input AND gate constitute a logic structure.

[0018] When m < 4, OE = 0, B n_m =Y n_m Y n_m The input signal is passed to the input terminal of the full adder, and the data Y is read from the same address for the fourth time in the one-time programmable memory. n_4 At the same time as the error correction module starts input, m > 3, OE = 1, the logic structure determines Y. m After inputting the error correction module, the first asynchronous reset register and the second asynchronous reset register output [CO] on the (m-1)th time. n_(m-1) SUM n_(m-1) Is it 2'b 00 or 2'b 11?

[0019] If [CO n_(m-1) SUM n_(m-1) ]=2'b 00 or 2'b 11, indicating that at least 3 out of the first m-1 reads from a specific address of the one-time programmable memory are either 1 or 0. n_m =0, Y n_m Unable to pass into the full adder to continue adding, [CO] n_m SUM n_m The lock exists in state 2'b 00 or 2'b 11;

[0020] If [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, meaning that there are no data points with a value of 1 more than or equal to 3 times in the first m-1 data points, Bn_m =Y n_m Y n_m The input signal is fed into the input terminal of the full adder; after each rising edge of CP1, the full adder will convert B... n_m Data and [CO] n_(m-1) SUM n_(m-1) When the data is added, the first asynchronous reset register and the second asynchronous reset register latch the sum SUM of the m full adders, respectively, after the rising edge of CP1. n_m and carry-over CO n_m The feedback is sent to the input of the full adder so that it can be used with the output B of the subsequent m+1 three-input AND gates. n_m Add; when m < 4, B n_m =Y n_m [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m When m > 3, if [CO n_(m-1) SUM n_(m-1) ] is 2'b 00 or 2'b 11, B n_m =0, the output of the full adder is [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =[CO n_(m-1) SUM n_(m-1) ], that is, 2'b00 or 2'b 11;

[0021] If [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, B n_m =Y n_m The output of the full adder [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m [CO] n_5 SUM n_5 ]=2'b 11, meaning that the number of times '1' appears in the data read from the one-time programmable memory is at least 3 times in 5 reads. [CO n_5 SUM n_5 ]<2'b 11,[COn_5 SUM n_5 The value represents the number of times 1 appears in the data read from the one-time programmable memory in 5 reads;

[0022] Two inputs and the goalkeeper CO n_m SUM n_m With, only [CO] n_5 SUM n_5 ]=2'b11=3,Q n =1, indicating that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q... n =0, which enables the output to vote on the most frequent data in 5 outputs, and can tolerate and correct 2 output errors.

[0023] In one implementation, the state machine controls the one-time programmable memory to read data Y sequentially from the same address. n_m The state machine controls the error correction module according to the following steps:

[0024] Step 1: Reset all registers in the error correction module using the RST signal, SUM n_0 =0, CO n_0 =0, Q n =0;

[0025] Step 2: Data Y at a specific address of the one-time programmable memory, bit n. n_1 The first read is sent to the error correction module, and OE is 0 at this point, so Y... n_1 After passing through the aforementioned logical structure, output B is obtained. n_1 =Y n_1 ;

[0026] Step 3, B n_1 With [CO] n_0 SUM n_0 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_1 SUM n_1 ]=[CO n_0 SUM n_0 ]+B n_1 =[0, Y n_1 ];

[0027] Step 4: Data Y at a specific address of the one-time programmable memory, bit n. n_2 The second read is sent to the error correction module. At this point, OE is 0, so Y... n_2 After passing through the aforementioned logical structure, output B is obtained. n_2 =Y n_2 ;

[0028] Step 5, B n_2 With [CO]n_1 SUM n_1 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_2 SUM n_2 ]=[CO n_1 SUM n_1 ]+B n_2 =[0, Y n_1 ]+Y n_2 =Y n_1 +Y n_2 ;

[0029] Step 6: Data Y at a specific address of the one-time programmable memory, bit n. n_3 The third read is sent to the error correction module. At this point, OE is 0, therefore Y... n_3 After passing through the aforementioned logical structure, output B is obtained. n_3 =Y n_3 ;

[0030] Step 7, B n_3 With [CO] n_2 SUM n_2 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_3 SUM n_3 ]=[CO n_2 SUM n_2 ]+B n_3 =Y n_1 +Y n_2 +Y n_3 ;

[0031] Step 8: Data Y at a specific address of the one-time programmable memory, bit n. n_4 The fourth read is sent to the error correction module. At this point, OE is 1, so Y... n_4 The output after passing through the aforementioned logical structure is:

[0032] If [CO n_3 SUM n_3 ]=2'b 11, then B n_4 =0 indicates that the one-time programmable memory has output 1 3 times; B n_4 With [CO] n_3 SUM n_3 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 11;

[0033] If [CO n_3 SUM n_3 ]=2'b 00, then B n_4 =0, indicating that the one-time programmable memory has output 0 three times; B n_4 With [CO] n_3 SUM n_3 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 00;

[0034] If [CO n_3 SUM n_3 If ] = 2'b01 or 2'b10, then B n_4 =Y n_4 This indicates that the first three outputs of the one-time programmable memory did not contain three 0s or 1s. n_4 With [CO] n_3 SUM n_3 In a full adder, addition will not overflow; latching occurs after the rising edge of CP1. n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =Y n_1 +Y n_2 +Y n_3 +Y n_4 [CO] n_4 SUM n_4 The value represents the number of times the number 1 appears in the data read from the one-time programmable memory in 4 reads;

[0035] Step 9: Data Y at a specific address of the one-time programmable memory, bit n. n_5 The error is read to the error correction module for the 5th time. OE is 1 at this point, therefore Y... n_5 The output after passing through the aforementioned logical structure is:

[0036] If [CO n_4 SUM n_4 ]=2'b 11, then B n_5 =0 indicates that the one-time programmable memory has output 1 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The sums are added in a full adder and latched after the rising edge of CP1. [CO]n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[CO n_4 SUM n_4 ]=2'b 11;

[0037] If [CO n_4 SUM n_4 ]=2'b 00, then B n_5 =0 indicates that the one-time programmable memory has output 0 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[CO n_4 SUM n_4 ]=2'b 00;

[0038] If [CO n_4 SUM n_4 If ] = 2'b01 or 2'b10, then B n_5 =Y n_5 This indicates that the first four outputs of the one-time programmable memory did not contain three 1s or Bs. n_5 With [CO] n_4 SUM n_4 In a full adder, addition will not overflow; latching occurs after the rising edge of CP1. n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =Y n_1 +Y n_2 +Y n_3 +Y n_4 +Y n_5 [CO] n_5 SUM n_5 The value represents the number of times the number 1 appears in the data read from the one-time programmable memory in 5 reads;

[0039] Step 10: When the rising edge of CP2 arrives, latch Q. n =CO n_5 &SUM n_5 , indicating that only [CO n_5 SUM n_5 ]=2'b11=3,Qn =1, indicating that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q... n =0, which enables the output to vote on the most frequent data in 5 outputs, and can tolerate and correct 2 output errors.

[0040] This invention provides a radiation-hardened structure for the readout logic of a one-time programmable memory, which corrects errors caused by single-event interference during data readout. This invention can correct data errors twice during the readout process, resulting in high reliability. Furthermore, the error correction module utilizes a feedback structure, requiring only 2 bits to represent the sum of 5 data additions, thus minimizing the area required. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the radiation-hardened structure of the one-time programmable memory readout logic provided by the present invention.

[0042] Figure 2 This is a schematic diagram of the hardware implementation structure of the error correction module provided by the present invention.

[0043] Figure 3 This is a schematic diagram of the working timing of the error correction module provided by the present invention. Detailed Implementation

[0044] The radiation-hardened structure for a one-time programmable memory readout logic proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0045] This invention provides a radiation-hardened structure for the read logic of a one-time programmable memory, such as... Figure 1 As shown, it includes: a state machine, a one-time programmable memory, and an error correction module; the output of the state machine is connected to the input control terminal of the one-time programmable memory, used to control the one-time programmable memory to repeatedly perform 5 read operations on the same address; the output of the one-time programmable memory is connected to the error correction module, and each bit of the output Y... n_m Connecting the data input terminal of an error correction module, if the output bit width of the one-time programmable memory is 8 bits, then 8 error correction modules are needed, each connected to one bit of the output. The other four outputs of the state machine are connected to the input of each error correction module, used to control the error correction module to correct the output of the one-time programmable memory. The error correction module finally outputs the data Q0~Q0 after the one-time programmable memory data has been hardened by the irradiation structure. n It allows for two errors during the five read operations, has a high fault tolerance rate, and has a small hardware implementation area.

[0046] The hardware structure of the error correction module is as follows: Figure 2 As shown, it includes: a three-input NAND gate 1, a three-input OR gate 2, a three-input AND gate 3, a full adder 4, an asynchronous reset register 5, an asynchronous reset register 6, a two-input AND gate 7, and an asynchronous reset register 8; the inputs of the three-input NAND gate 1 include: the OE signal and the Q output SUM of the asynchronous reset register 5. n_m The Q output of asynchronous reset register 6 is CO. n_m The inputs of the three-input OR gate 2 include: the Q-output SUM of the asynchronous reset register 5. n_m The Q output of asynchronous reset register 6 is CO. n_m The inverted signal of the OE signal; the inputs of the three-input AND gate 3 include: Y n_m The output of the three-input NAND gate 1 and the output of the three-input OR gate 2; the two addends of the three-input full adder 4 are the Q output of the asynchronous reset register 5 and the B output of the three-input AND gate 3. n_m The carry input is the Q output of asynchronous reset register 6; the D input of asynchronous reset register 5 is the SUM output of full adder 4, the Clk input of asynchronous reset register 5 is the CP1 input port (rising edge triggered), and the Reset input of asynchronous reset register 5 is the RST input port; the D input of asynchronous reset register 6 is the CO output of full adder 4, the Clk input of asynchronous reset register 6 is the CP1 input port (rising edge triggered), and the Reset input of asynchronous reset register 6 is the RST input port; the input of the two-input AND gate 7 includes: the SUM output signal from the Q output of asynchronous reset register 5. n_m The Q output signal CO of asynchronous reset register 6 n_m The D input of asynchronous reset register 8 is the output of two-input AND gate 7; the Clk input of asynchronous reset register 8 is the CP2 input port (rising edge triggered); the Reset input of asynchronous reset register 8 is the RST input port; and the Q output is Q. n .

[0047] Y n_m The OE input signal represents the nth bit of data output after the m-th repeated reading of a certain address from the one-time programmable memory, where m ranges from 1 to 5, and the range of n is determined by the output bit width of the one-time programmable memory. The OE input signal is set high when the one-time programmable memory reads data from a certain address for the 4th time, and is used to determine Y. n_m Whether the terminal signal is input to full adder 4; the CP1 signal in each Y n_mAfter the signal is input to the error correction module, a high pulse is triggered to latch the output of full adder 4; the RST signal triggers a low pulse before the first read of a certain address to reset the outputs of asynchronous reset registers 5, 6, and 8 to 0; an RST signal is triggered before each change of the address of the one-time programmable memory; the CP2 signal triggers a low pulse before the Y... n_5 signal (i.e. Y n_m (m=5) After the input to the voting unit and the CP1 signal high pulse latch register, a high pulse is generated to latch the final output Q of the error correction logic. n B n_m The signal is the output signal of a three-input AND gate 3.

[0048] The logic structure formed by combining three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3, where m < 4, OE = 0, B n_m =Y n_m Y n_m The input signal is passed to the input terminal of the full adder 4, and the data Y is read from the same address for the fourth time in the one-time programmable memory. n_4 At the same time as the error correction module starts input, i.e., m > 3, OE = 1, this logic structure determines Y. m After inputting the error correction module, the (m-1)th asynchronous reset register 5 and asynchronous reset register 6 output [CO] n_(m-1) SUM n_(m-1) Is it 2'b 00 or 2'b 11? If [CO] n_(m-1) SUM n_(m-1) If ]=2'b 00 or 2'b 11, it means that in the first m-1 reads of a certain address of the one-time programmable memory, at least 3 of the data are 1 or 0. n_m =0, Y n_m Unable to pass into full adder 4 for further addition, [CO] n_m SUM n_m The lock exists in state 2'b 00 or 2'b 11 if [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, meaning that there are no data points with a value of 1 more than or equal to 3 times in the m-1 data points, B n_m =Y n_m Y n_m The input signal is fed into the input terminal of full adder 4; after each rising edge of CP1, full adder 4 will add B... n_m Data and [CO] n_(m-1) SUM n_(m-1) When the data is added, asynchronous reset registers 5 and 6 latch the sum of m full adders 4 and SUM respectively after the rising edge of CP1. n_m and carry-over CO n_mThe feedback is sent to the input of the full adder 4 so that it can be combined with the output B of the subsequent m+1 times three-input AND gate 3. n_m Add; when m < 4, B n_m =Y n_m [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m When m > 3, if [CO n_(m-1) SUM n_(m-1) ] is 2'b 00 or 2'b 11, B n_m =0, the output of full adder 4 is [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =[CO n_(m-1) SUM n_(m-1) ], that is, 2'b 00 or 2'b 11, if [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, B n_m =Y n_m The output of full adder 4 [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m [CO] n_5 SUM n_5 ]=2'b 11, which means that the number of times 1 appears in the data read from the one-time programmable memory is at least 3 times. [CO n_5 SUM n_5 ]<2'b 11,[CO n_5 SUM n_5 The value of ] represents the number of times 1 is read from the one-time programmable memory in 5 reads; the two-input AND gate 7 will convert CO n_m SUM n_m With, only [CO] n_5 SUM n_5 ]=2'b11=3,Q n =1, meaning that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q = 1. n=0, which achieves the output of the most frequently occurring data in 5 output voting, and can tolerate and correct 2 output errors.

[0049] A state machine controls a one-time programmable memory to read data Y sequentially from the same address. n_m In this embodiment, the data bit width of the one-time programmable memory is 8 bits, so n=0~7, requiring a total of 8 error correction modules. The state machine simultaneously follows... Figure 3 The timing control signal controls the error correction module. The specific error correction steps are as follows:

[0050] 1. Reset all registers in the RST signal error correction module, SUM n_0 =0, CO n_0 =0, Q n =0;

[0051] 2. The nth bit of data Y at a certain address of a one-time programmable memory. n_1 The first read is sent to the error correction module, and OE is 0 at this point, so Y... n_1 After the combinational logic of three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3, the output is B. n_1 =Y n_1 ;

[0052] 3. B n_1 With [CO] n_0 SUM n_0 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_1 SUM n_1 ]=[CO n_0 SUM n_0 ]+B n_1 =[0, Y n_1 ];

[0053] 4. The nth bit of data Y at a certain address in a one-time programmable memory. n_2 The second read is sent to the error correction module. At this point, OE is 0, so Y... n_2 After the combinational logic of three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3, the output is B. n_2 =Y n_2 ;

[0054] 5. B n_2 With [CO] n_1 SUM n_1 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_2 SUM n_2 ]=[CO n_1 SUM n_1 ]+B n_2 =[0, Yn_1 ]+Y n_2 =Y n_1 +Y n_2 ;

[0055] 6. The nth bit data Y at a certain address of a one-time programmable memory n_3 The third read is sent to the error correction module. At this point, OE is 0, therefore Y... n_3 After the combinational logic of three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3, the output is B. n_3 =Y n_3 ;

[0056] 7. B n_3 With [CO] n_2 SUM n_2 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_3 SUM n_3 ]=[CO n_2 SUM n_2 ]+B n_3 =Y n_1 +Y n_2 +Y n_3 ;

[0057] 8. The nth bit of data Y at a certain address of a one-time programmable memory. n_4 The fourth read is sent to the error correction module. At this point, OE is 1, so Y... n_4 The output after combinational logic of three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3 is:

[0058] If [CO n_3 SUM n_3 If ] = 2'b 11, then B n_4 =0, which means that the one-time programmable memory has output 1 3 times; B n_4 With [CO] n_3 SUM n_3 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 11;

[0059] If [CO n_3 SUM n_3 If ]=2'b 00, then B n_4 =0, which means that the one-time programmable memory has output 0 3 times; B n_4With [CO] n_3 SUM n_3 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 00;

[0060] If [CO n_3 SUM n_3 If ] = 2'b01 or 2'b10, then B n_4 =Y n_4 This indicates that the first three outputs of the one-time programmable memory did not contain three 0s or 1s, therefore B... n_4 With [CO] n_3 SUM n_3 In a full adder 4, addition will not overflow; it is latched after the rising edge of CP1, i.e., [CO]. n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =Y n_1 +Y n_2 +Y n_3 +Y n_4 [CO] n_4 SUM n_4 The value of ] represents the number of times 1 appears in the data read from the one-time programmable memory in 4 reads;

[0061] 9. The nth bit of data Y at a certain address of a one-time programmable memory. n_5 The error is read to the error correction module for the 5th time. OE is 1 at this point, therefore Y... n_5 The output after combinational logic of three-input NAND gate 1, three-input OR gate 2, and three-input AND gate 3 is:

[0062] If [CO n_4 SUM n_4 If ] = 2'b 11, then B n_5 =0 indicates that the one-time programmable memory has output 1 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[COn_4 SUM n_4 ]=2'b 11;

[0063] If [CO n_4 SUM n_4 If ]=2'b 00, then B n_5 =0 indicates that the one-time programmable memory has output 0 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The summation occurs in full adder 4, and the summation is latched after the rising edge of CP1, i.e., [CO]. n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[CO n_4 SUM n_4 ]=2'b 00;

[0064] If [CO n_4 SUM n_4 If ] = 2'b01 or 2'b10, then B n_5 =Y n_5 This indicates that the first four outputs of the one-time programmable memory did not contain three 1s, therefore B n_5 With [CO] n_4 SUM n_4 In a full adder 4, addition will not overflow; it is latched after the rising edge of CP1, i.e., [CO]. n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =Y n_1 +Y n_2 +Y n_3 +Y n_4 +Y n_5 [CO] n_5 SUM n_5 The value of ] represents the number of times the number 1 appears in the data read from the one-time programmable memory in 5 reads;

[0065] 10. Latch Q when the rising edge of CP2 arrives. n =CO n_5 &SUM n_5 , indicating that only [CO n_5 SUM n_5 ]=2'b11=3,Q n =1, meaning that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q = 1. n=0, which achieves the output of the most frequently occurring data in 5 output voting, and can tolerate and correct 2 output errors.

[0066] This invention utilizes a state machine to control five redundant read operations of a one-time programmable memory (IPM). Combined with an error correction module, it achieves radiation hardening of the read circuit for IPMs that cannot be hardened through data refresh. It can tolerate two data errors caused by single-particle interference during data readout in an irradiated environment, resulting in high reliability. The error correction module employs a feedback structure to implement five error correction logic operations, and the sum of the five data entries requires only a 2-bit width to represent the result. Compared to triple-modular redundancy radiation hardening structures, it has a smaller area and lower power consumption.

[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A radiation-hardened structure for the read logic of a one-time programmable memory, characterized in that, include: State machine, one-time programmable memory, error correction module; The output of the state machine is connected to the input control terminal of the one-time programmable memory, and is used to control the one-time programmable memory to repeatedly perform a read operation on the same address 5 times. The output of the one-time programmable memory is connected to the error correction module, and each bit of the output Y... n_m Each error correction module's data input terminal is connected to one of the error correction modules; the other four outputs of the state machine are connected to the inputs of each error correction module, and are used to control the error correction modules to correct the outputs of the one-time programmable memory. The error correction module ultimately outputs the data Q0~Q after the one-time programmable memory data has been processed by the irradiation-hardened structure. n Two errors are allowed during the five read operations; The error correction module includes: a three-input NAND gate, a three-input OR gate, a three-input AND gate, a full adder, a first asynchronous reset register, a second asynchronous reset register, a two-input AND gate, and a third asynchronous reset register; The inputs of the three-input NAND gate include: the OE signal and the Q output SUM of the first asynchronous reset register. n_m The Q output of the second asynchronous reset register is CO. n_m The inputs of the three-input OR gate include: the Q-terminal output SUM of the first asynchronous reset register. n_m The Q output of the second asynchronous reset register is CO. n_m The inverted signal of the OE signal; the inputs of the three-input AND gate include: Y n_m The three input signals, the output of the three-input NAND gate, and the output of the three-input OR gate; the two addends of the three inputs in the full adder are the Q output of the first asynchronous reset register and the B output of the three-input AND gate. n_m The carry input is the Q output of the second asynchronous reset register; the D input of the first asynchronous reset register is the SUM output of the full adder, the Clk input of the first asynchronous reset register is the CP1 input port (rising edge triggered), and the Reset input of the first asynchronous reset register is the RST input port; the D input of the second asynchronous reset register is the CO output of the full adder, the Clk input of the second asynchronous reset register is the CP1 input port (rising edge triggered), and the Reset input of the second asynchronous reset register is the RST input port; the input of the two-input AND gate includes: the SUM output signal of the Q output of the first asynchronous reset register. n_m The Q output signal CO of the second asynchronous reset register n_m The D input of the third asynchronous reset register is the output of the two-input AND gate; the Clk input of the third asynchronous reset register is the CP2 input port, triggered on the rising edge; the Reset input of the third asynchronous reset register is the RST input port; and the Q output is Q. n ;in, Y n_m The terminal signal represents the nth bit of data output after the one-time programmable memory repeatedly reads a certain address for the mth time, where m ranges from 1 to 5, and the range of n is determined according to the output bit width of the one-time programmable memory; The OE input signal is set high when the one-time programmable memory reads data from a certain address for the fourth time, to determine Y. n_m Whether the terminal signal is input to the full adder; CP1 signal in each Y n_m After the signal is input to the error correction module, a high pulse is triggered to latch the output of the full adder; The RST signal triggers a low pulse before the first reading of a certain address, which is used to reset the output of the first asynchronous reset register, the second asynchronous reset register, and the third asynchronous reset register to 0. The RST signal is triggered once before the address of the one-time programmable memory is changed. Y of CP2 signal at m=5 n_5 After the signal input to the voting unit and the CP1 signal high-pulse latch register are input, a high pulse is generated to latch the final output Q of the error correction logic. n ; B n_m The signal is the output signal of the three-input AND gate.

2. The radiation-hardened structure for the read logic of a one-time programmable memory as described in claim 1, characterized in that, The three-input NAND gate, the three-input OR gate, and the three-input AND gate constitute the logic structure. When m < 4, OE = 0, B n_m =Y n_m Y n_m The input signal is passed to the input terminal of the full adder, and the data Y is read from the same address for the fourth time in the one-time programmable memory. n_4 At the same time as the error correction module starts input, m > 3, OE = 1, the logic structure determines Y. m After inputting the error correction module, the first asynchronous reset register and the second asynchronous reset register output [CO] on the (m-1)th time. n_(m-1) SUM n_(m-1) Is it 2'b 00 or 2'b 11? If [CO n_(m-1) SUM n_(m-1) ]=2'b 00 or 2'b 11, indicating that at least 3 out of the first m-1 reads from a specific address of the one-time programmable memory are either 1 or 0. n_m =0, Y n_m Unable to pass into the full adder to continue adding, [CO] n_m SUM n_m The lock exists in state 2'b 00 or 2'b 11; If [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, meaning that there are no data points with a value of 1 more than or equal to 3 times in the first m-1 data points, B n_m =Y n_m Y n_m The input signal is fed into the input terminal of the full adder; after each rising edge of CP1, the full adder will convert B... n_m Data and [CO] n_(m-1) SUM n_(m-1) When the data is added, the first asynchronous reset register and the second asynchronous reset register latch the sum SUM of the m full adders, respectively, after the rising edge of CP1. n_m and carry-over CO n_m The feedback is sent to the input of the full adder so that it can be used with the output B of the subsequent m+1 three-input AND gates. n_m Add; when m < 4, B n_m =Y n_m [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m When m > 3, if [CO n_(m-1) SUM n_(m-1) ] is 2'b 00 or 2'b 11, B n_m =0, the output of the full adder is [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =[CO n_(m-1) SUM n_(m-1) ], that is, 2'b00 or 2'b 11; If [CO n_(m-1) SUM n_(m-1) ]≠2'b 00 or 2'b 11, B n_m =Y n_m The output of the full adder [CO] n_m SUM n_m ]=[CO n_(m-1) SUM n_(m-1) ]+B n_m =Y n_1 +Y n_2 +…Y n_m [CO] n_5 SUM n_5 ]=2'b 11, meaning that the number of times '1' appears in the data read from the one-time programmable memory is at least 3 times in 5 reads. [CO n_5 SUM n_5 ]<2'b 11,[CO n_5 SUM n_5 The value represents the number of times a 1 appears in the data read from the one-time programmable memory in 5 reads; Two inputs and the goalkeeper CO n_m SUM n_m With, only [CO] n_5 SUM n_5 ]=2'b11=3,Q n =1, indicating that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q... n =0, which enables the output to vote on the most frequent data in 5 outputs, and can tolerate and correct 2 output errors.

3. The radiation-hardened structure for the read logic of a one-time programmable memory as described in claim 2, characterized in that, The state machine controls the one-time programmable memory to read data Y sequentially from the same address. n_m The state machine controls the error correction module according to the following steps: Step 1: Reset all registers in the error correction module using the RST signal, SUM n_0 =0, CO n_0 =0, Q n =0; Step 2: Data Y at a specific address of the one-time programmable memory, bit n. n_1 The first read is sent to the error correction module, and OE is 0 at this point, so Y... n_1 After passing through the aforementioned logical structure, output B is obtained. n_1 =Y n_1 ; Step 3, B n_1 With [CO] n_0 SUM n_0 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_1 SUM n_1 ]=[CO n_0 SUM n_0 ]+B n_1 =[0, Y n_1 ]; Step 4: Data Y at a specific address of the one-time programmable memory, bit n. n_2 The second read is sent to the error correction module. At this point, OE is 0, so Y... n_2 After passing through the aforementioned logical structure, output B is obtained. n_2 =Y n_2 ; Step 5, B n_2 With [CO] n_1 SUM n_1 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_2 SUM n_2 ]=[CO n_1 SUM n_1 ]+B n_2 =[0, Y n_1 ]+Y n_2 =Y n_1 +Y n_2 ; Step 6: Data Y at a specific address of the one-time programmable memory, bit n. n_3 The third read is sent to the error correction module. At this point, OE is 0, therefore Y... n_3 After passing through the aforementioned logical structure, output B is obtained. n_3 =Y n_3 ; Step 7, B n_3 With [CO] n_2 SUM n_2 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_3 SUM n_3 ]=[CO n_2 SUM n_2 ]+B n_3 =Y n_1 +Y n_2 +Y n_3 ; Step 8: Data Y at a specific address of the one-time programmable memory, bit n. n_4 The fourth read is sent to the error correction module. At this point, OE is 1, so Y... n_4 The output after passing through the aforementioned logical structure is: If [CO n_3 SUM n_3 ]=2'b 11, then B n_4 =0 indicates that the one-time programmable memory has output 1 3 times; B n_4 With [CO] n_3 SUM n_3 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 11; If [CO n_3 SUM n_3 ]=2'b 00, then B n_4 =0, indicating that the one-time programmable memory has output 0 3 times; B n_4 With [CO] n_3 SUM n_3 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =[CO n_3 SUM n_3 ]=2'b 00; If [CO n_3 SUM n_3 If ] = 2'b01 or 2'b10, then B n_4 =Y n_4 This indicates that the first three outputs of the one-time programmable memory did not contain three 0s or 1s. n_4 With [CO] n_3 SUM n_3 In a full adder, addition will not overflow; latching occurs after the rising edge of CP1. n_4 SUM n_4 ]=[CO n_3 SUM n_3 ]+B n_4 =Y n_1 +Y n_2 +Y n_3 +Y n_4 [CO] n_4 SUM n_4 The value represents the number of times the number 1 appears in the data read from the one-time programmable memory in 4 reads; Step 9: Data Y at a specific address of the one-time programmable memory, bit n. n_5 The error is read to the error correction module for the 5th time. OE is 1 at this point, therefore Y... n_5 The output after passing through the aforementioned logical structure is: If [CO n_4 SUM n_4 ]=2'b 11, then B n_5 =0 indicates that the one-time programmable memory has output 1 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[CO n_4 SUM n_4 ]=2'b 11; If [CO n_4 SUM n_4 ]=2'b 00, then B n_5 =0 indicates that the one-time programmable memory has output 0 at least 3 times; B n_5 With [CO] n_4 SUM n_4 The sums are added in a full adder and latched after the rising edge of CP1. [CO] n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =[CO n_4 SUM n_4 ]=2'b 00; If [CO n_4 SUM n_4 If ] = 2'b01 or 2'b10, then B n_5 =Y n_5 This indicates that the first four outputs of the one-time programmable memory did not contain three 1s or Bs. n_5 With [CO] n_4 SUM n_4 In a full adder, addition will not overflow; latching occurs after the rising edge of CP1. n_5 SUM n_5 ]=[CO n_4 SUM n_4 ]+B n_5 =Y n_1 +Y n_2 +Y n_3 +Y n_4 +Y n_5 [CO] n_5 SUM n_5 The value represents the number of times the number 1 appears in the data read from the one-time programmable memory in 5 reads; Step 10: When the rising edge of CP2 arrives, latch Q. n =CO n_5 &SUM n_5 , indicating that only [CO n_5 SUM n_5 ]=2'b11=3,Q n =1, indicating that the nth bit of the data read from the one-time programmable memory is 1 at least three times; otherwise, Q... n =0, which enables the output to vote on the most frequent data in 5 outputs, and can tolerate and correct 2 output errors.

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