A thin-film surface-emitting electro-optic chip structure and its fabrication method

Abstract

This application relates to a thin-film surface-emitting electro-optic chip structure and its fabrication method. The structure includes a heterojunction active region, a first conductive layer, a second conductive layer, a first reflector, a second reflector, a first electrode, and a second electrode. The first conductive layer includes a raised optical waveguide confinement structure, which protrudes away from the heterojunction active region for optical energy concentration. The first electrode makes ohmic contact with the first conductive layer to form a first ohmic contact region, and the second electrode makes ohmic contact with the second conductive layer to form a second ohmic contact region. The orthographic projections of the first and second ohmic contact regions are isolated by the orthographic projection of the optical waveguide confinement structure. By using an in-plane staggered electrode layout, combined with the channel transmission characteristics of the heterojunction active region and the optical field confinement mechanism of the optical waveguide confinement structure, the chip's in-plane current transmission capability and optical field energy accumulation efficiency are enhanced, alleviating the problem of high electrode current load.

Description

Technical Field

[0001] This application relates to the field of semiconductor optoelectronic device technology, and in particular to a thin-film surface-emitting electro-optic chip structure and its fabrication method. Background Technology

[0002] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser in which the laser emission direction is perpendicular to the surface of the chip. Due to its advantages such as low threshold current, monolithic integration of two-dimensional arrays, good divergence angle symmetry, easy coupling, and low manufacturing cost, it has been widely used in optical communication, optical sensing, and consumer electronics.

[0003] For semiconductor optoelectronic devices, to amplify optical signals or improve light quality, the chip structure typically needs to implement an internal optical field energy accumulation function, such as the chip structures widely used in superluminescent diodes or laser diodes. Radiative recombination of electrons and holes within the chip generates photons. When the chip is under a large forward bias, the generated photons can further promote the radiative recombination of related electrons and holes, thus forming stimulated emission gain. When the optical field energy is effectively accumulated, the radiative recombination efficiency within the chip and the intensity of light at specific frequencies can both be significantly enhanced.

[0004] To achieve effective accumulation of light field energy, chips typically require the construction of reflective mirrors on the upper and lower sides of the light-emitting region to form an optical resonant cavity. In visible light devices, insulating high-reflectivity mirrors are commonly used, but they suffer from insufficient in-plane current transmission capability.

[0005] Therefore, how to achieve efficient in-plane current transport and optical field energy accumulation has become a key technical problem that urgently needs to be solved in the development of devices in this field. Summary of the Invention

[0006] To address the aforementioned technical problems, the first aspect of this application provides a thin-film surface-emitting electro-optic chip structure, comprising:

[0007] The heterojunction active region includes a first emitter surface and a second emitter surface that are disposed opposite to each other;

[0008] A first conductive layer is disposed on the first emitting surface of the active region of the heterojunction. The first conductive layer includes a raised optical waveguide confinement structure. The optical waveguide confinement structure protrudes to the side away from the active region of the heterojunction. The optical waveguide confinement structure is used for optical field energy concentration.

[0009] The second conductive layer is disposed on the second emitter surface of the active region of the heterojunction, and the first conductive layer and the second conductive layer have different conductivity types.

[0010] The first reflector is disposed at least on the side of the optical waveguide confinement structure away from the active region of the heterojunction.

[0011] The second reflector is disposed on the side of the second conductive layer away from the active region of the heterojunction.

[0012] The first electrode is in ohmic contact with the first conductive layer to form a first ohmic contact region;

[0013] The second electrode forms a second ohmic contact region by ohmic contact with the second conductive layer. The orthographic projections of the first ohmic contact region and the second ohmic contact region are isolated by the orthographic projection of the optical waveguide confinement structure.

[0014] In one embodiment, the thickness of the optical waveguide confinement structure is greater than half the sum of the thicknesses of the first conductive layer, the heterojunction active region, and the second conductive layer.

[0015] In one embodiment, the shape of the optical waveguide confinement structure includes a columnar shape.

[0016] In one embodiment, the orthographic projections of the first ohmic contact area and the second ohmic contact area are symmetrically arranged on both sides of the orthographic projection of the optical waveguide confinement structure, and the orthographic projections of the first ohmic contact area and the second ohmic contact area are fan-shaped or square.

[0017] In one embodiment, the active region of the heterojunction includes at least overlapping narrow bandgap layers and wide bandgap layers, with a bandgap difference greater than 0.5 eV between the narrow bandgap layers and the wide bandgap layers, and the narrow bandgap layers are used for carrier transport.

[0018] In one embodiment, the first conductive layer is made of an n-type semiconductor material that conducts electrons, and the second conductive layer is made of a p-type semiconductor material that conducts holes.

[0019] In one embodiment, the area of ​​the orthographic projection of the first ohmic contact region and the second ohmic contact region is greater than or equal to 20% of the area of ​​the orthographic projection of the optical waveguide confinement structure.

[0020] The second aspect of this application provides a method for fabricating a thin-film surface-emitting electro-optic chip structure, comprising the following steps:

[0021] Provide substrate;

[0022] A first conductive layer, a heterojunction active region, a second conductive layer, and a second reflector are sequentially formed on the substrate.

[0023] Partially remove the second reflector until the surface of the second conductive layer is exposed;

[0024] A second electrode is formed at the exposed surface of the second conductive layer, and the second electrode makes ohmic contact with the second conductive layer to form a second ohmic contact region;

[0025] Remove the substrate to expose the first conductive layer;

[0026] The first conductive layer is etched to form an optical waveguide confinement structure. The optical waveguide confinement structure protrudes to the side away from the active region of the heterojunction. The optical waveguide confinement structure is used for optical field energy concentration.

[0027] A first reflector is formed on the first conductive layer, and the first reflector at least covers the optical waveguide confinement structure;

[0028] A first electrode is formed on the first conductive layer, and the first electrode makes ohmic contact with the first conductive layer to form a first ohmic contact region. The orthographic projections of the first ohmic contact region and the second ohmic contact region are isolated by the orthographic projection of the optical waveguide confinement structure.

[0029] A third aspect of this application provides a thin-film surface-emitting electro-optic chip, including the thin-film surface-emitting electro-optic chip structure described in any of the above claims.

[0030] A fourth aspect of this application provides a circuit module including the aforementioned thin-film surface-emitting electro-optic chip.

[0031] According to the thin-film surface-emitting electro-optic chip structure and its fabrication method, thin-film surface-emitting electro-optic chip and circuit module provided in the embodiments of this application, by using in-plane staggered electrode layout, combined with the channel transmission characteristics of the heterojunction active region and the optical field confinement mechanism of the optical waveguide confinement structure, the chip's in-plane current transmission capability and optical field energy accumulation efficiency are effectively enhanced, the problem of high current load on electrodes is alleviated, and the performance of the surface-emitting electro-optic chip is improved. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 A cross-sectional schematic diagram of the thin-film surface-emitting electro-optic chip structure provided in this application;

[0034] Figure 2 A schematic diagram of the structure of the heterojunction active region provided in this application;

[0035] Figure 3 A top view schematic diagram of the thin-film surface-emitting electro-optic chip structure provided in this application;

[0036] Figure 4 Another top view schematic diagram of the thin-film surface-emitting electro-optic chip structure provided in this application;

[0037] Figure 5 A flowchart illustrating the fabrication method of the thin-film surface-emitting electro-optic chip structure provided in this application;

[0038] Figure 6A A schematic cross-sectional view of the structure obtained after forming the first conductive layer, the heterojunction active region, the second conductive layer and the second mirror in step S520 of the fabrication method of the thin-film surface-emitting electro-optic chip structure provided in this application.

[0039] Figure 6B A schematic cross-sectional view of the structure obtained after etching the second reflector in step S530 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application.

[0040] Figure 6C A schematic cross-sectional view of the structure obtained after forming the second electrode in step S540 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application.

[0041] Figure 6D A schematic cross-sectional view of the structure obtained after removing the substrate in step S550 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application.

[0042] Figure 6E A schematic cross-sectional view of the structure obtained after forming the optical waveguide confinement structure in step S560 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application.

[0043] Figure 6F A schematic cross-sectional view of the structure obtained after forming the first reflector in step S570 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application;

[0044] Figure 6G This is a schematic cross-sectional view of the structure obtained after forming the first electrode in step S580 of the method for fabricating the thin-film surface-emitting electro-optic chip structure provided in this application. Detailed Implementation

[0045] To better understand the above-mentioned objectives, features, and advantages of this application, embodiments of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0046] Numerous specific details are set forth in the following description to provide a thorough understanding of this application, but this application may also be implemented in other ways than those described herein. Clearly, the embodiments described in the specification are only a portion of, and not all, of the embodiments of this application.

[0047] This application provides a thin-film surface-emitting electro-optic chip structure, with reference to... Figure 1 As shown, it includes:

[0048] The heterojunction active region 110 includes a first emission surface and a second emission surface that are disposed opposite to each other.

[0049] The first conductive layer 120 is disposed on the first emitting surface of the heterojunction active region 110. The first conductive layer includes a protruding optical waveguide confinement structure 121. The optical waveguide confinement structure protrudes to the side away from the heterojunction active region 110. The optical waveguide confinement structure 121 is used for optical field energy concentration.

[0050] The second conductive layer 130 is disposed on the second emission surface of the heterojunction active region 110, and the first conductive layer 120 and the second conductive layer 130 have different conductivity types.

[0051] The first reflector 140 is disposed at least on the side of the optical waveguide confinement structure 121 away from the heterojunction active region 110.

[0052] The second reflector 150 is disposed on the side of the second conductive layer 130 away from the heterojunction active region 110.

[0053] The first electrode 160 is in ohmic contact with the first conductive layer 120 to form a first ohmic contact area;

[0054] The second electrode 170 is in ohmic contact with the second conductive layer 130 to form a second ohmic contact area. The orthographic projections of the first ohmic contact area and the second ohmic contact area are isolated by the orthographic projection of the optical waveguide confinement structure 121.

[0055] In one embodiment, refer to Figure 1 and Figure 2 As shown, the heterojunction active region 110 includes at least overlapping narrow bandgap layer 111 and wide bandgap layer 112, wherein the bandgap difference between the narrow bandgap layer 111 and the wide bandgap layer 112 is greater than 0.5 eV, and the narrow bandgap layer 111 is used for carrier transport. The overlap of the narrow bandgap layer 111 and the wide bandgap layer 112 forms a heterojunction, and the interface of the narrow bandgap layer 111 in the heterojunction constitutes a carrier transport channel, utilizing the two-dimensional carrier gas in the channel to enhance the in-plane transport conductivity. The heterojunction active region 110 includes at least two heterojunction layers, in Figure 2 In the example shown, the heterojunction active region 110 comprises four heterojunction layers. Both the narrow bandgap layer 111 and the wide bandgap layer 112 are made of polar materials, and the heterojunction active region 110 is made using an Al-Ga-In-N material system. The material of the narrow bandgap layer 111 includes, but is not limited to, indium gallium nitride (InN). 0.25 Ga 0.75The material of the wide bandgap layer 112 includes, but is not limited to, gallium nitride (GaN). The thickness of the narrow bandgap layer 111 is less than the thickness of the wide bandgap layer 112. Specifically, the thickness of the narrow bandgap layer 111 ranges from 2 nm to 10 nm, for example, 3 nm, and the thickness of the wide bandgap layer 112 ranges from 5 nm to 20 nm, for example, 5 nm.

[0056] Furthermore, refer to Figure 2 As shown, the heterojunction active region 110 also includes an electron blocking layer 113 and a transition layer 114. The electron blocking layer 113 is made of a p-type semiconductor material and is used to provide hole carriers, preventing electrons from migrating through the active region and causing electron leakage. The material of the electron blocking layer 113 includes, but is not limited to, Mg-doped aluminum gallium nitride (Al₂O₃). 0.2 Ga 0.8 N), where the Mg doping concentration includes 1×10 19 cm -3 ~1×10 20 cm -3 For example, 8×10 19 cm -3 The thickness of the electron blocking layer 113 ranges from 10 nm to 20 nm, for example, 15 nm. The material of the transition layer 114 includes, but is not limited to, unintentionally doped GaN, and the thickness of the transition layer 114 ranges from 5 nm to 15 nm, for example, 10 nm. In the surface-emitting electro-optic chip structure, the heterojunction active region 110 includes a first emission surface and a second emission surface disposed opposite to each other, wherein the side containing the narrow bandgap layer 111 and the wide bandgap layer 112 is designated as the first emission surface, and the side containing the electron blocking layer 113 and the transition layer 114 is designated as the second emission surface.

[0057] In one embodiment, a first conductive layer 120 (also referred to as the upper conductive layer) is disposed on the first emitter surface of the heterojunction active region 110. The first conductive layer 120 is made of an electronically conductive n-type semiconductor material, for example, the first conductive layer 120 is made of silicon (Si) doped gallium nitride (n-GaN), wherein the Si doping concentration includes 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 For example, 1×10 19 cm -3 Optionally, the doping concentration of the first conductive layer 120 is non-uniform, wherein the doping concentration on the side closer to the heterojunction active region 110 is lower than that on the side farther from the heterojunction active region 110. Optionally, the first conductive layer 120 includes two n-GaN layers, wherein the doping concentration of the n-GaN layer on the side closer to the heterojunction active region 110 is lower than that on the side farther from the heterojunction active region 110. The thickness of the first conductive layer 120 ranges from 1 μm to 3 μm, for example, 2 μm.

[0058] Furthermore, the first conductive layer 120 includes a protruding optical waveguide confinement structure 121, which protrudes towards the side opposite to the heterojunction active region 110. The optical waveguide confinement structure 121 is used for optical field energy concentration. (Refer to...) Figure 1 As shown, since the surface of the optical waveguide confinement structure 121 is used to form the first reflector 140, the surface of the optical waveguide confinement structure 121 is a flat surface. Therefore, a raised platform is formed on the side of the first conductive layer 120 away from the heterojunction active region 110 as the optical waveguide confinement structure 121. The surface of the raised platform is parallel to the surface of the heterojunction active region 110. The surface of the raised platform is parallel to but not flush with the surface of other parts of the first conductive layer.

[0059] In one embodiment, the optical waveguide confinement structure 121 is used for optical field energy concentration. The thickness of the optical waveguide confinement structure 121 is greater than half the sum of the thicknesses of the first conductive layer 120, the heterojunction active region 110, and the second conductive layer 130. Specifically, the thickness of the optical waveguide confinement structure 121 ranges from 1 μm to 2 μm, for example, 1.8 μm. The shape of the optical waveguide confinement structure 121 includes a columnar shape, such as a cylinder or a quadrangular prism. The diameter of the optical waveguide confinement structure 121 ranges from 10 μm to 30 μm, for example, 20 μm. The projected area of ​​the optical waveguide confinement structure 121 does not exceed 80% of the projected area of ​​the heterojunction active region 110.

[0060] By forming an optical waveguide confinement structure 121, the optical field energy accumulated in the chip is concentrated in the central region of the optical waveguide confinement structure 121 by utilizing the optical confinement effect of the optical waveguide confinement structure 121. Furthermore, by utilizing the promoting effect of light on carrier recombination, the recombination of carriers is also concentrated and confined in the central region of the optical waveguide confinement structure 121, thereby further reducing ineffective recombination outside the optical waveguide confinement structure 121.

[0061] In one embodiment, a second conductive layer 130 (also referred to as a lower conductive layer) is disposed on the second emitter surface of the heterojunction active region 110. The second conductive layer 130 is made of a hole-conducting p-type semiconductor material, for example, Mg-doped gallium nitride (p-GaN), wherein the Mg doping concentration includes 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 For example, 1×10 20 cm -3The p-type ion doping concentration of the second conductive layer 130 is greater than that of the electron blocking layer 113. The thickness of the second conductive layer 130 ranges from 50 nm to 200 nm, for example, 100 nm. The thickness of the second conductive layer 130 is less than that of the first conductive layer 120, and the thickness of the second conductive layer 130 is greater than that of the electron blocking layer 113.

[0062] It should be noted that the first conductive layer 120 and the second conductive layer 130 should be respectively disposed on both sides of the heterojunction active region 110 to ensure that the current flows through the heterojunction active region 110 and avoid the first conductive layer 120 and the second conductive layer 130 from directly contacting each other and causing leakage.

[0063] In one embodiment, a first reflector 140 (also called an upper reflector) is disposed at least on the side of the optical waveguide confinement structure 121 opposite to the heterojunction active region 110. For example, on the side of the first conductive layer 120 opposite to the heterojunction active region 110, the area not covered by the first electrode 160 is covered by the first reflector 140. A second reflector 150 (also called a lower reflector) is disposed on the side of the second conductive layer 130 opposite to the heterojunction active region 110. For example, on the side of the second conductive layer 130 opposite to the heterojunction active region 110, the area not covered by the second electrode 170 is covered by the second reflector 150. To enable the first reflector 140 and the second reflector 150 to form an optical resonant cavity, the orthographic projections of the first reflector 140 and the second reflector 150 have at least an overlapping region. To ensure the effect of concentrated light field energy in the optical waveguide confinement structure 121, the orthographic projections of the first reflector 140 and the second reflector 150 both cover the orthographic projection of the optical waveguide confinement structure 121.

[0064] In one embodiment, both the first reflector 140 and the second reflector 150 are insulating reflectors. Specifically, both the first reflector 140 and the second reflector 150 are distributed Bragg reflectors composed of multiple periodic oxide dielectric layers made of insulating material, such as an Al2O3 / TiO2 distributed Bragg reflector. The thickness of Al2O3 is greater than the thickness of TiO2, with the Al2O3 thickness ranging from 50 nm to 100 nm (e.g., 75 nm) and the TiO2 thickness ranging from 20 nm to 70 nm (e.g., 50 nm). The thickness of the first reflector 140 is less than the thickness of the second reflector 150, and the number of Al2O3 / TiO2 overlapping layers in the first reflector 140 is less than the number of Al2O3 / TiO2 overlapping layers in the second reflector 150. For example, the first reflector 140 has 7 Al2O3 / TiO2 overlapping layers, and the second reflector 150 has 10 Al2O3 / TiO2 overlapping layers. By forming mirrors on both sides of the heterojunction active region 110, an optical resonant cavity is formed, thereby achieving effective accumulation of optical field energy.

[0065] In one embodiment, both the first electrode 160 (also referred to as the upper electrode) and the second electrode 170 (also referred to as the lower electrode) comprise metal electrodes. The first electrode 160 forms a first ohmic contact region by contacting the first conductive layer 120 ohms, and the second electrode 170 forms a first ohmic contact region by contacting the second conductive layer 130 ohms. (Refer to...) Figure 1 As shown, the orthographic projections (i.e., projections within the chip surface) of the first ohmic contact region and the second ohmic contact region are spatially staggered, meaning that the orthographic projections of the first ohmic contact region and the second ohmic contact region within the chip surface do not overlap. Furthermore, the distance between the orthographic projections of the first ohmic contact region and the second ohmic contact region is greater than 1 μm. In addition, there is no indium tin oxide (ITO) material layer between the first electrode 160, the second electrode 170, and the heterojunction active region 110.

[0066] Furthermore, the orthographic projections of the first ohmic contact region and the second ohmic contact region are isolated by the orthographic projection of the optical waveguide confinement structure 121. (Refer to...) Figure 3 As shown, the orthographic projections of the first ohmic contact area and the second ohmic contact area are symmetrically arranged on both sides of the orthographic projection of the optical waveguide confinement structure 121. Specifically, the orthographic projections of the first ohmic contact area and the second ohmic contact area are arranged axially symmetrically about the central axis of the optical waveguide confinement structure 121, and the orthographic projections of the first ohmic contact area and the second ohmic contact area form a fan-shaped ring. (Refer to...) Figure 4 As shown, the orthographic projections of the first and second ohmic contact areas are symmetrically arranged on both sides of the orthographic projection of the optical waveguide confinement structure 121. Specifically, the orthographic projections of the first and second ohmic contact areas are arranged axially symmetrically about the central axis of the optical waveguide confinement structure 121, and the orthographic projections of the first and second ohmic contact areas are square. Since increasing the area of ​​the first and second ohmic contact areas can alleviate the current load pressure on the electrodes, the area of ​​the orthographic projections of the first and second ohmic contact areas is greater than or equal to 20% of the orthographic projection area of ​​the optical waveguide confinement structure 121.

[0067] By employing an in-plane staggered electrode layout, an in-plane transport electric field for electrons and holes is constructed, achieving the effect that both electrons and holes drift towards the optical waveguide confinement structure 121 under forward bias. Simultaneously, most of the heterojunction active region 110 is confined within the projection of the optical waveguide confinement structure 121, significantly reducing ineffective recombination outside the optical waveguide confinement structure 121. Furthermore, by increasing the contact area between the electrode and the conductive region and reducing the effective recombination area, the current load pressure on the electrodes is significantly alleviated.

[0068] When fabricating heterojunction active regions using Al-Ga-In-N materials, the bulk resistivity is typically high due to its wide bandgap and strong polarization characteristics. Furthermore, the small difference in refractive index between heterojunction interfaces makes it difficult to form mirror structures with both high reflectivity and good conductivity. Therefore, insulating mirrors are usually used. However, chip structures using insulating mirrors often face the problem of insufficient in-plane current transport capability. As the current density in the resonant cavity region increases with the accumulation of optical field energy, the local current load on the electrodes easily approaches the material limit. If the generated heat cannot be dissipated in time, it can easily cause thermal damage to the electrodes or the electrode-semiconductor contact area, leading to device failure. To improve current transport, an additional indium tin oxide (ITO) layer is usually introduced as a current transport layer. However, ITO materials have a high light absorption rate, which is not conducive to the effective accumulation of optical field energy. Therefore, in this application, optical field energy is concentrated by forming an optical waveguide confinement structure 121, and the current load pressure of the electrodes is relieved by forming two electrodes that are isolated by the optical waveguide confinement structure. The thin film surface-emitting electro-optic chip structure does not contain indium tin oxide (ITO) material, thus getting rid of the dependence on ITO material, and at the same time realizing efficient in-plane current transmission and optical field energy accumulation.

[0069] This application provides a method for fabricating a thin-film planar electro-optic chip structure, referring to... Figure 5 as well as Figures 6A to 6G As shown, it includes the following steps:

[0070] Step S510: Provide a substrate;

[0071] Step S520: Sequentially form a first conductive layer, a heterojunction active region, a second conductive layer, and a second reflector on the substrate;

[0072] Step S530: Partially etch the second reflector until the surface of the second conductive layer is exposed;

[0073] Step S540: A second electrode is formed at the exposed surface of the second conductive layer, and the second electrode makes ohmic contact with the second conductive layer to form a second ohmic contact area;

[0074] Step S550: Remove the substrate to expose the first conductive layer;

[0075] Step S560: Etch the first conductive layer to form an optical waveguide confinement structure. The optical waveguide confinement structure protrudes to the side away from the active region of the heterojunction. The optical waveguide confinement structure is used for optical field energy concentration.

[0076] Step S570: Form a first reflector on the first conductive layer, wherein the first reflector at least covers the optical waveguide confinement structure;

[0077] Step S580: A first electrode is formed on the first conductive layer. The first electrode and the first conductive layer make ohmic contact to form a first ohmic contact area. The orthographic projections of the first ohmic contact area and the second ohmic contact area are isolated by the orthographic projection of the optical waveguide confinement structure.

[0078] First, execute step S510, referring to... Figure 6A As shown, a substrate 600 is provided.

[0079] In one embodiment, substrate 600 includes, but is not limited to, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a gallium arsenide substrate, a sapphire substrate, or a combination of the above substrates. Further, the embodiment includes the step of forming a buffer layer (not shown) on substrate 600. The buffer layer includes, but is not limited to, an oxide buffer layer or a nitride buffer layer, for example, silicon oxide formed on the surface of a silicon substrate as a buffer layer.

[0080] Next, proceed to step S520, referring to... Figure 6A As shown, a first conductive layer 120, a heterojunction active region 110, a second conductive layer 130, and a second reflector 150 are sequentially formed on a substrate 600.

[0081] In one embodiment, the first conductive layer 120 is made of an electronically conductive n-type semiconductor material, for example, the first conductive layer 120 is made of silicon (Si) doped gallium nitride (n-GaN), wherein the Si doping concentration includes 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 1×10 is preferred 19 cm -3 The thickness of the first conductive layer 120 ranges from 1 μm to 3 μm, for example, 2 μm. The method for forming the first conductive layer 120 includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMGa), a nitrogen source (e.g., NH3), and a Si dopant source (e.g., SiH4 or Si2H6) are transported into the reaction chamber via a carrier gas (e.g., H2 or N2) to deposit n-GaN on the surface of the substrate 600.

[0082] In one embodiment, refer to Figure 6A As shown, the material of the narrow bandgap layer 111 of the heterojunction active region 110 includes, but is not limited to, indium gallium nitride (InGaN). 0.25 Ga 0.75The thickness of the narrow bandgap layer 111 ranges from 2 nm to 10 nm, for example, 3 nm. The methods for forming the narrow bandgap layer 111 include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMIn and TMGa) and a nitrogen source (e.g., NH3) are transported into a reaction chamber via a carrier gas to deposit InGaN on the surface of the first conductive layer 120.

[0083] In one embodiment, refer to Figure 6A As shown, the material of the wide bandgap layer 112 of the heterojunction active region 110 includes, but is not limited to, gallium nitride (GaN), and the thickness of the wide bandgap layer 112 ranges from 5 nm to 20 nm, for example, 5 nm. The method for forming the wide bandgap layer 112 includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMGa) and a nitrogen source (e.g., NH3) are transported into the reaction chamber via a carrier gas (e.g., H2 or N2) to deposit GaN on the surface of the narrow bandgap layer 111.

[0084] In one embodiment, the heterojunction active region 110 includes at least overlapping narrow bandgap layers 111 and wide bandgap layers 112, with the narrow bandgap layers 111 and 112 overlapping to form a heterojunction. The heterojunction active region 110 includes at least two heterojunction layers. The steps of forming the narrow bandgap layer 111 and the wide bandgap layer 112 described above are repeated to form a multilayer heterojunction. Figure 6A In the example shown, the steps of forming the narrow bandgap layer 111 and the wide bandgap layer 112 are repeated for four cycles to form a four-layer heterojunction.

[0085] In one embodiment, the heterojunction active region 110 further includes an electron blocking layer 113. The electron blocking layer 113 is made of a p-type semiconductor material and is used to provide hole carriers, preventing electrons from migrating through the active region and causing electron leakage. The material of the electron blocking layer 113 includes, but is not limited to, Mg-doped aluminum gallium nitride (Al₂O₃). 0.2 Ga 0.8 N), where the Mg doping concentration includes 1×10 19 cm -3 ~1×10 20 cm -3 For example, 8×10 19 cm -3 The thickness of the electron blocking layer 113 ranges from 10 nm to 20 nm, for example, 15 nm. Methods for forming the electron blocking layer 113 include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMGa, TMAl, and Cp2Mg) and a nitrogen source (e.g., NH3) are transported into the reaction chamber via a carrier gas to deposit Mg-doped AlGaN on the surface of the wide gap layer 112.

[0086] In one embodiment, the heterojunction active region 110 further includes a transition layer 114. The material of the transition layer 114 includes, but is not limited to, unintentionally doped (UID) GaN, and the thickness of the transition layer 114 ranges from 5 nm to 15 nm, for example, 10 nm. The method for forming the transition layer 114 includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMGa) and a nitrogen source (e.g., NH3) are transported into the reaction chamber via a carrier gas. At this time, the flow rates of the n-type doping source (e.g., Si doping source) and the p-type doping source (e.g., Mg doping source) must be strictly shut off to deposit unintentionally doped GaN on the surface of the electron blocking layer 113.

[0087] In one embodiment, the second conductive layer 130 is a hole-conducting p-type semiconductor material, for example, the second conductive layer 130 is Mg-doped gallium nitride (p-GaN), wherein the Mg doping concentration includes 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 For example, 1×10 20 cm -3 The thickness of the second conductive layer 130 ranges from 50 nm to 200 nm, for example, 100 nm. The formation method of the second conductive layer 130 includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), in which a metal-organic source (e.g., TMGa and Cp2Mg) and a nitrogen source (e.g., NH3) are transported into the reaction chamber via a carrier gas to deposit p-GaN on the surface of the transition layer 114.

[0088] In one embodiment, the second reflector 150 is an insulating reflector, such as an Al2O3 / TiO2 distributed Bragg reflector. The method for forming the second reflector 150 includes, but is not limited to, atomic layer deposition (ALD), generating Al2O3 using an aluminum source (e.g., TMA) and an oxygen source (e.g., H2O or O3), and generating TiO2 using a titanium source (e.g., TiCl4) and an oxygen source (e.g., H2O or O3). The reflector comprises a multilayer Al2O3 / TiO2 overlapping structure, thus the steps of forming Al2O3 and TiO2 are repeatedly performed. For example, the steps of forming Al2O3 and TiO2 are repeated 10 times to form a second reflector 150 having a ten-layer Al2O3 / TiO2 overlapping structure.

[0089] Next, proceed to step S530, referring to... Figure 6B As shown, the second reflector 150 is partially removed until the surface of the second conductive layer 130 is exposed.

[0090] In one embodiment, a mask layer and a photoresist layer are formed on the second reflector 150. The mask layer can be either a nitride layer or an oxide layer, and the photoresist layer can be polyimide. Photolithography steps such as exposure and development are performed to form a patterned photoresist layer. Pattern transfer is then performed to form a patterned mask layer. Dry etching is then performed using the patterned mask layer as a mask to partially remove the second reflector 150 until the surface of the second conductive layer 130 is exposed. Figure 6B As shown, the removed portion of the second reflector 150 is located at the first end of the chip structure to form an opening at the first end of the chip structure.

[0091] Next, proceed to step S540, referring to... Figure 6C As shown, a second electrode 170 is formed on the exposed surface of the second conductive layer 130, and the second electrode 170 makes ohmic contact with the second conductive layer 130 to form a second ohmic contact area.

[0092] In one embodiment, the second electrode 170 comprises a metal electrode, such as copper or aluminum, and the method for forming the second electrode 170 includes, but is not limited to, at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and electrochemical deposition (ECD). Figure 6C In the example shown, the second electrode 170 not only fills the opening formed by removing the second reflector 150 and makes ohmic contact with the second conductive layer 130, but also covers the second reflector 150.

[0093] Next, proceed to step S550, referring to... Figure 6D As shown, the substrate 600 is removed to expose the first conductive layer 120.

[0094] In one embodiment, chemical mechanical polishing (CMP) is performed to completely remove the substrate 600 and the buffer layer (not shown) to fully expose the surface of the first conductive layer 120 on the side opposite to the heterojunction active region 110, and a polishing step is performed to process the surface of the first conductive layer 120.

[0095] Next, proceed to step S560, referring to... Figure 6E As shown, the first conductive layer 120 is etched to form an optical waveguide confinement structure 121. The optical waveguide confinement structure 121 protrudes to the side away from the heterojunction active region 110. The optical waveguide confinement structure 121 is used for optical field energy concentration.

[0096] In one embodiment, a mask layer and a photoresist layer are formed on the first conductive layer 120. The mask layer can be either a nitride layer or an oxide layer, and the photoresist layer can be polyimide. Photolithography steps such as exposure and development are performed to form a patterned photoresist layer. Pattern transfer is then performed to form a patterned mask layer. Dry etching is performed using the patterned mask layer as a mask to partially remove the first conductive layer 120, but a certain thickness of the first conductive layer 120 is retained in the etched area to avoid exposing the surface of the heterojunction active region 110. The etched area of ​​the first conductive layer 120 is located at the first and second ends of the chip structure, and the unetched area in the middle of the first conductive layer 120 becomes the optical waveguide confinement structure 121. Furthermore, the etching depth of the etched area of ​​the first conductive layer 120 can be different. Figure 6E In the example shown, the etching depth on both sides of the optical waveguide confinement structure 121 is greater than the etching depth at the second end of the chip structure. Specifically, when the etching depth on both sides of the optical waveguide confinement structure 121 is 1.8 μm, the height of the formed optical waveguide confinement structure 121 is 1.8 μm.

[0097] Next, proceed to step S570, referring to... Figure 6F As shown, a first reflector 140 is formed on the first conductive layer 120, and the first reflector 140 at least covers the optical waveguide confinement structure 121.

[0098] In one embodiment, the first reflector 140 is an insulating reflector, such as an Al2O3 / TiO2 distributed Bragg reflector. The method for forming the first reflector 140 includes, but is not limited to, atomic layer deposition (ALD), generating Al2O3 using an aluminum source (e.g., TMA) and an oxygen source (e.g., H2O or O3), and generating TiO2 using a titanium source (e.g., TiCl4) and an oxygen source (e.g., H2O or O3). The reflector comprises a multilayer Al2O3 / TiO2 overlapping structure, thus the steps of forming Al2O3 and TiO2 are repeatedly performed, for example, repeating the above steps of forming Al2O3 and TiO2 for seven cycles to form a first reflector 140 having a seven-layer Al2O3 / TiO2 overlapping structure.

[0099] After forming a first reflective mirror 140 that completely covers the first conductive layer 120, the process further includes a step of partially etching the first reflective mirror 140 until the surface of the first conductive layer 120 is exposed. Specifically, a photolithography process is performed on the first reflective mirror 140 to partially remove the first reflective mirror 140 until the surface of the first conductive layer 120 is exposed, such as... Figure 6F As shown, the removed portion of the first reflector 140 is located at the second end of the chip structure to form an opening at the second end of the chip structure. At this time, the remaining first reflector 140 not only covers the optical waveguide confinement structure 121, but also covers other areas of the first conductive layer 120 outside the opening.

[0100] Next, proceed to step S580, referring to... Figure 6G As shown, a first electrode 160 is formed on the first conductive layer 120. The first electrode 160 and the first conductive layer 120 form a first ohmic contact area. The orthographic projections of the first ohmic contact area and the second ohmic contact area are isolated by the orthographic projection of the optical waveguide confinement structure 121.

[0101] In one embodiment, the first electrode 160 includes a metal electrode, such as copper or aluminum, and the method for forming the first electrode 160 includes, but is not limited to, at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and electrochemical deposition (ECD). Figure 6G In the example shown, the first electrode 160 not only fills the opening formed by removing the first reflector 140 and making ohmic contact with the first conductive layer 120, but also covers a portion of the first conductive layer 120. By forming electrodes at the first and second ends of the chip structure, the orthographic projections (i.e., projections within the chip surface) of the formed first and second ohmic contact areas are spatially misaligned, meaning that the orthographic projections of the first and second ohmic contact areas within the chip surface do not overlap. Furthermore, the orthographic projections of the first and second ohmic contact areas are isolated by the orthographic projection of the optical waveguide confinement structure 121.

[0102] This concludes the introduction of the relevant steps in the fabrication method of the thin-film surface-emitting electro-optic chip structure according to the embodiments of the present invention. The process order of steps S570 and S580 can be adjusted according to the actual needs of the process operation. It is understood that the fabrication method of the thin-film surface-emitting electro-optic chip structure in this embodiment includes not only the above-described steps, but may also include other necessary steps before, during, or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0103] This application also provides a thin-film surface-emitting electro-optic chip, including the thin-film surface-emitting electro-optic chip structure described above.

[0104] This application also provides a circuit module, including the thin-film surface-emitting electro-optic chip described above.

[0105] According to the thin-film surface-emitting electro-optic chip structure and its fabrication method, thin-film surface-emitting electro-optic chip and circuit module provided in the embodiments of this application, by using an in-plane staggered electrode layout, combined with the channel transmission characteristics of the heterojunction active region and the optical field confinement mechanism of the columnar optical waveguide confinement structure, the chip's in-plane current transmission capability and optical field energy accumulation efficiency are effectively enhanced, the problem of high current load on the electrodes is alleviated, and the performance of the surface-emitting electro-optic chip is improved.

[0106] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to the process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0107] The above descriptions are merely embodiments of this application, which enable those skilled in the art to understand and implement this application. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A thin-film surface-emitting electro-optic chip structure, characterized in that, include: The heterojunction active region includes a first emitter surface and a second emitter surface that are disposed opposite to each other; A first conductive layer is disposed on the first emitting surface of the active region of the heterojunction. The first conductive layer includes a protruding optical waveguide confinement structure, which protrudes to the side away from the active region of the heterojunction. The optical waveguide confinement structure is used for optical field energy concentration. The second conductive layer is disposed on the second emission surface of the active region of the heterojunction, and the first conductive layer and the second conductive layer have different conductivity types. A first reflector is disposed at least on the side of the optical waveguide confinement structure away from the heterojunction active region; The second reflector is disposed on the side of the second conductive layer away from the active region of the heterojunction. The first electrode is in ohmic contact with the first conductive layer to form a first ohmic contact region; The second electrode forms a second ohmic contact region with the second conductive layer, and the orthographic projections of the first ohmic contact region and the second ohmic contact region are isolated by the orthographic projection of the optical waveguide confinement structure.

2. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The thickness of the optical waveguide confinement structure is greater than half the sum of the thicknesses of the first conductive layer, the heterojunction active region, and the second conductive layer.

3. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The shape of the optical waveguide confinement structure includes a columnar shape.

4. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The orthographic projections of the first ohmic contact area and the second ohmic contact area are symmetrically arranged on both sides of the orthographic projection of the optical waveguide confinement structure, and the orthographic projections of the first ohmic contact area and the second ohmic contact area are fan-shaped or square.

5. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The active region of the heterojunction includes at least overlapping narrow bandgap layers and wide bandgap layers, the bandgap difference between the narrow bandgap layer and the wide bandgap layer is greater than 0.5 eV, and the narrow bandgap layer is used for carrier transport.

6. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The first conductive layer is made of an n-type semiconductor material that conducts electrons, and the second conductive layer is made of a p-type semiconductor material that conducts holes.

7. The thin-film surface-emitting electro-optic chip structure according to claim 1, characterized in that, The area of ​​the orthographic projection of the first ohmic contact area and the second ohmic contact area is greater than or equal to 20% of the area of ​​the orthographic projection of the optical waveguide confinement structure.

8. A method for fabricating a thin-film surface-emitting electro-optic chip structure, characterized in that, Includes the following steps: Provide substrate; A first conductive layer, a heterojunction active region, a second conductive layer, and a second reflector are sequentially formed on the substrate. Partially remove the second reflector until the surface of the second conductive layer is exposed; A second electrode is formed on the exposed surface of the second conductive layer, and the second electrode makes ohmic contact with the second conductive layer to form a second ohmic contact area; Remove the substrate to expose the first conductive layer; The first conductive layer is etched to form an optical waveguide confinement structure, which protrudes toward the side opposite to the active region of the heterojunction, and the optical waveguide confinement structure is used for optical field energy concentration. A first reflector is formed on the first conductive layer, and the first reflector at least covers the optical waveguide confinement structure; A first electrode is formed on the first conductive layer, and the first electrode makes ohmic contact with the first conductive layer to form a first ohmic contact region. The orthographic projections of the first ohmic contact region and the second ohmic contact region are isolated by the orthographic projection of the optical waveguide confinement structure.

9. A thin-film surface-emitting electro-optic chip, characterized in that, The thin-film surface-emitting electro-optic chip structure includes any one of claims 1 to 7.

10. A circuit module, characterized in that, Includes the thin-film surface-emitting electro-optic chip as described in claim 9.

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