A charge-discharge management system compatible with multi-stage series battery cells

Abstract

The disclosure provides a charge-discharge management system compatible with multi-stage series battery cells, a main loop module includes a parallel sampling resistor group, a first parallel MOS tube group, a second parallel MOS tube group, and a first cascade control circuit and a second cascade control circuit; the parallel sampling resistor group is connected between the negative bus of the battery cell group and the charging side bus; the first parallel MOS tube group is connected to the charging side bus to provide a charging current channel for the charging side bus; the second parallel MOS tube group is connected to the discharging side bus to provide a discharging current channel for the discharging side bus; the first cascade control circuit controls the conduction of the first parallel MOS tube group according to the charge-discharge action signal of the AFE module; and the second cascade control circuit controls the conduction of the second parallel MOS tube group according to the charge-discharge action signal and the charging enable signal of the MCU module. The hardware level dynamic switching of the multi-stage series battery cells can be supported, the problems of poor compatibility and low efficiency of the traditional passive balancing are solved, and the high cost and complexity of the active balancing are avoided.

Description

Technical Field

[0001] This disclosure relates to the field of battery management system technology, and more specifically, to a charge and discharge management system compatible with multi-stage series-connected battery cells. Background Technology

[0002] With the widespread application of lithium battery technology, battery systems are developing towards higher integration, higher safety, and higher communication efficiency. In fields such as energy storage, electric vehicles, and portable devices, battery management systems (BMS) not only need to achieve real-time monitoring of cell voltage, current, and temperature, but also need to have effective control over the charging and discharging path, diagnosis and protection against circuit faults, and stability assurance for external communication interfaces. Against this backdrop, a BMS control circuit architecture with high integration, comprehensive functions, and simple wiring has become a key research and development focus.

[0003] Active balancing technology is a control method that transfers energy from high-voltage cells to low-voltage cells through energy transfer mechanisms (such as capacitors, inductors, or DC-DC converters) to achieve voltage consistency in a battery pack. Passive balancing technology is a control method that dissipates energy from excessively high-voltage cells in a battery pack through resistive discharge to achieve voltage consistency between cells.

[0004] In existing active balancing methods, the complex circuitry and high-precision components result in costs far exceeding those of passive balancing, making them difficult to apply in cost-sensitive fields such as consumer electronics. High-performance active balancing solutions (such as DC-DC converters) are typically optimized for a fixed number of stages, and adapting to dynamic stages requires sacrificing efficiency or adding redundant designs. High-frequency switching operations and energy transfer processes generate additional heat, necessitating a cooling system, further increasing size and complexity. Meanwhile, existing passive balancing methods suffer from poor compatibility with dynamic stages. Summary of the Invention

[0005] This disclosure provides at least one charging and discharging management system compatible with multi-level series-connected battery cells, which can support hardware-level dynamic switching of multi-level series-connected battery cells. It solves the problems of poor compatibility and low efficiency of traditional passive balancing, while avoiding the high cost and complexity of active balancing, filling the technical gap of low-cost and highly flexible battery management solutions.

[0006] This disclosure provides a charge and discharge management system compatible with multi-level series-connected battery cells, including: a main circuit module, an AFE module, and an MCU module connected to the main circuit module and the AFE module respectively;

[0007] The main circuit module includes a parallel sampling resistor group, a first parallel MOSFET group, a second parallel MOSFET group, a first cascaded control circuit, and a second cascaded control circuit.

[0008] The parallel sampling resistor group is connected between the negative terminal bus of the battery cell group and the charging side bus.

[0009] The first parallel MOSFET group is connected to the charging side bus, providing multiple charging current channels for the charging side bus; the second parallel MOSFET group is connected to the discharging side bus, providing multiple discharging current channels for the discharging side bus.

[0010] The first cascaded control circuit controls the first parallel MOS transistor group to turn on based on the charging and discharging action signal of the AFE module; the second cascaded control circuit controls the second parallel MOS transistor group to turn on based on the charging and discharging action signal of the AFE module and the charging enable signal of the MCU module.

[0011] In one optional implementation, the AFE module includes: an AFE chip and a plurality of sub-sampling circuits, each of the sub-sampling circuits being connected to a voltage sampling input port of the AFE chip;

[0012] Each of the sub-sampling circuits is connected to a battery cell and is used to collect the sampling voltage of the battery cell and feed it back to the AFE chip through the voltage sampling input port;

[0013] The AFE chip is used to generate the charging and discharging action signal according to the function trigger signal of the MCU module.

[0014] In one optional implementation, the first cascaded control circuit includes: a first transistor and a second transistor;

[0015] The base of the first transistor is connected to the AFE module to receive the charging and discharging action signal, the collector is connected to the charging side bus, and the emitter is connected to the base of the second transistor.

[0016] The emitter of the second transistor is connected to the gate of each first MOS transistor in the first parallel MOS transistor group, and the collector is connected to the charging side bus.

[0017] In one optional embodiment, the second cascaded control circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0018] The base of the third transistor is connected to the MCU module to receive the charging enable signal, the emitter is grounded, and the collector is connected to the base of the fourth transistor.

[0019] The emitter of the fourth transistor is connected to the AFE module to receive the charging and discharging action signal, and the collector is connected to the emitter of the fifth transistor.

[0020] The collector of the fifth transistor is connected to the discharge side bus, and the base is connected to the emitter of the sixth transistor. The connection node between the emitter and the collector of the fourth transistor is connected to the gate of each second MOS transistor in the second parallel MOS transistor group.

[0021] The collector and base of the sixth transistor are both connected to the discharge side bus.

[0022] In one optional implementation, for each first MOS transistor in the first parallel MOS transistor group, the charging current channel is formed by connecting the source and drain of the first MOS transistor.

[0023] For each second MOS transistor in the second parallel MOS transistor group, the discharge current channel is formed by connecting the source and drain of the second MOS transistor.

[0024] In one optional implementation, the sub-sampling circuit includes a sampling resistor, a seventh transistor, and a filter capacitor;

[0025] For any two adjacent first and second cells in the cell group, the sampling resistors are respectively set on the sampling channel between the first cell and the AFE chip, and on the sampling channel between the second cell and the AFE chip;

[0026] The filter capacitor and the seventh transistor are connected between adjacent sampling channels;

[0027] The collector of the seventh transistor is connected to the series node between the first battery cell and the corresponding sampling resistor, the emitter is connected to the series node between the second battery cell and the corresponding sampling resistor, and the base is connected to the series node between the sampling resistor of the second battery cell and the AFE chip.

[0028] In one optional implementation, the system further includes a communication module, which includes a serial communication unit, a one-line communication unit, a charger activation unit, a load activation unit, and a communication status detection unit.

[0029] The serial communication unit includes a data transmission line and a data reception line, which are connected between the MCU module and the external device to realize bidirectional data exchange between the MCU module and the external device;

[0030] The one-line communication unit includes a one-line communication protocol line equipped with a first optocoupler and a second optocoupler, which is connected between the MCU module and the external device to realize bidirectional signal isolation transmission between the MCU module and the external device;

[0031] The charger activation unit is connected to the MCU module and is used to detect whether a charger is connected, and generate a charger activation signal to be sent to the MCU module when a charger is connected.

[0032] The load activation unit is connected to the MCU module and is used to detect whether a load is connected, and generate a load activation signal to be sent to the MCU module when a load is connected.

[0033] The communication status detection unit is connected to the MCU module and is used to detect whether the external device is connected, and whether the communication status of the serial communication unit and the one-line communication unit is normal. Based on the monitoring results, it sends a communication status detection signal to the MCU module.

[0034] In one optional implementation, under the discharge function, the load activation unit generates a high-level load activation signal and sends it to the MCU module when it detects a load connection;

[0035] After receiving the load activation signal, the MCU module outputs the function trigger signal to the AFE module to trigger the AFE module to generate the charging and discharging action signal and input it to the first cascaded control circuit and the second cascaded control circuit.

[0036] The first cascaded control circuit and the second cascaded control circuit control the first parallel MOSFET group and the second parallel MOSFET group to conduct according to the charging and discharging action signal, so as to complete the discharging action.

[0037] In one optional implementation, during the charging function, the charger activation unit generates a high-level charger activation signal and sends it to the MCU module when it detects a load connection.

[0038] After receiving the charger activation signal, the MCU module outputs the charging enable signal to the second parallel MOS transistor group and outputs the function trigger signal to the AFE module to trigger the AFE module to generate the charging and discharging action signal input to the first cascaded control circuit and the second cascaded control circuit.

[0039] The first cascaded control circuit controls the first parallel MOSFET group to turn on according to the charging and discharging action signal, and the second cascaded control circuit controls the second parallel MOSFET group to turn on according to the charging enable signal and the charging and discharging action signal, thereby completing the charging action.

[0040] In one optional implementation, the one-line communication unit further includes a bus detection sub-circuit and a drive enable sub-circuit;

[0041] The bus detection sub-circuit is connected between the first optocoupler and the MCU module, and is used to detect the current level status of the one-wire communication bus;

[0042] The drive enable sub-circuit is connected between the second optocoupler and the MCU module, and is used to receive the one-wire communication drive signal sent by the MCU module to initiate communication on the one-wire communication bus;

[0043] The connection node between the first optocoupler and the second optocoupler is connected to the one-wire communication bus.

[0044] This disclosure provides a charge / discharge management system compatible with multi-stage series-connected battery cells, comprising: a main circuit module, an AFE module, and an MCU module connected to the main circuit module and the AFE module respectively; the main circuit module includes a parallel sampling resistor group, a first parallel MOSFET group, a second parallel MOSFET group, a first cascade control circuit, and a second cascade control circuit; the parallel sampling resistor group is connected between the negative terminal bus of the battery cell group and the charging side bus; the first parallel MOSFET group is connected to the charging side bus, providing multiple charging current channels for the charging side bus; the second parallel MOSFET group is connected to the discharging side bus, providing multiple discharging current channels for the discharging side bus; the first cascade control circuit controls the first parallel MOSFET group to conduct according to the charge / discharge action signal of the AFE module; the second cascade control circuit controls the second parallel MOSFET group to conduct according to the charge / discharge action signal of the AFE module and the charging enable signal of the MCU module. It supports hardware-level dynamic switching of multi-level series-connected cells, solving the problems of poor compatibility and low efficiency of traditional passive balancing, while avoiding the high cost and complexity of active balancing, filling the technological gap of low-cost and highly flexible battery management solutions.

[0045] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0047] Figure 1This diagram illustrates a structural schematic of a charge and discharge management system compatible with multi-stage series-connected battery cells provided in an embodiment of this disclosure.

[0048] Figure 2 A schematic diagram of the structure of a main circuit module provided in an embodiment of this disclosure is shown;

[0049] Figure 3 A schematic diagram of the structure of an AFE module provided in an embodiment of this disclosure is shown;

[0050] Figure 4 A schematic diagram of the structure of a one-line communication unit provided in an embodiment of this disclosure is shown;

[0051] Figure 5 A schematic diagram of the structure of a charger activation unit provided in an embodiment of this disclosure is shown;

[0052] Figure 6 A schematic diagram of the structure of a load activation unit provided in an embodiment of this disclosure is shown;

[0053] Figure 7 This diagram illustrates the structure of a serial communication unit provided in an embodiment of the present disclosure.

[0054] Figure 8 A schematic diagram of the structure of a communication status detection unit provided in an embodiment of this disclosure is shown;

[0055] Figure 9 A schematic diagram of the structure of an MCU module provided in an embodiment of this disclosure is shown;

[0056] Figure 10 A schematic diagram of the structure of a power module provided in an embodiment of this disclosure is shown. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0058] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0059] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0060] Research has revealed that existing active balancing methods, with their complex circuits and high-precision components, result in costs far exceeding those of passive balancing, making them unsuitable for cost-sensitive fields such as consumer electronics. High-performance active balancing solutions (such as DC-DC converters) are typically optimized for a fixed number of stages, and adapting to dynamic stages requires sacrificing efficiency or adding redundant designs. High-frequency switching operations and energy transfer processes generate additional heat, necessitating a cooling system and further increasing size and complexity. Meanwhile, existing passive balancing methods suffer from poor compatibility with dynamic stages.

[0061] Based on the above research, this disclosure provides a charge and discharge management system compatible with multi-level series-connected battery cells, including: a main circuit module, an AFE module, and an MCU module connected to the main circuit module and the AFE module respectively; the main circuit module includes a parallel sampling resistor group, a first parallel MOSFET group, a second parallel MOSFET group, a first cascade control circuit, and a second cascade control circuit; the parallel sampling resistor group is connected between the negative terminal bus of the battery cell group and the charging side bus; the first parallel MOSFET group is connected to the charging side bus, providing multiple charging current channels for the charging side bus; the second parallel MOSFET group is connected to the discharging side bus, providing multiple discharging current channels for the discharging side bus; the first cascade control circuit controls the first parallel MOSFET group to conduct according to the charge and discharge action signal of the AFE module; the second cascade control circuit controls the second parallel MOSFET group to conduct according to the charge and discharge action signal of the AFE module and the charging enable signal of the MCU module. It supports hardware-level dynamic switching of multi-level series-connected cells, solving the problems of poor compatibility and low efficiency of traditional passive balancing, while avoiding the high cost and complexity of active balancing, filling the technological gap of low-cost and highly flexible battery management solutions.

[0062] To facilitate understanding of this embodiment, a detailed description of a charge and discharge management system compatible with multi-stage series-connected battery cells, as disclosed in this disclosure, will be provided first. (See [link to relevant documentation]). Figure 1The diagram shown is a structural schematic of a charge and discharge management system compatible with multi-stage series-connected battery cells provided in an embodiment of this disclosure.

[0063] like Figure 1 As shown, the charge and discharge management system compatible with multi-level series cells includes: a main circuit module, an AFE module, an MCU module, and a communication module. The MCU module is bidirectionally connected to the AFE module and the communication module. The main circuit module is controlled by the MCU module and the AFE module to realize the charging and discharging functions. The MCU module communicates with external devices through the communication module.

[0064] For details, see Figure 2 The diagram shown is a structural schematic of a main circuit module provided in an embodiment of this disclosure. The main circuit module includes a parallel sampling resistor group; a first parallel MOSFET group, a second parallel MOSFET group, a first cascade control circuit, and a second cascade control circuit.

[0065] Here, the parallel sampling resistor group includes multiple sampling resistors R94, R100, R102, R105, R109, and R113 connected in parallel, between the negative bus of the battery cell group and the charging bus. The first parallel MOSFET group is connected to the charging bus, and the multiple first MOSFETs Q24, Q27, Q30, and Q32 included therein provide multiple charging current paths for the charging bus. The second parallel MOSFET group is connected to the discharging bus, and the multiple second MOSFETs Q25, Q28, Q31, and Q33 included therein provide multiple discharging current paths for the discharging bus.

[0066] In this parallel sampling resistor group, the sampling resistors R94, R100, R102, R105, and R109 can be 2mΩ precision resistors. Using six 2mΩ precision resistors in parallel for current sampling reduces the total resistance to approximately 0.333mΩ, significantly reducing the voltage drop during current flow and thus lowering the power loss of the sampling resistors, improving system efficiency. Each sampling resistor only bears 1 / 6 of the total current, greatly reducing the heat generated by a single resistor. Distributed heat reduces local temperature rise, preventing resistance drift or damage due to overheating, thus improving long-term stability. Multiple resistors share the total power, multiplying the overall power capacity. For example, if the total current is 300A, a single resistor only needs to withstand 50A, with a power of 5W (6 resistors totaling 30W), while a single resistor solution would need to withstand 180W, far exceeding the tolerance range of conventional resistors. The parallel structure averages the manufacturing error of individual resistors (e.g., ±1%), keeping the relative error of the total resistance the same as that of a single resistor, but with a smaller absolute error. Meanwhile, the effects of temperature changes on each sampling resistor may compensate for each other, further improving resistance stability. Furthermore, the parallel connection of multiple sampling resistors provides redundancy, ensuring the system can continue operating even if a single sampling resistor fails, thus enhancing the fault tolerance of the BMS.

[0067] It should be noted that the number of sampling resistors in the parallel sampling resistor group can be set according to actual needs, and no specific limit is set here.

[0068] Furthermore, the first parallel MOSFET group uses four first MOSFETs (Q24, Q27, Q30, Q32) connected in parallel, and the second parallel MOSFET group uses four second MOSFETs (Q25, Q28, Q31, Q33) connected in parallel. With this parallel configuration, the total on-resistance is 1 / 4 of the RDS(on) of a single MOSFET. For example, if the RDS(on) of a single MOSFET is 1mΩ, the total resistance after four parallel connections drops to 0.25mΩ. Power loss during current flow is significantly reduced, especially in high-current charging and discharging scenarios (such as 300A), which can greatly improve system efficiency. Each MOSFET only bears 1 / 4 of the total current, reducing the heat generated by individual devices and avoiding performance degradation or failure caused by localized high temperatures.

[0069] It should be noted that, for each of the first MOSFETs Q24, Q27, Q30, and Q32 in the first parallel MOSFET group, a charging current path is formed by the conduction of the source and drain of the first MOSFET Q24 / Q27 / Q30 / Q32; for each of the second MOSFETs Q25, Q28, Q31, and Q33 in the second parallel MOSFET group, a discharging current path is formed by the conduction of the source and drain of the second MOSFET Q25 / Q28 / Q31 / Q33.

[0070] In practical implementation, the charging-side bus is connected to the negative terminal of the battery cell assembly, and the discharging-side bus is connected to the load terminal. The charging-side bus and the discharging-side bus are connected through multiple charging current channels and discharging current channels formed by a first parallel MOSFET group and a second parallel MOSFET group. The first parallel MOSFET group controls the opening and closing of the battery's external discharge path. Multiple parallel first MOSFETs Q24, Q27, Q30, and Q32 carry large currents and are driven by a first cascaded control circuit. The second parallel MOSFET group controls the path from the external charger to the battery. Multiple parallel second MOSFETs Q25, Q28, Q31, and Q33 carry large currents and are driven by a second cascaded control circuit.

[0071] Here, the first cascaded control circuit includes: a first transistor Q35 and a second transistor Q37; the base of the first transistor Q35 is connected to the AFE module to receive charging and discharging operation signals, the collector is connected to the charging side bus, and the emitter is connected to the base of the second transistor Q37; the emitter of the second transistor Q37 is connected to the gate of each of the first MOSFETs Q24, Q27, Q30, and Q32 in the first parallel MOSFET group, and the collector is connected to the charging side bus. The second cascaded control circuit includes: a third transistor Q36, a fourth transistor Q34, a fifth transistor Q29, and a sixth transistor Q26; the base of the third transistor Q36 is connected to the MCU module to receive the charging enable signal, its emitter is grounded, and its collector is connected to the base of the fourth transistor Q34; the emitter of the fourth transistor Q34 is connected to the AFE module to receive the charging and discharging action signal, and its collector is connected to the emitter of the fifth transistor Q29; the collector of the fifth transistor Q29 is connected to the discharge side bus, and its base is connected to the emitter of the sixth transistor Q26; the connection node between the emitter and the collector of the fourth transistor Q34 is respectively connected to the gate of each of the second MOSFETs Q25, Q28, Q31, and Q33 in the second parallel MOSFET group; both the collector and base of the sixth transistor Q26 are connected to the discharge side bus.

[0072] Among them, the base of the first transistor Q35 is controlled by the DFET signal as the charging and discharging action signal of the AFE module, the base of the third transistor Q36 is controlled by the CHG_EN signal as the charging enable signal of the MCU module, and the emitter of the fourth transistor Q34 is controlled by the CFET signal as the charging and discharging action signal of the AFE module.

[0073] In practical applications, this embodiment achieves effective driving of the first parallel MOS transistor group and the second parallel MOS transistor group through a two-level cascaded control structure, ensuring good response speed, electrical isolation and safety under different operating modes.

[0074] Here, when the system detects the need for discharge (e.g., load startup), the AFE module sends a DFET signal, which controls the first transistor Q35 to turn on. The base of Q35 receives a high-level DFET signal, triggering its conduction. Its collector is connected to the charging-side bus, and its emitter transfers current to the base of the second transistor Q37. Q37 then turns on after receiving the base current from Q35. Its collector is also connected to the charging-side bus, and its emitter is connected to the gates of all the first MOSFETs Q24, Q27, Q30, and Q32 in the first parallel MOSFET group. After Q37 turns on, it provides a stable gate drive voltage (originating from the charging-side bus) to the first MOSFETs Q24, Q27, Q30, and Q32, thereby turning on the first parallel MOSFET group. Once the first MOSFET group is on, the current from the negative terminal of the battery pack (connected to the charging-side bus) flows through these MOSFETs to the discharge-side bus, thus supplying power to the load. In this structure, the driving capability can be enhanced by using a two-stage cascaded transistor method, while the parallel structure of MOSFETs can be used to improve the system discharge capability and reduce voltage drop and power consumption.

[0075] Here, when the system detects a need for charging (e.g., connecting a charger), the MCU module outputs a CHG_EN signal to control the third transistor Q36 to turn on. When CHG_EN is high, the base of Q36 is energized and conducts, and the collector outputs current to the base of the fourth transistor Q34. Whether Q34 turns on or off is controlled by the CFET signal received at its emitter, which also comes from the AFE module and is used to indicate whether charging is allowed. If CFET is high, Q34 turns on, and its collector generates current to drive the emitter of the fifth transistor Q29. After Q29 turns on, its collector is connected to the discharge side bus, and the emitter current flows to the node connecting the gates of all the second MOSFETs Q25, Q28, Q31, and Q33 in the second parallel MOSFET group. At this node, the sixth transistor Q26 acts as a clamp and isolation device, with its emitter connected to the base of Q29 and its collector and base connected in parallel to the discharge side bus to prevent abnormal triggering of the MOSFETs. The above control process ensures that the second MOSFET group will only conduct when both CHG_EN and CFET are active, thus guaranteeing the safety and controllability of the charging path.

[0076] In this embodiment, the charging path control is driven collaboratively by the MCU and AFE. Both CHG_EN and CFET signals must be high to ensure that the system is in a charging-allowed state and to prevent false charging caused by single-point faults. This is especially suitable for driving multiple parallel power MOS under high current conditions. Different numbers of MOS can be designed to be connected in parallel according to the system load capacity to improve conduction capability and heat dissipation balance. Through the control signals of AFE and MCU, the propagation of control failure between different modules can be isolated. Q26 ensures that the MOS gate will not be falsely turned on in case of abnormal triggering or undervoltage.

[0077] For example, in an electric vehicle or energy storage device, during the discharge start-up process, the system detects the load connection, the AFE outputs a DFET signal → Q35 and Q37 cascade conduct → MOS group Q24 and others conduct → battery discharge is completed; during the charging connection process, the charger is inserted, the MCU controls CHG_EN to be valid, the AFE outputs a CFET signal → Q36, Q34, and Q29 cascade conduct → MOS group Q25 and others conduct → charging path closure is completed.

[0078] For details, see Figure 3 The diagram shown is a structural schematic of an AFE module provided in an embodiment of this disclosure. The AFE module includes: an AFE chip U1 and multiple sub-sampling circuits; each sub-sampling circuit is connected to a battery cell B0-B16 and is used to collect the sampling voltage of the battery cell and feed it back to the AFE chip U1; the AFE chip U1 is used to generate charging and discharging action signals DFET and CFET signals according to the function trigger signal of the MCU module.

[0079] Here, for any two adjacent first and second cells in the cell group, sampling resistors are respectively set on the sampling channel between the first cell and the AFE chip U1, and on the sampling channel between the second cell and the AFE chip U1; a filter capacitor and a seventh transistor are connected between adjacent sampling channels; the collector of the seventh transistor is connected to the series node between the first cell and the corresponding sampling resistor, the emitter is connected to the series node between the second cell and the corresponding sampling resistor, and the base is connected to the series node between the sampling resistor of the second cell and the AFE chip U1.

[0080] like Figure 3 As shown, for cells B0-B16, cells B8 and B7 are adjacent first and second cells, respectively, with cell B8 being the first cell and cell B7 being the second cell. Similarly, cells B7 and B6 are adjacent first and second cells, with cell B7 being the first cell and cell B6 being the second cell. For ease of understanding, the following explanation uses cell B8 as the first cell and cell B7 as the second cell as an example to illustrate the AFE module. The implementation methods for other cells can be referenced from those for cells B8 and B7, and will not be elaborated upon here.

[0081] Here, for the first battery cell B8 and the second battery cell B7, the sub-sampling circuit includes sampling resistors R1 and R11, a seventh transistor Q1, and a filter capacitor C1; sampling resistor R1 is set in the sampling channel between the first battery cell B8 and the AFE chip U1, and sampling resistor R11 is set in the sampling channel between the second battery cell B7 and the AFE chip U1; filter capacitor C1 and the seventh transistor Q1 are connected between adjacent sampling channels; the collector of the seventh transistor Q1 is connected to the series node between the first battery cell B8 and the corresponding sampling resistor R1, the emitter is connected to the series node between the second battery cell B7 and the corresponding sampling resistor R11, and the base is connected to the series node between the sampling resistor R11 of the second battery cell B7 and the AFE chip U1.

[0082] In this circuit, the positive terminal of cell B8 is connected in series with the sampling resistor R1, and the other end of R1 is connected to the corresponding voltage sampling pin of AFE chip U1. Cell B7 is connected in the same way, via the sampling resistor R11 to AFE chip U1. One end of the filter capacitor C1 is connected to the connection node between R1 and cell B8, and the other end is connected to the connection node between R11 and cell B7. This is used to form a horizontal low-pass filter branch between two adjacent cells to suppress voltage jumps and high-frequency noise. Transistor Q1 adopts an NPN transistor structure, with its collector connected to the cell B8 side, its emitter connected to the cell B7 side, and its base connected to the node between R11 and AFE chip U1.

[0083] During normal operation, if the voltage of cell B8 is higher than that of B7, and the voltage difference between the two cells is large, transistor Q1 will automatically turn on under the condition that V_BE is met, thus balancing the current and effectively mitigating overvoltage at the AFE input. During conduction, Q1 essentially acts as a voltage buffer, effectively mitigating transient imbalances caused by wiring, thermal disturbances, and cell self-discharge in large-scale series sampling systems. Simultaneously, C1 and Q1 form a buffer network, providing a soft-coupled anti-impact mechanism for the AFE, further enhancing the system's anti-interference capability under pulsed loads and cell oscillation scenarios.

[0084] Thus, with the above structure, only one Q1 and one C1 need to be configured for any two adjacent cell channels to complete the series sampling module structure design of the entire cell group. In practical applications, cells B8~B0 sequentially form 16 sub-sampling channels, and multiple Q1s and multiple C1s are daisy-chained through the voltage sampling path of the entire cell stack, greatly reducing voltage measurement offset and channel interference.

[0085] Meanwhile, the AFE chip U1 polls the voltage of each channel through its internally integrated ADC channel and outputs the current DFET and CFET signals during the communication time slot triggered by the MCU module. These signals are used to control the battery pack's discharge and charging states, respectively. The above signal logic is received through the main control MCU pins, thereby achieving coordinated control and logical judgment of the entire system.

[0086] Here, the AFE chip U1 is responsible for accurately acquiring, filtering, and outputting voltage information from multiple series-connected cells, as well as issuing signals to control the charging and discharging status. The AFE chip U1 can be an integrated battery monitoring chip, such as BQ40390RSMR, SH3676016, or any AFE chip that supports multi-channel voltage sampling and discharge control pin output.

[0087] Among them, the AFE chip U1 has multiple voltage sampling input ports (VC0-VCn). Each port is connected to the connection node between adjacent cells in the cell group through a sampling channel. Voltage attenuation and noise suppression are achieved through precision sampling resistors and filtering networks.

[0088] Specifically, for cells B0 to B16, there are a total of 17 voltage sampling points. Each sampling input is periodically polled and collected in the internal ADC of the AFE chip U1. The collected voltage data can be used for anomaly detection (such as overvoltage, undervoltage), equalization control and subsequent status judgment. The AFE chip U1 can integrate an independent temperature detection module, current detection interface (such as SRP / SRN) and CRC verification mechanism to ensure highly reliable cell group status assessment.

[0089] It should be noted that the AFE chip U1 employs passive balancing technology, is compatible with multi-level series-connected cells, and uses a threshold voltage comparator and balancing resistor array to monitor the voltage differences of each cell in real time. It then performs discharge shunt on the high-voltage cells to achieve voltage consistency control. Taking a 16-level series-connected cell configuration as an example, it integrates a 16-channel independent ADC with 16-bit resolution, supporting voltage measurement accuracy of ±1mV. Each channel is configured with an independent sample-and-hold circuit to ensure real-time synchronous sampling during dynamic charging and discharging of the battery pack (such as acceleration / braking of an electric vehicle), avoiding voltage misjudgment due to timing deviations. It supports cascading up to three SH3676016 chips to manage 48 series-connected cells (total voltage up to 200V+). During cascading, the master chip synchronizes data from the slave chips via the SPI bus, with a communication delay of <2ms, ensuring the global state consistency of the high-voltage battery pack.

[0090] The AFE chip U1 has at least two logic output pins for controlling the on / off state of the main circuit: a DFET pin for controlling the opening or closing of the charging current channel, and a CFET pin for controlling the conduction state of the discharging current channel. The DFET and CFET signals can be directly output to the base control terminals of the cascaded transistor drive circuit in the main circuit, such as the emitters of Q35 and Q34 mentioned above, to drive the gates of the first and second MOS transistor groups to be on.

[0091] In practical implementation, for dynamic thresholds, the MCU feeds back the battery pack stage (e.g., 12S or 16S) and ambient temperature to adjust the equalization trigger threshold in real time (e.g., reducing the 0V threshold by 0.05V in high-temperature environments to prevent thermal runaway). Each channel is connected to an external current-sharing resistor (10Ω / 2W) and a low-resistance MOSFET (Rds(on) < 5mΩ), supporting equalization currents of 100mA~300mA. PWM duty cycle control (frequency 1kHz~10kHz) is used to achieve a balance between energy loss and equalization speed.

[0092] For example, when the cell voltage difference is >50mV, equalization is performed at full speed with a 100% duty cycle (300mA); when the voltage difference is <20mV, equalization is performed at low speed with a 30% duty cycle (90mA) to reduce ineffective discharge.

[0093] Meanwhile, the AFE chip U1 incorporates a built-in equalization queue management logic, prioritizing the processing of cells with the largest voltage deviations and shortening the overall equalization time (40% more efficient than traditional polling strategies). Each channel is equipped with a hardware comparator with two preset threshold levels. For the base threshold, fixed OV / UV protection values ​​are set according to the cell type (e.g., NMC, LiFePO4) (e.g., NMC cell OV=4.25V±5mV, UV=2.8V±5mV).

[0094] Furthermore, the communication module includes a serial communication unit, a one-line communication unit, a charger activation unit, a load activation unit, and a communication status detection unit, see [link to relevant documentation]. Figures 4-8 As shown, Figure 4 A schematic diagram of the structure of a one-line communication unit provided in an embodiment of this disclosure is shown; Figure 5 A schematic diagram of the structure of a charger activation unit provided in an embodiment of this disclosure is shown; Figure 6 A schematic diagram of the structure of a load activation unit provided in an embodiment of this disclosure is shown; Figure 7 A schematic diagram of the structure of a serial communication unit provided in an embodiment of this disclosure is shown.

[0095] like Figure 4As shown, the one-line communication unit includes a one-line communication protocol line with a first optocoupler U6 and a second optocoupler U5, connected between the MCU module and an external device to achieve bidirectional signal isolation transmission between the MCU module and the external device; it also includes a bus detection sub-circuit and a drive enable sub-circuit; the bus detection sub-circuit is connected between the first optocoupler and the MCU module to detect the current level state of the one-line communication bus; the drive enable sub-circuit is connected between the second optocoupler and the MCU module to receive the one-line communication drive signal sent by the MCU module to initiate communication on the one-line communication bus; the connection node between the first optocoupler and the second optocoupler is connected to the one-line communication bus.

[0096] Here, the one-wire communication line serves as the data transmission channel between the MCU module and external devices. This line employs a 1-Wire design, enabling bidirectional communication via a single signal line. To ensure system electrical safety and interference immunity, an optocoupler isolation protection structure is installed on this line.

[0097] The first optocoupler U6 (model LTV217TP1B-VG) is configured in the data receiving path from the external device to the MCU. Its input is connected to the one-wire communication bus on the external device side, and its output is connected to the receiving channel OW_RX of the MCU module. Its function is to perform opto-isolation and signal shaping on the single-wire signal transmitted from the external device before sending it to the MCU, so as to avoid damage to the MCU from high voltage crosstalk or surge interference.

[0098] The second optocoupler U5 (also model LTV217TP1B-VG) is positioned in the path where the MCU sends drive signals to the outside. Its input receives the drive control signal OW_EN from the MCU, and its output connects to the one-wire communication bus OW. It converts the MCU's low-voltage TTL drive signal into a standard one-wire level signal and provides optical isolation to protect external devices. The two optocouplers are connected to the one-wire communication bus OW via a common node, achieving bidirectional communication link isolation and protection between the MCU and external devices.

[0099] In practical applications, the bus detection sub-circuit is connected between the output of the first optocoupler U6 and the MCU module. It mainly consists of pull-up resistors, capacitors, and logic gates, and is used to detect the real-time level of the one-wire communication bus, thereby determining whether the bus is currently idle, active low, or occupied. It also provides pre-communication conflict detection (e.g., confirming bus high before communication) and allows the MCU to decide whether to initiate communication based on the detected status (avoiding conflicts). The drive enable sub-circuit is connected between the input of the second optocoupler U5 and the MCU module, and mainly consists of a control switch (such as a MOS or transistor), a drive current limiting resistor, and a signal amplifier or gate isolation structure. Its function is to pull down the input of the second optocoupler U5 when the MCU needs to actively send data, triggering the optocoupler to conduct and outputting a signal to the one-wire communication bus, thus achieving active drive. This drive action must be triggered only after the bus is detected as idle to avoid bus signal conflicts.

[0100] For example, when an external device sends data to the MCU, the signal is transmitted via a one-wire bus → first optocoupler U6 → bus detection sub-circuit → MCU receiving port OW_RX; when the MCU sends data to the outside, it controls the OW_EN signal to drive the second optocoupler U5 to conduct, and sends the data to the external device through the one-wire communication bus; the status monitoring during the communication process is achieved by reading the bus level through the OW_DET pin.

[0101] Furthermore, such as Figures 5-8 As shown, the serial communication unit includes a data transmission line and a data reception line, connected between the MCU module and the external device, used to realize bidirectional data exchange between the MCU module and the external device; the charger activation unit, connected to the MCU module, is used to detect whether a charger is connected, and generates a charger activation signal to be sent to the MCU module when a charger is connected; the load activation unit, connected to the MCU module, is used to detect whether a load is connected, and generates a load activation signal to be sent to the MCU module when a load is connected; the communication status detection unit, connected to the MCU module, is used to detect whether the external device is connected, and whether the communication status of the serial communication unit and the one-line communication unit is normal, and sends a communication status detection signal to the MCU module according to the monitoring results.

[0102] Here, the serial communication unit includes a data transmission line (TX) and a data reception line (RX), with their ends connected to the MCU module and an external serial device, respectively, to achieve bidirectional asynchronous data communication conforming to the UART protocol. In the actual circuit, the TX pin is connected to the RX terminal of the external device; the RX pin is connected to the TX terminal of the external device; and the MCU_TX and MCU_RX pins are connected to the MCU module. A TVS diode (such as PESD3V3) and a current-limiting resistor can be configured in the communication path to provide surge suppression and overvoltage protection. This unit supports remote data uploading and control command issuance to external BMS, charging pile control boards, and PC debugging terminals.

[0103] Here, the charger activation unit is used to determine whether a charger is plugged in. When the charger is connected to the power supply port, the charging voltage is sent to the comparator through the voltage divider network. If the voltage is greater than the set threshold, the output logic is high. The MCU reads this level through the CHG_DET pin, and can then identify whether a charger is connected and execute wake-up, state switching or initialization communication processes accordingly.

[0104] Here, the load activation unit structure is similar to that of the charger activation unit, used to detect whether an external load device (such as a host computer, motor controller, etc.) is connected and powered on. It consists of pull-up or pull-down resistors and a voltage detection circuit. The detection signal is fed back to the MCU. When a load is connected, the load voltage is recognized by the MCU, thereby activating subsequent communication enable logic or power supply switch control. Through this unit, the MCU can automatically identify the device connection status, achieving plug-and-play or entering a low-power standby mode.

[0105] Here, the communication status detection unit is used to detect whether external devices are connected, whether serial communication is abnormal, whether one-line communication is disconnected, or whether there are transmit / receive conflicts and other abnormal states. It periodically detects the signal levels and changes on the TX, RX, and OW buses to determine whether there is data exchange, whether there is a long period of no response or abnormal signal level. If an abnormality is detected, it reports an MCU_DET error to the MCU to trigger reconnection, protection, or alarm mechanisms.

[0106] Furthermore, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of an MCU module provided in an embodiment of the present disclosure. The MCU adopts the PY32F030E18ME from Proton. The peripherals include a 12-bit high-precision ADC (1Msps sampling rate) that supports multi-channel synchronous sampling for battery cell voltage / current signal acquisition, a 4-channel 16-bit PWM timer that supports dead-time control and complementary output to meet MOSFET drive requirements, and UART, I2C, and SPI interfaces to realize data interaction with the AFE module, communication module, and host computer.

[0107] In specific implementation, under the discharge function, the load activation unit generates a high-level load activation signal and sends it to the MCU module when it detects a load connection. Upon receiving the load activation signal, the MCU module outputs a function trigger signal to the AFE module, triggering the AFE module to generate a charge / discharge action signal input to the first and second cascaded control circuits. The first and second cascaded control circuits control the first and second parallel MOSFET groups to conduct according to the charge / discharge action signal, completing the discharge action. Under the charging function, the charger activation unit generates a high-level charger activation signal and sends it to the MCU module when it detects a load connection. Upon receiving the charger activation signal, the MCU module outputs a charging enable signal to the second parallel MOSFET group and a function trigger signal to the AFE module, triggering the AFE module to generate a charge / discharge action signal input to the first and second cascaded control circuits. The first cascaded control circuit controls the first parallel MOSFET group to conduct according to the charge / discharge action signal, and the second cascaded control circuit controls the second parallel MOSFET group to conduct according to the charging enable signal and the charge / discharge action signal, completing the charging action.

[0108] As one possible implementation method, see Figure 10 As shown, Figure 10 This is a schematic diagram of a power supply module provided in an embodiment of this disclosure. The power supply module supplies power to the main circuit module, AFE module, MCU module, and communication module. A diode at the input front end is used for reverse polarity protection, and a 100nF capacitor is used to pull it down to ground to filter high-frequency noise. An MMBT5551 diode is used as the regulating diode, and its base is controlled by a BZT52C12 Zener diode to achieve voltage regulation. A 100nF capacitor at the output end further filters high-frequency noise to ensure a smooth output voltage; a diode is used for reverse voltage protection at the output end. The output end uses a linear regulator LDO, model ME6210A33PG, to output 3.3V and 3.3-CTL signals. The ME6210A33PG, with its low dropout voltage, high PSRR, fast transient response, and highly integrated protection functions, is an ideal choice for low-noise, high-reliability power supply designs. Its compact package and low power consumption characteristics are particularly suitable for consumer electronics and industrial equipment, and with proper design, system energy efficiency and stability can be significantly improved. The input voltage of the linear regulator (LDO) is obtained from the simulation of the pre-set power supply circuit and the pre-amplifier circuit.

[0109] This disclosure provides a charge / discharge management system compatible with multi-stage series-connected battery cells, comprising: a main circuit module, an AFE module, and an MCU module connected to the main circuit module and the AFE module respectively; the main circuit module includes a parallel sampling resistor group, a first parallel MOSFET group, a second parallel MOSFET group, a first cascade control circuit, and a second cascade control circuit; the parallel sampling resistor group is connected between the negative terminal bus of the battery cell group and the charging side bus; the first parallel MOSFET group is connected to the charging side bus, providing multiple charging current channels for the charging side bus; the second parallel MOSFET group is connected to the discharging side bus, providing multiple discharging current channels for the discharging side bus; the first cascade control circuit controls the first parallel MOSFET group to conduct according to the charge / discharge action signal of the AFE module; the second cascade control circuit controls the second parallel MOSFET group to conduct according to the charge / discharge action signal of the AFE module and the charging enable signal of the MCU module. It supports hardware-level dynamic switching of multi-level series-connected cells, solving the problems of poor compatibility and low efficiency of traditional passive balancing, while avoiding the high cost and complexity of active balancing, filling the technological gap of low-cost and highly flexible battery management solutions.

[0110] In the several embodiments provided in this disclosure, it should be understood that the disclosed system can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some communication interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0111] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0113] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A charge and discharge management system compatible with multi-stage series-connected battery cells, characterized in that, include: The main circuit module, the AFE module, and the MCU module connected to the main circuit module and the AFE module respectively; The main circuit module includes a parallel sampling resistor group, a first parallel MOSFET group, a second parallel MOSFET group, a first cascaded control circuit, and a second cascaded control circuit. The parallel sampling resistor group is connected between the negative terminal bus of the battery cell group and the charging side bus. The first parallel MOSFET group is connected to the charging side bus, providing multiple charging current channels for the charging side bus; the second parallel MOSFET group is connected to the discharging side bus, providing multiple discharging current channels for the discharging side bus. The first cascaded control circuit controls the first parallel MOS transistor group to turn on based on the charging and discharging action signal of the AFE module; the second cascaded control circuit controls the second parallel MOS transistor group to turn on based on the charging and discharging action signal of the AFE module and the charging enable signal of the MCU module.

2. The charging and discharging management system according to claim 1, characterized in that, The AFE module includes: an AFE chip and multiple sub-sampling circuits, each of the sub-sampling circuits being connected to a voltage sampling input port of the AFE chip; Each of the sub-sampling circuits is connected to a battery cell and is used to collect the sampling voltage of the corresponding battery cell and feed it back to the AFE chip through the voltage sampling input port; The AFE chip is used to generate the charging and discharging action signal according to the function trigger signal of the MCU module.

3. The charging and discharging management system according to claim 1, characterized in that, The first cascaded control circuit includes: a first transistor and a second transistor; The base of the first transistor is connected to the AFE module to receive the charging and discharging action signal, the collector of the first transistor is connected to the charging side bus, and the emitter of the first transistor is connected to the base of the second transistor. The emitter of the second transistor is connected to the gate of each first MOS transistor in the first parallel MOS transistor group, and the collector of the second transistor is connected to the charging side bus.

4. The charging and discharging management system according to claim 1, characterized in that, The second cascaded control circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The base of the third transistor is connected to the MCU module to receive the charging enable signal, the emitter of the third transistor is grounded, and the collector of the third transistor is connected to the base of the fourth transistor. The emitter of the fourth transistor is connected to the AFE module to receive the charging and discharging action signal, and the collector of the fourth transistor is connected to the emitter of the fifth transistor. The collector of the fifth transistor is connected to the discharge side bus, the base of the fifth transistor is connected to the emitter of the sixth transistor, and the connection node between the emitter of the fifth transistor and the collector of the fourth transistor is respectively connected to the gate of each second MOS transistor in the second parallel MOS transistor group. The collector and base of the sixth transistor are both connected to the discharge side bus.

5. The charging and discharging management system according to claim 1, characterized in that... ； For each first MOS transistor in the first parallel MOS transistor group, the charging current channel is formed by connecting the source and drain of the first MOS transistor. For each second MOS transistor in the second parallel MOS transistor group, the discharge current channel is formed by connecting the source and drain of the second MOS transistor.

6. The charging and discharging management system according to claim 2, characterized in that, The sub-sampling circuit includes a sampling resistor, a seventh transistor, and a filter capacitor; For any two adjacent first and second cells in the cell group, the sampling resistors are respectively set on the sampling channel between the first cell and the AFE chip, and on the sampling channel between the second cell and the AFE chip; The filter capacitor and the seventh transistor are connected between adjacent sampling channels; The collector of the seventh transistor is connected to the series node between the first battery cell and the corresponding sampling resistor, the emitter of the seventh transistor is connected to the series node between the second battery cell and the corresponding sampling resistor, and the base of the seventh transistor is connected to the series node between the sampling resistor corresponding to the second battery cell and the AFE chip.

7. The charging and discharging management system according to claim 1, characterized in that, It also includes a communication module, which includes a serial communication unit, a one-line communication unit, a charger activation unit, a load activation unit, and a communication status detection unit. The serial communication unit includes a data transmission line and a data reception line, which are connected between the MCU module and the external device to realize bidirectional data exchange between the MCU module and the external device; The one-line communication unit includes a one-line communication protocol line equipped with a first optocoupler and a second optocoupler, which is connected between the MCU module and the external device to realize bidirectional signal isolation transmission between the MCU module and the external device; The charger activation unit is connected to the MCU module and is used to detect whether a charger is connected, and generate a charger activation signal to be sent to the MCU module when a charger is connected. The load activation unit is connected to the MCU module and is used to detect whether a load is connected, and generate a load activation signal to be sent to the MCU module when a load is connected. The communication status detection unit is connected to the MCU module and is used to detect whether the external device is connected, and whether the communication status of the serial communication unit and the one-line communication unit is normal. Based on the monitoring results, it sends a communication status detection signal to the MCU module.

8. The charging and discharging management system according to claim 7, characterized in that: In the discharge function, the load activation unit generates a high-level load activation signal and sends it to the MCU module when it detects that a load is connected. After receiving the load activation signal, the MCU module outputs the function trigger signal to the AFE module to trigger the AFE module to generate the charging and discharging action signal and input it to the first cascaded control circuit and the second cascaded control circuit. The first cascaded control circuit and the second cascaded control circuit control the first parallel MOSFET group and the second parallel MOSFET group to conduct according to the charging and discharging action signal, so as to complete the discharging action.

9. The charging and discharging management system according to claim 7, characterized in that: In the charging function, the charger activation unit generates a high-level charger activation signal and sends it to the MCU module when it detects a load connection; After receiving the charger activation signal, the MCU module outputs the charging enable signal to the second parallel MOS transistor group and outputs the function trigger signal to the AFE module to trigger the AFE module to generate the charging and discharging action signal input to the first cascaded control circuit and the second cascaded control circuit. The first cascaded control circuit controls the first parallel MOSFET group to turn on according to the charging and discharging action signal, and the second cascaded control circuit controls the second parallel MOSFET group to turn on according to the charging enable signal and the charging and discharging action signal, thereby completing the charging action.

10. The charging and discharging management system according to claim 7, characterized in that, The one-line communication unit also includes a bus detection sub-circuit and a drive enable sub-circuit; The bus detection sub-circuit is connected between the first optocoupler and the MCU module, and is used to detect the current level status of the one-wire communication bus; The drive enable sub-circuit is connected between the second optocoupler and the MCU module, and is used to receive the one-wire communication drive signal sent by the MCU module to initiate communication on the one-wire communication bus; The connection node between the first optocoupler and the second optocoupler is connected to the one-wire communication bus.

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