A fast-starting high-precision relaxation oscillator

Abstract

The application discloses a high-precision relaxation oscillator with fast starting, comprising: a reference voltage generating module for generating a first and a second reference voltage; a capacitor charging and discharging module for generating a periodically changing first and a second real-time voltage; a bypass reference voltage generating module electrically connected with the reference voltage generating module, for generating a bypass reference voltage based on the second reference voltage; a charging and discharging control module electrically connected with the reference voltage generating module and the capacitor charging and discharging module, for controlling the capacitor charging and discharging module to alternately charge and discharge based on the first reference voltage and the first and the second real-time voltage; and a bypass control module electrically connected with the reference voltage generating module and the bypass reference voltage generating module, for controlling the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage. The application can realize high-precision frequency output of the oscillator in a wide voltage and temperature range, and achieve a fast starting effect that is stable in the second cycle.

Description

Technical Field

[0001] This invention belongs to the field of oscillator technology, and more specifically, relates to a high-precision relaxation oscillator with fast start-up. Background Technology

[0002] As the core clock supply unit of a chip, the oscillator circuit provides the basic clock signal for timing synchronization and logic operations in various electronic systems. Its performance directly determines the chip's operating accuracy and stability. Currently, the mainstream oscillator circuits are mainly divided into relaxation oscillators, ring oscillators, and crystal oscillators. Among them, relaxation oscillators are widely used in many mid-to-high-end chip applications due to their relatively simple structure and controllable cost.

[0003] In high-precision chip products (such as precision measuring instruments, high-end industrial control chips, and medical electronic devices), stringent requirements are placed on the accuracy and stability of clock signals. Specifically, chips often need to operate in complex environments, where fluctuations in power supply voltage (such as voltage fluctuations caused by changes in the load of the power supply system) and drastic changes in operating temperature (such as the wide temperature range of -40℃ to 125℃ in industrial environments) are common conditions. This requires the oscillator to always output a stable clock signal when these variables change, in order to avoid problems such as data processing errors and decreased measurement accuracy caused by clock drift.

[0004] Meanwhile, in real-time response applications (such as fast-start sensor nodes, emergency processing circuits, and high-frequency data acquisition modules), the startup speed of the oscillator becomes a key performance indicator. Traditional oscillators mostly adopt a feedback structure, and their clock signal needs to go through multiple oscillation cycles to reach a stable output state. This delay characteristic is difficult to meet the application requirements for which startup speed is strictly required, and may lead to risks such as system response lag, data loss, or startup failure.

[0005] In existing technologies, there are two main types of typical solutions to the problems of oscillator stability and startup speed, but both have obvious drawbacks:

[0006] One type is the simplified structure of relaxation oscillators, such as... Figure 4 As shown, it achieves oscillation using a simple RC charging and discharging circuit and a comparator. Although it can start up quickly (outputting a stable frequency in the first cycle), the period formula T=kRC+T_dly includes a comparator delay term T_dly. Since the comparator delay is significantly affected by temperature and power supply voltage, the environmental adaptability of the output frequency of this type of oscillator is poor, and it cannot meet the stability requirements of high-precision scenarios.

[0007] Another type is an improved oscillator based on an operational amplifier regulator, such as... Figure 5As shown, by stabilizing the reference voltage Vref_int using an operational amplifier, the influence of comparator delay on the period is eliminated, simplifying the period formula to T=kRC, thereby improving frequency stability. However, the ratio of the integrating capacitor Cint to the charging / discharging capacitor Cx in this structure is relatively large, and the operational amplifier is located within the loop and needs to have high open-loop gain to suppress reference voltage mismatch error, resulting in a circuit stabilization time of 10 to 20 cycles and a severely insufficient startup speed.

[0008] Therefore, developing an oscillator circuit that can maintain a stable output frequency under different power supply voltages and temperatures, and has fast start-up characteristics, is the key to solving current technical bottlenecks and meeting the application requirements of high-precision, fast-response chips. Summary of the Invention

[0009] The purpose of this invention is to propose a high-precision relaxation oscillator with fast start-up, which solves the technical problem that existing oscillators cannot simultaneously achieve output frequency stability and fast start-up performance under different power supply voltages and temperatures, and that oscillator stability and start-up speed are difficult to coexist in high-precision scenarios. This invention achieves high-precision frequency output of the oscillator within a wide voltage and temperature range, and achieves a fast start-up effect that is stable in the second cycle.

[0010] To achieve the above objectives, this invention proposes a high-precision relaxation oscillator with fast start-up, comprising:

[0011] A reference voltage generation module is used to generate a first reference voltage and a second reference voltage.

[0012] The capacitor charging and discharging module is used to generate a periodically changing first real-time voltage and a second real-time voltage through alternating charging and discharging, thereby forming a periodic oscillation signal;

[0013] A bypass reference voltage generating module, electrically connected to the reference voltage generating module, is used to generate a bypass reference voltage based on the second reference voltage;

[0014] The charge-discharge control module is electrically connected to the reference voltage generation module and the capacitor charge-discharge module respectively. The charge-discharge control module is used to control the capacitor charge-discharge module to charge and discharge alternately based on the first reference voltage, the first real-time voltage and the second real-time voltage.

[0015] The bypass control module is electrically connected to the reference voltage generation module and the bypass reference voltage generation module, respectively, and is used to control the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage.

[0016] Optionally, the reference voltage generating module includes:

[0017] A first current source, a first resistor, a second resistor, and a third resistor are connected in series.

[0018] The first current source is connected to the current reference bus;

[0019] The output terminal of the first reference voltage is located between the first resistor and the second resistor;

[0020] The output terminal of the second reference voltage is located between the second resistor and the third resistor;

[0021] The output terminal of the third resistor is electrically connected to the ground terminal.

[0022] Optionally, the capacitor charging and discharging module includes:

[0023] Second current source, third current source, first control switch, second control switch, third control switch, fourth control switch, first bypass switch, second bypass switch, first capacitor and second capacitor;

[0024] The second current source and the third current source are both connected to the current reference bus.

[0025] The first control switch and the second control switch are connected in parallel to the second current source, and the first bypass switch and the second bypass switch are connected in parallel to the third current source;

[0026] The first control switch is connected in series with the first capacitor, and the second control switch is connected in series with the second capacitor;

[0027] The third control switch is connected in parallel with the first capacitor and the fourth control switch is connected in parallel with the second capacitor and the second control switch.

[0028] The output terminal of the first real-time voltage is located between the first control switch and the first capacitor;

[0029] The output terminal of the second real-time voltage is located between the second control switch and the second capacitor;

[0030] The other end of the first bypass switch is connected to the output terminal of the first real-time voltage, and the other end of the second bypass switch is connected to the output terminal of the second real-time voltage.

[0031] The output terminals of the first capacitor, the second capacitor, the third control switch, and the fourth control switch are all electrically connected to the ground terminal.

[0032] The first capacitor and the second capacitor are the same.

[0033] Optionally, the bypass reference voltage generating module includes:

[0034] Fourth current source, fifth control switch, sixth control switch, unity-gain negative feedback operational amplifier, first bypass capacitor and second bypass capacitor;

[0035] The fourth current source is connected to the current reference bus;

[0036] The input terminal of the fifth control switch is connected to the output terminal of the fourth current source;

[0037] The output terminal and the inverting terminal of the unity-gain negative feedback operational amplifier are both connected to the output terminal of the fifth control switch, and its non-inverting terminal is connected to the output terminal of the second reference voltage.

[0038] The input terminal of the first bypass capacitor is connected to the output terminal of the fourth current source, and its output terminal is electrically connected to the ground terminal.

[0039] The input terminal of the second bypass capacitor is connected to the output terminal of the fifth control switch, and its output terminal is electrically connected to the ground terminal.

[0040] The output terminal of the bypass reference voltage is located between the fourth current source and the first bypass capacitor;

[0041] The sixth control switch is connected in parallel with the first bypass capacitor.

[0042] Optionally, the charge / discharge control module includes:

[0043] The system consists of a first comparator, a second comparator, a latch composed of a first NAND gate and a second NAND gate, a first inverter, and a second inverter.

[0044] The non-inverting input of the first comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the first real-time voltage.

[0045] The non-inverting input of the second comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the second real-time voltage.

[0046] The first input terminal of the first NAND gate is electrically connected to the output terminal of the first comparator, its second input terminal is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the fourth control switch.

[0047] The first input terminal of the second NAND gate is electrically connected to the output terminal of the second comparator, its second input terminal is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the third control switch.

[0048] The input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the second control switch.

[0049] The input terminal of the second inverter is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the first control switch.

[0050] Optionally, the bypass control module includes:

[0051] The third comparator, the first AND gate, the second AND gate, and the third inverter;

[0052] The non-inverting input of the third comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the bypass reference voltage.

[0053] The first input terminal of the first AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the first control switch, and its output terminal is electrically connected to the control terminal of the first bypass switch.

[0054] The first input terminal of the second AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the second control switch, and its output terminal is electrically connected to the control terminal of the second bypass switch.

[0055] The input terminal of the third inverter is electrically connected to the output terminal of the third comparator, and its output terminal is electrically connected to the control terminal of the fifth control switch.

[0056] Optionally, the working mechanism of the high-precision relaxation oscillator includes:

[0057] Four-phase cycle.

[0058] Optionally, the high-precision relaxation oscillator is enabled before the following steps are taken:

[0059] The third, fourth, and sixth control switches are closed, and the first, second, fifth, first bypass, and second bypass switches are opened, so that the voltage of the first capacitor, the second capacitor, and the first bypass capacitor is zero.

[0060] When the voltage is zero, the third, fourth, and sixth control switches are disconnected.

[0061] Optionally, the four-phase cycle includes:

[0062] First phase:

[0063] When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier.

[0064] The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited.

[0065] When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the second phase.

[0066] Second phase:

[0067] When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops.

[0068] When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor.

[0069] When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase.

[0070] Third phase:

[0071] When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier.

[0072] The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited;

[0073] When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the fourth phase.

[0074] Fourth phase:

[0075] When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops.

[0076] When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor.

[0077] When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

[0078] Optionally, the four-phase cycle includes:

[0079] First phase:

[0080] When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier.

[0081] The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited;

[0082] When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the second phase.

[0083] Second phase:

[0084] When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops.

[0085] When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor.

[0086] When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase.

[0087] Third phase:

[0088] When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier.

[0089] The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited.

[0090] When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the fourth phase.

[0091] Fourth phase:

[0092] When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops.

[0093] When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor.

[0094] When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

[0095] The beneficial effects of this invention are as follows: the reference voltage generation module provides a stable first reference voltage and a second reference voltage, laying a precise voltage reference for the entire oscillation system; the bypass reference voltage generation module generates a bypass reference voltage based on the second reference voltage, and the bypass control module adjusts the charging current multiple based on the bypass reference voltage and the first reference voltage, which can effectively eliminate the influence of comparator delay, power supply voltage fluctuation and temperature change on the oscillation period in traditional oscillators, so that the oscillation period is determined only by the RC parameters, ensuring that the oscillator can output a high-precision and stable oscillation signal under different power supply voltage and temperature conditions.

[0096] The charging and discharging control module can quickly respond to voltage changes and control the capacitor to charge and discharge alternately based on the first reference voltage and the first and second real-time voltages generated by the capacitor charging and discharging module, avoiding the delay of multi-cycle adjustment in the traditional feedback structure. At the same time, the bypass control module can accelerate the capacitor charging and discharging process by precisely controlling the charging current multiple, so that the oscillation signal can reach a stable output state in the second cycle, significantly improving the start-up speed of the oscillator.

[0097] The synergistic effect of the bypass reference voltage generation module and the bypass control module can naturally eliminate voltage mismatch errors through the system loop, which simplifies circuit design, reduces hardware implementation costs, and further improves the accuracy and reliability of the oscillation signal.

[0098] This invention combines the dual core performance of frequency stability and fast startup. Its high-precision stable oscillation signal and fast startup capability can fully meet the stringent requirements of clock signals in high-precision scenarios such as precision measurement, industrial control, and medical electronics, and has broad application value and practicality.

[0099] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0100] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0101] Figure 1 A schematic diagram of a fast-starting, high-precision relaxation oscillator according to an embodiment of the present invention is shown.

[0102] Figure 2 A, Figure 2 B. Figure 2 C and Figure 2 D shows a schematic diagram of a first four-phase cycle of a high-precision relaxation oscillator with fast startup according to an embodiment of the present invention.

[0103] Figure 3 A, Figure 3 B. Figure 3 C and Figure 3 D shows a schematic diagram of a second four-phase cycle of a high-precision relaxation oscillator with fast startup according to an embodiment of the present invention.

[0104] Figure 4 A schematic diagram of a relaxation oscillator with a simplified structure according to the background art of the present invention is shown.

[0105] Figure 5 A schematic diagram of an improved oscillator based on an operational amplifier regulator according to the background technology of the present invention is shown. Detailed Implementation

[0106] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Example

[0107] like Figure 1 As shown, this embodiment provides a high-precision relaxation oscillator with fast start-up, including:

[0108] A reference voltage generation module is used to generate a first reference voltage VREF1 and a second reference voltage VREF2.

[0109] The capacitor charging and discharging module is used to generate a periodically changing first real-time voltage VC1 and a second real-time voltage VC2 through alternating charging and discharging, thereby forming a periodic oscillation signal;

[0110] A bypass reference voltage generating module, electrically connected to the reference voltage generating module, is used to generate a bypass reference voltage VBYP based on the second reference voltage VREF2;

[0111] The charge and discharge control module is electrically connected to the reference voltage generation module and the capacitor charge and discharge module respectively. The charge and discharge control module is used to control the capacitor charge and discharge module to charge and discharge alternately based on the first reference voltage VREF1, the first real-time voltage VC1 and the second real-time voltage VC2.

[0112] The bypass control module is electrically connected to the reference voltage generation module and the bypass reference voltage generation module, respectively, and is used to control the charging current multiple of the capacitor charging and discharging module based on the first reference voltage VREF1 and the bypass reference voltage VBYP.

[0113] Specifically, in this circuit system, the reference voltage generation module undertakes the basic and critical task of voltage generation. It can accurately generate the first reference voltage VREF1 and the second reference voltage VREF2, providing a stable voltage reference for the operation of subsequent modules.

[0114] The capacitor charging and discharging module generates a periodically changing first real-time voltage signal VC1 and a second real-time voltage signal VC2 through alternating charging and discharging operations. These signals are further combined to form a periodic oscillation signal, which is the core part of the circuit to realize the oscillation function.

[0115] The bypass reference voltage generating module is electrically connected to the reference voltage generating module. It generates the bypass reference voltage VBYP based on the second reference voltage VREF2, providing the required voltage signal for bypass-related circuit control.

[0116] The charge and discharge control module is electrically connected to the reference voltage generation module and the capacitor charge and discharge module, respectively. Its function is to precisely control the alternating charge and discharge process of the capacitor charge and discharge module based on the first reference voltage VREF1, the first real-time voltage VC1 signal and the second real-time voltage VC2 signal, so as to ensure that the capacitor charge and discharge proceeds in accordance with the expected rhythm and pattern.

[0117] The bypass control module is also electrically connected to the reference voltage generation module and the bypass reference voltage generation module respectively. It controls the charging current multiple of the capacitor charging and discharging module according to the first reference voltage VREF1 and the bypass reference voltage VBYP, thereby adjusting the charging current to meet the current requirements under different working scenarios.

[0118] The synergistic effect of the bypass reference voltage generation module and the bypass control module can naturally eliminate voltage mismatch errors through the system loop, which simplifies circuit design, reduces hardware implementation costs, and further improves the accuracy and reliability of the oscillation signal.

[0119] The high-precision relaxation oscillator provided in this embodiment brings multiple significant benefits by introducing an innovative bypass loop and four-phase operation timing, successfully solving the core contradiction of traditional structures that are difficult to balance between accuracy, stability and speed.

[0120] Firstly, it achieves high precision and high stability. The most significant benefit of this embodiment lies in the fact that its oscillation period is ultimately determined solely by stable resistor and capacitor values ​​and the reference current (T=kRC), completely eliminating the comparator delay (T_dly), an error source heavily influenced by power supply voltage and temperature variations. This is achieved through a bypass loop, which actively "measures" and "stores" the delay error in each cycle and dynamically compensates for it in subsequent phases, thus ensuring that the output frequency remains highly stable under different operating voltage and temperature conditions.

[0121] Secondly, it achieves rapid start-up. Unlike traditional high-precision oscillators that require 10-20 cycles to achieve stable output, this embodiment uses a unity-gain operational amplifier to quickly establish a bypass voltage reference and optimizes the switching timing, enabling the oscillator to output a stable target frequency in the second cycle. This feature greatly satisfies the needs of low-power applications and systems requiring rapid response.

[0122] Thirdly, the structure is simple and reliable, reducing implementation difficulty and cost. This embodiment avoids the use of complex high-gain, high-bandwidth operational amplifiers, employing only a simple unity-gain buffer, whose offset voltage can be averaged out by the system loop. Furthermore, the entire design is based on matched current mirrors and capacitors, which greatly facilitates integrated circuit implementation and improves the consistency and reliability of mass production.

[0123] In summary, this embodiment cleverly utilizes analog circuit timing control to simultaneously achieve the three traditionally mutually restrictive goals of high precision, high stability, and fast startup. It also provides an easily integrated and robust solution with extremely high practical value and market competitiveness.

[0124] In this embodiment, the reference voltage generating module includes:

[0125] The first current source Is1, the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series.

[0126] The first current source Is1 is connected to the current reference bus L;

[0127] The output terminal OUT1 of the first reference voltage VREF1 is set between the first resistor R1 and the second resistor R2;

[0128] The output terminal OUT2 of the second reference voltage VREF2 is located between the second resistor R2 and the third resistor R3;

[0129] The output terminal of the third resistor R3 is electrically connected to the ground terminal GND.

[0130] Specifically, the reference voltage generation module is a circuit based on a precision resistor voltage divider network. Its core function is to convert a stable input reference current into two reference voltages with a precise proportional relationship. The module's input is a precision current source Is1, which is insensitive to changes in power supply voltage and temperature. This current source is connected to the current reference bus L, providing a stable current reference I_REF (1x current). The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series with resistors of the same resistance value, forming a high-precision voltage divider.

[0131] After the current I_REF flows out of Is1, it flows sequentially through the first resistor R1, the second resistor R2, and the third resistor R3. According to Ohm's law, the voltage drop across each resistor is V_R = I_REF. R (where R is the resistance of a single resistor). Therefore, the output terminal OUT1 between the first resistor R1 and the second resistor R2 outputs a first reference voltage VREF1, the value of which is VREF1 = I_REF. (R² + R³) = 2 I_REF R. The output terminal OUT2, located between the second resistor R2 and the third resistor R3, outputs a second reference voltage VREF2, whose value is VREF2 = I_REF. R3=I_REF R. The other end of the third resistor R3 is grounded, providing a return path for the current.

[0132] Since the first reference voltage VREF1 and the second reference voltage VREF2 originate from the same reference current and the same series of matched resistors, any change in absolute resistance or current fluctuation caused by process variations or temperature variations will synchronously and proportionally affect the two output voltages. This means that the voltage ratio between them remains constant, while the oscillator period formula T=k R The voltage ratio R in C is proportional to VREF / I_REF, therefore this proportional stability is crucial for ensuring the stability of the oscillation frequency. This structure is simple and reliable, requires no operational amplifier, and achieves high-precision voltage ratio generation through the use of carefully placed matching resistors in the integrated circuit.

[0133] In this embodiment, the capacitor charging and discharging module includes:

[0134] Second current source Is2, third current source Is3, first control switch S1, second control switch S2, third control switch S3, fourth control switch S4, first bypass switch S1_byp, second bypass switch S2_byp, first capacitor C1 and second capacitor C2;

[0135] The second current source Is2 and the third current source Is3 are both connected to the current reference bus L;

[0136] The first control switch S1 and the second control switch S2 are connected in parallel to the second current source Is2, and the first bypass switch S1_byp and the second bypass switch S2_byp are connected in parallel to the third current source Is3.

[0137] The first control switch S1 is connected in series with the first capacitor C1, and the second control switch S2 is connected in series with the second capacitor C2.

[0138] The third control switch S3 is connected in parallel with the first capacitor C1 to the first control switch S1, and the fourth control switch S4 is connected in parallel with the second capacitor C2 to the second control switch S2.

[0139] The output terminal OUT3 of the first real-time voltage VC1 is located between the first control switch S1 and the first capacitor C1;

[0140] The output point of the second real-time voltage VC2 is set between the second control switch S2 and the second capacitor C2;

[0141] The other end of the first bypass switch S1_byp is connected to the output terminal OUT3 of the first real-time voltage VC1, and the other end of the second bypass switch S2_byp is connected to the output point of the second real-time voltage VC2.

[0142] The output terminals of the first capacitor C1, the second capacitor C2, the third control switch S3, and the fourth control switch S4 are all electrically connected to the ground terminal GND.

[0143] The first capacitor C1 and the second capacitor C2 are the same.

[0144] Specifically, the capacitor charging and discharging module is the core actuator of the oscillator. Its function is to alternately charge and discharge two matched capacitors through precisely controlled current to generate the required periodic voltage ramp signal. The core of the module consists of two identical first capacitors C1 and second capacitor C2, as well as a parallel charging path composed of a second current source Is2 and a third current source Is3. The charging and discharging process is managed by the coordinated action of the first control switch S1, the second control switch S2, the third control switch S3, the fourth control switch S4, the first bypass switch S1_byp, and the second bypass switch S2_byp.

[0145] The charging path consists of two independent 1x second current source Is2 and a third current source Is3, both of which draw bias from the current reference bus L to ensure stable and matched output current. Charging operation is precisely controlled by two pairs of switches:

[0146] Normal charging path (1x current): dominated by the first control switch S1 and the second control switch S2. When the first control switch S1 is closed, the current from the second current source Is2 charges the first capacitor C1, generating the first real-time voltage VC1; when the second control switch S2 is closed, the current from the second current source Is2 charges the second capacitor C2, generating the second real-time voltage VC2.

[0147] Fast charging path (superimposed current of 2x): Primarily driven by the first bypass switch S1_byp and the second bypass switch S2_byp. When the first control switch S1 and the first bypass switch S1_byp are closed simultaneously, the second current source Is2 and the third current source Is3 are connected in parallel, jointly charging the first capacitor C1, thus doubling the total charging current (2x). Similarly, the simultaneous closing of the second control switch S2 and the second bypass switch S2_byp enables fast charging of the second capacitor C2. This design is crucial for achieving fast startup.

[0148] The discharge path is controlled by the third control switch S3 and the fourth control switch S4. When the third control switch S3 is closed, it short-circuits the two ends of the first capacitor C1 to the ground terminal GND, causing it to discharge and reset quickly; similarly, when the fourth control switch S4 is closed, it discharges the second capacitor C2. These two switches are activated when the oscillator is initialized or when the capacitor state needs to be reset, ensuring that each oscillation cycle starts from a known zero-voltage state.

[0149] In summary, this module, by receiving switching signals from the charge / discharge control module, flexibly combines the aforementioned paths to achieve switching between three states: reset (discharge), normal charging (1x current), and fast charging (2x current) for the first capacitor C1 and the second capacitor C2. This generates two alternating, linearly changing voltage ramps (first real-time voltage VC1 and second real-time voltage VC2) at output terminals OUT3 and OUT4, providing a foundation for the subsequent comparator circuit to generate a stable oscillation signal.

[0150] In this embodiment, the bypass reference voltage generation module includes:

[0151] Fourth current source Is4, fifth control switch S5, sixth control switch S6, unity-gain negative feedback operational amplifier A_BYP, first bypass capacitor Cbyp, and second bypass capacitor CL;

[0152] The fourth current source Is4 is connected to the current reference bus L;

[0153] The input terminal of the fifth control switch S5 is connected to the output terminal of the fourth current source Is4;

[0154] The output and inverting input of the unity-gain negative feedback operational amplifier A_BYP are both connected to the output of the fifth control switch S5, and its non-inverting input is connected to the output OUT2 of the second reference voltage VREF2.

[0155] The input terminal of the first bypass capacitor Cbyp is connected to the output terminal of the fourth current source Is4, and its output terminal is electrically connected to the ground terminal GND.

[0156] The input terminal of the second bypass capacitor CL is connected to the output terminal of the fifth control switch S5, and its output terminal is electrically connected to the ground terminal GND.

[0157] The output terminal OUT5 of the bypass reference voltage VBYP is located between the fourth current source Is4 and the first bypass capacitor Cbyp;

[0158] The sixth control switch S6 is connected in parallel with the first bypass capacitor Cbyp.

[0159] Specifically, this bypass reference voltage generation module is the core innovative module for achieving high-precision frequency control. Its core task is to quickly establish, maintain, and replicate an accurate reference voltage, and measure comparator delay for compensation. This module receives a second reference voltage VREF2 from the reference voltage generation module and generates the crucial bypass reference voltage VBYP through a clever circuit composed of a unity-gain operational amplifier and switched capacitors. The module's operating mode is determined by the fifth control switch S5 (where the sixth control switch S6 is only closed before the oscillator is enabled and remains open after enabling), and mainly consists of two modes:

[0160] 1. Sampling / Clamping Mode (Fifth Control Switch S5 Closed): In this mode, the unity-gain negative feedback operational amplifier A_BYP plays a crucial role. Its non-inverting input is connected to a stable second reference voltage VREF2, while its output is directly connected to the inverting input via the fifth control switch S5, forming a standard unity-gain buffer (voltage follower) configuration. At this time, the unity-gain negative feedback operational amplifier A_BYP, with its low output impedance, powerfully and quickly clamps the voltage at the output OUT5 and the second bypass capacitor CL precisely to the second reference voltage VREF2. The second bypass capacitor CL acts as a compensation and filtering capacitor, stabilizing the op-amp output and preventing oscillation. This mode is used to establish a clean and accurate voltage reference point for subsequent measurements during system initialization or loop start-up. This mode is used to quickly and accurately clamp the bypass reference voltage VBYP to the second reference voltage VREF2 during oscillator startup or the initial stage of a loop.

[0161] 2. Hold / Measurement Mode (Fifth Control Switch S5 Open): When the fifth control switch S5 is open, the unity-gain negative feedback operational amplifier A_BYP is isolated from the main circuit, and the output terminal OUT5 enters the hold state. At this time, the first bypass capacitor Cbyp becomes the core component. The fourth current source Is4 (providing a stable 1x current) begins to charge the first bypass capacitor Cbyp. Since the other end of the first bypass capacitor Cbyp is grounded, the voltage at its input terminal will rise linearly from the previously clamped second reference voltage VREF2, and the rate of change of its voltage is determined by the current I and the value of the first bypass capacitor Cbyp (dV / dt=I / Cbyp). This linearly rising ramp voltage is used for comparison with the first reference voltage VREF1, and its charging time includes the comparator's delay information, which is crucial for achieving error measurement.

[0162] When the oscillator is working normally, since the fifth control switch S5 is connected to VREF2 through the unity-gain negative feedback operational amplifier A_BYP, the first bypass capacitor Cbyp will discharge to VREF2, providing an initial state for the next cycle and ensuring that the measurement accuracy is not affected by the residual charge of the previous cycle.

[0163] In summary, this module achieves accurate and rapid voltage establishment through the fast clamping function of the operational amplifier, and then converts time information into voltage information by charging the capacitor through a constant current source. It cleverly realizes the "sampling" and "measurement" of circuit delay, providing crucial support for the high precision and rapid stability of the entire system.

[0164] In this embodiment, the charge / discharge control module includes:

[0165] The first comparator CMPa, the second comparator CMPb, the latch consisting of the first NAND gate N1 and the second NAND gate N2, the first inverter F1 and the second inverter F2;

[0166] The non-inverting input of the first comparator CMPa is electrically connected to the output terminal OUT1 of the first reference voltage VREF1, and its inverting input is electrically connected to the output terminal of the first real-time voltage VC1.

[0167] The non-inverting input of the second comparator CMPb is electrically connected to the output terminal OUT1 of the first reference voltage VREF1, and its inverting input is electrically connected to the output terminal of the second real-time voltage VC2.

[0168] The first input terminal of the first NAND gate N1 is electrically connected to the output terminal of the first comparator CMPa, its second input terminal is electrically connected to the output terminal of the second NAND gate N2, and its output terminal is electrically connected to the control terminal of the fourth control switch S4.

[0169] The first input terminal of the second NAND gate N2 is electrically connected to the output terminal of the second comparator CMPb, its second input terminal is electrically connected to the output terminal of the first NAND gate N1, and its output terminal is electrically connected to the control terminal of the third control switch S3.

[0170] The input terminal of the first inverter F1 is electrically connected to the output terminal of the first NAND gate N1, and its output terminal is electrically connected to the control terminal of the second control switch S2.

[0171] The input terminal of the second inverter F2 is electrically connected to the output terminal of the second NAND gate N2, and its output terminal is electrically connected to the control terminal of the first control switch S1.

[0172] Specifically, the charge / discharge control module is the core decision-making unit of the oscillator's logic function. It is responsible for monitoring the capacitor voltage state and generating corresponding switching control signals to precisely manage the alternating process of capacitor charging and discharging. The core of the module is the first comparator CMPa and the second comparator CMPb, which act as the system's "judgment organs," continuously comparing the first real-time voltage VC1 and the second real-time voltage VC2 with the stable first reference voltage VREF1.

[0173] Its working principle is as follows: When the first real-time voltage VC1 or the second real-time voltage VC2 rises linearly during the charging process and reaches VREF1, the output of the first comparator CMPa or the second comparator CMPb will flip. This flip signal is fed into an SR latch composed of a first NAND gate N1 and a second NAND gate N2 cross-coupled. This latch latches the transient jump signal generated by the comparator into a stable logic state (i.e., "first capacitor C1 is charging, second capacitor C2 is discharging" or "second capacitor C2 is charging, first capacitor C1 is discharging"), thereby eliminating the risk of output jitter that may exist in the comparator and ensuring the stability and determinism of the control signal.

[0174] The latch output directly drives the discharge control path: the output of the first NAND gate N1 directly controls the fourth control switch S4 (connected in parallel with the second capacitor C2), while the output of the second NAND gate N2 directly controls the third control switch S3 (connected in parallel with the first capacitor C1). This design means that the state of the latch directly determines which capacitor is discharged.

[0175] Simultaneously, to generate complementary charging control signals, the latch outputs are passed through a first inverter F1 and a second inverter F2. The first inverter F1 inverts the output of the first NAND gate N1, and the result is used to control the second control switch S2 (controlling the charging of the second capacitor C2); the second inverter F2 inverts the output of the second NAND gate N2, and the result is used to control the first control switch S1 (controlling the charging of the first capacitor C1). Through the inverters, it is ensured that the logic states of the charging switch (first control switch S1 / second control switch S2) and the discharging switch (third control switch S3 / fourth control switch S4) are always opposite, thereby strictly preventing short-circuit operations that would simultaneously charge and discharge the same capacitor.

[0176] In summary, this module, through the coordinated operation of comparators, latches, and inverters, transforms the analog signal changes of capacitor voltage into a set of stable, complementary, and conflict-free digital switching control signals. This reliably coordinates the alternating operation of the entire capacitor charging and discharging module, which is crucial for the continuous and stable operation of the oscillator.

[0177] In this embodiment, the bypass control module includes:

[0178] The third comparator CMPc, the first AND gate Y1, the second AND gate Y2, and the third inverter F3;

[0179] The non-inverting input of the third comparator CMPc is electrically connected to the output terminal OUT1 of the first reference voltage VREF1, and its inverting input is electrically connected to the output terminal of the bypass reference voltage VBYP.

[0180] The first input terminal of the first AND gate Y1 is electrically connected to the output terminal of the third comparator CMPc, its second input terminal is electrically connected to the control terminal of the first control switch S1, and its output terminal is electrically connected to the control terminal of the first bypass switch S1_byp;

[0181] The first input terminal of the second AND gate Y2 is electrically connected to the output terminal of the third comparator CMPc, its second input terminal is electrically connected to the control terminal of the second control switch S2, and its output terminal is electrically connected to the control terminal of the second bypass switch S2_byp;

[0182] The input terminal of the third inverter F3 is electrically connected to the output terminal of the third comparator CMPc, and its output terminal is electrically connected to the control terminal of the fifth control switch S5.

[0183] Specifically, the bypass control module is an intelligent management unit for the oscillator to achieve fast charging and delay compensation functions. Its core responsibility is to monitor the status of the bypass reference voltage VBYP and, only within the correct timing window, intelligently enable the fast charging path (control the first bypass switch S1_byp and the second bypass switch S2_byp) and manage the sampling and measurement mode of the bypass voltage (control the fifth control switch S5).

[0184] The core of this module is the third comparator CMPc, which continuously compares the stable first reference voltage VREF1 with the linearly changing bypass reference voltage VBYP. When the bypass reference voltage VBYP is lower than the first reference voltage VREF1 during the charging process, the third comparator CMPc outputs a high level; when the bypass reference voltage VBYP rises above the first reference voltage VREF1, the output of the third comparator CMPc flips to a low level. This flipping action is the key to triggering phase switching and achieving delay compensation.

[0185] The first AND gate Y1 and the second AND gate Y2 together constitute the enabling logic for fast charging. Their first input terminals are both connected to the output terminal of the third comparator CMPc, and the second input terminals are respectively connected to the control terminals of the first control switch S1 and the second control switch S2. This connection method means that to enable fast charging (i.e., activate the first bypass switch S1_byp or the second bypass switch S2_byp), two conditions must be met simultaneously: one, the output of the third comparator CMPc is high (indicating VBYP < VREF1, and the system is in the measurement phase); two, the corresponding main charging switch (the first control switch S1 or the second control switch S2) has been turned on (indicating that the first capacitor C1 or the second capacitor C2 is being charged). This "AND" logic ensures that the fast charging function will only be activated during a specific period within the main charging cycle, thus achieving precise timing control.

[0186] The third inverter F3 directly negates the output of the third comparator CMPc, and its output is used to control the fifth control switch S5. When the output of the third comparator CMPc is high (VBYP < VREF1), the third inverter F3 outputs a low level, which closes the fifth control switch S5, connects the unity-gain negative feedback operational amplifier A_BYP to the circuit, and clamps the bypass reference voltage VBYP to VREF2. When the output of the third comparator CMPc flips to low (VBYP ≥ VREF1), the third inverter F3 outputs a high level, thereby disconnecting the fifth control switch S5, disconnecting the output terminal OUT5 of the bypass reference voltage VBYP from the unity-gain negative feedback operational amplifier A_BYP, and entering the constant-current charging stage dominated by the fourth current source Is4.

[0187] In summary, through the combination of a comparator, logic gates, and inverters, this bypass control module converts the voltage state information of the bypass reference voltage VBYP into precise control signals for the fast charging switches (the first bypass switch S1_byp, the second bypass switch S2_byp) and the mode switching switch (the fifth control switch S5), and is the core logic circuit that coordinates the seamless connection of the three processes of normal charging, fast charging, and delay measurement.

[0188] In this embodiment, the working mechanism of the high-precision relaxation oscillator includes:

[0189] Four-phase cycle.

[0190] Before enabling the high-precision relaxation oscillator in this embodiment:

[0191] Control the third control switch S3, the fourth control switch S4, and the sixth control switch S6 to close, and control the first control switch S1, the second control switch S2, the fifth control switch S5, the first bypass switch S1_byp, and the second bypass switch S2_byp to open, so that the voltages of the first capacitor C1, the second capacitor C2, and the first bypass capacitor Cbyp are zero;

[0192] After the voltages of the first capacitor C1, the second capacitor C2, and the first bypass capacitor Cbyp are zero, control the third control switch S3, the fourth control switch S4, and the sixth control switch S6 to open.

[0193] In this embodiment, the SR latch composed of two NAND gates (the first NAND gate N1, the second NAND gate N2) has two stable output states:

[0194] State A (Q=0, QA=1): Q=0 (output of first NAND gate N1) → Close first control switch S1 (via second inverter F2) → Stop charging first capacitor C1. QA=1 (output of second NAND gate N2) → Open second control switch S2 (via inverter F1) → Start charging second capacitor C2. Simultaneously, QA=1 → Open fourth control switch S4 (direct connection) → Short-circuit and discharge first capacitor C1.

[0195] State B (Q=1, QA=0): Q=1 (output of first NAND gate N1) → Turn on first control switch S1 → Start charging first capacitor C1. QA=0 (output of second NAND gate N2) → Turn off second control switch S2 → Stop charging second capacitor C2. Simultaneously, Q=1 → Turn on third control switch S3 (direct connection) → Short-circuit and discharge second capacitor C2.

[0196] Therefore, as Figure 2 and Figure 3 As shown (the sixth control switch S6 remains open in this high-precision relaxation oscillator, therefore...) Figure 2 and Figure 3 (not shown in the image), there are two types of four-phase cycles;

[0197] The first type, such as Figure 2 The four-phase cycle includes:

[0198] First phase:

[0199] When the fifth control switch S5 is closed, the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unity-gain negative feedback operational amplifier A_BYP.

[0200] The first control switch S1 is open, the first bypass switch S1_byp and the third control switch S3 are closed, and the first capacitor C1 is short-circuited.

[0201] The second control switch S2 is closed, the second bypass switch S2_byp and the fourth control switch S4 are open, the second current source Is2 charges the second capacitor C2 until the second real-time voltage VC2 reaches the first reference voltage VREF1, the output of the second comparator CMPb flips and enters the second phase.

[0202] Second phase:

[0203] When the second control switch S2 and the second bypass switch S2_byp are open, the fourth control switch S4 is closed, the second capacitor C2 is short-circuited, and charging stops.

[0204] When the first control switch S1 and the first bypass switch S1_byp are closed, the third control switch S3 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the first capacitor C1.

[0205] The fifth control switch S5 is open, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips and enters the third phase.

[0206] Third phase:

[0207] When the fifth control switch S5 is closed, the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unity-gain negative feedback operational amplifier A_BYP.

[0208] The second control switch S2 is open, the fourth control switch S4 and the second bypass switch S2_byp are closed, and the second capacitor C2 is short-circuited.

[0209] The first control switch S1 is closed, the third control switch S3 and the first bypass switch S1_byp are open, the second current source Is2 charges the first capacitor C1 until the first real-time voltage VC1 reaches the first reference voltage VREF1, the output of the first comparator CMPa flips, and enters the fourth phase.

[0210] Fourth phase:

[0211] The first control switch S1 and the first bypass switch S1_byp are disconnected, the third control switch S3 is closed, the first capacitor C1 is short-circuited, and charging is stopped.

[0212] When the second control switch S2 and the second bypass switch S2_byp are closed, the fourth control switch S4 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the second capacitor C2.

[0213] When the fifth control switch S5 is turned off, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1. Then the output of the third comparator CMPc flips and enters the first phase.

[0214] Specifically, this high-precision relaxation oscillator operates through a precisely defined four-phase cycle, with each phase switched by a comparator, ensuring the stability of the output frequency and fast start-up characteristics.

[0215] like Figure 2As shown in Figure A, Phase ① (Initialization and C2 Charging): At the start of this phase, the fifth control switch S5 closes, connecting the unity-gain negative feedback operational amplifier A_BYP to the circuit. This allows the bypass reference voltage VBYP node to be precisely clamped to the second reference voltage VREF2, establishing a clean reference. Simultaneously, the first capacitor C1 is short-circuited and reset through the closed third control switch S3 and the first bypass switch S1_byp, ensuring its voltage is zero. The second control switch S2 closes, allowing the second current source Is2 to charge the second capacitor C2, causing its second real-time voltage VC2 to rise linearly from zero. The end of this phase is determined by the second comparator CMPb. When the second real-time voltage VC2 rises to reach the first reference voltage VREF1, the output of the second comparator CMPb flips, triggering the system to enter the second phase.

[0216] like Figure 2 As shown in Figure B, Phase ② (Fast charging and delayed sampling of the first capacitor C1): Upon entering the second phase, the second control switch S2 opens, stopping the charging of the second capacitor C2, and immediately closes the fourth control switch S4 to short-circuit and reset the second capacitor C2. The first control switch S1 and the first bypass switch S1_byp close simultaneously, causing the second current source Is2 and the third current source Is3 to connect in parallel, jointly charging the first capacitor C1 with twice the current (2x). At the same time, the fifth control switch S5 opens, connecting the output terminal OUT5 of the bypass reference voltage VBYP to the unity-gain negative feedback operational amplifier A_BYP. The fourth current source Is4 begins charging the first bypass capacitor Cbyp. Since its initial voltage is the second reference voltage VREF2, the bypass reference voltage VBYP rises linearly from this value. The end of this phase is determined by the third comparator CMPc. When the bypass reference voltage VBYP rises to the first reference voltage VREF1, the output of the third comparator CMPc flips, indicating that a charging time including its own delay has been measured and the system enters the third phase.

[0217] like Figure 2As shown in Figure C, Phase ③ (normal charging of the first capacitor C1 and reset of the second capacitor C2): In the third phase, the fifth control switch S5 closes again, and the unity-gain negative feedback operational amplifier A_BYP clamps the bypass reference voltage VBYP back to the second reference voltage VREF2, preparing for the next measurement. The second capacitor C2 remains short-circuited through the closed fourth control switch S4 and the second bypass switch S2_byp. The first control switch S1 remains closed, but the first bypass switch S1_byp is open, so the charging current for the first capacitor C1 returns to one current (1x), which continues to complete the charging. The end of this phase is determined by the first comparator CMPa. When the first real-time voltage VC1 rises to the first reference voltage VREF1, the output of the first comparator CMPa flips, and the system enters the fourth phase.

[0218] like Figure 2 As described in D, Phase ④ (Fast charging and delay compensation of the second capacitor C2): The last phase is symmetrically complementary to the second phase. The first control switch S1 and the first bypass switch S1_byp are open, and the first capacitor C1 is short-circuited and reset through the closed third control switch S3. The second control switch S2 and the second bypass switch S2_byp are simultaneously closed, causing the second current source Is2 and the third current source Is3 to be connected in parallel again, rapidly charging the second capacitor C2 with twice the current (2x). The fifth control switch S5 is open, and the fourth current source Is4 charges the first bypass capacitor Cbyp again, with the initial conditions being exactly the same as in the second phase. When the bypass reference voltage VBYP charges again from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips, and the time taken is exactly the same as in the second phase, thus accurately compensating for the comparator delay. This flip signal triggers the system to return to the first phase, starting the next complete oscillation cycle, thereby continuously generating a stable clock output.

[0219] The second type, such as Figure 3 As shown, the four-phase cycle includes:

[0220] First phase:

[0221] When the fifth control switch S5 is closed, the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unity-gain negative feedback operational amplifier A_BYP.

[0222] The second control switch S2 is open, the fourth control switch S4 and the second bypass switch S2_byp are closed, and the second capacitor C2 is short-circuited.

[0223] The first control switch S1 is closed, the third control switch S3 and the first bypass switch S1_byp are open, the second current source Is2 charges the first capacitor C1 until the first real-time voltage VC1 reaches the first reference voltage VREF1, the output of the first comparator CMPa flips and enters the second phase.

[0224] Second phase:

[0225] The first control switch S1 and the first bypass switch S1_byp are disconnected, the third control switch S3 is closed, the first capacitor C1 is short-circuited, and charging is stopped.

[0226] When the second control switch S2 and the second bypass switch S2_byp are closed, the fourth control switch S4 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the second capacitor C2.

[0227] The fifth control switch S5 is open, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips and enters the third phase.

[0228] Third phase:

[0229] When the fifth control switch S5 is closed, the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unity-gain negative feedback operational amplifier A_BYP.

[0230] The first control switch S1 is open, the first bypass switch S1_byp and the third control switch S3 are closed, and the first capacitor C1 is short-circuited.

[0231] The second control switch S2 is closed, the second bypass switch S2_byp and the fourth control switch S4 are open, the second current source Is2 charges the second capacitor C2 until the second real-time voltage VC2 reaches the first reference voltage VREF1, the output of the second comparator CMPb flips and enters the fourth phase.

[0232] Fourth phase:

[0233] When the second control switch S2 and the second bypass switch S2_byp are open, the fourth control switch S4 is closed, the second capacitor C2 is short-circuited, and charging stops.

[0234] When the first control switch S1 and the first bypass switch S1_byp are closed, the third control switch S3 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the first capacitor C1.

[0235] When the fifth control switch S5 is turned off, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1. Then the output of the third comparator CMPc flips and enters the first phase.

[0236] Specifically, such as Figure 3 As described in A, 3B, 3C, and 3D, the second type of four-phase cycle operates on the same principle as the first type, except for the charging sequence of the capacitors. The first type of four-phase cycle completes the initial sampling and compensation of the comparator delay by rapidly charging the first capacitor C1 first, followed by rapidly charging the second capacitor C2, thus guiding the circuit from a disordered initial state into a stable oscillation cycle. The second type of four-phase cycle completes the initial sampling and compensation of the comparator delay by rapidly charging the second capacitor C2 first, followed by rapidly charging the first capacitor C1, thus guiding the circuit from a disordered initial state into a stable oscillation cycle. That is, the rapid charging phases of the first capacitor C1 and the second capacitor C2 are arranged in different phases (the second capacitor C2 is in the second phase, and the first capacitor C1 is in the fourth phase), so that in each complete oscillation cycle, both capacitors are rapidly charged and the delay is compensated once, thereby maintaining the continuous stability of the frequency.

[0237] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A relaxation oscillator, characterized in that, include: A reference voltage generation module is used to generate a first reference voltage and a second reference voltage. The capacitor charging and discharging module is used to generate a periodically changing first real-time voltage and a second real-time voltage through alternating charging and discharging, thereby forming a periodic oscillation signal; A bypass reference voltage generating module, electrically connected to the reference voltage generating module, is used to generate a bypass reference voltage based on the second reference voltage; The charge-discharge control module is electrically connected to the reference voltage generation module and the capacitor charge-discharge module respectively. The charge-discharge control module is used to control the capacitor charge-discharge module to charge and discharge alternately based on the first reference voltage, the first real-time voltage and the second real-time voltage. The bypass control module is electrically connected to the reference voltage generation module and the bypass reference voltage generation module, respectively, and is used to control the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage.

2. The relaxation oscillator according to claim 1, characterized in that, The reference voltage generating module includes: A first current source, a first resistor, a second resistor, and a third resistor are connected in series. The first current source is connected to the current reference bus; The output terminal of the first reference voltage is located between the first resistor and the second resistor; The output terminal of the second reference voltage is located between the second resistor and the third resistor; The output terminal of the third resistor is electrically connected to the ground terminal.

3. The relaxation oscillator according to claim 2, characterized in that, The capacitor charging and discharging module includes: Second current source, third current source, first control switch, second control switch, third control switch, fourth control switch, first bypass switch, second bypass switch, first capacitor and second capacitor; The second current source and the third current source are both connected to the current reference bus. The first control switch and the second control switch are connected in parallel to the second current source, and the first bypass switch and the second bypass switch are connected in parallel to the third current source; The first control switch is connected in series with the first capacitor, and the second control switch is connected in series with the second capacitor; The third control switch is connected in parallel with the first capacitor, and the fourth control switch is connected in parallel with the second capacitor; The output terminal of the first real-time voltage is located between the first control switch and the first capacitor; The output terminal of the second real-time voltage is located between the second control switch and the second capacitor; The other end of the first bypass switch is connected to the output terminal of the first real-time voltage, and the other end of the second bypass switch is connected to the output terminal of the second real-time voltage. The output terminals of the first capacitor, the second capacitor, the third control switch, and the fourth control switch are all electrically connected to the ground terminal. The first capacitor and the second capacitor are the same.

4. The relaxation oscillator according to claim 3, characterized in that, The bypass reference voltage generating module includes: Fourth current source, fifth control switch, sixth control switch, unity-gain negative feedback operational amplifier, first bypass capacitor and second bypass capacitor; The fourth current source is connected to the current reference bus; The input terminal of the fifth control switch is connected to the output terminal of the fourth current source; The output terminal and the inverting terminal of the unity-gain negative feedback operational amplifier are both connected to the output terminal of the fifth control switch, and its non-inverting terminal is connected to the output terminal of the second reference voltage. The input terminal of the first bypass capacitor is connected to the output terminal of the fourth current source, and its output terminal is electrically connected to the ground terminal. The input terminal of the second bypass capacitor is connected to the output terminal of the fifth control switch, and its output terminal is electrically connected to the ground terminal. The output terminal of the bypass reference voltage is located between the fourth current source and the first bypass capacitor; The sixth control switch is connected in parallel with the first bypass capacitor.

5. The relaxation oscillator according to claim 4, characterized in that, The charge / discharge control module includes: The system consists of a first comparator, a second comparator, a latch composed of a first NAND gate and a second NAND gate, a first inverter, and a second inverter. The non-inverting input of the first comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the first real-time voltage. The non-inverting input of the second comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the second real-time voltage. The first input terminal of the first NAND gate is electrically connected to the output terminal of the first comparator, its second input terminal is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the fourth control switch. The first input terminal of the second NAND gate is electrically connected to the output terminal of the second comparator, its second input terminal is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the third control switch. The input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the second control switch. The input terminal of the second inverter is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the first control switch.

6. The relaxation oscillator according to claim 5, characterized in that, The bypass control module includes: The third comparator, the first AND gate, the second AND gate, and the third inverter; The non-inverting input of the third comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the bypass reference voltage. The first input terminal of the first AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the first control switch, and its output terminal is electrically connected to the control terminal of the first bypass switch. The first input terminal of the second AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the second control switch, and its output terminal is electrically connected to the control terminal of the second bypass switch. The input terminal of the third inverter is electrically connected to the output terminal of the third comparator, and its output terminal is electrically connected to the control terminal of the fifth control switch.

7. The relaxation oscillator according to claim 6, characterized in that, The working mechanism of the relaxation oscillator includes: Four-phase cycle.

8. The relaxation oscillator according to claim 7, characterized in that, The relaxation oscillator is enabled before the following: The third, fourth, and sixth control switches are closed, and the first, second, fifth, first bypass, and second bypass switches are opened, so that the voltage of the first capacitor, the second capacitor, and the first bypass capacitor is zero. When the voltage is zero, the third, fourth, and sixth control switches are disconnected.

9. The relaxation oscillator according to claim 8, characterized in that, The four-phase cycle includes: First phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited. When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the second phase. Second phase: When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops. When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase. Third phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited; When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the fourth phase. Fourth phase: When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops. When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

10. The relaxation oscillator according to claim 8, characterized in that, The four-phase cycle includes: First phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited; When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the second phase. Second phase: When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops. When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase. Third phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited. When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the fourth phase. Fourth phase: When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops. When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

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