High-speed data serialization circuit for high-speed high-energy-efficiency wired interface application

Abstract

The invention discloses a high-speed data serialization circuit for high-speed and high-energy-efficiency wired interface application. The high-speed data serialization circuit comprises a plurality of edge enhanced unit interval pulse generation circuits and an all-in-one multiplexer circuit, each edge enhanced unit interval pulse generation circuit is used for generating a pulse signal with a unit interval width based on the states of an input data signal and a clock signal and a preset pre-charging and rapid discharging strategy; and each input end of the all-in-one multiplexer circuit is correspondingly connected with the output end of one edge enhanced unit interval pulse generation circuit, and is used for serializing all pulse signals through an active peaking technology and outputting the pulse signals to an output node. The high-speed data serialization circuit provided by the invention can expand the bandwidth of the output node so as to adapt to higher frequency requirements.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a high-speed data serialization circuit for high-speed and high-energy-efficiency wired interface applications. BACKGROUND

[0002] With the continuous development of technologies such as 5G communication networks, high-performance computing, artificial intelligence, machine learning, and large-scale data centers in recent years, the demand for high data throughput is increasing. In order to meet the demand for large bandwidth, the data rate of single-channel wired interfaces doubles every three to four years. In recent years, the development has reached a level of more than 100 Gb / s. The standard published by the Universal Electrical Interface Standard Protocol OIF-CEI-05.2 in 2024 has defined the requirements and index requirements related to 112 Gb / s. The goal of the next generation of communication protocols is to promote the data rate to more than 200 Gb / s.

[0003] In order to avoid the problems such as large crosstalk and difficult clock synchronization of traditional parallel interface technology, the mainstream high-speed wired communication is realized through Serdes (serializer / deserializer) at the present stage. The serial link wired transmitter serializes the parallel data, and the receiver receives the data after the channel, and then deserializes the data. This has many advantages, some of which are listed here: 1. saves the number of interfaces; 2. avoids synchronous switch noise; 3. the clock is embedded in the transmitted signal, and the clock signal is recovered at the receiving end to avoid the problem of clock synchronization; 4. equalization technology can be introduced at the transmitting end and the receiving end to ensure signal quality while achieving higher data transmission rate.

[0004] The existing high-speed wired transmitter generally has two architectures, namely a digital-to-analog converter (DAC) based architecture and an analog feed-forward equalizer (FFE) based architecture. The transmitter based on the DAC architecture generally performs pre-equalization processing on the signal by a digital signal processing (DSP) module first, outputs a low-speed signal, and then serializes and retimes the low-speed signal to obtain high-speed data. The high-speed data is serialized and then output through a driver. The architecture based on the analog FFE is similar to the above process, but the pre-equalization process is completed in the analog domain. Therefore, both of the two architectures need a high-speed data serialization circuit, and for the increasingly high data rate requirement, the insufficient bandwidth of the internal nodes becomes a major limiting factor and a design difficulty in designing a high-speed wired transmitter. SUMMARY

[0005] In order to solve the problem that the insufficient bandwidth of the internal nodes becomes a major limiting factor and a design difficulty in designing a high-speed wired transmitter with increasingly high data rate requirement, the application provides a high-speed data serialization circuit for high-speed and high-energy-efficiency wired interface applications. The technical problem to be solved by the application is solved by the following technical scheme: This invention provides a high-speed data serialization circuit for high-speed, high-efficiency wired interface applications, comprising: multiple edge-enhanced unit-interval pulse generation circuits and an all-in-one multiplexer circuit. Each edge-enhanced unit-interval pulse generation circuit generates a pulse signal with a unit interval width based on the state of the input data signal and clock signal, as well as a preset pre-charge and fast discharge strategy. Each input of the all-in-one multiplexer circuit is connected to the output of an edge-enhanced unit-interval pulse generation circuit, which is used to serialize all pulse signals and output them to the output node through active peaking technology.

[0006] In one embodiment of the present invention, the edge-enhanced unit-interval pulse generation circuit includes transistors M1, M2, M3, M4, M5, and M6. The gate of transistor M1 receives a data signal, the source of transistor M1 is connected to the power supply, and the drain of transistor M1 is connected to the source of transistor M5, the source of transistor M2, and the drain of transistor M4 to form a second node. The second node is an auxiliary node for adjusting the discharge rate of the output terminal of the edge-enhanced unit-interval pulse generation circuit. The gate of transistor M2 receives a first clock signal, which is the clock signal of any phase of the eight-phase clock. Transistor M2 is connected to the common drain of transistors M5, M3, and M6 to form a first node, which is the node for outputting pulse signals. The gate of transistor M3 receives the first clock signal, and the source of transistor M3 is grounded. The gate of transistor M4 receives the first clock signal, and the source of transistor M4 is grounded. The gate of transistor M5 receives a second clock signal, which is a clock signal whose phase lags behind the first clock signal. The gate of transistor M6 receives the second clock signal, and the source of transistor M6 is grounded.

[0007] In one embodiment of the present invention, each edge-enhanced unit-interval pulse generation circuit is specifically used for: When the data signal is low, based on the state of the clock signal and the preset pre-charge and fast discharge strategies, the first node is subjected to pre-charge operation, charging operation, fast discharge operation and reset operation to generate pulse signal.

[0008] In one embodiment of the present invention, the pre-charging operation includes: When the first clock signal is low and the second clock signal is high, transistors M1 and M2 charge the first node with high impedance, and transistor M6 discharges the first node with low impedance, so as to control the voltage of the first node within the range of 1 / 3 to 1 / 4 of the power supply voltage. Charging operations include: When both the first clock signal and the second clock signal are at a low level, transistors M1, M2 and M5 together perform low-impedance charging on the first node. Rapid discharge operations include: When the first clock signal is high and the second clock signals are both low, transistor M3 discharges the first node with low impedance and transistor M4 discharges the second node with low impedance to reduce the high impedance charging of the first node by transistors M1 and M5. The reset operation includes: When both the first clock signal and the second clock signal are at a high level, transistors M3, M4, and M6 together perform low-impedance discharge on the first node to reduce the voltage of the first node to zero.

[0009] In one embodiment of the present invention, transistors M1, M2 and M5 are all PMOS transistors, and transistors M3, M4 and M6 are all NMOS transistors.

[0010] In one embodiment of the present invention, the eight-in-one multiplexer circuit includes: eight NMOS transistors M7 and an active load circuit for active peaking. The drains of eight NMOS transistors M7 are connected together to form an output node, and the output node is connected to the input terminal of the active load circuit. The sources of the eight NMOS transistors M7 are all grounded. The gate of each NMOS transistor M7 serves as an input terminal of an eight-in-one multiplexer circuit and is connected to the output terminal of an edge-enhanced unit-interval pulse generation circuit. Eight NMOS transistors M7 are used to amplify all pulse signals through transconductance, convert the amplified pulse signals into current signals, and input the current signals to the active load circuit through the output node; An active load circuit is used to generate a voltage signal that converts the current signal at the output node.

[0011] In one embodiment of the present invention, the active load circuit includes: transistor M8, transistor M9, transistor M10 and transistor M11; The gate of transistor M8 is connected to the power supply. Transistor M8 and transistor M9 are connected to the common source and to the gates of transistors M10 and M11. Transistor M8, transistors M9, M10 and M11 are connected to the common drain and to the output node. The gate of transistor M9 is grounded. The source of transistor M10 is connected to the power supply. The source of transistor M11 is grounded.

[0012] In one embodiment of the present invention, transistors M8 and M11 are NMOS transistors, and transistors M9 and M10 are PMOS transistors.

[0013] Another aspect of the present invention provides a transmitter chip for high-speed, high-efficiency wired interface applications, the chip including the high-speed data serialization circuit described in any of the above embodiments.

[0014] Another aspect of the present invention provides an electronic device including the transmitter chip in the above embodiments.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This invention provides a high-speed data serialization circuit for high-speed and high-efficiency wired interface applications, including: multiple edge-enhanced unit-interval pulse generation circuits and a multi-in-one multiplexer circuit. Each input terminal of the multi-in-one multiplexer circuit is connected to the output terminal of an edge-enhanced unit-interval pulse generation circuit, which can provide sufficient charge accumulation for pulse generation during the pre-charging stage and quickly release these charges during the fast discharge stage, thereby forming a steep falling edge. This not only improves the width of the pulse signal, but also ensures the consistency and stability of the pulse shape. Therefore, compared with the ordinary 1-UI pulse generation circuit, the proposed edge-enhanced unit-interval pulse generation circuit can generate pulse signals with a unit interval width, that is, it can generate wider pulse signals. In addition, due to the pre-charging and fast discharge design, the circuit can complete the charging and discharging process faster in each cycle, thereby adapting to higher frequency requirements.

[0016] (2) Since parasitic capacitance and inductance can cause signal attenuation in high-frequency circuits, especially the high-frequency components, in multi-in-one multiplexer circuits, by using active peaking technology to introduce specially designed active components (such as transistors), these parasitic effects can be compensated to a certain extent, especially the signal loss in the high-frequency band, thereby improving the high-frequency gain. This helps to increase the speed of the rising and falling edges of the signal, thereby expanding the bandwidth of the output node and increasing the eye diagram opening of the output node.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a high-speed data serialization circuit for high-speed, high-efficiency wired interface applications provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the working principle of the pre-charge operation of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the working principle of the charging operation of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the working principle of the fast discharge operation of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the working principle of the reset operation of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention; Figure 6 This is a timing diagram of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention; Figure 7 This is a comparative schematic diagram of the pulse signals generated by a conventional 1-UI pulse generation circuit provided in an embodiment of the present invention and the edge-enhanced 1-UI pulse generation circuit provided in this application; Figure 8 This is a small-signal model of an active load provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the frequency characteristics of the input impedance of an active load provided in an embodiment of the present invention; Figure 10 This is a schematic diagram comparing the eye diagrams at the output node of an 8:1 MUX circuit with and without active peaking, according to an embodiment of the present invention. Figure 11 This is a schematic diagram comparing the eye diagrams of the output nodes of an 8:1 MUX circuit with and without active peaking after PAM-8 modulation, as provided in an embodiment of the present invention. Detailed Implementation

[0019] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a high-speed data serialization circuit for high-speed, high-efficiency wired interface applications based on the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0020] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0022] This invention addresses the problem that insufficient bandwidth of internal nodes has become a major limiting factor and design challenge in the design of high-speed wired transmitters due to increasingly higher data rate requirements. It proposes a high-speed data serialization circuit for high-speed, high-energy-efficiency wired interface applications. Please refer to [link to relevant documentation]. Figure 1 The circuit 100 includes: multiple edge-enhanced unit interval (1-UI) pulse generation circuits 101 and an all-in-one multiplexer circuit 102.

[0023] It should be noted that the high-speed data serialization circuit 100 provided in this application embodiment specifically includes eight edge-enhanced 1-UI pulse generation circuits 101 and an 8:1 MUX circuit 102.

[0024] Each edge-enhanced 1-UI pulse generation circuit 101 is used to generate a 1-UI pulse signal based on the state of the input (i.e., the data signal generated by the previous stage) and the clock signal, as well as a preset pre-charge and fast discharge strategy.

[0025] Each input terminal of the 8:1 MUX circuit 102 is connected to the output terminal of an edge-enhanced unit-interval pulse generation circuit, which is used to serialize all pulse signals and output them to the output node 103 through active peaking technology.

[0026] The edge-enhanced 1-UI pulse generation circuit 101 will be described in detail below.

[0027] Specifically, such as Figure 1 As shown, the edge-enhanced 1-UI pulse generation circuit includes transistors M1, M2, M3, M4, M5, and M6.

[0028] Among them, transistors M1, M2 and M5 are all PMOS transistors, while transistors M3, M4 and M6 are all NMOS transistors.

[0029] Furthermore, the gate of transistor M1 receives the data signal (DATA), the source of transistor M1 is connected to the power supply, and the drain of transistor M1 is connected to the source of transistor M5, the source of transistor M2, and the drain of transistor M4 to form a second node X. The second node X is an auxiliary node for adjusting the discharge rate of the output terminal of the edge-enhanced 1-UI pulse generation circuit. The gate of transistor M2 receives the first clock signal CK8_A, which is the clock signal of any phase of the eight-phase clock CK8. Transistor M2 is connected to transistors M5, M3, and M4. The common-drain transistors M6 and M7 form a first node Y, which is the node for outputting pulse signals. The gate of transistor M3 receives the first clock signal CK8_A, and the source of transistor M3 is grounded. The gate of transistor M4 receives the first clock signal CK8_A, and the source of transistor M4 is grounded. The gate of transistor M5 receives the second clock signal CK8_B, which is a clock signal whose phase lags behind the first clock signal CK8_A. The gate of transistor M6 receives the second clock signal CK8_B, and the source of transistor M6 is grounded. The drain of transistor M6 is connected to the first node Y.

[0030] It should be noted that the 8-phase clock CK8 is a clock signal generation technology that provides eight clock signals with the same frequency but sequentially phased by 45 degrees. That is, there are eight clock signals with phases of 0°, 45°, ..., 270°, and 315°. This means that within a complete cycle (360°), eight different time points are used as references, each phase separated by 45°. Specifically, the first clock signal CK8_A is the clock signal for any phase of the 8-phase clock CK8, and the second clock signal CK8_B is a clock signal whose phase lags behind the first clock signal CK8_A. Specifically, the second clock signal CK8_B lags the first clock signal by 135°.

[0031] In one embodiment of the present invention, each edge-enhanced unit-interval pulse generation circuit is specifically used for: When the data signal is low, based on the state of the clock signal (i.e., the first clock signal CK8_A and the second clock signal CK8_B) and the preset pre-charge and fast discharge strategy, the first node Y is subjected to pre-charge operation, charging operation, fast discharge operation and reset operation to generate a pulse signal with a width of 1-UI.

[0032] It should be noted that when the data signal is at a high level, the voltage of the first node Y is periodically pulled down to zero by the transistor M4, and there is no effective pulse signal output.

[0033] The width of 1-UI is the interval between the same edges of two clock signals that are 45° out of phase.

[0034] It should be noted that, in this embodiment of the invention, the state of transistor M1 is controlled by the data signal. Specifically, when the data signal is at a low level, transistor M1 is in the on state; when the data signal is at a high level, transistor M1 is in the off state.

[0035] Specifically, such as Figure 2 As shown, the specific process of pre-charging the first node Y is as follows: When the first clock signal CK8_A is low and the second clock signal CK8_B is high, transistors M1 and M2 charge the first node Y with high impedance, and transistor M6 discharges the first node Y with low impedance, so as to control the voltage of the first node Y within the range of 1 / 3 to 1 / 4 of the power supply voltage.

[0036] It is understandable that during the pre-charging operation of the first node Y, transistors M1, M2, and M6 are in the on state, while the other transistors are in the off state.

[0037] It should be noted that transistors M1 and M2 charge the first node Y with high impedance, while transistor M6 discharges the first node Y with low impedance. This can be understood as the voltage of the first node Y being weakly pulled up by transistors M1 and M2, while the voltage of the first node Y is strongly pulled down by transistor M6. This results in the voltage of the first node Y being the voltage division value Va of transistors M1, M2, and M6, which is within the range of 1 / 3 to 1 / 4 of the power supply voltage (VDD).

[0038] The reason for controlling the voltage of the first node Y within the range of 1 / 3 to 1 / 4 of the power supply voltage is to ensure that the voltage of the first node Y is lower than the threshold voltage of the NMOS transistor, so as to prevent the NMOS transistor M7 in the subsequent 8:1 MUX circuit from turning on prematurely. This avoids the impact of this stage on the subsequent 8:1 MUX circuit and saves power consumption.

[0039] In addition, since the pre-charge is more extensive, the voltage change during the subsequent charging process will be smaller. Therefore, raising the voltage of the first node Y to the range of 1 / 3VDD to 1 / 4VDD can speed up the subsequent charging operation of the first node Y.

[0040] It should be noted that the size ratio of transistor M1 to transistor M2 can be changed to alter the... The pull-up strength of transistors M1 and M2 to the first node Y can also be changed by altering the size ratio of transistor M6 to the first node Y. In other words, by rationally designing the size ratio of transistors M1, M2, and M6, the voltage of the first node Y can be controlled within the range of 1 / 3VDD to 1 / 4VDD.

[0041] like Figure 3 As shown, the specific process of charging the first node Y is as follows: When the first clock signal CK8_A and the second clock signal CK8_B are both at a low level, transistors M1, M2 and M5 together perform low-impedance charging on the first node Y.

[0042] It is understandable that during the charging operation of the first node Y, transistors M1, M2, and M5 are in the on state, while the other transistors are in the off state.

[0043] It should be noted that transistors M1, M2, and M5 together perform low-impedance charging of the first node Y. This can be understood as the voltage of the first node Y being strongly pulled up simultaneously by transistors M1, M2, and M5. Figure 3 As shown, a pure pull-up path is formed at this point, and the pull-down path is blocked (transistors M3 and M6 are in the off state), meaning there is no pull-down path. This results in a steep rising edge at the first node Y (see details). Figure 6 ).

[0044] like Figure 4 As shown, the specific process of performing a rapid discharge operation on the first node Y is as follows: When the first clock signal is high and both second clock signals are low, transistor M3 discharges the first node Y with low impedance, and transistor M4 discharges the second node X with low impedance, so as to reduce the high impedance charging of the first node Y by transistors M1 and M5.

[0045] It is understandable that during the rapid discharge operation of the first node Y, transistors M1, M3, M4, and M5 are in the on state, while the remaining transistors are in the off state.

[0046] It should be noted that transistor M3 performs low-impedance discharge to the first node Y, and transistor M4 performs low-impedance discharge to the second node X, in order to weaken the high-impedance charging of the first node Y by transistors M1 and M5. This can be understood as the voltage of the first node Y being strongly pulled down by transistor M3, while the voltage of the second node X is also strongly pulled down by transistor M4, thus weakening the weak pull-up of the first node Y by transistors M1 and M5, thereby accelerating the discharge speed of the first node Y. At this point, both pull-up and pull-down paths exist simultaneously, resulting in a relatively steep rising edge at the first node Y (see [link to details]). Figure 6 It is understandable that during this process, the voltage at the first node Y is lower than the voltage divider value Va but not zero.

[0047] like Figure 5 As shown, the specific process of resetting the first node Y is as follows: When both the first clock signal CK8_A and the second clock signal CK8_B are at a high level, transistors M3, M4, and M6 perform low-impedance discharge on the first node Y to reduce the voltage of the first node Y to zero.

[0048] Understandably, during the reset operation of the first node Y, transistors M1, M3, M4, and M6 are in the ON state, while the remaining transistors are in the OFF state. Although transistor M1 is in the ON state during this process, there is no pull-up path to the first node Y.

[0049] It should be noted that transistors M3, M4, and M6 perform low-impedance discharge on the first node Y to reduce its voltage to zero. This can be understood as the voltage at the first node Y being strongly pulled down by transistors M3, M4, and M6. Figure 5 As shown, a pure pull-down path is formed at this time, and the pull-up path is blocked, that is, there is no pull-up path, thus reducing the voltage of the first node Y to zero.

[0050] For further details, please see Figure 6 , Figure 6 This is a timing diagram of an edge-enhanced 1-UI pulse generation circuit provided in an embodiment of the present invention, as shown below. Figure 6 As shown, when the data signal DATA is high (H), the edge-enhanced 1-UI pulse generation circuit is inactive and idle; when the data signal DATA is low (L), the edge-enhanced 1-UI pulse generation circuit is activated. Specifically, when the first clock signal CK8_A is low and the second clock signal CK8_B is high, the voltage at the first node Y rises to the voltage divider value Va (corresponding to...). Figure 2During the pre-charge operation, when both the first clock signal CK8_A and the second clock signal are low, the voltage at the first node Y rises rapidly (corresponding to...). Figure 3 During the charging operation, when the first clock signal CK8_A is high and the second clock signal CK8_B is low, the voltage at the first node Y drops rapidly (corresponding to...). Figure 4 During the rapid discharge operation, when both the first clock signal CK8_A and the second clock signal CK8_B are at a high level, the voltage at the first node Y is pulled down to zero (corresponding to...). Figure 5 (Reset operation).

[0051] As can be seen from the above, the edge-enhanced 1-UI pulse generation circuit 101 in this embodiment of the invention uses fewer stacked pull-up path transistors, which can reduce the size of the pull-up transistors and obtain higher bandwidth. Furthermore, since the edge-enhanced 1-UI pulse generation circuit 101 provided by this invention benefits from the principle of pre-charging and fast discharging, it has more sufficient charging time and a fast discharge edge, therefore... Figure 7 As shown, at the same rate, compared with the existing 1-UI pulse generation circuit, the edge-enhanced 1-UI pulse generation circuit 101 proposed in this invention generates a higher amplitude pulse signal, that is, a wider pulse signal width. Therefore, the edge-enhanced 1-UI pulse generation circuit proposed in this invention can adapt to higher frequency requirements.

[0052] After introducing the edge-enhanced 1-UI pulse generation circuit 101, the 8:1 MUX circuit 102 will be described in detail next.

[0053] Specifically, such as Figure 1 As shown, the 8:1 MUX circuit 102 includes eight NMOS transistors M7 and an active load circuit 103 for active peaking.

[0054] The drains of eight NMOS transistors M7 are connected together to form an output node OUT, and the output node OUT is connected to the input terminal of the active load circuit 103. The sources of the eight NMOS transistors M7 are all grounded, and the gate of each NMOS transistor M7 is connected to the output terminal of an edge-enhanced unit-interval pulse generation circuit as the input terminal of the 8:1 MUX circuit 102.

[0055] Among them, eight NMOS transistors M7 are used to amplify all pulse signals through transconductance, convert the transconductance amplified pulse signals into current signals, and input the current signals to the active load circuit 103 through the output node OUT.

[0056] Specifically, such as Figure 1As shown, the eight pulse signals PG<7:0> generated by the lower edge enhancement type 1-UI pulse generation circuit of the front stage are respectively passed through the NMOS transistor M7 in the 8:1 MUX circuit 102. <7> M7 <7> M7 <6> ... M7 <1> M7 <0> Eight NMOS transistors perform transconductance amplification, convert the transconductance amplified pulse signal into a current signal, and input the current signal to the active load circuit 103 through the output node OUT.

[0057] The active load circuit 103 is used to generate a voltage signal that converts the current signal at the output node OUT.

[0058] Furthermore, the active load circuit 103 includes transistors M8, M9, M10, and M11.

[0059] Among them, transistors M8 and M11 are NMOS transistors, and transistors M9 and M10 are PMOS transistors.

[0060] Specifically, such as Figure 1 As shown, the gate of transistor M8 is connected to the power supply. Transistor M8 and transistor M9 are connected to the common source and to the gates of transistors M10 and M11. Transistor M8, transistors M9, M10 and M11 are connected to the common drain and to the output node OUT. The gate of transistor M9 is grounded. The source of transistor M10 is connected to the power supply. The source of transistor M11 is grounded.

[0061] To verify that the active load circuit 103 can extend the bandwidth of the output node OUT, the transmission gates (i.e., transistors M8, M9, M10, and M11) operating in the transistor region can be represented as a resistor. And construct a small-signal model for active loads used for active peaking (the small-signal model is as follows). Figure 8 A simplified analysis is performed (as shown).

[0062] Specifically, based on the small-signal model of the active load and the current conservation relationship, the following equation can be obtained:

[0063]

[0064] in, The voltage at the output node. For load capacitance, This is the sum of the transconductances of transistors M10 and M11. For the Laplace operator, Gate-source capacitance, This is the input current, which is the current output by the eight NMOS transistors M7. The input impedance of the active load is... Figure 8 In This is the gate-source voltage.

[0065] From the formula It can be seen that an active load has one zero and two poles (i.e., the dominant pole and the secondary pole), and combined with Figure 9 , Figure 9 This is a schematic diagram of the frequency response of the input impedance of an active load according to an embodiment of the present invention, wherein, Figure 9 In the middle x-axis, Z1 represents the absolute value of the zero-point frequency, P1 represents the absolute value of the dominant pole frequency, and P2 represents the absolute value of the secondary pole frequency. It can be seen that the characteristics of the active load between the zero and dominant poles can be equivalent to an inductor, thus offsetting the load capacitance to a certain extent. Due to the influence of this, the bandwidth of the output node OUT can be expanded.

[0066] To verify that the active load circuit 103 can increase the eye diagram opening of the output node OUT, the eye diagrams of the 8:1 MUX circuit with and without active peaking (i.e., using a PMOS load) at the output node OUT were simulated. The simulation results can be found in [reference needed]. Figure 10 ,Depend on Figure 10 As can be seen, the level dispersion is reduced after using active peaking. Since high-speed wired transmitters often require higher-order modulation methods, such as PAM-4 and PAM-8, to further illustrate the benefits of reduced level dispersion, eye diagrams of the output node OUT of an 8:1 MUX circuit with and without active peaking, after PAM-8 modulation, were simulated. The simulation results can be found in [reference needed]. Figure 11 ,Depend on Figure 11 It can be seen that the 8:1 MUX circuit with source peaking provided in this embodiment of the invention has a significantly larger eye diagram opening at the output node OUT.

[0067] It should be noted that since the lower edge enhanced 1-UI pulse generation circuit 101 adopts an 8:1 MUX after the stage, the propagation delay margin (Tcq) of the reset data signal is relaxed to 7-UI instead of the traditional 4:1 MUX architecture. The data needs to be stable within 3-UI. Therefore, the timing constraints on the front-end lower edge enhanced 1-UI pulse generation circuit are lower, which allows the lower edge enhanced 1-UI pulse generation circuit 101 to use fewer pull-up path stacked transistors, thereby reducing power consumption and increasing bandwidth.

[0068] In summary, this invention provides a high-speed data serialization circuit for high-speed, high-efficiency wired interface applications, comprising: multiple edge-enhanced 1-UI pulse generation circuits and a multi-in-one multiplexer circuit. Each input terminal of the multi-in-one multiplexer circuit is connected to the output terminal of an edge-enhanced 1-UI pulse generation circuit, which can provide sufficient charge accumulation for pulse generation during the pre-charging phase and rapidly release these charges during the fast discharge phase, thereby forming a steep falling edge. This not only improves the pulse signal width but also ensures the consistency and stability of the pulse shape. Therefore, compared with ordinary 1-UI pulse generation circuits, the proposed edge-enhanced 1-UI pulse generation circuit can generate pulse signals with a 1-UI width, i.e., it can generate wider pulse signals. In addition, due to the pre-charging and fast discharge design, the circuit can complete the charging and discharging process faster in each cycle, thereby adapting to higher frequency requirements.

[0069] In addition, parasitic capacitance and inductance can cause signal attenuation in high-frequency circuits, especially affecting high-frequency components. Therefore, in multi-in-one multiplexer circuits, the introduction of specially designed active components (such as transistors) using active peaking technology can compensate for these parasitic effects to a certain extent, especially the signal loss in the high-frequency band, thereby improving the high-frequency gain. This helps to increase the speed of the signal's rising and falling edges, thereby expanding the bandwidth of the output node and increasing the eye diagram opening of the output node.

[0070] Another embodiment of the present invention provides a transmitter chip for high-speed, high-efficiency wired interface applications, the chip including the high-speed data serialization circuit in the above embodiment.

[0071] Another embodiment of the present invention provides an electronic device that includes the transmitter chip described in the above embodiments.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-speed data serialization circuit for high-speed, high-efficiency wired interface applications, characterized in that, include: Multiple edge-enhanced unit-interval pulse generation circuits and one all-in-one multiplexer circuit; Each of the aforementioned edge-enhanced unit-interval pulse generation circuits is used to generate a pulse signal with a unit interval width based on the state of the input data signal and clock signal, as well as a preset pre-charge and fast discharge strategy. Each input terminal of the all-in-one multiplexer circuit is connected to the output terminal of the edge-enhanced unit-interval pulse generation circuit, which is used to serialize all the pulse signals and output them to the output node through active peaking technology.

2. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 1, characterized in that, The edge-enhanced unit-interval pulse generation circuit includes transistors M1, M2, M3, M4, M5, and M6. The gate of transistor M1 receives the data signal, the source of transistor M1 is connected to the power supply, and the drain of transistor M1 is connected to the source of transistor M5, the source of transistor M2, and the drain of transistor M4 to form a second node. The second node is an auxiliary node for adjusting the discharge rate of the output terminal of the edge-enhanced unit-interval pulse generation circuit. The gate of transistor M2 receives a first clock signal, which is the clock signal of any phase of an eight-phase clock. Transistor M2, transistor M5, transistor M3, and transistor M6 share a common drain to form a first node, which is the node that outputs the pulse signal. The gate of transistor M3 receives the first clock signal, and the source of transistor M3 is grounded. The gate of transistor M4 receives the first clock signal, and the source of transistor M4 is grounded. The gate of transistor M5 receives a second clock signal, which is a clock signal whose phase lags behind the first clock signal. The gate of transistor M6 receives the second clock signal, and the source of transistor M6 is grounded.

3. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 2, characterized in that, Each of the aforementioned edge-enhanced unit-interval pulse generation circuits is specifically used for: When the data signal is at a low level, based on the state of the clock signal and the preset pre-charge and fast discharge strategy, the first node is subjected to pre-charge operation, charging operation, fast discharge operation and reset operation to generate the pulse signal.

4. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 3, characterized in that, The pre-charging operation includes: When the first clock signal is at a low level and the second clock signal is at a high level, transistors M1 and M2 charge the first node with high impedance, and transistor M6 discharges the first node with low impedance, so as to control the voltage of the first node within the range of 1 / 3 to 1 / 4 of the power supply voltage. The charging operation includes: When both the first clock signal and the second clock signal are at a low level, transistor M1, transistor M2 and transistor M5 together perform low-impedance charging on the first node; The rapid discharge operation includes: When the first clock signal is at a high level and both of the second clock signals are at a low level, the transistor M3 discharges the first node with low impedance and the transistor M4 discharges the second node with low impedance to reduce the high impedance charging of the first node by the transistors M1 and M5. The reset operation includes: When both the first clock signal and the second clock signal are at a high level, transistors M3, M4, and M6 together perform low-impedance discharge on the first node to reduce the voltage of the first node to zero.

5. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 2, characterized in that, Transistor M1, transistor M2, and transistor M5 are all PMOS transistors, while transistor M3, transistor M4, and transistor M6 are all NMOS transistors.

6. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 1, characterized in that, The eight-in-one multiplexer circuit includes: eight NMOS transistors M7 and an active load circuit for active peaking. The drains of the eight NMOS transistors M7 are connected together to form the output node, and the output node is connected to the input terminal of the active load circuit. The sources of the eight NMOS transistors M7 are all grounded, and the gate of each NMOS transistor M7 serves as an input terminal of the eight-in-one multiplexer circuit and is correspondingly connected to the output terminal of the edge-enhanced unit-interval pulse generation circuit. The eight NMOS transistors M7 are used to amplify all the pulse signals through transconductance, convert the amplified pulse signals into current signals, and input the current signals to the active load circuit through the output node. The active load circuit is used to generate a voltage signal that converts the current signal at the output node.

7. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 6, characterized in that, The active load circuit includes transistors M8, M9, M10, and M11. The gate of transistor M8 is connected to the power supply. Transistor M8 is connected to the common source of transistor M9, and is also connected to the gate of transistor M10 and the gate of transistor M11. Transistor M8 is connected to the common drain of transistors M9, M10, and M11, and is connected to the output node. The gate of transistor M9 is grounded. The source of transistor M10 is connected to the power supply. The source of transistor M11 is grounded.

8. The high-speed data serialization circuit for high-speed, high-efficiency wired interface applications according to claim 7, characterized in that, Transistor M8 and transistor M11 are NMOS transistors, and transistor M9 and transistor M10 are PMOS transistors.

9. A transmitter chip for high-speed, high-efficiency wired interface applications, characterized in that, Includes the high-speed data serialization circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the transmitter chip as described in claim 9.

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