Differential output driver in current driving mode

Abstract

The invention relates to the field of differential output drivers, in particular to a differential output driver in a current driving mode, which comprises an enabling module and a driving module, and is characterized in that the driving module comprises an H-bridge branch, and the H-bridge branch comprises an MOS tube N5, an MOS tube N6, an MOS tube N7 and an MOS tube N8; a first signal output end of the enabling module is electrically connected with a grid electrode of the MOS tube N5 and a grid electrode of the MOS tube N8, a second signal output end of the enabling module is electrically connected with a grid electrode of the MOS tube N7 and a grid electrode of the MOS tube N6, a source electrode of the MOS tube N5 and a drain electrode of the MOS tube N6 serve as output ends D-to be connected with the outside, and a source electrode of the MOS tube N7 and a drain electrode of the MOS tube N8 serve as output ends D + to be connected with the outside. The first signal output end is changed to output a high level or a low level to adjust the positive differential voltage or the differential voltage, and the H-bridge branch directionally guides the constant current to pass through the external load to form the differential voltage.

Description

Technical Field

[0001] This invention relates to the field of differential output drivers, and more specifically to a current-driven differential output driver. Background Technology

[0002] A differential output driver is an electronic device that converts single-ended or differential signals into differential output signals. Its core function is to generate signal pairs with equal amplitude and 180° phase difference through a complementary output mechanism, thereby effectively suppressing common-mode noise and electromagnetic interference during transmission. These drivers are typically implemented using differential amplifiers or dedicated driver circuits and have high-speed characteristics; their output swing is usually twice that of a single-ended driver.

[0003] In analog / digital video transmission, differential drivers can replace traditional transformer solutions, preserving low-frequency and DC information while reducing line attenuation; in ADC driving scenarios, their fixed gain characteristics and level shifting capabilities can simplify circuit design.

[0004] Traditional differential output drivers use voltage-mode driving, which requires charging and discharging the load capacitor to change the voltage level. To obtain a faster edge, a larger drive current is required, resulting in slower switching speed and a significant increase in power consumption and heat generation. Summary of the Invention

[0005] The purpose of this invention is to provide a current-driven differential output driver, which aims to improve the problems of traditional differential output drivers that use voltage-driven mode, require charging and discharging the load capacitor to change the voltage level, require a larger drive current to obtain a faster edge, have a slow switching speed, and have a significant increase in power consumption and heat generation.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A current-driven differential output driver includes an enable module, a reference current source module, and a drive module. The drive module includes an H-bridge branch, which includes MOSFETs N5, N6, N7, and N8, and resistors R5 and R6. The first signal output terminal of the enable module is electrically connected to the gate of MOSFET N5 and the gate of MOSFET N8. The second signal output terminal of the enable module is electrically connected to the gate of MOSFET N7 and the gate of MOSFET N6. The reference current source module outputs a drive current to one end of resistor R5. The other end of resistor R5 is electrically connected to the drain of MOSFET N5 and the drain of MOSFET N7. The source of MOSFET N5 and the drain of MOSFET N6 are electrically connected and serve as the output terminal D- connected to the outside. The source of MOSFET N7 and the drain of MOSFET N8 are electrically connected and serve as the output terminal D+ connected to the outside. An external load is connected between the output terminals D- and D+. The source of both MOS transistor N6 and MOS transistor N8 is electrically connected to one end of resistor R6, and the other end of resistor R6 is grounded.

[0007] Furthermore, the enabling module includes MOSFETs P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21 and N11, N12, N13, N14, N15, N16, N17, and N18; External power supply outputs VCC to the source of MOSFET P10, the source of MOSFET P11, the source of MOSFET P12, the source of MOSFET P13, the source of MOSFET P16, the source of MOSFET P17, the source of MOSFET P18, and the source of MOSFET P19. An external input signal DIN is input to the gates of MOSFET P10 and N11. The drains of MOSFET P10 and N11 are both connected to the gates of MOSFET P11, N12, P16, and N15. The drains of MOSFET P11 and N12 are both electrically connected to the gates of MOSFET P14, P15, and N13. The drains of MOSFET P14 and N13 are both electrically connected to the drains of MOSFET P15 and N14, and are also electrically connected as the first signal output terminal to the gates of MOSFET N5 and N8. An external low-level enable signal EN is input to the gates of MOSFETs P12, P13, N14, P18, P19, and N18; the drain of MOSFET P12 is electrically connected to the source of MOSFET P14, and the drain of MOSFET P13 is electrically connected to the source of MOSFET P15. The drains of MOSFET P16 and N15 are electrically connected to the gates of MOSFET P17 and N16, respectively. The drains of P17 and N16 are electrically connected to the gates of MOSFET P20, P21, and N17, respectively. The drain of MOSFET P18 is electrically connected to the source of MOSFET P20, and the drain of MOSFET P19 is electrically connected to the source of MOSFET P21. The drains of MOSFET P20 and N17 are electrically connected to the drains of MOSFET P21 and N18, and are also electrically connected as a second signal output terminal to the gates of MOSFET N7 and N6, respectively. The sources of MOSFETs N11, N12, N13, N14, N15, N16, N17, and N18 are all grounded.

[0008] Furthermore, the reference current source module includes an operational amplifier U100, MOSFETs P0, P1, P2, P3, N0, N1, Q0, Q1, Q2, and resistors R1, R2, R3, and R4. External power supply outputs VCC to the source of MOSFET P0, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3; The gate and drain of MOSFET P1 are electrically connected to the drain of MOSFET N0, the gate of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3. The drain of MOSFET P1 is electrically connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of operational amplifier U100. The other end of resistor R3 is electrically connected to the emitter of transistor Q1 and the non-inverting input of operational amplifier U100. The other end of resistor R2 is electrically connected to the emitter of transistor Q0. The output of operational amplifier U100 is electrically connected to the gate of MOSFET N0. The drain of MOSFET P2 is electrically connected to one end of resistor R4 and serves as the first current output terminal, which is electrically connected to the drive module. The other end of resistor R4 is electrically connected to the emitter of transistor Q2. The drain of MOSFET P3 is electrically connected to the drain and gate of MOSFET N1 and serves as the second current output terminal, which is electrically connected to the drive module. The source of MOSFET N0, the source of MOSFET N1, the base of transistor Q0, the emitter of transistor Q0, the base of transistor Q1, the emitter of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2 are all grounded.

[0009] Furthermore, the drive module also includes a drive branch, a feedback branch, and a control branch; The reference current source module outputs a reference current to the drive branch and the feedback branch. The output terminal of the drive branch is electrically connected to the input terminal of the H-bridge branch and the input terminal of the feedback branch. The control branch is connected between the ground terminal of the H-bridge branch and the control terminal of the feedback branch.

[0010] Furthermore, the driving branch includes MOSFET P4, MOSFET P5, MOSFET P6 and MOSFET N2; An external power supply outputs VCC to the source of MOSFET P4, the source of MOSFET P5, and the source of MOSFET P6. The drain of MOSFET P6 is electrically connected to the control branch. The reference current source module outputs a reference current to the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the gate and drain of MOSFET P4, the gate of MOSFET P5, and the gate of MOSFET P6. The drain of MOSFET P5 is electrically connected to one end of resistor R5 and the feedback branch. The source of the MOS transistor N2 is grounded.

[0011] Furthermore, the feedback branch includes operational amplifier U101, MOSFET P8, MOSFET N3, and MOSFET N4; The external power supply outputs VCC to the source of MOSFET P8; The reference current source module outputs a reference current to the non-inverting input of the operational amplifier U101. The output of the drive branch is electrically connected to the drain of the MOS transistor N4 and the inverting input of the operational amplifier U101. The output of the operational amplifier U101 is electrically connected to the gate of the MOS transistor P8. The drain of the MOS transistor P8 is electrically connected to the gate and drain of the MOS transistor N3 and the gate of the MOS transistor N4. The sources of both MOS transistor N3 and MOS transistor N4 are grounded.

[0012] Furthermore, the control branch includes MOSFETs P7, P9, N9, and N10; External power supply outputs VCC to the source of MOSFET P7 and the source of MOSFET P9; The source of MOSFET N6 and the source of MOSFET N8 are both electrically connected to the gate of MOSFET N9. The output terminal of the drive branch is electrically connected to the drain of MOSFET N9, the gate of MOSFET P9, and the gate of MOSFET N10. The drain of MOSFET P9 and the drain of MOSFET N10 are both electrically connected to the gate of MOSFET P7. The drain of MOSFET P7 is electrically connected to the control terminal of the feedback branch. The sources of both MOS transistor N9 and MOS transistor N10 are grounded.

[0013] Furthermore, the following condition is satisfied: (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 ; Among them, (W / L) NX This represents the width-to-length ratio (W / L) of the MOSFET NX. N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7 N8 This represents the width-to-length ratio of the MOSFET N8.

[0014] Furthermore, the following condition is satisfied: (W / L) P0 (W / L) P1 (W / L) P2 (W / L) P3 =1:M:N:1; R1=R3; Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P0 The width-to-length ratio (W / L) of MOSFET P0 P1 The width-to-length ratio (W / L) of MOSFET P1 P2 The width-to-length ratio (W / L) of MOSFET P2 P3 R1 is the width-to-length ratio of MOSFET P3; M and N are proportionality coefficients; R1 is the resistance value of resistor R1, and R3 is the resistance value of resistor R3.

[0015] Furthermore, the following condition is satisfied: (W / L) P4(W / L) P5 =K:J; R5=R6; Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P4 The width-to-length ratio (W / L) of MOSFET P4 P5 R5 is the width-to-length ratio of MOSFET P5; K and J are proportionality coefficients; R5 is the resistance value of resistor R5, and R6 is the resistance value of resistor R6.

[0016] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: The second signal output terminal of the enable module stably outputs a low-level signal. By changing the output level of the first signal output terminal to high or low level, the positive differential voltage or differential voltage can be adjusted to achieve current control and generate a differential signal. The constant current is guided through the H-bridge branch to form a differential voltage through the external load. The current direction can be switched with a small current, without the need to provide a large transient current for charging and discharging the capacitor, which effectively improves the switching speed and reduces the heat generation of power consumption. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the differential output driver in the current-driven mode described in this invention. Figure 2 This is a signal simulation diagram of the differential output driver in the current-driven mode described in this invention; Figure 3 This is a simulation diagram of the power supply rejection ratio (PSRR) of the differential output driver in the current-driven mode described in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0020] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0021] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0022] Please refer to Figure 1-3 As shown, this embodiment provides a current-driven differential output driver, including an enable module, a reference current source module, and a drive module. The drive module includes an H-bridge branch, which includes MOSFETs N5, N6, N7, and N8, and resistors R5 and R6.

[0023] The first signal output terminal of the enable module is electrically connected to the gates of MOSFETs N5 and N8. The second signal output terminal of the enable module is electrically connected to the gates of MOSFETs N7 and N6. The reference current source module outputs drive current to the drains of MOSFETs N5 and N7, i.e., the output terminal of the reference current source module is electrically connected to one end of resistor R5, and the other end of resistor R5 is electrically connected to the drains of MOSFETs N5 and N7. The source of MOSFET N5 and the drain of MOSFET N6 are electrically connected and serve as the output terminal D-, connected to the external circuitry. The source of MOSFET N7 and the drain of MOSFET N8 are electrically connected and serve as the output terminal D+, connected to the external circuitry. An external load is connected between the output terminals D- and D+.

[0024] The sources of MOSFETs N6 and N8 are both electrically connected to one end of resistor R6, and the other end of resistor R6 is grounded. In this embodiment, resistor R7 is an external load circuit, referring to an external load.

[0025] The second signal output terminal of the enable module stably outputs a low-level signal. By changing the output level of the first signal output terminal to high or low level, the positive differential voltage or differential voltage can be adjusted to achieve current control and generate a differential signal. The constant current is guided through the H-bridge branch to form a differential voltage through the external load. The current direction can be switched with a small current, without the need to provide a large transient current for charging and discharging the capacitor, which effectively improves the switching speed and reduces the heat generation of power consumption.

[0026] Please refer to Figure 1As shown, the enable module includes MOSFETs P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21 and N11, N12, N13, N14, N15, N16, N17, and N18.

[0027] External power supply outputs VCC to the source of MOSFET P10, the source of MOSFET P11, the source of MOSFET P12, the source of MOSFET P13, the source of MOSFET P16, the source of MOSFET P17, the source of MOSFET P18, and the source of MOSFET P19.

[0028] The external input signal DIN is input to the gates of MOSFET P10 and N11. The drains of MOSFET P10 and N11 are both connected to the gates of MOSFET P11, N12, P16, and N15. The drains of MOSFET P11 and N12 are electrically connected to the gates of MOSFET P14, P15, and N13. The drains of MOSFET P14 and N13 are electrically connected to the drains of MOSFET P15 and N14, and serve as the first signal output terminal, electrically connected to the gates of MOSFET N5 and N8.

[0029] An external low-level enable signal EN is input to the gates of MOSFETs P12, P13, N14, P18, P19, and N18; the drain of MOSFET P12 is electrically connected to the source of MOSFET P14, and the drain of MOSFET P13 is electrically connected to the source of MOSFET P15.

[0030] The drains of MOSFET P16 and N15 are electrically connected to the gates of MOSFET P17 and N16. The drains of P17 and N16 are electrically connected to the gates of MOSFET P20, P21, and N17. The drain of MOSFET P18 is electrically connected to the source of MOSFET P20, and the drain of MOSFET P19 is electrically connected to the source of MOSFET P21. The drains of MOSFET P20 and N17 are electrically connected to the drains of MOSFET P21 and N18, and serve as the second signal output terminal, electrically connected to the gates of MOSFET N7 and N6.

[0031] The sources of MOSFETs N11, N12, N13, N14, N15, N16, N17, and N18 are all grounded.

[0032] Please refer to Figure 2 As shown, attached Figure 2 This is a signal simulation diagram, attached. Figure 2 It can be seen that when the external low-level enable signal EN outputs a low level and the external input signal DIN outputs a high level, the drain outputs of MOSFETs P15 and N14 are low, while the drain outputs of MOSFETs P21 and N18 are high. This drives MOSFETs N6 and N7 to turn on, and MOSFETs N5 and N8 to turn off. The drive current flows from the output terminal D+ to the output terminal D- and then to ground. D+ -V D- >0 generates a positive differential voltage, where V D+ V is the voltage value at the output terminal D+. D- This is the voltage value at the output terminal D-.

[0033] When the external low-level enable signal EN outputs a low level and the external input signal DIN outputs a low level: the drain outputs of MOSFETs P15 and N14 are high, and the drain outputs of MOSFETs P21 and N18 are low. This drives MOSFETs N5 and N8 to turn on, and MOSFETs N6 and N7 to turn off. The drive current flows from the output terminal D- to the output terminal D+ and then to ground. D+ -V D- A value less than 0 generates a negative differential voltage. When the external low-level enable signal EN outputs a high level, the circuit does not output a differential level.

[0034] Please refer to Figure 1 As shown, the reference current source module includes operational amplifier U100, MOSFETs P0, P1, P2, P3, N0, N1, transistors Q0, Q1, Q2, and resistors R1, R2, R3, and R4.

[0035] The external power supply outputs VCC to the source of MOSFET P0, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3.

[0036] The gate and drain of MOSFET P1 are electrically connected to the drain of MOSFET N0, the gate of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3. The drain of MOSFET P1 is electrically connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of operational amplifier U100. The other end of resistor R3 is electrically connected to the emitter of transistor Q1 and the non-inverting input of operational amplifier U100. The other end of resistor R2 is electrically connected to the emitter of transistor Q0. The output of operational amplifier U100 is electrically connected to the gate of MOSFET N0.

[0037] The drain of MOSFET P2 is electrically connected to one end of resistor R4, serving as the first current output terminal and electrically connected to the drive module. The other end of resistor R4 is electrically connected to the emitter of transistor Q2. The drain of MOSFET P3 is electrically connected to the drain and gate of MOSFET N1, serving as the second current output terminal and electrically connected to the drive module.

[0038] The source of MOSFET N0, the source of MOSFET N1, the base of transistor Q0, the emitter of transistor Q0, the base of transistor Q1, the emitter of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2 are all grounded.

[0039] The gate and drain of MOSFET P0 are shorted to generate a reference current I. REF And the current is output to the drive module through the first current output terminal and the second current output terminal. Furthermore, the operational amplifier U100 outputs the reference current I... REF The control mechanism works as follows: when the current flowing through MOSFET P1 increases, the voltage at nodes X and Y increases, the output voltage of operational amplifier U100 decreases, and the current flowing through MOSFET N0 decreases, thereby controlling the reference current I. REF Reduced. In this embodiment, node X is located at the non-inverting input of operational amplifier U100, and node Y is located at the inverting input of operational amplifier U100.

[0040] Please refer to Figure 1 As shown, the drive module also includes a drive branch, a feedback branch, and a control branch. The reference current source module outputs a reference current to the drive branch and the feedback branch. The output terminal of the drive branch is electrically connected to the input terminals of the H-bridge branch and the feedback branch. The control branch is connected between the ground terminal of the H-bridge branch and the control terminal of the feedback branch. The drive branch provides drive current to the H-bridge branch; the feedback branch provides negative feedback to the drive circuit to ensure that the drive current maintains a standard value; the control branch controls the operating state of the drive module. When no current flows through the H-bridge branch, the drive module is in a shut-off state, i.e., it enters a low-power state under no-load conditions, reducing energy consumption.

[0041] Specifically, the drive branch includes MOSFETs P4, P5, P6, and N2.

[0042] The external power supply outputs VCC to the source of MOSFET P4, the source of MOSFET P5, and the source of MOSFET P6. The drain of MOSFET P6 is electrically connected to the control branch.

[0043] The reference current source module outputs a reference current to the gate of MOSFET N2. Specifically, the drain of MOSFET P3 and the drain and gate of MOSFET N1 are electrically connected to the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the gate and drain of MOSFET P4, the gate of MOSFET P5, and the gate of MOSFET P6. The drain of MOSFET P5 is electrically connected to one end of resistor R5 and the feedback branch. The source of MOSFET N2 is grounded.

[0044] MOSFETs N2 and P4 affect the reference current I. REF Replication is performed, and the input current I is controlled through MOSFET P5. REF After being proportionally amplified, it is output as a drive circuit to the H-bridge branch, feedback branch, and control branch.

[0045] Specifically, the feedback branch includes operational amplifier U101, MOSFET P8, MOSFET N3, and MOSFET N4; the external power supply output VCC is connected to the source of MOSFET P8.

[0046] The reference current source module outputs a reference current to the non-inverting input of operational amplifier U101, meaning the drain of MOSFET P2 is electrically connected to the non-inverting input of operational amplifier U101. The output of the drive branch is electrically connected to the drain of MOSFET N4 and the inverting input of operational amplifier U101, meaning the drain of MOSFET P5 is electrically connected to the drain of MOSFET N4 and the inverting input of operational amplifier U101. The output of operational amplifier U101 is electrically connected to the gate of MOSFET P8, and the drain of MOSFET P8 is electrically connected to the gate and drain of MOSFET N3 and the gate of MOSFET N4. The sources of MOSFET N3 and MOSFET N4 are both grounded.

[0047] MOSFET P2 for reference current I REFThe circuit replicates the input voltage VP of the non-inverting input of operational amplifier U101, which is formed by resistor R4 and transistor Q2. Transistor Q2 further raises VP to avoid excessive current consumption by resistor R4 alone. The drain voltages of MOSFETs P5 and N4 serve as the inverting input voltage VN of operational amplifier U101. MOSFET N4 acts as a sampling transistor. When the drive current is too high, its drain voltage rises, causing the output voltage of operational amplifier U101 to drop. This raises the gate voltage of MOSFET N4, increasing its sampling current and restoring the drive current to its standard value. Conversely, when the drive current is too low, the sampling current of MOSFET N4 decreases, ensuring that as much of the current flowing through MOSFET P5 as possible serves as the drive current, thus restoring the drive circuit to its standard value.

[0048] Specifically, the control branch includes MOSFETs P7, P9, N9, and N10; the external power supply outputs VCC to the source of MOSFETs P7 and P9.

[0049] The sources of MOSFETs N6 and N8 are both electrically connected to the gate of MOSFET N9. The output of the drive branch is electrically connected to the drain of MOSFET N9, the gate of MOSFET P9, and the gate of MOSFET N10; that is, the drain of MOSFET P6 is electrically connected to the drain of MOSFET N9, the gate of MOSFET P9, and the gate of MOSFET N10. The drains of MOSFETs P9 and N10 are both electrically connected to the gate of MOSFET P7. The drain of MOSFET P7 is electrically connected to the control terminal of the feedback branch; that is, the drain of MOSFET P7 is electrically connected to the output of operational amplifier U101. The sources of MOSFETs N9 and N10 are both grounded.

[0050] Under normal operating conditions, i.e., under load, MOSFET N9 is in the ON state, and the drains of MOSFET P9 and N10 output a high level to turn off MOSFET P7. When there is no load, since there is no current path in the H-bridge branch, resistor R6 does not generate a voltage drop, causing MOSFET N9 to be in the OFF state. The drains of MOSFET P9 and N10 output a low level to turn on MOSFET N7. MOSFET N7 conducts, introducing a high level from external VCC, which turns off MOSFET P8, thus shutting down the drive module and effectively reducing power consumption.

[0051] Furthermore, the following condition is satisfied: (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L)N8 ; (W / L) P0 (W / L) P1 (W / L) P2 (W / L) P3 =1:M:N:1; (W / L) P4 (W / L) P5 =K:J; (W / L) N1 = (W / L) N2 ; R1=R3; R5=R6; Among them, (W / L) NX This represents the width-to-length ratio (W / L) of the MOSFET NX. N1 The width-to-length ratio (W / L) of MOSFET N1 N2 The width-to-length ratio (W / L) of MOSFET N2 N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7 N8 This represents the width-to-length ratio of the MOSFET N8.

[0052] Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P0 The width-to-length ratio (W / L) of MOSFET P0 P1 The width-to-length ratio (W / L) of MOSFET P1 P2 The width-to-length ratio (W / L) of MOSFET P2 P3 The width-to-length ratio (W / L) of MOSFET P3 P4 The width-to-length ratio (W / L) of MOSFET P4 P5 R1 is the width-to-length ratio of MOSFET P5; M and N are proportionality coefficients, K and J are proportionality coefficients; R1 is the resistance value of resistor R1, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, and R6 is the resistance value of resistor R6.

[0053] According to the appendix Figure 1 From the specific circuit diagram, we can see that the current flowing through transistor Q1 is... IQ1 It is equal to the current flowing through R3, that is ; Where V Z It is the voltage at node Z, V X It is the voltage at node X, where node Z is located at the drain of MOSFET P1.

[0054] The open-loop gain relationship of operational amplifier U100 is as follows: ; Among them, V out It is the output voltage of operational amplifier U100, A OL V is the open-loop gain of the operational amplifier. Y Let be the voltage at node Y.

[0055] Because of the existence of negative feedback regulation, that is, ; Where β is a feedback coefficient less than 1.

[0056] From this, we can obtain, ; Due to the operational amplifier A OL Approaching infinity Right now, ; The voltage drop across resistor R2 can be expressed as: ; Among them, V BE0 V is the base-emitter voltage of transistor Q0. BE1 V is the base-emitter voltage of transistor Q1, n is the ratio of the number of transistors Q1 and Q2 connected in parallel, and V is the base-emitter voltage of transistor Q1. T This is thermal voltage.

[0057] According to the appendix Figure 1 From the specific circuit diagram, we can see that the current I flowing through transistor Q0 is... Q0 The current flowing through resistor R2 is equal to the current flowing through resistor R2, and due to the negative feedback adjustment of operational amplifier U100, the current is equal to the current flowing through resistor R2. ; According to the current mirror ratio, the current I flowing through MOSFET P1 is... P1 It is the current I flowing through the MOSFET P0 REF M times, and I P1 =I Q0 +I Q1 From this, we can obtain ; According to the current mirror ratio, the current I flowing through MOSFET P2 is... P2 It is the current I flowing through the MOSFET P0 REF N times, that is, ; Therefore, the input voltage VP at the non-inverting input terminal of operational amplifier U101 is: ; Among them, V BE2 This is the base-emitter voltage of transistor Q2.

[0058] According to the current mirror ratio, the current flowing through MOSFET P3 is equal to the current flowing through MOSFET P0. Therefore, the current I flowing through MOSFET P5 is... P5 for: ; Let the driving current flowing through resistor R5 be I. D The on-state voltage drops of MOSFETs N5, N6, N7, and N8 are negligible. Therefore, the input voltage VN at the inverting input terminal of operational amplifier U101 is: ; Where R7 is the resistance value of resistor R7.

[0059] Due to the negative feedback regulation of operational amplifier U101, the drive current I D The following conditions must be met: ; Therefore, the differential output voltage V can be obtained. DIFF for: ; Therefore, the differential output voltage V DIFF It is independent of the external voltage VCC, meaning it is less affected by power supply noise.

[0060] Please refer to Figure 3 As shown, attached Figure 3 The simulation graph for Power Supply Rejection Ratio (PSRR) is provided by [the relevant source]. Figure 3 As can be seen, the differential output driver disclosed in this embodiment can achieve a PSRR of 86dB, meaning that a large amount of noise on the input power supply has only a negligible effect on the output. Therefore, the output level of the differential output driver is determined by the drive current and load resistance, and is independent of the power supply voltage, thus exhibiting an extremely high power supply rejection ratio.

[0061] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A differential output driver in current-driven mode, characterized in that, It includes an enable module, a reference current source module, and a drive module. The drive module includes an H-bridge branch, which includes MOSFETs N5, N6, N7, and N8, and resistors R5 and R6. The first signal output terminal of the enable module is electrically connected to the gate of MOSFET N5 and the gate of MOSFET N8. The second signal output terminal of the enable module is electrically connected to the gate of MOSFET N7 and the gate of MOSFET N6. The reference current source module outputs a drive current to one end of resistor R5. The other end of resistor R5 is electrically connected to the drain of MOSFET N5 and the drain of MOSFET N7. The source of MOSFET N5 and the drain of MOSFET N6 are electrically connected and serve as the output terminal D- connected to the outside. The source of MOSFET N7 and the drain of MOSFET N8 are electrically connected and serve as the output terminal D+ connected to the outside. An external load is connected between the output terminals D- and D+. The source of both MOS transistor N6 and MOS transistor N8 is electrically connected to one end of resistor R6, and the other end of resistor R6 is grounded.

2. The differential output driver in current-driven mode according to claim 1, characterized in that: The enabling module includes MOSFETs P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21 and N11, N12, N13, N14, N15, N16, N17, and N18. External power supply outputs VCC to the source of MOSFET P10, the source of MOSFET P11, the source of MOSFET P12, the source of MOSFET P13, the source of MOSFET P16, the source of MOSFET P17, the source of MOSFET P18, and the source of MOSFET P19. An external input signal DIN is input to the gates of MOSFET P10 and N11. The drains of MOSFET P10 and N11 are both connected to the gates of MOSFET P11, N12, P16, and N15. The drains of MOSFET P11 and N12 are both electrically connected to the gates of MOSFET P14, P15, and N13. The drains of MOSFET P14 and N13 are both electrically connected to the drains of MOSFET P15 and N14, and are also electrically connected as the first signal output terminal to the gates of MOSFET N5 and N8. An external low-level enable signal EN is input to the gates of MOSFETs P12, P13, N14, P18, P19, and N18; the drain of MOSFET P12 is electrically connected to the source of MOSFET P14, and the drain of MOSFET P13 is electrically connected to the source of MOSFET P15. The drains of MOSFET P16 and N15 are electrically connected to the gates of MOSFET P17 and N16, respectively. The drains of P17 and N16 are electrically connected to the gates of MOSFET P20, P21, and N17, respectively. The drain of MOSFET P18 is electrically connected to the source of MOSFET P20, and the drain of MOSFET P19 is electrically connected to the source of MOSFET P21. The drains of MOSFET P20 and N17 are electrically connected to the drains of MOSFET P21 and N18, and are also electrically connected as a second signal output terminal to the gates of MOSFET N7 and N6, respectively. The sources of MOSFETs N11, N12, N13, N14, N15, N16, N17, and N18 are all grounded.

3. The differential output driver in current-driven mode according to claim 1, characterized in that: The reference current source module includes an operational amplifier U100, MOSFETs P0, P1, P2, P3, N0, N1, Q0, Q1, Q2, and resistors R1, R2, R3, and R4. External power supply outputs VCC to the source of MOSFET P0, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3; The gate and drain of MOSFET P1 are electrically connected to the drain of MOSFET N0, the gate of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3. The drain of MOSFET P1 is electrically connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of operational amplifier U100. The other end of resistor R3 is electrically connected to the emitter of transistor Q1 and the non-inverting input of operational amplifier U100. The other end of resistor R2 is electrically connected to the emitter of transistor Q0. The output of operational amplifier U100 is electrically connected to the gate of MOSFET N0. The drain of MOSFET P2 is electrically connected to one end of resistor R4 and serves as the first current output terminal, which is electrically connected to the drive module. The other end of resistor R4 is electrically connected to the emitter of transistor Q2. The drain of MOSFET P3 is electrically connected to the drain and gate of MOSFET N1 and serves as the second current output terminal, which is electrically connected to the drive module. The source of MOSFET N0, the source of MOSFET N1, the base of transistor Q0, the emitter of transistor Q0, the base of transistor Q1, the emitter of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2 are all grounded.

4. The differential output driver in current-driven mode according to claim 1, characterized in that: The drive module further includes a drive branch, a feedback branch, and a control branch; The reference current source module outputs a reference current to the drive branch and the feedback branch. The output terminal of the drive branch is electrically connected to the input terminal of the H-bridge branch and the input terminal of the feedback branch. The control branch is connected between the ground terminal of the H-bridge branch and the control terminal of the feedback branch.

5. The differential output driver in current-driven mode according to claim 4, characterized in that: The drive branch includes MOSFET P4, MOSFET P5, MOSFET P6 and MOSFET N2; An external power supply outputs VCC to the source of MOSFET P4, the source of MOSFET P5, and the source of MOSFET P6. The drain of MOSFET P6 is electrically connected to the control branch. The reference current source module outputs a reference current to the gate of MOSFET N2. The drain of MOSFET N2 is electrically connected to the gate and drain of MOSFET P4, the gate of MOSFET P5, and the gate of MOSFET P6. The drain of MOSFET P5 is electrically connected to one end of resistor R5 and the feedback branch. The source of the MOS transistor N2 is grounded.

6. The differential output driver in current-driven mode according to claim 4, characterized in that: The feedback branch includes operational amplifier U101, MOSFET P8, MOSFET N3, and MOSFET N4; The external power supply outputs VCC to the source of MOSFET P8; The reference current source module outputs a reference current to the non-inverting input of the operational amplifier U101. The output of the drive branch is electrically connected to the drain of the MOS transistor N4 and the inverting input of the operational amplifier U101. The output of the operational amplifier U101 is electrically connected to the gate of the MOS transistor P8. The drain of the MOS transistor P8 is electrically connected to the gate and drain of the MOS transistor N3 and the gate of the MOS transistor N4. The sources of both MOS transistor N3 and MOS transistor N4 are grounded.

7. The differential output driver in current-driven mode according to claim 4, characterized in that: The control branch includes MOSFETs P7, P9, N9, and N10; External power supply outputs VCC to the source of MOSFET P7 and the source of MOSFET P9; The source of MOSFET N6 and the source of MOSFET N8 are both electrically connected to the gate of MOSFET N9. The output terminal of the drive branch is electrically connected to the drain of MOSFET N9, the gate of MOSFET P9, and the gate of MOSFET N10. The drain of MOSFET P9 and the drain of MOSFET N10 are both electrically connected to the gate of MOSFET P7. The drain of MOSFET P7 is electrically connected to the control terminal of the feedback branch. The sources of both MOS transistor N9 and MOS transistor N10 are grounded.

8. The differential output driver in current-driven mode according to claim 1, characterized in that: The following conditions must be met. (W / L) N5 =(W / L) N6 =(W / L) N7 =(W / L) N8 ; Among them, (W / L) NX This represents the width-to-length ratio (W / L) of the MOSFET NX. N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7 N8 This represents the width-to-length ratio of the MOSFET N8.

9. The differential output driver in current-driven mode according to claim 3, characterized in that: The following conditions must be met. (W / L) P0 :(W / L) P1 :(W / L) P2 :(W / L) P3 =1:M:N:1; R1=R3; Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P0 The width-to-length ratio (W / L) of MOSFET P0 P1 The width-to-length ratio (W / L) of MOSFET P1 P2 The width-to-length ratio (W / L) of MOSFET P2 P3 R1 is the width-to-length ratio of MOSFET P3; M and N are proportionality coefficients; R1 is the resistance value of resistor R1, and R3 is the resistance value of resistor R3.

10. The differential output driver in current-driven mode according to claim 5, characterized in that: The following conditions must be met. (W / L) P4 :(W / L) P5 =K:J; R5=R6; Among them, (W / L) PX This represents the width-to-length ratio (W / L) of the MOSFET PX. P4 The width-to-length ratio (W / L) of MOSFET P4 P5 R5 is the width-to-length ratio of MOSFET P5; K and J are proportionality coefficients; R5 is the resistance value of resistor R5, and R6 is the resistance value of resistor R6.

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