Methods, apparatuses, and articles of manufacture to align data to address boundaries in memory

Abstract

An example device includes example packet decode circuitry (406) to decode a packet of instructions for programmable circuitry into at least one instruction. In addition, the example device includes example instruction map circuitry (408) to ignore a padding instruction included in the at least one instruction that has not been assigned to any functional unit (410) of the programmable circuitry.

Description

[0001] This specification generally relates to computer architecture, and more specifically, to methods, apparatuses, and articles of manufacture for aligning data to address boundaries in memory. BACKGROUND

[0002] Manufacturers of integrated circuits (ICs) have developed techniques for manufacturing compact ICs that contain components of computers and / or other electronic systems. Such ICs are referred to as systems on a chip, or SoCs. Typically, such SoCs contain a central processing unit (CPU), memory, input / output ports, and auxiliary storage, all on the same substrate. The memory and / or auxiliary storage can be implemented by random access memory (RAM), ferroelectric random access memory (FRAM), not- or (NOR) flash memory, one-time programmable read-only memory (OTP ROM), etc. The SoC can be configured to act as a microcontroller that can be used for processes that are writable into a coded instruction set that can be executed to carry out a desired process in an automated manner. SUMMARY

[0003] For a method, apparatus, and article of manufacture for aligning data to address boundaries in memory, one example apparatus includes example packet decoding circuitry to decode an instruction packet for programmable circuitry into at least one instruction.

[0004] Additionally, the example apparatus includes example instruction mapping circuitry to ignore a pad instruction included in the at least one instruction that has not been assigned to any functional unit of the programmable circuitry. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 An example memory is shown that includes an example instruction packet that is not aligned with a width of the memory.

[0006] Figure 2 An example memory is shown that includes an example instruction packet that is aligned with a width of the memory.

[0007] Figure 3 is a block diagram showing an example system on a chip (SoC) implemented in accordance with example pad instructions disclosed herein.

[0008] Figure 4 is a block diagram showing an example implementation of a bus master of Figure 3 operating in accordance with example pad instructions disclosed herein.

[0009] Figure 5 An example 16-bit pad instruction is shown.

[0010] Figure 6 An example instruction packet containing four padding instructions is shown.

[0011] Figure 7 An example instruction packet containing two padding instructions is shown.

[0012] Figure 8 An example instruction packet containing one padding instruction is shown.

[0013] Figure 9 An example memory containing an example instruction packet aligned with a width of the memory via one or more padding instructions is shown.

[0014] Figure 10 An example memory containing another example instruction packet aligned with a width of the memory via one or more padding instructions is shown.

[0015] Figure 11 is an example programmable circuitry implementation of a bus master of Figure 3 and / or 4 to execute, instantiate, and / or implement example machine-readable instructions and / or example operations.

[0016] Figure 12 is a block diagram of an example processing platform of programmable circuitry of a bus master of Figure 11 to execute, instantiate, and / or implement example machine-readable instructions and / or example operations to achieve Figure 11 of a bus master of Figure 3 and / or 4.

[0017] The same reference numbers or other reference indicators in the drawings represent the same or similar (functionally and / or structurally) features. DETAILED DESCRIPTION

[0018] The drawings are not necessarily to scale. Generally, the same reference numbers in the drawings indicate same or similar components. Although the drawings depict zones with clear lines and boundaries, some or all of these lines and / or boundaries can be idealized. In practice, boundaries and / or lines can be unobservable, blended, and / or irregular.

[0019] Some programmable devices, such as System-on-a-Chip (SoC) and Central Processing Unit (CPU), are designed based on a Very Long Instruction Word (VLIW) architecture. During operation, a programmable device can use a programmable circuit system to execute one or more instructions. Instructions can be formatted into instruction packets, where each instruction packet contains one or more instructions. To conform to an example VLIW architecture, each instruction packet contains at least one instruction, and the size of each instruction within the instruction packet can vary. In some such VLIW architectures, the instruction packet is aligned to address boundaries in memory. For example, the location in memory storing the instruction packet is aligned to a multiple of the specific address width (e.g., 8-bit address boundaries, 16-bit address boundaries, 32-bit address boundaries, etc.).

[0020] Furthermore, devices implementing VLIW architectures utilize predefined bus widths (e.g., program bus width, data bus width, etc.). For example, in some VLIW architectures, the bus (e.g., program bus, data bus, etc.) is 128 bits wide. Therefore, in devices implementing such VLIW architectures, a programmable circuit system (e.g., CPU) can fetch as much data as the bus can support in each clock cycle (e.g., program bus width, data bus width, etc.). However, at discontinuities in the program (e.g., branch instructions, calls, interrupts, etc.), the destination address associated with the discontinuity may not be aligned with the width of the bus (e.g., program bus, data bus, etc.). For example, destination addresses aligned with the 128-bit width of the bus are 0x0, 0x10, 0x20, etc. (e.g., the remainder is zero when the address value is divided by 16), while destination addresses not aligned with the 128-bit width of the bus are 0x2, 0x4, 0x6, etc. (e.g., the remainder is non-zero when the address value is divided by 16). In other words, the example memory is divided into 128-bit segments (e.g., rows), where each segment is read or written as a whole.

[0021] If the destination address is not aligned with the bus width, not all bits read through the bus will be used by the program; some data will be discarded. For example, Figure 1 An example memory 100 is shown containing an example instruction packet 102 that is not aligned with the width of the memory 100. Figure 1 In this example, memory 100 includes a first example line 104, a second example line 106, and a third example line 108. Figure 1 In this example, memory 100 is a 128-bit (e.g., 16-byte) wide byte-addressable memory, where instruction packets are aligned with a set of address boundaries every 16 bits within a given 128-bit line. Figure 1 In the example, the instruction packet is between 16 bits and 128 bits, and the size of individual instructions can vary between 16 bits, 32 bits, and 48 bits.

[0022] In Figure 1 the illustrated example, the first row 104 begins at address 0x00 in hexadecimal notation (e.g., 0 in base-10 notation). Additionally, the second example row 106 begins at address 0x10 in hexadecimal notation (e.g., 16 in base-10 notation). In Figure 1 the example, the third row 108 begins at address 0x20 in hexadecimal notation (e.g., 32 in base-10 notation). Moreover, in Figure 1 the example, the instruction packet 102 is associated with (e.g., contains) a branch instruction having an example destination address of 0x0C (e.g., 12 in base-10 notation) 110. As such, the instruction packet 102 is not aligned with the width of the memory 100, and bytes 0-11 of the first row 104 corresponding to a different packet will not be used after the branch is taken.

[0023] Thus, when the example programmable circuitry takes the branch to the instruction packet 102, the programmable circuitry can utilize at least five clock cycles to execute the instruction packet 102. For example, the programmable circuitry execution pipeline can be a multi-stage pipeline in which instructions are executed in the fourth stage. The example programmable circuitry execution pipeline contains a first stage in which the programmable circuitry requests an instruction packet from the memory over a program bus, a second stage in which the instruction packet is returned from the memory and captured by the programmable circuitry, a third stage in which the programmable circuitry dispatches the instruction packet to be decoded, and a fourth stage in which the programmable circuitry executes the instruction packet when it is available.

[0024] In Figure 1 the illustrated example, after the programmable circuitry processes the branch instruction associated with (e.g., that is part of) the instruction packet 102, the programmable circuitry requests data from the destination address 0x0C 110 during the first clock cycle. To this end, the programmable circuitry requests data in the first row 104, which contains a 12-byte instruction packet identified as I-Packet-X and the 4 bytes of the instruction packet 102. During the second clock cycle, the programmable circuitry requests data in the second row 106 and receives data in the first row 104. The data in the second row 106 contains the remaining 12 bytes of the instruction packet 102 and a 4-byte instruction packet identified as I-Packet-1. In Figure 1 the example, because the access to data in the first row 104 is associated with the instruction packet 102, the programmable circuitry ignores the 12-byte instruction packet identified as I-Packet-X.

[0025] In Figure 1In the example shown of FIG. 1, during the third clock cycle, the programmable circuitry receives the data in the second row 106 and attempts to dispatch the instruction packet 102 based on the data received during the second clock cycle. However, because the remaining 12 bytes of the instruction packet 102 have not yet been returned from the memory, the programmable circuitry cannot dispatch the instruction packet 102. As such, the programmable circuitry waits until the remaining 12 bytes of the instruction packet 102 are returned from the memory before forming the instruction packet 102. Additionally, because the access to the data in the second row 106 is associated with the instruction packet 102, the programmable circuitry can ignore the 4-byte instruction packet identified as I-packet-1 after the instruction packet 102 (e.g., if execution proceeds non-linearly).

[0026] In Figure 1 In the example shown of FIG. 1, during the third clock cycle, the programmable circuitry receives the data in the second row 106 and attempts to dispatch the instruction packet 102 based on the data received during the second clock cycle. However, because the remaining 12 bytes of the instruction packet 102 have not yet been returned from the memory, the programmable circuitry cannot dispatch the instruction packet 102. As such, the programmable circuitry waits until the remaining 12 bytes of the instruction packet 102 are returned from the memory before forming the instruction packet 102. Additionally, because the access to the data in the second row 106 is associated with the instruction packet 102, the programmable circuitry can ignore the 4-byte instruction packet identified as I-packet-1 after the instruction packet 102 (e.g., if execution proceeds non-linearly). Figure 1 In the example shown of FIG. 1, because the instruction packet 102 is not aligned with the width of the memory 100, the programmable circuitry executes the instruction packet 102 in five clock cycles. This latency can be exacerbated if the discontinuity is at the beginning of a loop (e.g., a for loop, a while loop, etc.). For example, if the loop is iterated N times, the misaligned instruction packet increases the execution time of the loop by N cycles.

[0027] In a programmable circuitry implementing the execution pipeline described above, the minimum number of clock cycles taken to execute an instruction packet is four clock cycles after the discontinuity. This best-case scenario is possible as long as the instruction packet is aligned with the width of the memory. For example, Figure 2 An example memory 200 containing an example instruction packet 202 that is aligned with the width of the memory 200 is shown. In the example shown of FIG. 2, the memory 200 contains a first example row 204, a second example row 206, a third example row 208, and a fourth example row 210. In the example shown of FIG. 2, the memory 200 is a byte-addressable memory that is 128 bits (e.g., 16 bytes) wide, where instruction packets are aligned to 16-bit address boundaries. In the example shown of FIG. 2, the instruction packet 202 is 128 bits long. Figure 2 In the example shown of FIG. 2, the memory 200 contains a first example row 204, a second example row 206, a third example row 208, and a fourth example row 210. In the example shown of FIG. 2, the memory 200 is a byte-addressable memory that is 128 bits (e.g., 16 bytes) wide, where instruction packets are aligned to 16-bit address boundaries. In the example shown of FIG. 2, the instruction packet 202 is 128 bits long. Figure 2 In the example shown of FIG. 2, the memory 200 contains a first example row 204, a second example row 206, a third example row 208, and a fourth example row 210. In the example shown of FIG. 2, the memory 200 is a byte-addressable memory that is 128 bits (e.g., 16 bytes) wide, where instruction packets are aligned to 16-bit address boundaries. In the example shown of FIG. 2, the instruction packet 202 is 128 bits long. Figure 2 In the example shown of FIG. 2, the memory 200 contains a first example row 204, a second example row 206, a third example row 208, and a fourth example row 210. In the example shown of FIG. 2, the memory 200 is a byte-addressable memory that is 128 bits (e.g., 16 bytes) wide, where instruction packets are aligned to 16-bit address boundaries. In the example shown of FIG. 2, the instruction packet 202 is 128 bits long.

[0028] InFigure 2 In the example shown, the first line 204 begins at address 0x00 in hexadecimal representation (e.g., 0 in a base-10 representation). Additionally, the second example line 206 begins at address 0x10 in hexadecimal representation (e.g., 16 in a base-10 representation). Figure 2 In the example, the third line 208 begins at address 0x20 in hexadecimal representation (e.g., 32 in a base-10 representation). Additionally, the fourth example line 210 begins at address 0x30 in hexadecimal representation (e.g., 48 in a base-10 representation). Furthermore, in Figure 2 In this example, instruction packet 202 is associated with a branch instruction having an example destination address of 0x10 (e.g., 16 in a base-10 representation) 212. Therefore, instruction packet 202 is aligned with the width of memory 200. Thus, when the programmable circuitry reaches the branch instruction, it will execute instruction packet 202 in four clock cycles, compared to the five clock cycles required to execute instruction packet 102 which is not aligned with the width of memory 100.

[0029] For example, in Figure 2 In the illustrated example, after the programmable circuit system processes the branch instruction associated with instruction packet 202, the programmable circuit system requests data from destination address 0x10 212 during the first clock cycle. To do this, the programmable circuit system requests data in the second line 206 containing instruction packet 202. During the second clock cycle, the programmable circuit system receives the data in the second line 206. Since the data in the second line 206 contains only instruction packet 202, the programmable circuit system does not ignore any data from the second line 206.

[0030] exist Figure 2 In the example shown, during the third clock cycle, the programmable circuit system attempts to dispatch instruction packet 202 based on the data received during the second clock cycle. Because instruction packet 202 (e.g., the entire instruction packet 202) has been returned from memory, the programmable circuit system successfully dispatches instruction packet 202 during the third clock cycle. During the fourth clock cycle, the programmable circuit system executes instruction packet 202. Figure 2 As shown in the example, because instruction packet 202 is aligned with the width of memory 200, the programmable circuit system can execute the aligned instruction packet in four clock cycles, compared to at least five clock cycles required to execute instruction packet 102 which is not aligned with the width of memory 100. Therefore, the performance of the programmable circuit system is improved when the instruction packet is aligned with the width of memory, at least because the number of clock cycles required to execute the aligned instruction packet is reduced compared to the number of clock cycles required to execute the unaligned instruction packet.

[0031] To reduce the number of clock cycles taken by programmable circuitry to execute a misaligned instruction packet, some programmable device architectures have inserted no-operation (NOP) instructions in memory to align misaligned instruction packets. A NOP instruction is an instruction with an explicit purpose to not change the state of any program-accessible component (e.g., register, status flag, memory, etc.). NOP instructions are most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy branch delay slots, to invalidate existing instructions (e.g., jump instructions), or as targets of execution instructions. Additionally, NOP instructions can have minor side effects, such as synchronizing the execution pipeline of the programmable circuitry.

[0032] In some instances, when a NOP instruction in memory is encountered, the programmable circuitry assigns the NOP instruction to a functional unit of the programmable circuitry. As such, the NOP instruction in memory can be limited to a particular size that corresponds to the size of the functional unit of the programmable circuitry. For example, if the size of the functional unit is 16 bits, then the NOP instruction can also be 16 bits. The functional unit of the programmable circuitry can be designed to accommodate NOP instructions of multiple sizes, but a tradeoff of doing so can be reserving additional space within the limited footprint of the programmable circuitry to accommodate multiple sizes. As such, the NOP instruction can not be flexible because the NOP instruction can only be assigned to a functional unit that has a size that matches the size of the NOP instruction, and if the developer of the programmable circuitry wants to accommodate various NOP instruction sizes, the programmable circuitry can sacrifice space that would otherwise be relegated to different functionality.

[0033] Additionally, because the NOP instruction is assigned to the functional unit of the programmable circuitry, the programmable circuitry executes the NOP instruction in a defined number of clock cycles. Thus, the number of clock cycles to align a misaligned instruction packet with a NOP instruction depends on the number of NOP instructions inserted to align the misaligned instruction packet. As such, while the number of clock cycles taken to execute a misaligned instruction packet is reduced, inserting NOP instructions into memory to compensate for misaligned instruction packets still causes the programmable circuitry to take more clock cycles than would be taken to execute an aligned instruction packet otherwise. Moreover, utilizing NOP instructions is detrimental to code density for a program and degrades timing.

[0034] To ensure that unaligned instruction packets are executed by the programmable circuitry system in fewer clock cycles (e.g., the same number of clock cycles required to execute aligned instruction packets), the examples disclosed herein include a new instruction referred to herein as a padding instruction. A padding instruction is a 16-bit instruction that can be multiplied multiple times within the same instruction packet to create padding of any number of bits from 16 to 128. Furthermore, when processing a padding instruction, the programmable circuitry system does not assign the padding instruction to a function unit. Because padding instructions are variable in size and not assigned to function units (unlike NOP instructions, which can be limited to a fixed size and assigned to function units), the example padding instructions disclosed herein can be added to an instruction packet to enable the programmable circuitry system to execute unaligned instruction packets without incurring excessive clock cycles.

[0035] Figure 3 This is a block diagram illustrating an example system-on-chip (SoC) 300 implemented according to the example fill instructions disclosed herein. Figure 3 In this example, SoC 300 includes an example bus master 302, an example address decoder 304, an example memory controller 306, and an example memory 308. Figure 3 The example bus master 302 includes dual-purpose terminals (e.g., input and / or output terminals). As used herein, the term "dual-purpose terminal" refers to a terminal that serves two purposes. For example, a dual-purpose terminal can be used as both an input terminal and an output terminal.

[0036] exist Figure 3 In the example shown, the address decoder 304 includes a first dual-purpose terminal, a second dual-purpose terminal, and an output terminal. Figure 3 In one example, the memory controller 306 includes a dual-purpose terminal, a first input terminal, a second input terminal, and an output terminal. Figure 3 In this example, memory 308 includes input terminals and output terminals. As used herein, the term "dual-purpose terminal" can be used in place of "input terminal" and / or "output terminal" depending on whether the component containing the dual-purpose terminal is transmitting or receiving data. Additionally, in some instances, the term "terminal" may be omitted from the terms "input terminal," "output terminal," and "dual-purpose terminal."

[0037] exist Figure 3 In the illustrated example, the dual-purpose terminal of the bus master 302 is coupled to the first dual-purpose terminal of the address decoder 304 via the example program bus 310, the example data read bus 312, and the example data write bus 314. Figure 3 In this example, the output terminal of the address decoder 304 is coupled to the first input terminal of the memory controller 306 via the example memory request channel 316. Figure 3In this example, the second dual-purpose terminal of the address decoder 304 is coupled to the dual-purpose terminal of the memory controller 306 via the example memory program bus 318, the example memory data read bus 320, and the example memory data write bus 322. The output terminal of the memory controller 306 is coupled to the memory 308 via the example bus. The second input terminal of the memory controller 306 is coupled to the output terminal of the memory 308 via the example bus.

[0038] exist Figure 3 In the example shown, the bus master 302 is implemented by a CPU based on a VLIW architecture. In alternative examples, the bus master 302 can be implemented by any other type of programmable circuit system (e.g., one or more accelerators (e.g., one or more control law accelerators (CLAs), one or more background CRC (BGCRC) units, one or more Ethernet media access controllers (EMACs), etc.)). Figure 3 In this example, the bus master 302 includes one or more functional units. Example functional units are components of a programmable circuit system (e.g., a CPU) that implement operations and / or computations forwarded to the programmable circuit system. Example functional units include an arithmetic logic unit (ALU), a floating-point unit (FPU), an address generation unit (AGU), a load-memory unit (LSU), a fast integer division (FINTDIV) unit, a trigonometric mathematics unit (TMU), a Viterbi, complex mathematics, and a cyclic redundancy check (CRC) unit (VCU), etc.

[0039] exist Figure 3 In the example shown, the bus master 302 contains 17 functional units, eight of which can execute instructions in parallel. Additionally, in Figure 3 In this example, the functional unit of the bus master 302 can execute 16-bit instructions. Figure 3 The example bus master 302 executes one or more programs and / or instructions depending on the use case in which the SoC 300 is implemented. In order to execute programs and / or instructions, the bus master 302 accesses memory 308 (e.g., via address decoder 304 and / or memory controller 306) to obtain one or more instruction packets.

[0040] As described below, Figure 3The memory 308 of the instance may contain one or more padding instructions to align instruction packets that would otherwise be misaligned with the width of the memory 308. For example, a compiler and / or assembler implemented outside the SoC 300 may insert one or more padding instructions into the program before the program is stored in the memory 308 of the SoC 300. To insert padding instructions into the program, the compiler and / or assembler (1) identifies discontinuities in the program (e.g., branch instructions, calls, interrupts, etc.) and (2) determines whether instruction packets before and / or after the destination address associated with the discontinuity are misaligned with the width of the memory 308. For example, discontinuities are often present in loops (e.g., for loops, while loops, etc.), where a branch instruction at the end of the loop instructs the CPU to return to an earlier instruction (e.g., a destination address in memory) and repeat one or more instructions that are part of the loop. If an instruction packet before and / or after the destination address is not aligned with the width of memory 308, the compiler and / or assembler inserts one or more padding instructions into the instruction packet and / or as another instruction packet preceding the instruction packet (e.g., a padding instruction packet) to align the instruction packet with the width of memory 308. Advantageously, when bus master 302 encounters a padding instruction, bus master 302 ignores the padding instruction and does not assign it to a functional unit of bus master 302. Thus, bus master 302 does not waste clock cycles executing instructions included for memory alignment purposes.

[0041] exist Figure 3 In the illustrated example, the address decoder 304 is implemented by a logic circuit system (e.g., a sequential logic circuit system and / or a combinational logic circuit system). In other or alternative examples, the address decoder 304 may be implemented by hardware, firmware, and / or software. Figure 3 In this example, address decoder 304 routes address and / or control information (e.g., memory address, data to be written, etc.) to memory controller 306. For instance, memory 308 may contain a base address based on the memory mapping of SoC 300, and individual memory cells within memory 308 may be accessed via an offset address to the corresponding base address. Figure 3 In one instance, the address decoder 304 determines the base address of the requested memory based on information transmitted to the address decoder 304 on the program bus 310, the data read bus 312, and / or the data write bus 314.

[0042] exist Figure 3In the illustrated example, the memory controller 306 is implemented by a logic circuit system (e.g., a sequential logic circuit system and / or a combinational logic circuit system). In other or alternative examples, the memory controller 306 is implemented by an integrated memory controller (IMC), a memory chip controller (MCC), a memory controller unit (MCU), and / or a memory management unit (MMU), etc. Figure 3 In this example, memory controller 306 controls when and which components of SoC 300 (e.g., bus master 302 of SoC 300 and / or any other bus master) access memory 308. For example, when bus master 302 requests control of a bus (e.g., memory program bus 318, memory read bus 320, memory write bus 322), bus master 302 may request access via memory request channel 316. Figure 3 In one instance, the memory request channel 316 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to request access to memory 308.

[0043] exist Figure 3 In the illustrated example, memory controller 306 arbitrates requests from components of SoC 300 and generates signals for accessing memory 308. For example, memory controller 306 determines which components of SoC 300 (e.g., bus master 302 and / or any other bus master) can access the bus based on the priority of one or more components of SoC 300, fairness in servicing the requesting component relative to other components of SoC 300, and / or whether the bus is currently in use. Memory controller 306 may employ daisy-chaining, polling, and / or independent requests to service connected components of SoC 300. Figure 3 In this example, after arbitrating which components of the SoC 300 will access memory 308, the memory controller 306 generates one or more signals for accessing memory 308. For example, the memory controller 306 may enable access to memory 308 via a memory enable signal. Alternatively, the memory controller 306 may access memory 308 via an offset address to the base address of memory 308. For example, the base address is hard-coded at the memory controller 306.

[0044] exist Figure 3In the illustrated example of FIG. 3, memory 308 is implemented by a memory storage array, such as a programmable logic array, a field programmable gate array, or the like. For example, memory 308 can be implemented as a dynamic random access memory (DRAM), a static RAM (SRAM), one or more hard disk drives, or the like. Memory 308 includes word lines and bit lines that operate as indicators of row-column pairs. Memory controller 306 selects particular address information in memory 308 to read and / or write data based on information received from address decoder 304.

[0045] In Figure 3 In the illustrated example of FIG. 3, memory 308 is a DRAM and thus includes a number of switches and capacitors. The switches can be transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), junction gate field effect transistors (JFETs), heterojunction bipolar transistors (HBTs), or the like. The use of transistors and capacitors together form memory cells that correspond to individual data bits. The word lines and bit lines of memory 308 specify the location of individual memory cells from which data is read and / or in which data is stored. In additional or alternative examples, memory 308 can be implemented by read-only memory (ROM), flash memory, and / or any other type of memory.

[0046] In Figure 3 In the illustrated example of FIG. 3, program bus 310 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transfer instructions, addresses, and / or operands to memory 308. For example, program bus 310 is implemented as an internal bus within SoC 300. In Figure 3 In the example of FIG. 3, the width of program bus 310, which is dedicated to transferring instructions, addresses, and / or operands, is 128 bits. Additionally, program bus 310 includes a number of conductors to transfer error correction codes (ECCs) and / or parity codes for address, data, and control information. In Figure 3 In the illustrated example of FIG. 3, memory program bus 318 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transfer information on program bus 310 between memory 308 and a requesting component of SoC 300 (e.g., bus master 302). For example, memory program bus 318 is implemented as an internal bus within SoC 300. In Figure 3 In the example of FIG. 3, the width of memory program bus 318, which is dedicated to transferring information on program bus 310, is 128 bits. Additionally, memory program bus 318 includes a number of conductors to transfer ECCs and / or parity codes.

[0047] In Figure 3In the illustrated example, the data read bus 312 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transmit operands read from memory 308 and / or corresponding addresses. For example, the data read bus 312 is implemented as an internal bus within the SoC 300. Figure 3 In this example, the data read bus 312, dedicated to transmitting operands read from memory 308 and / or corresponding addresses, is 128 bits wide. Additionally, the data read bus 312 includes multiple conductors to transmit sideband ECC and / or parity check codes for address, data, and control information. Figure 3 In an example, the memory data read bus 320 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transfer information on the data read bus 312 between the memory 308 and a requesting component (e.g., bus master 302) of the SoC 300. For example, the memory data read bus 320 is implemented as an internal bus within the SoC 300. Figure 4 In this example, the memory data read bus 320, dedicated to transmitting information on the data read bus 312, is 128 bits wide. Additionally, the memory data read bus 320 includes multiple conductors for transmitting ECC and / or parity check codes.

[0048] exist Figure 3 In the illustrated example, the data write bus 314 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transmit data to be written to memory 308 and / or corresponding addresses. For example, the data write bus 314 is implemented as an internal bus within the SoC 300. The data write bus 314 also transmits sideband ECC and / or parity check codes for address, data, and control information. Figure 4 In this example, the memory data write bus 322 can be implemented using any suitable hardware (e.g., wires, optical fibers, etc.) and / or software (e.g., communication protocols, etc.) communication technology to transfer information on the data write bus 314 between the memory 308 and requesting components of the SoC 300. For example, the memory data write bus 322 is implemented as an internal bus within the SoC 300. As described above, the various buses of the SoC 300 reserve 128 bits for transmitting information to and / or from the bus master 302. Thus, the bus master 302 can fetch up to 128 bits from the memory 308 per clock cycle.

[0049] exist Figure 4In the example shown, memory 308 stores one or more instruction packets. Example instruction packets are between 16 bits and 128 bits in size, where the instructions within the packet can vary in size to 16 bits, 32 bits, and 48 bits. Therefore, an instruction packet can contain one to eight instructions. Figure 4 In this example, the width of memory 308 dedicated to instruction packets is 128 bits. The example instruction packet is aligned to 16-bit address boundaries in memory 308 (e.g., because the minimum instruction packet size is 16 bits). Figure 4 In this example, memory 308 is byte-addressable, meaning that aligned addresses are quantized in multiples of two bytes (e.g., 0x0, 0x2, 0x4, etc. in hexadecimal representation). Advantageously, memory 308 includes one or more padding instructions to reduce the number of instruction packets that are not aligned with the width of the program bus 310 and / or data read bus 312. Therefore, Figure 4 The example bus master 302 can access instruction packets that would otherwise be unaligned with memory 308 with reduced clock cycles (e.g., the same number of clock cycles used to execute aligned instruction packets).

[0050] Figure 4 This demonstrates how to operate according to the example fill instructions disclosed herein. Figure 4 A block diagram of an example implementation of the bus master 302. Figure 3 In this instance, the bus master 302 can be instantiated (e.g., instantiated, made to any time length, materialized, implemented, etc.) by a programmable circuit system (e.g., a central processing unit (CPU)) that executes the first instruction. Alternatively, Figure 4 The bus master 302 can be instantiated (e.g., instantiated, made to any time length, materialized, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA) constructed and / or configured to implement operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that... Figure 4 Some or all of the circuit system can therefore be instantiated at the same or different times. Figure 4 Some or all of the circuitry can be instantiated, for example, in one or more threads that execute concurrently on hardware and / or serially on hardware. Furthermore, in some instances, Figure 4 Some or all of the circuitry in the system can be implemented by a microprocessor circuitry that executes instructions and / or an FPGA circuitry that performs operations to implement one or more virtual machines and / or containers.

[0051] exist Figure 4The illustrated example of bus master 302 includes example fetch unit circuitry 402, example instruction buffer 404, example packet decode circuitry 406, example instruction mapping circuitry 408, and example functional units 410. For example, functional units 410 include a first example functional unit 410 A , a second example functional unit 410 B , a third example functional unit 410 C , a fourth example functional unit 410 D , a fifth example functional unit 410 E , a sixth example functional unit 410 F , a seventh example functional unit 410 G , and an eighth example functional unit 410 H . Although eight functional units are shown in Figure 4 , bus master 302 can include the 17 functional units described above in connection with Figure 4 .

[0052] In the illustrated example of Figure 4 , fetch unit circuitry 402 includes a first dual-purpose (e.g., input / output) terminal, a second dual-purpose terminal, and an output terminal. In the example of Figure 4 , instruction buffer 404 includes an input terminal and an output terminal. Figure 4 The example packet decode circuitry 406 includes an input terminal and an output terminal. In the example of Figure 4 , instruction mapping circuitry 408 includes an input terminal and multiple sets of output terminals. For example, instruction mapping circuitry 408 includes the same number of sets of output terminals as the number of functional units 410. Additionally, each of functional units 410 includes an input terminal and an output terminal.

[0053] In the illustrated example of Figure 4 , the first dual-purpose terminal, the second dual-purpose terminal, and the output terminal of fetch unit circuitry 402 can support 128 data bits. In the example of Figure 4 , the first dual-purpose terminal of fetch unit circuitry 402 is coupled to program bus 310. Additionally, Figure 4 the second dual-purpose terminal of example fetch unit circuitry 402 is coupled to data read bus 312. In the example of Figure 4 , the output terminal of fetch unit circuitry 402 is coupled to the input terminal of instruction buffer 404.

[0054] In the illustrated example of Figure 4 , the input terminal and the output terminal of instruction buffer 404 can support 128 data bits. In the example of Figure 11In this example, the input terminals of the instruction buffer 404 are coupled to the output terminals of the fetch unit circuit system 402. Additionally, the output terminals of the instruction buffer 404 are coupled to the input terminals of the instruction mapping circuit system 408. Figure 4 In this example, the input terminals of the instruction mapping circuit system 408 can support 128 data bits. Additionally, each set of output terminals of the instruction mapping circuit system 408 can support 48 data bits. Figure 4 In this example, the input terminals of the instruction mapping circuit system 408 are coupled to the output terminals of the packet decoding circuit system 406. Figure 12 Each set of output terminals of the example instruction mapping circuit system 408 is coupled to the input terminal of the corresponding one in the functional unit 410.

[0055] exist Figure 11 In the illustrated example, the input terminals of the corresponding functional unit in functional unit 410 can support 48 data bits. Figure 4 In one example, the input terminal of a corresponding unit in functional unit 410 is coupled to the corresponding set of output terminals in instruction mapping circuit system 408. Additionally, in Figure 4 In one example, the output terminal of the corresponding one of the functional units 410 is coupled to the data write bus 314.

[0056] exist Figure 4 In the illustrated example, the extraction unit circuit system 402 is implemented by a logic circuit system (e.g., a sequential logic circuit system and / or a combinational logic circuit system). In other or alternative examples, the extraction unit circuit system 402 may be implemented by hardware, firmware, and / or software. In some examples, the extraction unit circuit system 402 is executed by extracting unit instructions and / or configured to perform operations (e.g., by...). Figure 11 The instantiation of a programmable circuit system (the operations represented in the flowchart). Figure 4 In one example, the fetch unit circuitry 402 requests one or more instruction packets from memory 308 via program bus 310. For instance, during the first clock cycle of bus master 302, the fetch unit circuitry 402 requests instruction packets from memory 308 via program bus 310.

[0057] exist Figure 4In the illustrated example of FIG. 4, the fetch unit circuitry 402 accesses (e.g., receives) one or more instruction packets from the memory 308 via the data read bus 312. For example, during the second clock cycle of the bus master 302, the fetch unit circuitry 402 accesses an instruction packet from the memory 308 via the data read bus 312 and stores (e.g., causes to store) the instruction packet in the instruction buffer 404. As described below, examples described herein pad the number of instruction packets that are not aligned with the bit width of the memory 308. Thus, when aligned, the fetch unit circuitry 402 can access an instruction packet from the memory 308 in one clock cycle. Additionally, the example fetch unit circuitry 402 dispatches one or more instruction packets from the instruction buffer 404 to the packet decode circuitry 406. For example, during the third clock cycle of the bus master 302, the fetch unit circuitry 402 dispatches an instruction packet from the instruction buffer 404 to the packet decode circuitry 406 when the instruction packet is present in the instruction buffer 404.

[0058] In some examples, the bus master 302 includes means for fetching. For example, the means for fetching can be implemented by the fetch unit circuitry 402. In some examples, the fetch unit circuitry 402 can be instantiated by programmable circuitry (e.g., the example programmable circuitry 1212) of the bus master 302. For example, the fetch unit circuitry 402 can be instantiated by the execution of machine executable instructions (e.g., by the execution of machine executable instructions by the example programmable circuitry 1212) of the bus master 302. Figure 4 In some examples, the bus master 302 includes means for fetching. For example, the means for fetching can be implemented by the fetch unit circuitry 402. In some examples, the fetch unit circuitry 402 can be instantiated by programmable circuitry (e.g., the example programmable circuitry 1212) of the bus master 302. For example, the fetch unit circuitry 402 can be instantiated by the execution of machine executable instructions (e.g., by the execution of machine executable instructions by the example programmable circuitry 1212) of the bus master 302. Figure 12The example microprocessor is instantiated with at least those instructions implemented in blocks 1102, 1104, and 1106. In some instances, the extraction unit circuit system 402 may be instantiated by a hardware logic circuit system, which may be implemented by an ASIC, XPU, or FPGA circuit system configured and / or constructed to implement operations corresponding to machine-readable instructions. For example, an XPU may be implemented by a heterogeneous computing system comprising various types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more network processing units (NPUs), one or more digital signal processors (DSPs), etc., and / or any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can assign computational tasks to any one or more types of programmable circuit systems suitable for and available for implementing the computational tasks. Alternatively or additionally, the extraction unit circuit system 402 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the extraction unit circuit system 402 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers, logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0059] exist Figure 11 In the illustrated example, instruction buffer 404 is implemented using one or more registers and / or storage elements. In other or alternative examples, instruction buffer 404 can be implemented using any type of memory. Figure 4 In one example, instruction buffer 404 stores one or more instruction packets to be dispatched to packet decoding circuitry system 406.

[0060] exist Figure 11 In the illustrated example, the packet decoding circuitry 406 is implemented by a logic circuitry (e.g., a sequential logic circuitry and / or a combinational logic circuitry). In other or alternative examples, the packet decoding circuitry 406 may be implemented by hardware, firmware, and / or software. In some examples, the packet decoding circuitry 406 is implemented by executing packet decoding instructions and / or configured to perform operations (e.g., by...). Figure 4 The instantiation of a programmable circuit system (the operations represented in the flowchart). Figure 4In the illustrated example of FIG. 4, the packet decode circuitry 406 is implemented by combinational logic and operates with the instruction map circuitry 408 as described herein to decode and map instructions into one or more of the functional units 410 in the same clock cycle of the bus master 302. In additional or alternative examples, the packet decode circuitry 406 can operate asynchronously (e.g., independent of the clock signal of the bus master 302). For example, when an instruction packet is dispatched to the packet decode circuitry 406, the packet decode circuitry 406 decodes the instruction packet into one or more instructions regardless of the value of the clock signal of the bus master 302.

[0061] In Figure 4 In the illustrated example of FIG. 4, the packet decode circuitry 406 interprets one or more opcodes that are part of the instruction packet. For example, the instruction packet can include one to eight instructions represented as opcodes. Example opcodes correspond to instructions to be executed by the functional units 410. In Figure 4 In the illustrated example of FIG. 4, the packet decode circuitry 406 decodes one or more instructions in an opcode representation (e.g., instruction opcodes) into one or more instructions in a data representation (e.g., instruction data). For example, the packet decode circuitry 406 decodes one or more instruction opcodes into instruction data (e.g., binary instruction data) that can be used to assign one or more instructions to one or more of the functional units 410 for execution.

[0062] In some examples, the bus master 302 includes means for decoding. For example, the means for decoding can be implemented by the packet decode circuitry 406. In some examples, the packet decode circuitry 406 can be instantiated by programmable circuitry (e.g., example programmable circuitry 1212 of FIG. 12). For example, the packet decode circuitry 406 can be instantiated by execution of machine executable instructions (e.g., by execution of machine executable instructions by the programmable circuitry 1212 of FIG. 12). Figure 12 Figure 11 ​example microprocessor instantiations of at least those instructions implemented by block 1108. In some examples, packet decode circuitry 406 can be instantiated by hardware logic circuitry, which can be implemented by ASIC, XPU, or FPGA circuitry configured and / or structured to perform operations corresponding to machine-readable instructions. Additionally or alternatively, packet decode circuitry 406 can be instantiated by any other combination of hardware, software, and / or firmware. For example, packet decode circuitry 406 can be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of machine-readable instructions and / or to perform some or all of the operations corresponding to machine-readable instructions without executing software or firmware, although other configurations are equally suitable.

[0063] In Figure 5 In the illustrated example of FIG. 4, instruction mapping circuitry 408 is implemented by logic circuitry (e.g., sequential logic circuitry and / or combinational logic circuitry). In additional or alternative examples, instruction mapping circuitry 408 can be implemented by hardware, firmware, and / or software. In some examples, instruction mapping circuitry 408 is instantiated by programmable circuitry that executes instruction mapping instructions and / or is configured to perform operations (e.g., those operations represented by flowchart of FIG. 4) corresponding to machine-readable instructions. Figure 5 In Figure 5 In the illustrated example of FIG. 4, instruction mapping circuitry 408 is implemented by logic circuitry (e.g., sequential logic circuitry and / or combinational logic circuitry). In additional or alternative examples, instruction mapping circuitry 408 can be implemented by hardware, firmware, and / or software. In some examples, instruction mapping circuitry 408 is instantiated by programmable circuitry that executes instruction mapping instructions and / or is configured to perform operations (e.g., those operations represented by flowchart of FIG. 4) corresponding to machine-readable instructions.

[0064] In Figure 5In the illustrated example of FIG. 4, instruction mapping circuitry 408 processes one or more instructions in data representation to assign the one or more instructions to one or more of functional units 410. For example, an instruction (e.g., in data representation) to be assigned to one of functional units 410 includes a mapping segment (e.g., between 1 bit and 15 bits) that indicates one or more of functional units 410 to which the instruction is to be assigned. Additionally, a remaining portion of the instruction (e.g., in data representation) includes data to be processed by the one or more of functional units 410 to which the instruction is assigned.

[0065] In Figure 5 In the illustrated example of FIG. 4, to assign an instruction to a functional unit, instruction mapping circuitry 408 parses instruction data to identify a mapping segment of the instruction data. Based on the mapping segment of the instruction data, instruction mapping circuitry 408 maps the instruction to one or more of functional units 410. In Figure 5 In examples, instruction mapping circuitry 408 can be implemented by one or more demultiplexers, where the mapping segment of an instruction is used to select an output of the one or more demultiplexers. In some examples, instruction mapping circuitry 408 can be implemented by multiple instances of instruction mapping circuitry 408 (e.g., multiple instruction mapping circuits). For example, each of functional units 410 can be associated with a dedicated instance of instruction mapping circuitry 408, where if an instruction includes a mapping segment that corresponds to a functional unit to which the instance of instruction mapping circuitry 408 is dedicated, the dedicated instance of instruction mapping circuitry 408 maps the instruction to the corresponding functional unit.

[0066] In some examples, bus master 302 includes means for mapping. For example, the means for mapping can be implemented by instruction mapping circuitry 408. In some examples, instruction mapping circuitry 408 can be instantiated by programmable circuitry (e.g., example programmable circuitry 1212 of FIG. 12). For example, instruction mapping circuitry 408 can be instantiated by execution of machine- executable instructions (e.g., by processor 1202 of FIG. 12). Figure 6-7 Figure 6 ​The instruction mapping circuit system 408 is instantiated from an example microprocessor that implements at least those instructions in blocks 1110, 1112, and 1114. In some instances, the instruction mapping circuit system 408 may be instantiated from a hardware logic circuit system, which may be implemented by an ASIC, XPU, or FPGA circuit system configured and / or constructed to perform operations corresponding to machine-readable instructions. Alternatively or concurrently, the instruction mapping circuit system 408 may be instantiated from any other combination of hardware, software, and / or firmware. For example, the instruction mapping circuit system 408 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers, logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally applicable.

[0067] As described above, when the bus master 302 encounters a padding instruction, it ignores the instruction and does not assign it to any functional unit of its own. Therefore, in some instances, the packet decoding circuitry 406 removes any padding instructions from the instruction set before providing the instruction set within the instruction packet to the instruction mapping circuitry 408. Alternatively, the instruction mapping circuitry 408 may discard any padding instructions received from the packet decoding circuitry 406 during the allocation of instructions among functional units 410. In this regard, a padding instruction is an instruction with a specific purpose that is not assigned to a functional unit of the programmable circuitry. The example padding instructions described herein are 16-bit instructions that can be instantiated multiple times within the same instruction packet.

[0068] For example, Figure 6 Example 16-bit padding instruction 500 is shown. Figure 6 The instance of the padding instruction 500 includes the example opcode 502. In Figure 6 In this example, opcode 502 is d60. Therefore, when packet decoding circuitry 406 receives opcode d60, it decodes the opcode into data (e.g., as...). Figure 6 (The data shown). Figure 6 In the example, bit 504 of padding instruction 500 is reserved to indicate whether padding instruction 500 is the last instruction in the instruction packet. For example, a value of 0 for bit 504 of padding instruction 500 indicates that padding instruction 500 is the last instruction in the instruction packet, while a value of 1 for bit 504 of padding instruction 500 indicates that padding instruction 500 is not the last instruction in the instruction packet.

[0069] like Figure 3As shown, the fill instruction 500 does not contain a mapping segment. Therefore, during instruction mapping to a functional unit of the bus master 302, the instruction mapping circuitry 408 does not map the fill instruction to any functional unit of the bus master 302. Instead, the instruction mapping circuitry 408 ignores example fill instructions and thus saves clock cycles (e.g., by preventing the bus master 302 from executing the fill instruction). In another or alternative instance, the fill instruction can be implemented such that it contains a mapping segment. In such an instance, the mapping segment of the fill instruction may contain data that does not correspond to a functional unit of the bus master 302. For example, the mapping segment of the fill instruction may contain data that would prevent the instruction mapping circuitry 408 from mapping the fill instruction to a functional unit.

[0070] Figure 6 The diagram illustrates instruction packets containing varying numbers of padding instructions. Instruction packets can contain a variable number of padding instructions or no padding instructions, such that adjacent instruction packets (e.g., immediately following instruction packets) are aligned with memory address boundaries. Figure 7 Example instruction package 600 containing four padding instructions is shown. Figure 7 In this example, instruction package 600 is a 128-bit instruction package containing eight 16-bit instructions, four of which are padding instructions. For example, instruction package 600 contains a first example instruction 602 to be executed by the functional unit, a second example instruction 604 to be executed by the functional unit, a third example instruction 606 to be executed by the functional unit, and a fourth example instruction 608 to be executed by the functional unit. Additionally, for example, instruction package 600 contains a first example padding instruction 610, a second example padding instruction 612, a third example padding instruction 614, and a fourth example padding instruction 616.

[0071] exist Figure 7 In the illustrated example, the first instruction 602, the second instruction 604, the third instruction 606, the fourth instruction 608, the first padding instruction 610, the second padding instruction 612, the third padding instruction 614, and the fourth padding instruction 616 reserve a bit to indicate whether the instruction package 600 contains additional instructions. For example, the 16th bit of the first instruction 602, the second instruction 604, the third instruction 606, the fourth instruction 608, the first padding instruction 610, the second padding instruction 612, the third padding instruction 614, and the fourth padding instruction 616 indicates whether the instruction is the last instruction in the instruction package 600. Figure 7 In this example, a value of 1 for bit 1 of the instruction indicates that the instruction packet contains additional instructions. Conversely, in Figure 7 In this example, a value of 0 for the 16th bit of the instruction indicates that the instruction packet does not contain any additional instructions.

[0072] like Figure 7As shown in the example, the first padding instruction 610, the second padding instruction 612, the third padding instruction 614, and the fourth padding instruction 616 cause the instruction packet following instruction packet 600 to be synchronized with a 128-bit wide memory (e.g., ...). Figure 3 The instruction packet (308) is aligned with the memory. For example, if the length of the instruction packet following instruction packet 600 is greater than 64 bits, then the instruction packet following instruction packet 600 will be unaligned with the 128-bit wide memory. Advantageously, by including a first padding instruction 610, a second padding instruction 612, a third padding instruction 614, and a fourth padding instruction 616 in instruction packet 600, the example described herein aligns the instruction packet following instruction packet 600 with the 128-bit wide memory, allowing subsequent instruction packets to be accessed from memory in one clock cycle.

[0073] exist Figure 7 In the illustrated example, the first instruction 602, the second instruction 604, the third instruction 606, and the fourth instruction 608 include corresponding mapping segments identifying the functional units to which they will be assigned. Additionally, the first fill instruction 610, the second fill instruction 612, the third fill instruction 614, and the fourth fill instruction 616 do not include mapping segments. Therefore, the first fill instruction 610, the second fill instruction 612, the third fill instruction 614, and the fourth fill instruction 616 will not be mapped to any functional unit. Thus, besides aligning instruction packets that would otherwise be misaligned, the first fill instruction 610, the second fill instruction 612, the third fill instruction 614, and the fourth fill instruction 616 also improve the operation of the programmable circuit system by saving clock cycles that would otherwise be used to execute instructions.

[0074] Figure 8 Example instruction package 700 containing two padding instructions is shown. Figure 8 In this example, instruction packet 700 is a 64-bit instruction packet containing four 16-bit instructions, two of which are padding instructions. For example, instruction packet 700 contains a first example instruction 702 to be executed by the functional unit and a second example instruction 704 to be executed by the functional unit. Additionally, for example, instruction packet 700 contains a first example padding instruction 706 and a second example padding instruction 708.

[0075] exist Figure 8 In the illustrated example, the first instruction 702, the second instruction 704, the first padding instruction 706, and the second padding instruction 708 reserve a bit to indicate whether the instruction packet 700 contains additional instructions. For example, the 16th bit of the first instruction 702, the second instruction 704, the first padding instruction 706, and the second padding instruction 708 indicates whether the instruction is the last instruction in the instruction packet 700. Figure 8In the example of FIG. 7, the 16th bit of the instruction indicates that additional instructions are included in the instruction packet with a value of 1. Conversely, in the example of FIG. 8, the 16th bit of the instruction indicates that no additional instructions are included in the instruction packet with a value of 0. Figure 8 In the example of FIG. 7, the 16th bit of the instruction indicates that additional instructions are included in the instruction packet with a value of 1. Conversely, in the example of FIG. 8, the 16th bit of the instruction indicates that no additional instructions are included in the instruction packet with a value of 0.

[0076] As shown in the example of FIG. 7, the first padding instruction 706 and the second padding instruction 708 align the instruction packet 700 that follows the instruction packet 700 with a 128-bit wide memory (e.g., the memory 308 of FIG. 3). For example, if the instruction packet that follows the instruction packet 700 is greater than 32 bits in length, the instruction packet that follows the instruction packet 700 will not be aligned with the 128-bit wide memory. Advantageously, by including the first padding instruction 706 and the second padding instruction 708 in the instruction packet 700, the examples described herein align the instruction packet 700 that follows the instruction packet 700 with the 128-bit wide memory so that the subsequent instruction packet can be accessed from the memory in one clock cycle. Figure 8 Figure 3 In the example of FIG. 7, the first instruction 702 and the second instruction 704 include respective mapping sections that identify the functional units to which the first instruction 702 and the second instruction 704 are to be assigned. Additionally, the first padding instruction 706 and the second padding instruction 708 do not include mapping sections. As such, the first padding instruction 706 and the second padding instruction 708 will not be mapped to any functional units. Thus, in addition to aligning instruction packets that would otherwise be misaligned, the first padding instruction 706 and the second padding instruction 708 also improve the operation of the programmable circuitry by conserving clock cycles that would otherwise be used to execute instructions.

[0077] In the example of FIG. 7, the first instruction 702 and the second instruction 704 include respective mapping sections that identify the functional units to which the first instruction 702 and the second instruction 704 are to be assigned. Additionally, the first padding instruction 706 and the second padding instruction 708 do not include mapping sections. As such, the first padding instruction 706 and the second padding instruction 708 will not be mapped to any functional units. Thus, in addition to aligning instruction packets that would otherwise be misaligned, the first padding instruction 706 and the second padding instruction 708 also improve the operation of the programmable circuitry by conserving clock cycles that would otherwise be used to execute instructions. Figure 8

[0078] An example instruction packet 800 that includes one padding instruction is shown. In the example of FIG. 8, the instruction packet 800 is a 64-bit instruction packet that includes one 32-bit instruction and two 16-bit instructions (one of which is a padding instruction). For example, the instruction packet 800 includes a first example instruction 802 to be executed by a functional unit and a second example instruction 804 to be executed by the functional unit. Additionally, for example, the instruction packet 800 includes an example padding instruction 806. Figure 4 Figure 4 In the example of FIG. 8, the first instruction 802, the second instruction 804, and the padding instruction 806 reserve one bit to indicate whether additional instructions are included in the instruction packet 800. For example, the 16th bit of the first instruction 802, the second instruction 804, and the padding instruction 806 indicates whether the instruction is the last instruction in the instruction packet 800. In the example of FIG. 8, the 16th bit of the instruction is a value of 1 to indicate that additional instructions are included in the instruction packet. Conversely, in the example of FIG. 9, the 16th bit of the instruction is a value of 0 to indicate that no additional instructions are included in the instruction packet.

[0079] In the example of FIG. 8, the first instruction 802, the second instruction 804, and the padding instruction 806 reserve one bit to indicate whether additional instructions are included in the instruction packet 800. For example, the 16th bit of the first instruction 802, the second instruction 804, and the padding instruction 806 indicates whether the instruction is the last instruction in the instruction packet 800. In the example of FIG. 8, the 16th bit of the instruction is a value of 1 to indicate that additional instructions are included in the instruction packet. Conversely, in the example of FIG. 9, the 16th bit of the instruction is a value of 0 to indicate that no additional instructions are included in the instruction packet. Figure 9 Figure 9 In the example of FIG. 8, the first instruction 802, the second instruction 804, and the padding instruction 806 reserve one bit to indicate whether additional instructions are included in the instruction packet 800. For example, the 16th bit of the first instruction 802, the second instruction 804, and the padding instruction 806 indicates whether the instruction is the last instruction in the instruction packet 800. In the example of FIG. 8, the 16th bit of the instruction is a value of 1 to indicate that additional instructions are included in the instruction packet. Conversely, in the example of FIG. 9, the 16th bit of the instruction is a value of 0 to indicate that no additional instructions are included in the instruction packet. Figure 9 ​​​​

[0080] like Figure 9 As shown in the example, the fill instruction 806 causes the instruction packet following instruction packet 800 to be filled with a 128-bit wide memory (e.g., ...). Figure 9 The instruction packet (308) is aligned with the memory. For example, if the instruction packet following instruction packet 800 is 64 bits long, then the instruction packet following instruction packet 800 will be unaligned with the 128-bit wide memory. Advantageously, by including a padding instruction 806 in instruction packet 800, the example described herein aligns the instruction packet following instruction packet 800 with the 128-bit wide memory, allowing subsequent instruction packets to be accessed from memory in one clock cycle.

[0081] exist Figure 9 In the illustrated example, the first instruction 802 and the second instruction 804 include corresponding mapping sections identifying the functional units to which the first instruction 802 and the second instruction 804 will be assigned. Additionally, the fill instruction 806 does not contain a mapping section. Therefore, the fill instruction 806 will not be mapped to any functional unit. Thus, besides aligning instruction packets that would otherwise be misaligned, the fill instruction 806 also improves the operation of the programmable circuit system by saving clock cycles that would otherwise be used to execute instructions.

[0082] Return to Figure 9 In the illustrated example, functional unit 410 is implemented by a logic circuit system (e.g., a sequential logic circuit system and / or a combinational logic circuit system). In other or alternative examples, functional unit 410 may be implemented by hardware, firmware, and / or software. In some examples, functional unit 410 includes an ALU, FPU, AGU, LSU, FINTDIV unit, TMU, and / or VCU. Figure 1 In one example, the corresponding functional unit in functional unit 410 executes one or more instructions assigned to the corresponding functional unit in functional unit 410. For example, the packet decoding circuit system 406 and the instruction mapping circuit system 408 decode the instructions and map them to the first functional unit 410. A During the fourth clock cycle, when instructions are provided by instruction mapping circuitry system 408, the first functional unit 410 A Execution assigned to the first functional unit 410 A The instructions.

[0083] Figure 9 An example memory 900 is shown, which includes an example instruction package 902 aligned with the width of the memory 900 via one or more padding instructions. Figure 1 In this example, memory 900 includes a first example line 904, a second example line 906, a third example line 908, and a fourth example line 910. Figure 9In this example, memory 900 is a 128-bit (e.g., 16-byte) wide byte-addressable memory, where instruction packets are aligned to 16-bit address boundaries. Figure 9 In the example, the instruction packet is between 16 bits and 128 bits, and the size of individual instructions can vary between 16 bits, 32 bits, and 48 bits.

[0084] exist Figure 9 In the example shown, the first line 904 begins at address 0x00 in hexadecimal representation (e.g., 0 in a base-10 representation). Additionally, the second example line 906 begins at address 0x10 in hexadecimal representation (e.g., 16 in a base-10 representation). Figure 1 In the example, the third line 908 begins at address 0x20 in hexadecimal representation (e.g., 32 in a base-10 representation). Additionally, the fourth example line 910 begins at address 0x30 in hexadecimal representation (e.g., 48 in a base-10 representation). Figure 10 In instances of pre-compiled and / or pre-assembled instructions, the instruction packet identified as I-packet-X can be a 12-byte (e.g., 96-bit) instruction packet, resulting in an instruction packet 902 that is not aligned with the width of the memory 900 pre-compiled and / or pre-assembled (similar to...). Figure 10 (See the illustration). Therefore, during pre-compilation and / or pre-assembly, the instructions in an instruction package identified as I-package-X contain a number of bits less than the bit width of 900 bytes of memory (e.g., 96 bits < 128 bits).

[0085] exist Figure 10 In the illustrated example of pre-compiled and / or pre-assembled instructions, instruction packet 902 is associated with a branch instruction having an example first destination address of 0x0C (e.g., 12 in a base-10 representation) 912. Therefore, without adjustment, additional clock cycles are spent accessing instruction packet 902 whenever a branch instruction is reached (e.g., in a loop). Advantageously, the compiler and / or assembler inserts two 16-bit padding instructions into the instruction packet identified as I-packet-X, aligning instruction packet 902 with the width of memory 900. Thus, the two padding instructions increase the number of bits in the instruction packet identified as I-packet-X to equal the bit width of memory 900. Additionally, the compiler and / or assembler updates the branch instruction associated with instruction packet 902 to have an example second destination address of 0x10 (e.g., 16 in a base-10 representation) 914. Therefore, when the programmable circuitry reaches the branch instruction of instruction packet 902, it is associated with executing an unaligned instruction packet (e.g., ...). Figure 10 Compared to the five clock cycles required to execute instruction packet 102, the programmable circuit system will execute instruction packet 902 in four clock cycles.

[0086] For example, inFigure 10 In the illustrated example, after the programmable circuit system processes the branch instruction associated with instruction packet 902, the programmable circuit system requests data from the second destination address 0x10 914 during the first clock cycle. To do this, the programmable circuit system requests data in the second line 906, which contains instruction packet 902. During the second clock cycle, the programmable circuit system receives the data in the second line 906. Since the data in the second line 906 contains only instruction packet 902, the programmable circuit system does not ignore any data from the second line 906.

[0087] exist Figure 10 In the example shown, during the third clock cycle, the programmable circuit system attempts to dispatch instruction packet 902 based on data received during the second clock cycle. Because instruction packet 902 (e.g., the entire instruction packet 902) has been returned from memory, the programmable circuit system successfully dispatches instruction packet 902 during the third clock cycle. During the fourth clock cycle, the programmable circuit system executes instruction packet 902. Figure 10 As shown in the example, because instruction packet 902 is aligned with the width of memory 900, it is compatible with the execution of unaligned instruction packets (e.g., Figure 10 Compared to the instruction packet 102) which takes at least five clock cycles, a programmable circuit system can execute an aligned instruction packet in four clock cycles.

[0088] Figure 1 An example memory 1000 is shown, which includes another example instruction package 1002 aligned with the width of the memory 1000 via one or more padding instructions. Figure 10 In this example, memory 1000 includes a first example line 1004, a second example line 1006, a third example line 1008, a fourth example line 1010, and a fifth example line 1012. Figure 10 In this example, memory 1000 is a 128-bit (e.g., 16-byte) wide byte-addressable memory, where instruction packets are aligned to 16-bit address boundaries. Figure 1 In the example, the instruction packet is between 16 bits and 128 bits, and the size of individual instructions can vary between 16 bits, 32 bits, and 48 bits.

[0089] exist Figure 10 In the example shown, the first line 1004 begins at address 0x10 in hexadecimal representation (e.g., 16 in a base-10 representation). Additionally, the second example line 1006 begins at address 0x20 in hexadecimal representation (e.g., 32 in a base-10 representation). Figure 10In the illustrated example of FIG. 10, the third row 1008 begins at address 0x30 in hexadecimal notation (e.g., 48 in base-10 notation). Additionally, the fourth example row 1010 begins at address 0x40 in hexadecimal notation (e.g., 64 in base-10 notation). In the illustrated example of FIG. 10, the fifth row 1012 begins at address 0x50 in hexadecimal notation (e.g., 80 in base-10 notation). In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 10 In the illustrated example of FIG. 10, the fifth row 1012 begins at address 0x50 in hexadecimal notation (e.g., 80 in base-10 notation). In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 1 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 10 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9).

[0090] In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 10 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 4-10 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 3 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9).

[0091] In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 4 In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9).

[0092] In the illustrated example of FIG. 10, the instruction packet identified as I-Packet-X is a 16-byte (e.g., 128-bit) instruction packet, resulting in a width-misaligned instruction packet 1002 precompiled and / or preassembled with the memory 1000 (similar to the instruction packet 102 of FIG. 9). Figure 3In the example shown, during the third clock cycle, the programmable circuit system attempts to dispatch instruction packet 1002 based on data received during the second clock cycle. Because instruction packet 1002 (e.g., the entire instruction packet 1002) has been returned from memory, the programmable circuit system successfully dispatches instruction packet 1002 during the third clock cycle. During the fourth clock cycle, the programmable circuit system executes instruction packet 1002. Figure 4 As shown in the example, because instruction packet 1002 is aligned with the width of memory 1000, it is compatible with the execution of unaligned instruction packets (e.g., Figure 4 Compared to the instruction packet 102) which takes at least five clock cycles, a programmable circuit system can execute an aligned instruction packet in four clock cycles.

[0093] exist Figure 4 In the example shown, the programmable circuit system can perform operations related to... Figure 4 Accessing an instruction packet identified as I-packet-X requires an additional clock cycle. For example, because an instruction packet identified as I-packet-X is a 128-bit instruction packet, the compiler and / or assembler may not insert one or more padding instructions before the instruction packet identified as I-packet-X to align it with the width of memory 1000. Therefore, when a programmable circuit requests an instruction packet identified as I-packet-X, the programmable circuit may spend two clock cycles accessing the instruction packet identified as I-packet-X. However, the additional clock cycle spent accessing the instruction packet identified as I-packet-X is a one-time cost because the instruction packet identified as I-packet-X is not associated with discontinuities.

[0094] In some instances, the compiler and / or assembler may also recognize that an instruction packet identified as I-packet-X is not aligned with the width of memory 1000, and insert one or more padding instructions before the instruction packet identified as I-packet-X to align it with the width of memory 1000. In such instances, one or more padding instructions inserted before the instruction packet identified as I-packet-X can align instruction packet 1002 with the width of memory 1000. Therefore, in such instances, the programmable circuit system can access the data in the first row 1004 in four clock cycles, the data in the second row 1006 in four clock cycles, and the data in the third row 1008 in four clock cycles.

[0095] like Figure 4 As shown, the padding instruction inserted into memory 308 allows the original... Figure 11The width of the instruction packets of the memory 308 are not aligned. Thus, the bus master 302 (e.g., the fetch unit circuitry 402) does not waste clock cycles to access more than one row of memory per instruction packet. Additionally, the bus master 302 (e.g., one or more of the functional units 410) can reduce the number of clock cycles to execute one or more instructions. For example, the bus master 302 (e.g., one or more of the functional units 410) ignores, discards, disregards, etc. the padding instructions and does not map the padding instructions to the functional units of the bus master 302. Thus, the padding instructions allow the bus master 302 (e.g., one or more of the functional units 410) to execute one or more instructions in a reduced number of clock cycles. For example, the padding instructions allow the bus master 302 (e.g., one or more of the functional units 410) to execute one or more instructions in a reduced number of clock cycles as compared to inserting NOP instructions into the memory to compensate for the misaligned instruction packets.

[0096] While an example manner of implementing the bus master 302 of Figure 4 is shown in FIG. 1 1, one or more of the elements, processes and / or devices illustrated in Figure 11 may be combined, divided, re-arranged, omitted, eliminated and / or implemented in any other way. Further, the example fetch unit circuitry 402, the example instruction buffer 404, the example packet decode circuitry 406, the example instruction mapping circuitry 408, the example functional units 410, and / or more generally the example bus master 302 of Figure 12 may be implemented by hardware alone or any combination of hardware and software and / or firmware. Thus, for example, any of the example fetch unit circuitry 402, the example instruction buffer 404, the example packet decode circuitry 406, the example instruction mapping circuitry 408, the example functional units 410, and / or more generally the example bus master 302 of Figure 11 may be implemented by programmable circuitry in combination with machine readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic devices (PLD), and / or field programmable logic devices (FPLD) such as FPGAs. Further, the example bus master 302 of Figure 3 may include one or more elements, processes and / or devices in addition to, or instead of those illustrated in FIG. 1 1, and / or can include more than one of any or all of the illustrated elements, processes and devices. Figure 11 Figure 11

[0097] Figure 3 An example manner of implementing the bus master 302 of Figure 11 ​​a flowchart of example behavior of the bus master 302. Figure 11 The operations in can be implemented by hard coded circuitry, by Figure 11 The machine-readable instructions can be one or more executable programs or portions of programs, and / or can be one or more functions, or portions of functions, to be implemented by the example programmable circuitry (e.g., FPGA) described below in the example programmable circuitry platform 1200 shown. In some instances, the machine-readable instructions cause operations, tasks, etc. to be performed and / or implemented in an automated fashion in the real world. As used herein, “automated” means without human intervention.

[0098] The programs can be embodied in instructions stored on one or more non-transitory computer- and / or machine-readable storage media, such as cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard drive, etc.), an optical storage device or disk (e.g., a Blu-ray disk, a compact disk (CD), a digital versatile disk (DVD), etc.), a RAID, registers, ROM, SSD, SSD memory, non-volatile memory (e.g., electrically-erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or disk. The instructions of the non-transitory computer- and / or machine-readable media can be programmed and / or executed by programmable circuitry located in one or more hardware devices, but the entire program and / or portions thereof can alternatively be executed and / or instantiated by one or more hardware devices other than programmable circuitry and / or embodied in dedicated hardware. The machine-readable instructions can be distributed on multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, a client hardware device can be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediary client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communications between a server and an endpoint client hardware device. Similarly, the non-transitory computer-readable storage media can include one or more media. Furthermore, although the example program is described with reference to the flowchart illustrated in FIG. 1, alternative examples can be used instead. For example, not all of the acts illustrated in FIG. 1 can be required to implement the example program in all alternative examples. Figure 11 The operations in can be implemented by hard coded circuitry, by Figure 11Many other methods of example bus master 302 of 4 are possible. For example, the order of execution of the blocks of the flowcharts can be changed, and / or some of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowcharts can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) structured to implement the corresponding operations without executing software or firmware. Programmable circuitry can be distributed in different network locations and / or local to one or more hardware devices (e.g., single core processors (e.g., single core CPUs), multi-core processors (e.g., multi-core CPUs, XPU, etc.)). For example, programmable circuitry can be one or more processors in a single machine, a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings), multiple processors distributed across a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0099] The machine-readable instructions described herein can be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as part of an instruction, code, a representation of code, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, the machine-readable instructions can be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in an edge device, etc.). The machine-readable instructions can be installed, modified, adjusted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, reassigned, and / or compiled, etc., so that they are directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions can be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that together can form, for example, a program described herein.

[0100] In another example, machine-readable instructions can be stored in a state in which they can be read by programmable circuitry, but enhanced with a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a particular computing device or other device. In another example, machine-readable instructions can require configuration (e.g., stored settings, data input, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding program can execute in whole or in part. Thus, machine-readable, computer-readable, and / or machine-readable medium, as used herein, can include instructions and / or programs, regardless of the particular format or state of the machine-readable instructions and / or programs.

[0101] The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0102] As described above, Figure 11Example operations of the application can be implemented using executable instructions stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage devices and / or storage disks including optical, magnetic, HDD, flash, readonly memory (ROM), CD, DVD, cache, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for extended periods of time, permanently, for brief instances, for temporary buffering, and / or for caching of the information). As used herein, the terms “non-transitory computer-readable storage device” and “non-transitory machine-readable storage device” are defined to include any physical (mechanical, magnetic, and / or electrical) hardware that retains information for any duration (excluding propagating signals and transmission media). Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include any type of random access memory, any type of read only memory, solid state memory, flash memory, optical disk, magnetic disk, disk drive, and / or redundant array of independent disks (RAID) system. As used herein, the term “device” refers to a physical structure such as a mechanical and / or electrical apparatus, hardware, and / or circuitry that can or can not be configured by, and / or manufactured to execute, computer-readable instructions, machine-readable instructions, and / or the like.

[0103] “Including” and “comprising” (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, comprising, includes, including, having, etc.) as a preamble, it is understood that additional elements, terms, etc. can be present in the corresponding claim, beyond those explicitly recited. As used herein, when the phrase “at least” is used as a transitional term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended.

[0104] As used herein, singular references (e.g., "a(a / an)", "first", "second", etc.) do not exclude multiples. As used herein, the term "a(a)" or "a(an)" refers to one or more of the objects mentioned. The terms "a(a) (or a(an))", "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, while individual features may be included in different instances or claims, these features may be combined, and inclusion in different instances or claims does not imply that the combination of features is not feasible and / or advantageous.

[0105] Figure 11 It means that it can be used. Figure 11 A flowchart of an example hard-coded and / or example programmable circuit system implementation of bus master 302 and / or 4 to perform, instantiate and / or implement example operation 1100. Figure 12 Example operation 1100 begins at block 1102, where the fetch unit circuitry 402 requests an instruction packet from memory via the program address bus. For example, at block 1102, the fetch unit circuitry 402 requests an instruction packet from memory 308 by requesting data at an address and / or within an address range in memory 308 via program bus 310.

[0106] exist Figure 11 In the illustrated example, at block 1104, the extraction unit circuitry 402 accesses an instruction packet from memory via a program data read bus. For example, at block 1104, the extraction unit circuitry 402 accesses an instruction packet from memory 308 via data read bus 312 and stores the instruction packet (e.g., such that the instruction packet is stored) in instruction buffer 404. Figure 3 In an example, the instruction packet may contain one or more padding instructions, one or more instructions for the functional unit to be mapped to the bus master 302, and / or a combination of one or more padding instructions and one or more instructions for the functional unit to be mapped to the bus master 302. Figure 11 In this example, at block 1106, the extraction unit circuitry 402 dispatches an instruction packet from the instruction buffer 404 to the packet decoding circuitry 406. For instance, at block 1106, the extraction unit circuitry 402 uses opcodes to indicate that one or more instructions of the instruction packet are dispatched to the packet decoding circuitry 406.

[0107] exist ​In the illustrated example, at block 1108, the packet decoding circuit system 406 decodes the instruction packet into at least one instruction. For example, at block 1108, the packet decoding circuit system 406 decodes, converts, translates, etc., the opcode representation of the instruction packet into a data representation. Additionally, the packet decoding circuit system 406 provides at least one instruction from the instruction packet to the instruction mapping circuit system 408. ​ In one example, when the instruction packet contains padding instructions, the packet decoding circuitry 406 only provides instructions that are not padding instructions to the instruction mapping circuitry 408. Alternatively, padding instructions may be provided, and the instruction mapping circuitry 408 may discard the padding instructions without providing them to the functional unit 410.

[0108] In an instance where a padding instruction can be provided to the instruction mapping circuitry system 408, at block 1110, the instruction mapping circuitry system 408 determines whether at least one instruction contains a padding instruction. For example, at block 1110, the instruction mapping circuitry system 408 parses at least one instruction to determine whether each instruction contains information indicating the functional unit to which the instruction will be assigned. Based on the instruction mapping circuitry system 408 determining that the instruction does not contain information indicating the functional unit to which the instruction will be assigned, the instruction mapping circuitry system 408 determines that the instruction is a padding instruction.

[0109] Alternatively, at block 1110, instruction mapping circuitry 408 parses at least one instruction to identify a corresponding mapping segment of the instruction and determines whether the corresponding mapping segment corresponds to a functional unit to which the instruction will be assigned. Based on instruction mapping circuitry 408 determining that a mapping segment of the instruction does not correspond to a functional unit, instruction mapping circuitry 408 determines that the instruction is a fill instruction. In some instances, fill instructions do not contain a mapping segment. Therefore, based on instruction mapping circuitry 408 determining that the instruction does not contain a mapping segment, instruction mapping circuitry 408 determines that the instruction is a fill instruction.

[0110] As described above, in some instances, the instruction mapping circuit system 408 is implemented by multiple instances of the instruction mapping circuit system 408. In such instances, multiple instances of the instruction mapping circuit system 408 may be implemented by multiple instruction mapping circuit systems associated with corresponding functional units in functional unit 410. For example, at block 1110, associated with the first functional unit 410 A The associated first instruction mapping circuit analysis is for the first functional unit 410 A The corresponding first information instruction, and based on the instruction not containing any related to the first functional unit 410 A The corresponding first information is ignored (e.g., at box 1112) and the instruction (e.g., fill instruction) is ignored. Additionally, for example, at box 1110, with the second functional unit 410...B The associated second instruction mapping circuitry parses the instructions for the second functional unit 410 B corresponding second information, and ignores (e.g., at block 1112) the instructions (e.g., padding instructions) based on the instructions not containing the second information corresponding to the second functional unit 410 B Thus, the multiple instances of instruction mapping circuitry 408 ignore padding instructions that do not contain information that would cause the padding instructions to be mapped to any of the functional units 410.

[0111] In the illustrated example of FIG. 11, based on (e.g., in response to) the instruction mapping circuitry 408 determining that at least one instruction contains a padding instruction (block 1110: YES), the operations 1100 proceed to block 1112. Based on (e.g., in response to) the instruction mapping circuitry 408 determining that at least one instruction does not contain a padding instruction (block 1110: NO), the operations 1100 proceed to block 1114. At block 1112, the instruction mapping circuitry 408 ignores the padding instruction. For example, at block 1112, the instruction mapping circuitry 408 does not assign (e.g., map) the padding instruction to any of the functional units 410. ​ In the illustrated example of FIG. 11, at block 1114, the instruction mapping circuitry 408 assigns the remaining instructions of the at least one instruction to at least one functional unit. For example, at block 1114, the instruction mapping circuitry assigns the remaining instructions of the at least one instruction to at least one of the functional units 410 based on information (e.g., a mapping section of the remaining instructions of the at least one instruction) indicating the functional units to which the remaining instructions of the at least one instruction correspond. In some examples, after ignoring a padding instruction, the at least one instruction can not contain any remaining instructions. For example, an instruction packet can contain only one padding instruction, or an instruction packet can contain only multiple padding instructions. In such examples, block 1114 can be omitted.

[0112] ​ In the illustrated example of FIG. 11, at block 1114, the instruction mapping circuitry 408 assigns the remaining instructions of the at least one instruction to at least one functional unit. For example, at block 1114, the instruction mapping circuitry assigns the remaining instructions of the at least one instruction to at least one of the functional units 410 based on information (e.g., a mapping section of the remaining instructions of the at least one instruction) indicating the functional units to which the remaining instructions of the at least one instruction correspond. In some examples, after ignoring a padding instruction, the at least one instruction can not contain any remaining instructions. For example, an instruction packet can contain only one padding instruction, or an instruction packet can contain only multiple padding instructions. In such examples, block 1114 can be omitted.

[0113] As shown in FIG. 11, if an instruction packet contains a padding instruction, the instruction mapping circuitry 408 ignores the padding instruction during the instruction assignment. For example, the bus master 302 can operate in an instruction assignment mode of operation that begins when the instruction mapping circuitry 408 evaluates whether one or more instructions of an instruction packet contain information (e.g., a mapping section) indicating a functional unit to which the one or more instructions are to be assigned, and ends when the instruction mapping circuitry 408 has ignored and / or assigned all one or more instructions of the instruction packet to a functional unit. The operations 1100 can be repeated for each instruction packet of a program. ​

[0114] ​​​ It is constructed to execute and / or instantiate ​ Example machine-readable instructions and / or example operations to implement ​ A block diagram of an example programmable circuit system platform 1200 with a bus master 302 of 4 and / or 5. The programmable circuit system platform 1200 can be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, such as iPad). TM This includes tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, set-top boxes, headphones (e.g., augmented reality (AR) headphones, virtual reality (VR) headphones, etc.) or other wearable devices, or any other type of computing and / or electronic device. In some instances, the programmable circuit system platform 1200 can be implemented as a SoC. In such instances, the programmable circuit system platform 1200 can be implemented by digital logic circuit systems (e.g., sequential logic circuit systems and / or combinational logic circuit systems).

[0115] The programmable circuit system platform 1200 of the illustrated example includes a programmable circuit system 1212. The programmable circuit system 1212 of the illustrated example is hardware. For example, the programmable circuit system 1212 can be implemented by a digital logic circuit system (e.g., a sequential logic circuit system and / or a combinational logic circuit system). In some instances, the programmable circuit system 1212 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 1212 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1212 implements an example extraction unit circuit system 402, an example packet decoding circuit system 406, an example instruction mapping circuit system 408, and an example functional unit 410.

[0116] The programmable circuitry 1212 of the illustrated example includes local memory 1213 (e.g., a cache, registers, etc.). In this example, the local memory 1213 implements the instruction buffer 404. The programmable circuitry 1212 of the illustrated example communicates with a main memory 1214, 1216 via a bus 1218 that includes a volatile memory 1214 and a non-volatile memory 1216. The volatile memory 1214 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1216 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1214, 1216 of the illustrated example is controlled by a memory controller 1217. In some examples, the memory controller 1217 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer that is used to manage the flow of data to and from the main memory 1214, 1216.

[0117] The programmable circuitry platform 1200 of the illustrated example also includes interface circuitry 1220. The interface circuitry 1220 can be implemented by hardware according to any type of interface standard (e.g., an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface).

[0118] In the illustrated example, one or more input devices 1222 are connected to the interface circuitry 1220. The input devices 1222 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 1212. The input devices 1222 can be implemented, for example, by audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touch screens, touchpads, trackballs, pointing devices, and / or voice recognition systems.

[0119] One or more output devices 1224 are also connected to the interface circuitry 1220 of the illustrated example. The output devices 1224 can be implemented, for example, by display devices (e.g., light emitting diodes (LEDs), organic light emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-place switching (IPS) displays, touchscreens, etc.), tactile output devices, printers, and / or speakers. Thus, the interface circuitry 1220 of the illustrated example typically includes graphics driver cards, graphics driver chips, and / or graphics processor circuitry such as GPUs.

[0120] The interface circuitry 1220 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via network 1226. Communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, a satellite system, a terrestrially- based system, a light-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, or an optical connection.

[0121] The programmable circuitry platform 1200 of the illustrated example also includes one or more mass storage devices or units 1228 for storing software, firmware, and / or data. Examples of such mass storage devices or units 1228 include magnetic storage devices (e.g., diskette, hard drive, HDD, etc.), optical storage devices (e.g., Blu-ray disk, CD, DVD, etc.), RAID systems, and / or solid-state storage devices such as flash memory devices and / or SSDs.

[0122] Machine-readable instructions 1232 that can be implemented by the machine- readable instructions of ​ Machine-readable instructions 1232 that can be implemented by the machine- readable instructions of

[0123] In this description, the term "and / or," where used in, for example, a form such as A, B, and / or C, means any combination or subset of A, B, and / or C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A, B, and C. Also, as used in this description, the phrase, "at least one of A or B" (or "at least one of A and B") means that an implementation include any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0124] In this description, the term "coupled" can cover a connection, a communication, or a signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through intermediate component C, provided that intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A through the control signal generated by device A.

[0125] Numerical designators such as "first," "second," "third," and so on, are merely used to distinguish between elements of substantially similar type. As is used in the detailed description, these designators are not necessarily used consistently with the designators used in the claims.

[0126] An apparatus "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired), at a time of manufacturing by a manufacturer, and / or can be configured (or reconfigured) by a user after manufacturing to perform the task and / or function and / or other additional or alternative tasks and / or functions. The configuration can be through firmware and / or software programming of the apparatus, through construction and / or layout of hardware components and interconnections of the apparatus, or a combination thereof.

[0127] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" can be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote an interconnection or a terminal between elements of a circuit, a circuit element, an integrated circuit, a device, or other electronic device or semiconductor component.

[0128] Circuits or devices described herein as including certain components can actually be adapted to be coupled to those components to form the described circuitry or device. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be adapted to be coupled to at least some of the passive elements and / or sources, at a time of manufacture or after a time of manufacture, such as by a terminal user and / or a third party, to form the described structure.

[0129] The circuits described herein can be reconfigurable to include alternative components to provide at least some functionality similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be a plurality of resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can in fact be a plurality of resistors or capacitors respectively coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments additional or fewer features can be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit can be included in the integrated circuit, and / or some features shown as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means circuit(s) that are: (i) incorporated in / onto a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in the same printed circuit board.

[0130] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of the present specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value, or a reasonable range of values near zero if the value is zero.

[0131] Modifications can be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0132] From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods to align address boundaries in memory have been described. The example systems, apparatus, articles of manufacture, and methods described herein reduce the number of clock cycles taken to read data (e.g., instruction packets) from memory. In addition, the examples described herein do not assign padding instructions to functional units and do not spend clock cycles to execute instructions included for memory alignment purposes. The described systems, apparatus, articles of manufacture, and methods improve efficiency of using a computing device by reducing the number of clock cycles taken to read and execute instructions, which improves performance of the computing device by reducing power consumption. Thus, the described systems, apparatus, articles of manufacture, and methods relate to one or more improvements in the operation of a machine (e.g., a computer or other electronic and / or mechanical device).

[0133] The accompanying claims are hereby incorporated into this detailed description by reference. Although certain example systems, devices, articles, and methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods falling within the scope of the claims appended hereto.

Claims

1. An apparatus comprising: Packet decoding circuitry system for decoding instruction packets for programmable circuitry systems into at least one instruction; as well as An instruction mapping circuit system is used to ignore padding instructions contained in the at least one instruction, which have not yet been assigned to any functional unit of the programmable circuit system.

2. The device of claim 1, wherein the at least one instruction comprises the padding instruction and the second instruction, and the instruction mapping circuit system is configured to ignore the padding instruction during instruction assignment of the second instruction to at least one functional unit of the programmable circuit system.

3. The device of claim 1, wherein the instruction mapping circuitry is configured to determine whether information contained in the fill instruction indicates that the fill instruction is assigned to any functional unit of the programmable circuitry.

4. The device of claim 1, wherein the at least one instruction comprises the fill instruction and the second instruction, and the instruction mapping circuit system is configured to: Parse the at least one instruction to identify a first mapping segment of the filling instruction and a second mapping segment of the second instruction, the second mapping segment indicating the first functional unit to which the second instruction will be assigned; and The fill instruction is ignored because the first mapping segment contains information that does not correspond to any functional unit of the programmable circuit system.

5. The device of claim 1, wherein the at least one instruction comprises the fill instruction and the second instruction, and the instruction mapping circuit system is configured to: Parsing the at least one instruction to identify a first mapping segment of the second instruction, the first mapping segment indicating the first functional unit to which the second instruction will be assigned; and The fill instruction is ignored because it does not contain a second mapping segment.

6. The device according to claim 1, wherein: The instruction packet is the first instruction packet; The device further includes an extraction unit circuit system and a memory, the memory being used to store the first instruction packet and the second instruction packet; The padding instruction aligns the second instruction packet to the bit width of the memory; and The extraction unit circuit system is used to align the second instruction packet to the bit width of the memory based on the padding instruction and access the second instruction packet from the memory in one clock cycle.

7. The device according to claim 1, wherein: The programmable circuit system includes a first functional unit and a second functional unit; and The instruction mapping circuit system includes: A first instruction mapping circuit associated with the first functional unit, the first instruction mapping circuit being used for: Parse the fill instruction to obtain first information corresponding to the first functional unit; and The fill instruction is ignored because it does not contain the first information corresponding to the first functional unit; and A second instruction mapping circuit associated with the second functional unit, the second instruction mapping circuit being used for: Parse the fill instruction to obtain second information corresponding to the second functional unit; and The fill instruction is ignored because it does not contain the second information corresponding to the second functional unit.

8. The device according to claim 1, wherein the programmable circuit system is based on a very long instruction word architecture.

9. The device of claim 8, wherein the filling instruction is a first filling instruction, and the instruction package includes a second filling instruction.

10. A non-transitory machine-readable storage medium comprising: A first instruction packet, stored in a first line of the non-transitory machine-readable storage medium, includes a first instruction associated with a first functional unit of the programmable circuit system and at least one padding instruction not associated with any functional unit of the programmable circuit system. The first instruction includes a first number of bits smaller than the bit width of the non-transitory machine-readable storage medium. The second instruction packet, stored in a second line of the non-transitory machine-readable storage medium, contains a second instruction associated with a second functional unit of the programmable circuit system. The at least one padding instruction is used to align the second instruction packet to the bit width of the non-transitory machine-readable storage medium by increasing the first number of bits of the first instruction packet to be equal to the bit width of the non-transitory machine-readable storage medium.

11. The non-transitory machine-readable storage medium of claim 10, wherein the at least one padding instruction comprises a first padding instruction and a second padding instruction.

12. The non-transitory machine-readable storage medium of claim 10, wherein the second instruction packet comprises a second number of bits equal to the bit width of the non-transitory machine-readable storage medium.

13. A method comprising: A packet decoding circuit system is used to decode instruction packets intended for programmable circuit systems into at least one instruction. as well as The instruction mapping circuit system ignores padding instructions contained in the at least one instruction, which have not yet been assigned to any functional unit of the programmable circuit system.

14. The method of claim 13, wherein the at least one instruction comprises the padding instruction and the second instruction, and the method further comprises ignoring the padding instruction during instruction assignment of the second instruction to at least one functional unit of the programmable circuit system.

15. The method of claim 13, further comprising determining whether information contained in the fill instruction indicates that the fill instruction is assigned to any functional unit of the programmable circuit system.

16. The method of claim 13, wherein the at least one instruction comprises the filling instruction and the second instruction, and the method further comprises: Parse the at least one instruction to identify a first mapping segment of the filling instruction and a second mapping segment of the second instruction, the second mapping segment indicating the first functional unit to which the second instruction will be assigned; and The fill instruction is ignored because the first mapping segment contains information that does not correspond to any functional unit of the programmable circuit system.

17. The method of claim 13, wherein the at least one instruction comprises the filling instruction and the second instruction, and the method further comprises: Parsing the at least one instruction to identify a first mapping segment of the second instruction, the first mapping segment indicating the first functional unit to which the second instruction will be assigned; and The fill instruction is ignored because it does not contain a second mapping segment.

18. The method of claim 13, wherein the instruction packet is a first instruction packet, and the method further comprises accessing the second instruction packet from the memory in one clock cycle by aligning the second instruction packet to the bit width of the memory based on the padding instruction, the memory being used to store the first instruction packet and the second instruction packet.

19. The method of claim 13, wherein: The programmable circuit system includes a first functional unit and a second functional unit; The instruction mapping circuit system includes a first instruction mapping circuit associated with the first functional unit and a second instruction mapping circuit associated with the second functional unit; and The method further includes: The first instruction mapping circuit is used to parse the fill instruction to obtain first information corresponding to the first functional unit; The first instruction mapping circuit is used to ignore the fill instruction because the fill instruction does not contain the first information corresponding to the first functional unit; The second instruction mapping circuit is used to parse the fill instruction to obtain second information corresponding to the second functional unit; as well as The second instruction mapping circuit ignores the fill instruction because it does not contain the second information corresponding to the second functional unit.

20. The method of claim 13, wherein the programmable circuit system is based on a very long instruction word architecture.

21. The method of claim 20, wherein the fill instruction is a first fill instruction, and the instruction package includes a second fill instruction.

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