Gate drive circuit

Abstract

A gate drive circuit (100) is provided with: a signal conversion circuit (2) that converts a gate control signal (11) into a differential signal (21) comprising a positive signal (21A) and a negative signal (21B); a first pulse transformer (3) having a primary winding and a secondary winding each having a neutral point, the neutral point of the primary winding being set to the potential of the first ground, and a positive signal (21A) and a negative signal (21B) being inputted to both ends of the primary winding, respectively; an input differential voltage generation circuit (6) that generates a pair of input differential voltages (22A, 22B) at both ends of the pair of resistive elements on the basis of the voltages at both ends of the secondary winding of the first pulse transformer (3); a differential amplifier circuit (7) that differentially amplifies the pair of input differential voltages (22A, 22B) and outputs a pair of output differential voltages (23A, 23B); and a gate drive signal generation circuit (9) that generates a gate drive signal (25A) on the basis of the pair of output difference voltages (23A, 23B).

Description

TECHNICAL FIELD

[0001] The present application relates to a gate drive circuit. BACKGROUND

[0002] This application claims priority based on Japanese Patent Application No. 2023-074978 filed on April 28, 2023, and the contents thereof are hereby incorporated by reference.

[0003] In the past, it has been known that, in a gate drive circuit that drives a switching element that operates in a floating state, the input side and the output side are insulated. In such a case, sometimes common mode noise is generated due to switching of the switching element or the like. As a countermeasure against this common mode noise, various schemes have been proposed. For example, in the gate drive circuit of Patent Literature 1, the input side and the output side are insulated by a pulse transformer, the input side is grounded to a first ground potential point, and the output side is grounded to a second ground potential point. Further, a primary winding of the pulse transformer is input with a primary side gate drive signal, the output of a secondary side of the pulse transformer is differentially amplified by a comparator, and is output as a secondary side gate drive signal. Further, an electrostatic shield plate grounded to the second ground potential point is disposed between the primary winding and the secondary winding of the pulse transformer.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2013-074079 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] The gate drive circuit of Patent Literature 1 can remove common mode noise superimposed on the output side, but cannot remove common mode noise superimposed on the input side.

[0009] The present application was completed in order to solve such a problem, and aims to provide a gate drive circuit that can remove common mode noise superimposed on the output side and the input side.

[0010] MEANS FOR SOLVING THE PROBLEMS

[0011] To achieve the above object, a gate drive circuit according to an aspect of the present disclosure includes: a signal conversion circuit that operates with a potential of a first ground terminal as a reference potential, converts a gate control signal that is a single-ended signal into a differential signal constituted by a positive signal and a negative signal corresponding to the gate control signal in a difference in signal levels therebetween, and outputs the differential signal; a first pulse transformer that has a primary winding and a secondary winding electrically insulated from each other and each having a neutral point, the neutral point of the primary winding is set to the potential of the first ground terminal, and both ends of the primary winding are input with the positive signal and the negative signal of the differential signal, respectively; an input differential voltage generation circuit that has a pair of resistance elements connected in series with each other, both ends and a connection point of the pair of resistance elements are electrically connected directly to both ends and the neutral point of the secondary winding of the first pulse transformer or are connected to both ends and the neutral point of the secondary winding of the first pulse transformer via a transmission cable and a second pulse transformer, respectively, and generates a pair of input differential voltages with the potential of the connection point as a reference at both ends of the pair of resistance elements; a differential amplification circuit that is electrically connected to the input differential voltage generation circuit, differentially amplifies the pair of input differential voltages, and outputs a pair of output differential voltages; and a gate drive signal generation circuit that is electrically connected to the differential amplification circuit, generates a gate drive signal that is a single-ended signal with a prescribed potential as a reference based on the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates with a potential of a second ground terminal as a reference.

[0012] Effects of Invention

[0013] The present application achieves the following effects: A gate drive circuit capable of removing common mode noise superimposed on an output side and an input side can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a circuit diagram showing a structure of a push-pull amplification circuit using the gate drive circuit of the present disclosure.

[0015] Figure 2A is a block diagram showing a first structure example of the gate drive circuit of Figure 1

[0016] Figure 2B is a block diagram showing a second structure example of the gate drive circuit of Figure 1

[0017] Figure 3 is a circuit diagram showing an example of a specific circuit structure of the first structure example of the gate drive circuit of Figure 2A

[0018] Figure 4A is a waveform diagram showing a waveform of a differential signal to which common mode noise is superimposed.​​​

[0019] Figure 4B is a waveform chart showing a waveform of a differential signal induced in a 1st pulse transformer from a differential voltage generated by an input differential voltage generation circuit. Figure 4A

[0020] Figure 4C is a waveform chart showing a waveform of an input differential voltage generated by an input differential voltage generation circuit from a signal of a differential signal induced in a 1st pulse transformer from a differential voltage generated by an input differential voltage generation circuit. Figure 4B

[0021] Figure 5 is a circuit diagram showing an operation of a switching power supply device using a push-pull amplification circuit of Figure 3

[0022] Figure 6 is a schematic diagram showing a switching noise generated by a switching module of Figure 5 DETAILED DESCRIPTION

[0023] A gate drive circuit of an aspect of the present disclosure has: a signal conversion circuit that operates with a potential of a 1st ground terminal as a reference potential, converts a gate control signal that is a single-ended signal into a differential signal constituted by a positive signal and a negative signal whose signal level difference from each other corresponds to the gate control signal; a 1st pulse transformer that has a primary winding and a secondary winding that are electrically insulated from each other and each has a neutral point, the neutral point of the primary winding is set to the potential of the 1st ground terminal, and both ends of the primary winding are respectively input with the positive signal and the negative signal of the differential signal; an input differential voltage generation circuit that has a pair of resistance elements connected in series with each other, both ends and a connection point of the pair of resistance elements are respectively electrically connected with both ends and the neutral point of the secondary winding of the 1st pulse transformer directly or via a transmission cable and a 2nd pulse transformer, a pair of input differential voltages with the potential of the connection point as a reference are generated at both ends of the pair of resistance elements; a differential amplification circuit that is electrically connected with the input differential voltage generation circuit, differentially amplifies the pair of input differential voltages to output a pair of output differential voltages; and a gate drive signal generation circuit that is electrically connected with the differential amplification circuit, generates a gate drive signal that is a single-ended signal with a prescribed potential as a reference from the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates with a potential of a 2nd ground terminal as a reference.

[0024] ​​​​According to the configuration, the input side and the output side of the gate drive circuit are insulated from each other by the first pulse transformer, and the output side is connected to the switching element to become a floating state with reference to the potential of the second ground terminal, with respect to the input side with reference to the potential of the first ground terminal. In this state, the gate control signal as a single-ended signal is converted into a differential signal by the signal conversion circuit, the differential signal is composed of a positive signal and a negative signal whose signal level difference from each other corresponds to the gate control signal, and the neutral point of the primary winding of the first pulse transformer is set to the potential of the first ground terminal, and both ends of the primary winding are inputted with the differential signal. Thereby, the positive signal and the negative signal are converted into a pair of single-ended voltage signals respectively having an amplitude of twice and phases opposite to each other (plus-minus opposite) as their both-end voltage induced in the same transformer winding. Therefore, when the positive signal and the negative signal respectively superimposed with common mode noise at the input side, the plus-minus of the common mode noise of the positive signal and the common mode noise of the negative signal are opposite to each other, and thus the common mode noise of the positive signal and the common mode noise of the negative signal are cancelled and removed in the first pulse transformer.

[0025] Also, at the output side, both ends and the connection point of the pair of resistance elements of the input differential voltage generation circuit are directly electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer, or are connected to both ends and the neutral point of the secondary winding of the first pulse transformer via the transmission cable and the second pulse transformer, respectively, and a pair of input differential voltages with reference to the potential of the connection point are generated at both ends of the pair of resistance elements, and the pair of input differential voltages are differentially amplified by the differential amplification circuit. Therefore, when common mode noise is superimposed on the pair of wirings directly or indirectly connected to both ends of the secondary winding of the first pulse transformer at the output side, the common mode noise of the pair of wirings is opposite to each other in the pair of input differential voltages generated by the input differential voltage generation circuit, and is removed by the differential amplification circuit. Also, since the load current of the first pulse transformer flows through the pair of resistance elements of the input differential voltage generation circuit, the impedance of the transmission path of the differential signal is lowered, and the common mode noise removal capability is improved.

[0026] As a result, it is possible to provide a gate drive circuit capable of removing common mode noise superimposed on the output side and the input side.

[0027] Also, the second pulse transformer can have a primary winding and a secondary winding which are electrically insulated from each other and each have a neutral point, both ends and the neutral point of the primary winding of the second pulse transformer can be electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer via the transmission cable, respectively, and both ends and the connection point of the pair of resistance elements of the input differential voltage generation circuit can be connected to both ends and the neutral point of the secondary winding of the second pulse transformer, respectively.

[0028] According to this structure, in the case where common mode noise is superimposed on the secondary winding of the first pulse transformer and the transmission cable, the second pulse transformer can be used to remove the common mode noise as with the first pulse transformer. As a result, by extending the transmission cable, the control device that generates the gate control signal can be disposed away from the switching element, and the computer that constitutes the control device can be appropriately protected from the noise generated by the switching operation of the switching element.

[0029] Also, the two switching elements can constitute a first switching element and a second switching element that are push-pull connected to each other, the gate drive circuit can have a first differential amplification circuit and a second differential amplification circuit as the differential amplification circuit, the gate drive circuit can have a first gate drive signal generation circuit and a second gate drive signal generation circuit as the gate drive signal generation circuit, the first differential amplification circuit can be a circuit that is electrically connected to the input differential voltage generation circuit, differentially amplifies the pair of input differential voltages, and outputs a pair of first output differential voltages of high potential, the second differential amplification circuit can be a circuit that is electrically connected to the input differential voltage generation circuit, differentially amplifies the pair of input differential voltages, and outputs a pair of second output differential voltages of low potential that is lower than the pair of first output differential voltages, the first gate drive signal generation circuit can be a circuit that is electrically connected to the first differential amplification circuit, generates a first gate drive signal that is the gate drive signal based on a positive potential from the pair of first output differential voltages, and outputs the first gate drive signal to the first switching element, and the second gate drive signal generation circuit can be a circuit that is electrically connected to the second differential amplification circuit, generates a second gate drive signal that is the gate drive signal based on a negative potential from the pair of second output differential voltages, and outputs the second gate drive signal to the second switching element.

[0030] According to this structure, the first switching element and the second switching element that are push-pull connected to each other can be driven while removing common mode noise superimposed on the output side and the input side.

[0031] Also, the gate drive signal generation circuit can be a circuit that includes a flip-flop that is input with the pair of output differential voltages and outputs a single-ended signal based on a prescribed potential, and outputs the single-ended signal as the gate drive signal.

[0032] According to this structure, the gate drive signal that is a single-ended signal based on a prescribed potential can be generated using a flip-flop. Also, the waveform of the pair of output differential voltages of the differential amplification circuit can be shaped, and thus the common mode noise can be further removed.

[0033] A detailed description is given below of the embodiments of the present disclosure with reference to the drawings. Note that the same reference numerals are used throughout the drawings for the same or similar elements, and repetitive description is omitted. Also, the drawings used in the following description are used only for describing the present disclosure, and thus there are cases where elements unrelated to the present disclosure are omitted, cases where the dimensions are not accurate for the purpose of exaggeration or the like, cases of simplification, cases where the shapes of elements corresponding to each other in a plurality of drawings are not consistent, and the like. Also, the present disclosure is not limited to the following embodiments.

[0034] (Embodiment)

[0035] First, the environment in which the gate drive circuit of the present disclosure is used is described.

[0036] [Environment of use]

[0037] Figure 1 is a circuit diagram illustrating the structure of a push-pull amplifier circuit 500 using the gate drive circuit 100 of the present disclosure. Referring to Figure 1 , the push-pull amplifier circuit 500 includes a pair of switching elements 60 connected in push-pull and the gate drive circuit 100. The pair of switching elements 60 is configured by connecting a high-side first switching element 61, for example, configured by a PMOSFET, and a low-side second switching element 62, for example, configured by an NMOSFET, in series between a positive power supply VDD and a second ground terminal GND2, and an output is taken out from the connection point thereof. In the gate drive circuit 100, the input side is insulated from the output side, the input side is connected to a first ground terminal GND1, and the output side is electrically connected to the pair of switching elements 60. Thus, the output side is in a floating state with respect to the first ground terminal GND1 of the input side. The gate drive circuit 100 generates a gate drive signal in accordance with a gate control signal 11 input from a control board 1, and drives the pair of switching elements 60 by the gate drive signal. Next, the structure of the gate drive circuit 100 is described.

[0038] [Structure of gate drive circuit 100]

[0039] First, a summary of the structure of the gate drive circuit 100 is described. The gate drive circuit 100 includes a first structure example to a third structure example.

[0040] {Summary}

[0041] Figure 2A is a block diagram illustrating the first structure example of the gate drive circuit 100 of Figure 1 .

[0042] First, the first structure example is described. The first structure example is a structure example of the gate drive circuit 100 in a case where a transmission cable 4 and a second pulse transformer are provided. Referring to Figure 2AThe gate drive circuit 100 includes a signal conversion circuit 2, a first pulse transformer 3, a transmission cable 4, a second pulse transformer 5, an input differential voltage generation circuit 6, a first differential amplification circuit 7, a second differential amplification circuit 8, a first gate drive signal generation circuit 9, and a second gate drive signal generation circuit 10.

[0043] The signal conversion circuit 2 operates with a potential of the first ground terminal GND1 as a reference potential, converts the gate control signal 11 from the control substrate 1, which is a single-ended signal, into a differential signal 21 composed of a positive signal 21A and a negative signal 21B whose signal level difference from each other corresponds to the gate control signal 11.

[0044] The first pulse transformer 3 transmits the differential signal 21 to the input differential voltage generation circuit 6 via the transmission cable 4 and the second pulse transformer 5. Thus, the input side and the output side of the gate drive circuit 100 are insulated by the first pulse transformer 3 and the second pulse transformer 5.

[0045] The input differential voltage generation circuit 6 generates a pair of input differential voltages 22A, 22B in accordance with the transmitted differential signal 21. The first differential amplification circuit 7 differentially amplifies the pair of input differential voltages 22A, 22B to output a pair of first output differential voltages 23A, 23B of high potential. The first gate drive signal generation circuit 9 generates a first gate drive signal 25A with a prescribed positive potential as a reference in accordance with the pair of first output differential voltages 23A, 23B, and outputs the first gate drive signal 25A to the first switching element 61 (refer to Figure 1 ). On the other hand, the second differential amplification circuit 8 differentially amplifies the pair of input differential voltages 22A, 22B to output a pair of second output differential voltages 24A, 24B of lower potential than the pair of first output differential voltages 23A, 23B. The second gate drive signal generation circuit 10 generates a second gate drive signal 25B with a prescribed negative potential as a reference in accordance with the pair of second output differential voltages 24A, 24B, and outputs the second gate drive signal 25B to the second switching element 62 (refer to Figure 1 ).

[0046] Such a first configuration example is applied to a case where it is desired to protect a computer constituting the control substrate (control device) 1 from a generation source of common mode noise as much as possible.

[0047] Next, a second configuration example will be described. Figure 2B is a block diagram showing a second configuration example of the gate drive circuit 100 of Figure 1 . Refer to Figure 2BIn the second configuration example, the transmission cable 4 and the second pulse transformer 5 are omitted. Therefore, in the second configuration example, the input side and the output side of the gate drive circuit 100 are insulated by the first pulse transformer 3. Also, the input differential voltage generation circuit 6 generates a pair of input differential voltages 22A, 22B based on the differential signal 21 output to the secondary winding of the first pulse transformer 3. The configuration other than this is the same as that of the first configuration example, and therefore the description thereof is omitted. Such a second configuration example is applied to a case where it is not necessary to distance the control substrate 1 from the source of the common mode noise.

[0048] Next, the third configuration example is described. In the third configuration example, the gate drive circuit 100 has only one set of the differential amplification circuit and the gate drive signal generation circuit (for example, the first differential amplification circuit 7 and the first gate drive signal generation circuit 9 or the second differential amplification circuit 8 and the second gate drive signal generation circuit 10). The configuration other than this is the same as that of the first configuration example or the second configuration example, and therefore the description thereof is omitted. Such a third configuration example is applied to a case where the individual switching element (for example, the first switching element 61 or the second switching element 62) is driven. Figure 1

[0049] Next, the detailed configuration and operation of the gate drive circuit 100 of the first configuration example are described. Also, with respect to the second configuration example and the third configuration example, since only the elements of the first configuration example are omitted, the detailed configuration and operation thereof are omitted. Figure 2A

[0050] {Detailed Configuration}

[0051] Figure 3 is a circuit diagram showing an example of the detailed circuit configuration of the first configuration example of the gate drive circuit 100. Figure 2A

[0052] Referring to the circuit shown in Figure 3 , Figure 3 , the circuit includes the gate drive circuit 100 of Figure 2A and the pair of switching elements 60 of the push-pull connection of Figure 1 , and is configured as a push-pull amplification circuit 500.

[0053] The signal conversion circuit 2 includes a logic circuit 31, a positive signal generation circuit 32, and a negative signal generation circuit 33.

[0054] The logic circuit 31 uses a logic circuit to generate the in-phase signal 12A and the inverted-phase signal 12B thereof based on the gate control signal 11 from the control substrate 1.

[0055] ​​​The positive signal generating circuit 32 is formed by a pair of transistors Q1, Q2 connected in push-pull, which are connected to a positive power supply of 5 V and a first ground terminal GND1 via resistive elements R3, R4, respectively. In addition, the pair of transistors Q1, Q2 are connected in parallel with diodes oriented in opposite directions. The transistors Q1 and Q2 are formed by, for example, PMOSFET and NMOSFET, and the in-phase signal 12A from the logic circuit 31 is input to their gates via a resistive element Rl. Thus, the positive signal generating circuit 32 outputs a positive signal in which the in-phase signal 12A is amplified from the connection point of the transistors Q1 and Q2.

[0056] The negative signal generating circuit 33 is formed by a pair of transistors Q3, Q4 connected in push-pull, which are connected to a positive power supply of 5 V and a first ground terminal GND1 via resistive elements R5, R6, respectively. The pair of transistors Q3, Q4 are connected in parallel with diodes oriented in opposite directions. The transistors Q3 and Q4 are formed by, for example, PMOSFET and NMOSFET, and the anti-phase signal 12B from the logic circuit 31 is input to their gates via a resistive element R2. Thus, the negative signal generating circuit 33 outputs a negative signal in which the anti-phase signal 12B is amplified from the connection point of the transistors Q3 and Q4.

[0057] The first pulse transformer 3 has a primary winding and a secondary winding which are electrically insulated from each other and have neutral points MP1, MP2, respectively. The neutral point MP1 of the primary winding is connected to the first ground terminal GND1. The first end EP1 of the primary winding is connected to the connection point of the transistors Q1 and Q2 of the positive signal generating circuit 32, and the first end EP1 is input with the positive signal 21A. The second end EP2 of the primary winding is connected to the connection point of the transistors Q3 and Q4 of the negative signal generating circuit 33, and the second end EP2 is input with the negative signal 21B.

[0058] The second pulse transformer 5 has a primary winding and a secondary winding which are electrically insulated from each other and have neutral points MP3, MP4, respectively. The first end EP5, the second end EP6, and the neutral point MP3 of the primary winding are connected to the first end EP3, the second end EP4, and the neutral point MP2 of the secondary winding of the first pulse transformer 3 via the transmission cable 4, respectively.

[0059] The input differential voltage generating circuit 6 includes a pair of resistance elements R9, R10 connected in series with each other. The pair of resistance elements R9, R10 have appropriate resistance values equal to each other. In addition, from the viewpoint of completely canceling common mode noise, it is preferable that the resistance values of the pair of resistance elements R9, R10 be equal to each other. However, the resistance values of the pair of resistance elements R9, R10 can also be unequal to each other. In this case, although cancellation is not complete, it is possible to reduce common mode noise. The high potential side end, the low potential side end, and the connection point N1 of the pair of resistance elements R9, R10 are connected to the first end EP7, the second end EP8, and the neutral point MP4 of the secondary winding of the second pulse transformer 5, respectively. Thereby, a pair of input differential voltages 22A, 22B with the potential of the connection point N1 as a reference is generated across the pair of resistance elements R9, R10.

[0060] The first differential amplifier circuit 7 includes a pair of transistors Q5, Q6 as amplifying elements. One transistor Q5 is connected to the positive power supply VCC via a transistor Q7 and a resistance element R19, and is connected to the negative power supply VEE via a common resistance element R21. The other transistor Q6 is connected to the positive power supply VCC via a transistor Q8 and a resistance element R20, and is connected to the negative power supply VEE via the common resistance element R21. The pair of transistors Q5, Q6 is constituted by, for example, npn type bipolar transistors. The base of the transistor Q5 is connected to the high potential side end of the pair of resistance elements R9, R10 via a base resistance element R17, and the base of the transistor Q5 is input with the input differential voltage 22A (high potential side differential voltage). The base of the transistor Q6 is connected to the low potential side end of the pair of resistance elements R9, R10 via a base resistance element R18, and the base of the transistor Q6 is input with the input differential voltage 22B (low potential side differential voltage).

[0061] Further, in the gate drive circuit 100, a circuit that resistance-divides the voltage between the positive power supply VCC and the negative power supply VEE is formed. In this circuit, for example, four resistance elements R11 to R14 are connected in series between the positive power supply VCC and the negative power supply VEE, the resistance element R11 and the resistance element 14 have resistance values equal to each other, and the resistance element R12 and the resistance element R13 have resistance values equal to each other. Thereby, the connection point N2 of the resistance element R12 and the resistance element R13 has a potential intermediate between the positive power supply VCC and the negative power supply VEE, and the connection point N2 is connected to the connection point N1 of the input differential voltage generating circuit 6. Thereby, the potential of the connection point N1 is fixed by the positive power supply VCC and the negative power supply VEE, but this structure can also be omitted.

[0062] The bases of the transistors Q7, Q8 are connected to the connection point of the resistance element R11 and the resistance element R12, and the resistance values of these resistance elements R11, R12 can be appropriately selected so that the transistors Q7, Q8 have a prescribed high resistance value.

[0063] With the above structure, the first differential amplification circuit 7 differentially amplifies the pair of input differential voltages 22A, 22B and outputs a pair of first output differential voltages 23A, 23B to the connection point N3 and the connection point N4, respectively.

[0064] The second differential amplification circuit 8 includes a pair of transistors Q9, Q10 as amplifying elements. One of the transistors Q9 is connected to the positive power supply VCC via a common resistance element R22 and to the negative power supply VEE via a transistor Q11 and a resistance element R23. The other of the transistors Q10 is connected to the positive power supply VCC via the common resistance element R22 and to the negative power supply VEE via a transistor Q12 and a resistance element R24. The pair of transistors Q9, Q10 is constituted by, for example, pnp type bipolar transistors. The base of the transistor Q9 is connected to the end of the high potential side of the pair of resistance elements R9, R10 via a base resistance element R16, and the base of the transistor Q9 is input with the input differential voltage 22A (high potential side differential voltage). The base of the transistor Q10 is connected to the end of the low potential side of the pair of resistance elements R9, R10 via a base resistance element R15, and the base of the transistor Q9 is input with the input differential voltage 22B (low potential side differential voltage).

[0065] The bases of the transistors Q11, Q12 are connected to the connection point of the resistance element R13 and the resistance element R14, and the resistance values of these resistance elements R13, R14 can be appropriately selected so that the transistors Q11, Q12 have a prescribed high resistance value.

[0066] With the above structure, the second differential amplification circuit 8 differentially amplifies the pair of input differential voltages 22A, 22B and outputs a pair of second output differential voltages 24A, 24B to the connection point N5 and the connection point N6, respectively.

[0067] The first gate drive signal generating circuit 9 is constituted by a waveform shaping circuit of a rectangular wave. As the waveform shaping circuit, for example, an RS flip-flop as a logic circuit is used. The RS flip-flop operates with a prescribed high potential as a reference. In the RS flip-flop, for example, the set input terminal is connected to the connection point N3 via a resistance element R25, the reset input terminal is connected to the connection point N4 via a resistance element R26, and the set output terminal is connected to the gate of the first switching element 61. The set input terminal and the reset input terminal are input with a pair of first output differential voltages 23A, 23B constituted by single-ended signals of opposite phases to each other, and thus a single-ended signal of the same phase as the first output differential voltage 23A is output from the set output terminal. The first gate drive signal generating circuit 9 outputs the single-ended signal as a first gate drive signal 25A to the first switching element 61.

[0068] The 2nd gate drive signal generating circuit 10 is constituted by a waveform shaping circuit of a rectangular wave. As the waveform shaping circuit, for example, an RS flip-flop as a logic circuit is used. The RS flip-flop operates with a prescribed low potential as a reference. In the RS flip-flop, for example, a set input terminal is connected to a connection point N5 via a resistance element R28, a reset input terminal is connected to a connection point N6 via a resistance element R27, and a set output terminal is connected to a gate of the 2nd switching element 62. The set input terminal and the reset input terminal are inputted with a pair of 2nd output difference voltages 24A, 24B constituted by single-end signals of phases opposite to each other, and thus a single-end signal of the same phase as the 2nd output difference voltage 24A is outputted from the set output terminal. The 2nd gate drive signal generating circuit 10 outputs the single-end signal as the 2nd gate drive signal 25B to the 2nd switching element 62.

[0069] In addition, as the above-described waveform shaping circuit, other rectangular wave shaping circuits can be used.

[0070] [Operation of the gate drive circuit 100]

[0071] Next, the operation of the gate drive circuit 100 constituted as described above will be described with reference to Figure 3 and Figures 4A to 4C Figure 4A is a waveform chart showing the waveform of the differential signal 21 to which common mode noise is superimposed. Figure 4A The upper waveform chart of Figure 4A The lower waveform chart of Figure 4B is a waveform chart showing the waveform of the differential signal 21 induced in the 1st pulse transformer 3 from the differential signal 21 of Figure 4A Figure 4C is a waveform chart showing the waveforms of the input difference voltages 22A, 22B generated by the input difference voltage generating circuit 6 from the signal of the differential signal 21 induced in the 1st pulse transformer 3 from Figure 4B

[0072] With reference to Figure 3 , the logic circuit 31 generates the in-phase signal 12A and the anti-phase signal 12B in accordance with the gate control signal 11 from the control substrate 1. The positive signal generating circuit 32 outputs the positive signal 21A amplified from the in-phase signal 12A. The negative signal generating circuit 33 outputs the negative signal 21B amplified from the anti-phase signal 12B. The positive signal 21A and the negative signal 21B are inputted to the 1st end EP1 and the 2nd end EP2 of the primary winding of the 1st pulse transformer 3, respectively.

[0073] With reference to Figure 4A ​​​Here, the positive signal 21A and the negative signal 21B are both binary single-ended signals of which a high level of a positive voltage (5 V) and a low level of a zero voltage (a potential of the first ground terminal GND1, 0 V) are taken, and have phases opposite to each other. At time tO, the first end EP1 and the second end EP2 of the primary winding are input with the positive signal 21A and the negative signal 21B, respectively.

[0074] In the first half cycle of the positive signal 21A and the negative signal 21B, when it becomes time tO, in the primary winding of the first pulse transformer, the first end EP1 is applied with the positive voltage of the positive signal 21A, and the second end EP2 is applied with the zero voltage of the negative signal 21B, so the excitation current flows from the first end EP1 toward the neutral point MP1. Referring to Figure 4B Thus, in the primary winding of the first pulse transformer 3, a voltage from the second end EP2 toward the first end EP1 is induced. In this case, since the potential of the neutral point MP1 of the primary winding is 0 V, the voltage VI of the first end EP1 becomes a positive voltage. On the other hand, the second end EP2 is connected to the first ground terminal GND1 via the resistance element R8 at this time tO, so the voltage V2 of the second end EP2 becomes a negative voltage, and a current flows from the neutral point MP1 toward the second end EP2. Also, at this time, by the above excitation current, voltages corresponding to the turns ratio of the first pulse transformer 3 and the second pulse transformer 5 are induced in the secondary winding of the first pulse transformer 3 and the primary winding and the secondary winding of the second pulse transformer 5.

[0075] In the next half cycle of the positive signal 21A and the negative signal 21B, when it becomes time tl, contrary to the above, in the primary winding of the first pulse transformer 3, the first end EP1 is applied with the zero voltage of the positive signal 21A, and the second end EP2 is applied with the positive voltage of the negative signal 21B, so the excitation current flows from the second end EP2 toward the neutral point MP1. Thus, in the primary winding of the first pulse transformer 3, a voltage from the first end EP1 toward the second end EP2 is induced. In this case, since the potential of the neutral point MP1 of the primary winding is 0 V, the voltage V2 of the second end EP2 becomes a positive voltage. On the other hand, the first end EP1 is connected to the first ground terminal GND1 via the resistance element R7 at this time tl, so the voltage VI of the first end EP1 becomes a negative voltage, and a current flows from the neutral point MP1 toward the first end EP1. Also, at this time, by the above excitation current, voltages corresponding to the turns ratio of the first pulse transformer 3 and the second pulse transformer 5 are induced in the secondary winding of the first pulse transformer 3 and the primary winding and the secondary winding of the second pulse transformer 5. After that (t2, t3,...), the above one cycle is repeated.

[0076] Thus, the positive signal 21A and the negative signal 21B, which have the voltage VI and the voltage V2 having 2 times the amplitude, respectively, are converted into a pair of single-ended voltage signals having phases opposite to each other (positive and negative opposite) in the 1st pulse transformer 3, and are transmitted to the secondary winding of the 2nd pulse transformer 5 via the transmission cable 4.

[0077] Here, the removing effect of the common mode noise on the input side of the gate drive circuit 100 will be described. Referring to Figure 4A , for example, assume that the common mode noise is superimposed on the positive signal 21A and the negative signal 21B, respectively, between the time to and the time tl. Referring to Figure 3 , the common mode noise superimposed on the positive signal 21A causes the excitation current to flow between the 1st end EP1 of the primary winding of the 1st pulse transformer 3 and the neutral point MP1, and the common mode noise superimposed on the negative signal 21B causes the excitation current to flow between the 2nd end EP2 of the primary winding of the 1st pulse transformer 3 and the neutral point MP1. However, as shown in Figure 4B , both of the excitation currents are currents having opposite directions to each other, and thus a voltage having positive and negative opposite to each other is induced in the primary winding, and the both cancel each other. Thus, the common mode noise superimposed on the positive signal 21A and the negative signal 21B is removed from the pair of single-ended voltage signals converted from the positive signal 21A and the negative signal 21B by the 1st pulse transformer 3. In addition, the common mode noise superimposed on the transmission cable 4 is also removed from the pair of single-ended voltage signals by the same effect as described above in the 2nd pulse transformer 5.

[0078] Referring to Figure 3 , in the input differential voltage generating circuit 6, the input differential voltages 22A and 22B are generated from the pair of single-ended voltage signals transmitted to the secondary winding of the 2nd pulse transformer 5 as follows. Referring to Figure 4C , a single-ended voltage signal corresponding to the voltage VI of Figure 4B appears at the end of the high potential side of the resistive element R9, but the voltage of the middle of the amplitude of the single-ended voltage signal becomes zero voltage of the low level when the connection point N2 is taken as a reference, and thus becomes a single-ended voltage signal having the waveform as shown in the upper stage of Figure 4C . On the other hand, a single-ended voltage signal corresponding to the voltage V2 of Figure 4B appears at the end of the low potential side of the resistive element R10, but the voltage of the middle of the amplitude of the single-ended voltage signal becomes zero voltage of the low level when the connection point N2 is taken as a reference, and thus becomes a single-ended voltage signal having the waveform as shown in the lower stage of Figure 4C . Thus, the pair of input differential voltages 22A and 22B have waveforms corresponding to the positive signal 21A and the negative signal 21B of Figure 4A , respectively.

[0079] Further, in the input differential voltage generating circuit 6, a pair of resistive elements R9, R10 flows the load current of the second pulse transformer 5, and thus a corresponding load current flows in the first pulse transformer 3. In Figure 3 The current of the transmission path of the differential signal 21 when the positive signal 21A is high is shown in FIG. 9. As a result, the impedance of the first pulse transformer 3 and the second pulse transformer 5 becomes low, a large current can flow in the transmission path of the differential signal 21 including the first pulse transformer 3, the transmission cable 4, and the second pulse transformer 5, and thus the removal ability of the common mode noise at the input side of the gate drive circuit 100 can be improved.

[0080] Referring to Figure 3 In a case where the common mode noise is superimposed on a pair of wirings from the secondary winding of the second pulse transformer 5 to the first and second differential amplification circuits 7, 8, the common mode noise of the pair of wirings is opposite in polarity to each other in a pair of input differential voltages 22A, 22B generated by the input differential voltage generating circuit 6. The first and second differential amplification circuits 7, 8 differentially amplify the pair of input differential voltages 22A, 22B, and thus the superimposed common mode noise can be removed.

[0081] Further, there is a case where the timing of inputting the pair of input differential voltages 22A, 22B to the first and second differential amplification circuits 7, 8, respectively, is slightly shifted from each other due to the manner of the wirings from the secondary winding of the second pulse transformer 5 to the first and second differential amplification circuits 7, 8. In a case where the first and second differential amplification circuits 7, 8 operate at high speed, the common mode noise is not completely removed due to the slight shift of the timing. However, since the first and second gate drive signal generating circuits 9, 10 are constituted by the waveform shaping circuits, the waveforms of a pair of first output differential voltages 23A, 23B and a pair of second output differential voltages 24A, 24B output from the first and second differential amplification circuits 7, 8, respectively, are shaped, and thus the remaining components of the common mode noise can be removed from the pair of first output differential voltages 23A, 23B and the pair of second output differential voltages 24A, 24B. In particular, when the waveform shaping circuits are flip-flops, the noise in which the common mode noise is converted to a normal mode in the preceding stage circuit can be appropriately removed. In this way, the common mode noise is removed at the output side of the gate drive circuit 100.

[0082] [Mounting to a substrate]

[0083] Referring to Figure 3In the push-pull amplification circuit 500, the signal conversion circuit 2 and the first pulse transformer 3 are mounted on the first substrate 81, and the second pulse transformer 5, the input differential voltage generation circuit 6, the first differential amplification circuit 7, the second differential amplification circuit 8, the first gate drive signal generation circuit 9, the second gate drive signal generation circuit 10, and the pair of switching elements 60 are mounted on the second substrate 82. Further, the secondary winding of the first pulse transformer 3 of the first substrate 81 and the primary winding of the second pulse transformer 5 of the second substrate 82 are connected by the transmission cable 4.

[0084] Therefore, by arranging the second substrate 82 in the vicinity of the switching module 800 (refer to Figure 5 ) driven by the pair of switching elements 60, for example, and extending the transmission cable 4, the first substrate 81 is arranged in the vicinity of the control substrate 1 away from the switching module 800, whereby the computer constituting the control substrate 1 can be appropriately protected from the common mode noise generated due to the switching operation of the switching module 800.

[0085] [Application to switching power supply device]

[0086] Figure 5 is a circuit diagram showing the operation of the switching power supply device 1000 using the Figure 3 push-pull amplification circuit 500. In Figure 3 , the reference numerals of the elements of the detailed parts are omitted for easy observation of the drawing.

[0087] Referring to Figure 5 , the switching power supply device 1000 includes the switching module 800 and the first and second push-pull amplification circuits 500A, 500B. The switching module 800 includes a high-side switching element SWH and a low-side switching element SWL. The high-side switching element SWH and the low-side switching element SWL are constituted by IGBTs, for example. Further, the high-side switching element SWH and the low-side switching element SWL are connected in parallel with reverse diodes, respectively.

[0088] The first push-pull amplification circuit 500A includes the first gate drive circuit 100A and the first pair of switching elements 60A. The second push-pull amplification circuit 500B includes the second gate drive circuit 100B and the second pair of switching elements 60B.

[0089] The high-side switching element SWH is connected to the first pair of switching elements 60A of the first push-pull amplifier circuit 500A, and the gate of the high-side switching element SWH is input to the output of the first pair of switching elements 60A. The low-side switching element SWL is connected to the second pair of switching elements 60B of the second push-pull amplifier circuit 500B, and the gate of the low-side switching element SWL is input to the output of the second pair of switching elements 60B. Furthermore, the control board 1 and the signal conversion circuit 2 of the first and second gate drive circuits 100A and 100B are grounded. The first pair of switching elements 60A is connected to the frame ground terminal, and the second pair of switching elements 60B is connected to the signal ground terminal.

[0090] In the switching power supply device 1000 configured in this way, a high-side gate control signal 11A is input from the control board 1 to the logic circuit 31 of the first gate drive circuit 100A. As a result, first and second gate drive signals are generated in the first gate drive circuit 100A, thereby outputting a high-side gate drive signal 26A from the first pair of switching elements 60A to the gate of the high-side switching element SWH. On the other hand, a low-side gate control signal 11B is input from the control board 1 to the logic circuit 31 of the second gate drive circuit 100B. As a result, first and second gate drive signals are generated by the second gate drive circuit 100B, thereby outputting a low-side gate drive signal 26B from the second pair of switching elements 60B to the gate of the low-side switching element SWL. Here, as... Figure 5 As shown, the phases of the high-side gate control signal 11A and the low-side gate control signal 11B are staggered.

[0091] Therefore, the high-side switching element SWH and the low-side switching element SWL perform switching on / off actions at different times, and the control power of the switching module 800 is output from the connection point Nout of the high-side switching element SWH and the low-side switching element SWL.

[0092] However, by switching the high-side switching element SWH and the low-side switching element SWL on and off respectively, the voltage (potential) Vm at connection point Nout changes. This change in voltage Vm at connection point Nout generates… Figure 6 The switching noise shown is as described. Figure 6 It is shown Figure 5 A schematic diagram of the switching noise generated by the 800 switching module. Figure 6 In this diagram, Vm1 represents the voltage fluctuation at connection point Nout when the high-side switching element SWH is open and the low-side switching element SWL is closed, and Vm2 represents the voltage fluctuation at connection point Nout when the high-side switching element SWH is closed and the low-side switching element SWL is open. Voltage fluctuations Vm1 and Vm2 occur at different times, but... Figure 6 For convenience, this is represented as occurring at the same time. Additionally,Figure 6 It is generated by tracking the waveform image of the actual voltage, so its waveform is not accurate.

[0093] When generated Figure 6 When the voltage Vm (Vm1, Vm2) at the connection point Nout as shown varies, switching noise is radiated from the connection point Nout. This switching noise is then superimposed as common-mode noise on the wiring of the first and second gate drive circuits 100A and 100B. However, as described above, the common-mode noise superimposed on the wiring of the first and second gate drive circuits 100A and 100B is removed.

[0094] As explained above, the gate drive circuit 100 according to this disclosure can remove common-mode noise superimposed on the output side and the input side. Furthermore, it can appropriately protect the computer constituting the control board 1 from the common-mode noise generated by the switching operation of the switching module 800.

[0095] Based on the above description, many modifications and other implementations will be apparent to those skilled in the art. Therefore, the above description should be interpreted as illustrative only.

[0096] Industrial availability

[0097] The gate drive circuit of the present invention is useful as a gate drive circuit capable of removing common-mode noise superimposed on the output side and the input side.

[0098] Label Explanation

[0099] 1: Control board; 2: Signal conversion circuit; 3: First pulse transformer; 4: Transmission cable; 5: Second pulse transformer; 6: Input differential voltage generation circuit; 7: First differential amplifier circuit; 8: Second differential amplifier circuit; 9: First gate drive signal generation circuit; 10: Second gate drive signal generation circuit; 11: Gate control signal; 12A: In-phase signal; 12B: Out-of-phase signal; 21: Differential signal; 21A: Positive signal; 21B: Negative signal; 22A, 22B: Input differential voltage; 23A, 23B: First output differential voltage; 24A, 24B: 25A: 1st gate drive signal; 25B: 2nd gate drive signal; 26A: High-side gate drive signal; 26B: Low-side gate drive signal; 31: Logic circuit; 32: Positive signal generation circuit; 33: Negative signal generation circuit; 60: A pair of switching elements; 61: 1st switching element; 62: 2nd switching element; 81: 1st substrate; 82: 2nd substrate; 100: Gate drive circuit; 500: Push-pull amplifier circuit; 800: Switching module; 1000: Switching power supply device; GND1: 1st ground terminal; GND2: 2nd ground terminal.

Claims

1. A gate driving circuit, comprising: The signal conversion circuit operates with the potential of the first ground terminal as a reference potential, converting the gate control signal, which is a single-ended signal, into a differential signal. The differential signal is composed of the signal level difference between each other and the positive and negative signals corresponding to the gate control signal. The first pulse transformer has a primary winding and a secondary winding that are electrically insulated from each other and each have a neutral point. The neutral point of the primary winding is set to the potential of the first ground terminal, and the two ends of the primary winding are respectively input with a positive signal and a negative signal of the differential signal. An input differential voltage generating circuit has a pair of resistive elements connected in series with each other. The two ends and the connection point of the pair of resistive elements are directly electrically connected to the two ends of the secondary winding of the first pulse transformer and the neutral point, respectively, or connected to the two ends of the secondary winding of the first pulse transformer and the neutral point via a transmission cable and a second pulse transformer, respectively, to generate a pair of input differential voltages based on the potential of the connection point across the pair of resistive elements. A differential amplifier circuit, which is electrically connected to the input differential voltage generation circuit, differentially amplifies the pair of input differential voltages to output a pair of output differential voltages; as well as A gate drive signal generation circuit, which is electrically connected to the differential amplifier circuit, generates a gate drive signal as a single-ended signal based on a specified potential according to the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates based on the potential of the second ground terminal.

2. The gate driving circuit according to claim 1, wherein, The second pulse transformer has a primary winding and a secondary winding that are electrically insulated from each other and each have a neutral point. The two ends of the primary winding and the neutral point of the second pulse transformer are electrically connected to the two ends of the secondary winding and the neutral point of the first pulse transformer via the transmission cable. The two ends of the pair of resistive elements and the connection point of the input differential voltage generation circuit are respectively connected to the two ends of the secondary winding and the neutral point of the second pulse transformer.

3. The gate driving circuit according to claim 1 or 2, wherein, The two switching elements constitute a first switching element and a second switching element connected in a push-pull configuration. The gate drive circuit includes a first differential amplifier circuit and a second differential amplifier circuit as the differential amplifier circuit. The gate driving circuit includes a first gate driving signal generation circuit and a second gate driving signal generation circuit as the gate driving signal generation circuit. The first differential amplifier circuit is electrically connected to the input differential voltage generation circuit, and differentially amplifies the pair of input differential voltages to output a pair of first output differential voltages at a high potential. The second differential amplifier circuit is electrically connected to the input differential voltage generation circuit, and differentially amplifies the pair of input differential voltages to output a pair of second output differential voltages that are at a lower potential than the pair of first output differential voltages. The first gate drive signal generation circuit is electrically connected to the first differential amplifier circuit, generates a first gate drive signal with a positive potential as a reference based on the pair of first output difference voltages, and outputs the first gate drive signal to the first switching element. The second gate drive signal generation circuit is as follows: it is electrically connected to the second differential amplifier circuit, generates a second gate drive signal with a negative potential as a reference based on the pair of second output differential voltages, and outputs the second gate drive signal to the second switching element.

4. The gate drive circuit according to any one of claims 1 to 3, wherein, The gate drive signal generation circuit is a circuit that includes a flip-flop that is input to the pair of output differential voltages and outputs a single-ended signal based on a specified potential. The gate drive signal generation circuit outputs this single-ended signal as the gate drive signal.

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