Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device provided with a semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate being provided with a diode section, the diode section having a first cathode region of a first conductivity type and a second cathode region of a second conductivity type, the first cathode region and the second cathode region being provided so as to overlap in a first direction, and the first cathode region and the second cathode region being provided so as to overlap in a second direction. The repetition pitch of the first cathode region and the second cathode region in the first direction is 40 [mu] m or more and 200 [mu] m or less, and the area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] Conventionally, as a cathode region of a diode, a structure in which regions of N type and P type are mixed is known (for example, refer to Patent Documents 1 and 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-091857 Patent Document 2: Japanese Patent Application Publication No. 2022-015861 SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION In a semiconductor device, it is preferable to arrange cathode regions of N type and P type to have predetermined characteristics.

[0005] SOLUTION TO THE PROBLEM To solve the above problem, in a first aspect of the present application, there is provided a semiconductor device provided with a semiconductor substrate having an upper surface and a lower surface, and a diode portion provided in the semiconductor substrate. In the above semiconductor device, the diode portion can have a drift region of a first conductivity type provided in the semiconductor substrate. In any of the above semiconductor devices, the diode portion can have a first cathode region of the first conductivity type provided so as to be in contact with the lower surface of the semiconductor substrate, and having a higher doping concentration than the doping concentration of the drift region. In any of the above semiconductor devices, the diode portion can have a second cathode region of a second conductivity type provided so as to be in contact with the lower surface of the semiconductor substrate. Any of the above semiconductor devices can be such that the first cathode region and the second cathode region are repeatedly provided in a first direction, and the repeat pitch of the first cathode region and the second cathode region in the first direction is 40 μm or more and 200 μm or less. Any of the above semiconductor devices can be such that the area ratio of the second cathode region with respect to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

[0006] In any of the above semiconductor devices, the repeat pitch can be 80 μm or more and 160 μm or less.

[0007] In any of the above semiconductor devices, the area ratio can be 0.6 or less.

[0008] In any of the above semiconductor devices, the first cathode region and the second cathode region can each have a long side in a long side direction different from the first direction. In any of the above semiconductor devices, the area ratio can be 0.5 or less.

[0009] In any of the semiconductor devices described above, the first cathode region and the second cathode region can be repeatedly arranged in a second direction different from the first direction. In any of the semiconductor devices described above, the area ratio can be 0.6 or less.

[0010] In any of the semiconductor devices described above, the repeat pitch can be 100 μm or more and 130 μm or less.

[0011] In any of the semiconductor devices described above, the repeat pitch can be 40 μm or more and 80 μm or less.

[0012] In any of the semiconductor devices described above, the diode portion can have an anode region of the second conductivity type disposed so as to be in contact with the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the dose of dopant ions of the anode region can be 5.0 x 1011 / cm2or more and 5.0 x 1013 / cm2or less. 12 / cm2 2 / cm2 13 / cm2 2 / cm2or more and 5.0 x 1013 / cm2or less.

[0013] In any of the semiconductor devices described above, the dose of dopant ions of the second cathode region can be 1.0 x 1011 / cm2or more and 1.0 x 1013 / cm2or less. 13 / cm2 2 / cm2 14 / cm2 2 / cm2or more and 1.0 x 1013 / cm2or less.

[0014] In any of the semiconductor devices described above, a transistor portion can be provided in the semiconductor substrate so as to be connected in anti-parallel with the diode portion.

[0015] In any of the semiconductor devices described above, the transistor portion can have a collector region of the second conductivity type disposed so as to be in contact with the lower surface of the semiconductor substrate, and in any of the semiconductor devices described above, the doping concentration of the second cathode region and the doping concentration of the collector region can be the same.

[0016] In any of the semiconductor devices described above, the diode portion can have an anode region of the second conductivity type disposed so as to be in contact with the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the transistor portion can have an emitter region of the first conductivity type disposed so as to be in contact with the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the transistor portion can have the drift region. In any of the semiconductor devices described above, the transistor portion can have a base region of the second conductivity type disposed between the emitter region and the drift region. In any of the semiconductor devices described above, the doping concentration of the anode region and the doping concentration of the base region can be the same.

[0017] ​​​​​​In any of the above-described semiconductor devices, the carrier lifetime in the drift region of the diode portion can be 1 μs or more.

[0018] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising a semiconductor substrate having an upper surface and a lower surface and a drift region having a first conductivity type, and a diode portion disposed on the semiconductor substrate. In this manufacturing method, a first cathode region of the first conductivity type and a second cathode region of the second conductivity type can be formed. The first cathode region of the first conductivity type is disposed in contact with the lower surface of the semiconductor substrate and has a higher doping concentration than the drift region. The second cathode region of the second conductivity type is disposed in contact with the lower surface of the semiconductor substrate. In any of the above manufacturing methods, in the formation of the first cathode region and the second cathode region, the first cathode region and the second cathode region are repeatedly disposed in a first direction, and the repeating spacing of the first cathode region and the second cathode region in the first direction can be 40 μm or more and 200 μm or less. In any of the above manufacturing methods, in the formation of the first cathode region and the second cathode region, the area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region can be 0.1 or more and 0.8 or less.

[0019] In any of the above manufacturing methods, the semiconductor device may have a transistor portion disposed on the semiconductor substrate and connected in reverse parallel with the diode portion. In any of the above manufacturing methods, the transistor portion may have a collector region of a second conductivity type disposed in contact with the lower surface of the semiconductor substrate. In any of the above manufacturing methods, the collector region may be formed using a process common to the second cathode region.

[0020] In any of the above manufacturing methods, the semiconductor device may have a transistor portion disposed on the semiconductor substrate and connected in reverse parallel with the diode portion. In any of the above manufacturing methods, the diode portion may have an anode region of a second conductivity type disposed in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the transistor portion may have an emitter region of a first conductivity type disposed in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the transistor portion may have the drift region. In any of the above manufacturing methods, the transistor portion may have a base region of a second conductivity type disposed between the emitter region and the drift region. In any of the above manufacturing methods, the anode region and the base region can be formed using a common process.

[0021] In any of the above manufacturing methods, the diode portion may have an anode region of a second conductivity type disposed in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, an initial value for the design doping concentration of the anode region can be set. In any of the above manufacturing methods, the forward voltage-reverse recovery loss characteristics of the diode portion using the initial value can be obtained for a plurality of repeating intervals. In any of the above manufacturing methods, the design value for the doping concentration of the anode region can be adjusted based on a plurality of forward voltage-reverse recovery loss characteristics for a plurality of repeating intervals.

[0022] The above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute other inventions. Attached Figure Description

[0023] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0024] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0025] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0026] Figure 4A This is a diagram showing an example of the configuration of the first cathode region 81 and the second cathode region 82 at the lower surface 23 of the semiconductor substrate 10.

[0027] Figure 4B This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0028] Figure 4C This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0029] Figure 5A This is a diagram showing another configuration example of the first cathode region 81 and the second cathode region 82 in a diode section 80.

[0030] Figure 5B This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0031] Figure 5C This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0032] Figure 6AThis is a diagram showing another configuration example of the first cathode region 81 and the second cathode region 82 in a diode section 80.

[0033] Figure 6B This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0034] Figure 6C This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83.

[0035] Figure 7 This is a graph showing the relationship between the area ratio R and the forward voltage of the diode section 80.

[0036] Figure 8 This is a graph showing the relationship between forward voltage and reverse recovery loss relative to the area ratio R.

[0037] Figure 9 This is a graph showing the relationship between the forward voltage and the reverse recovery loss relative to the length Y2 in the first direction of the second cathode region 82.

[0038] Figure 10 This shows the relationship between the magnitude of the positive voltage deviation caused by patterning deviations in the manufacturing process and the area ratio R.

[0039] Figure 11 The relationship between the magnitude of the deviation in positive voltage caused by patterning deviations in the manufacturing process and the length Y2 of the second cathode region 82 is shown.

[0040] Figure 12 The relationship between the magnitude of the forward voltage deviation and the area ratio R is shown when the patterning deviation is set to ±0.2 μm.

[0041] Figure 13 The relationship between the magnitude of the forward voltage deviation and the length Y2 of the second cathode region 82 is shown when the patterning deviation is set to ±0.2 μm.

[0042] Figure 14 This is a graph showing another example of the relationship between the area ratio R and the forward voltage of the diode section 80.

[0043] Figure 15 This is a diagram showing the anode voltage-anode current characteristics of the diode section 80.

[0044] Figure 16 This is a diagram showing another example of the anode voltage-anode current characteristics of diode section 80.

[0045] Figure 17 This is a graph showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage.

[0046] Figure 18 This is a graph showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage.

[0047] Figure 19 This is a diagram illustrating the manufacturing method of the semiconductor device 100.

[0048] Figure 20 This is a diagram illustrating an example of design step S1002.

[0049] Symbol Explanation 10. Semiconductor substrate, 11. Well region, 12. Emitter region, 14. Base region, 15. Contact region, 16. Accumulation region, 18. Drift region, 20. Buffer zone, 21. Upper surface, 22. Collector region, 23. Lower surface, 24. Collector electrode, 29. Straight portion, 30. Dummy trench portion, 31. Front end portion, 32. Dummy insulating film, 34. Dummy conductive portion, 38. Interlayer insulating film, 39. Straight portion, 40. Gate trench portion, 41. Front end portion, 42. Gate insulating film, 44. Gate conductive portion Electrical section, 52···Emitter electrode, 54···Contact hole, 60, 61···Mesa section, 70···Transistor section, 80···Diode section, 81···First cathode region, 82···Second cathode region, 83···Cathode region, 84···Marginal region, 85···Repetitive structure, 90···Boundary, 91···Chamfered section, 100···Semiconductor device, 130···Outer periphery gate wiring, 131···Active side gate wiring, 150···Edge termination structure section, 160···Active section, 162···End edge, 164···Gate pad, 302···Characteristics, 304···Characteristic group Detailed Implementation

[0050] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0051] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the actual direction in which the semiconductor device is mounted.

[0052] In this specification, rectangular coordinate axes, namely the X-axis, Y-axis, and Z-axis, are sometimes used to illustrate technical matters. Rectangular coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the direction of height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0053] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0054] Sometimes the region extending from the center of the semiconductor substrate along its depth direction to the top surface of the semiconductor substrate is called the top surface side. Similarly, sometimes the region extending from the center of the semiconductor substrate along its depth direction to the bottom surface of the semiconductor substrate is called the bottom surface side.

[0055] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0056] In this specification, the conductivity type of the doped region containing impurities is described as P-type or N-type. In this specification, impurity sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to introducing a donor or acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0057] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the polarities of the charges, with the donor concentration set to the concentration of positive ions and the acceptor concentration set to the concentration of negative ions. For example, if the donor concentration is set to N... D And set the acceptor concentration to N A Then the actual net doping concentration at any position becomes N. D -N A In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0058] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of taking electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron-supplying donors. Hydrogen donors can be donors that combine at least vacancies (V) and hydrogen (H). Alternatively, interlattice Si-H, formed by the combination of interlattice silicon (Si-i) and hydrogen in a silicon semiconductor, and CiOi-H, formed by the combination of interlattice carbon (Ci), interlattice oxygen (Oi), and hydrogen, also function as electron-supplying donors. In this specification, VOH defects, CiOi-H, or interlattice Si-H are sometimes referred to as hydrogen donors.

[0059] In this specification, the semiconductor substrate is integrally distributed with N-type body donors. Body donors are donors formed by dopants that are substantially uniformly contained within the ingot during the fabrication of the ingot that forms the basis of the semiconductor substrate. In this example, the body donor is an element other than hydrogen. Although the dopants for the body donor are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, they are not limited to these. In this example, the body donor is phosphorus. The body donor is also contained within the P-type region. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip formed by monolithically combining wafers. The semiconductor ingot can be manufactured using any of the following methods: Czochralski (CZ) method, magnetic field crystal pulling (MCZ) method, and floating zone melting (FZ) method. In this example, the ingot is manufactured using the MCZ method. The substrate manufactured using the MCZ method contains an oxygen concentration of 1 × 10⁻⁶. 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured using the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 / cm 3 There is a tendency for hydrogen donors to form when oxygen concentration is high. The bulk donor concentration can be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or a value between 90% and 100% of that chemical concentration. Alternatively, an undoped substrate, free of dopants such as phosphorus, can be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the undoped substrate is, for example, 1 × 10⁻⁶. 10 / cm 3 Above and 5×10 12 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 The above. The bulk donor concentration (D0) of the undoped substrate is preferably 5 × 10⁻⁶. 12 / cm 3It should be noted that the concentrations used in this invention can be values ​​at room temperature. As an example, values ​​at room temperature can be those at 300 K (Kelvin) (approximately 26.9°C).

[0060] In this specification, "P+" or "N+" indicates a higher doping concentration than "P" or "N" type, while "P-" or "N-" indicates a lower doping concentration than "P" or "N" type. Similarly, "P++" or "N++" indicates a higher doping concentration than "P+" or "N+" type. Unless otherwise stated, the units used in this specification are SI units. Although length is sometimes expressed in cm, all calculations should be converted to meters (m) before proceeding.

[0061] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration can be measured using, for example, secondary ion mass spectrometry (SIMS). The net doping concentration can be measured using voltage-capacitance (CV) measurement. Alternatively, the carrier concentration measured using extended resistance (SR) measurement can be used as the net doping concentration. The carrier concentration measured by CV or SR can be considered as the value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is much greater than the acceptor concentration; therefore, the carrier concentration in this region can also be defined as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be defined as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0062] When the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of the donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can also be taken as the concentration of the donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atoms / cm³. 3 or / cm 3 This unit is used to indicate the concentration of donors or acceptors, or the chemical concentration, within a semiconductor substrate. The "atoms" designation can also be omitted.

[0063] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of extended resistance, within the current flow range, there are cases where the carrier mobility of the semiconductor substrate is lower than the carrier mobility value in the crystalline state. This decrease in carrier mobility is due to the dispersion of carriers caused by crystal structure disorder (disorder) caused by lattice defects, etc.

[0064] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which act as donors), or the acceptor concentration of boron (which acts as acceptor), is approximately 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which acts as a donor) is approximately 0.1% to 10% of the chemical concentration of hydrogen. The semiconductor substrate can be silicon, silicon carbide, gallium nitride, diamond, or gallium oxide.

[0065] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 The image shows the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10. Figure 1 In this paper, only a portion of the components of the semiconductor device 100 are shown, and some components are omitted.

[0066] Semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" refers to the view from the upper surface side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that are opposite each other when viewed from above. Figure 1 In the diagram, the X and Y axes are parallel to one end edge 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0067] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region between the upper and lower surfaces of the semiconductor substrate 10 where the main current flows along the depth direction when the semiconductor device 100 is operating. An emitter electrode is provided above the active portion 160, but... Figure 1 The text has been omitted. The active portion 160 can refer to the area where the emitting electrodes overlap when viewed from above. Additionally, the area held by the active portion 160 when viewed from above can also be included within the active portion 160.

[0068] The active section 160 includes a diode section 80 containing diode elements such as a freewheeling diode (FWD). The active section 160 may also include a transistor section 70 containing transistor elements such as an IGBT (Insulated Gate Bipolar Transistor). Figure 1In this example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined alignment direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conduction type IGBT (RC-IGBT). The transistor section 70 and the diode section 80 are connected in parallel in reverse order. That is, the emitter of the transistor section 70 is electrically connected to the anode of the diode section 80, and the collector of the transistor section 70 is electrically connected to the cathode of the diode section 80.

[0069] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0070] The diode section 80 has an N+ type first cathode region and a P+ type second cathode region in the area contacting the lower surface of the semiconductor substrate 10. In this specification, a repeating structure including the first and second cathode regions is periodically arranged along a predetermined direction on the lower surface of the semiconductor substrate 10. The area where the first or second cathode region is disposed is referred to as the diode section 80. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in an area other than the diode section 80.

[0071] The transistor section 70 has a P+ type collector region in the region that is in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0072] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near the edge 162. "Near the edge 162" refers to the area between edge 162 and the emitter electrode when viewed from above. When actually mounting semiconductor device 100, each pad can be connected to external circuitry via wiring such as leads.

[0073] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, a shading line is marked on the gate wiring.

[0074] The gate wiring in this example includes an outer peripheral gate wiring 130 and an active-side gate wiring 131. The outer peripheral gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 in plan view. In this example, the outer peripheral gate wiring 130 surrounds the active portion 160 in plan view. Alternatively, the area surrounded by the outer peripheral gate wiring 130 in plan view can also be designated as the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region refers to a P-type region with a higher concentration than the base region (described later), and is formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the base region. Alternatively, the area surrounded by the well region in plan view can also be designated as the active portion 160.

[0075] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum, etc.

[0076] An active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the deviation of the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0077] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 can be wiring formed from semiconductors such as polysilicon doped with impurities.

[0078] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 is provided to cross the active portion 160 in the X-axis direction, approximately at the center of the Y-axis, from the outer peripheral gate wiring 130 on one side that holds the active portion 160 to the outer peripheral gate wiring 130 on the other side. When the active portion 160 is divided using the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0079] The semiconductor device 100 may include: a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like; and a current sensing unit (not shown) which simulates the operation of the transistor unit disposed in the active unit 160.

[0080] Viewed from above, the semiconductor device 100 of this example has an edge termination structure 150 between the active portion 160 and the edge 162. In this example, the edge termination structure 150 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 150 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 150 may include at least one of a protective ring surrounding the active portion 160 in an annular shape, a field plate, and a surface electric field reduction section.

[0081] Figure 2 yes Figure 1 An enlarged view of region D is shown. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0082] An interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate 10, and between the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10. Figure 2 The details are omitted. In this example, the interlayer insulating film has contact holes 54 that penetrate through it. Figure 2 In the middle, the shading of the diagonal lines marks each contact hole 54.

[0083] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Furthermore, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole disposed in the interlayer insulating film. The front end of the emitter electrode 52 in the dummy trench portion 30 in the Y-axis direction can be connected to the dummy conductive portion of the dummy trench portion 30. The dummy conductive portion of the dummy trench portion 30 may not be connected to the emitter electrode 52 and the gate conductive portion, or it may be controlled to have a potential different from that of the emitter electrode 52 and the gate conductive portion.

[0084] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at its front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0085] The emitting electrode 52 is formed of a material containing metal. Figure 2 The area where the emitter electrode 52 is disposed is shown. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 may have a barrier metal formed of titanium or titanium compounds in the lower layer of the region formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum or the like may be provided within the contact hole.

[0086] The well region 11 is disposed overlapping with the active-side gate wiring 131. The well region 11 also extends with a predetermined width in a region that does not overlap with the active-side gate wiring 131. In this example, the well region 11 is separated from the active-side gate wiring 131 by its end in the Y-axis direction relative to the contact hole 54. The well region 11 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0087] Both the transistor section 70 and the diode section 80 have multiple trench sections arranged along the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately arranged along the arrangement direction. In the diode section 80 of this example, multiple dummy trench sections 30 are arranged along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0088] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight in the extension direction) extending in an extension direction perpendicular to the arrangement direction, and a front end portion 41 connecting the two straight portions 39. Figure 2 The direction of extension in the middle is the Y-axis direction.

[0089] Preferably, at least a portion of the front end portion 41 is curved when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction to each other through the front end portion 41, the electric field concentration at the ends of the straight portions 39 can be alleviated.

[0090] In the transistor section 70, dummy trench sections 30 are provided between each straight portion 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight portion 39, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending in the extension direction, or it may have the same straight portion 29 and front end portion 31 as the gate trench section 40. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31, and a dummy trench portion 30 with a front end portion 31.

[0091] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This helps to alleviate electric field concentration at the bottom of each trench portion.

[0092] Mesa-shaped portions are provided between the trench portions in the arrangement direction. A mesa-shaped portion refers to the area within the semiconductor substrate 10 that is held between the trench portions. For example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped portion has the same depth as the lower end of the trench portion. In this example, the mesa-shaped portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa-shaped portion 60 is provided in the transistor portion 70, and a mesa-shaped portion 61 is provided in the diode portion 80. In this specification, when referred to simply as a mesa-shaped portion, the terms mesa-shaped portion 60 and mesa-shaped portion 61 are used interchangeably.

[0093] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 within the mesa, positioned closest to the active-side gate wiring 131, is designated as base region 14-e. Figure 2 Although a base region 14-e is shown disposed at one end of each stage in the extending direction, a base region 14-e is also disposed at the other end of each stage. In each stage, the area sandwiched by the base region 14-e in top view may be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0094] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is grounded to the gate trench portion 40. A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided on the mesa portion 60 that is in contact with the gate trench portion 40.

[0095] Each contact area 15 and each emission area 12 in the platform surface 60 extends from a groove portion on one side to a groove portion on the other side in the X-axis direction. As an example, the contact areas 15 and emission areas 12 of the platform surface 60 are alternately arranged along the extension direction of the groove portion (Y-axis direction).

[0096] In other examples, the contact area 15 and the emission area 12 of the platform 60 can be arranged in a strip shape along the extension direction (Y-axis direction) of the groove. For example, the emission area 12 is provided in the area that is in contact with the groove, and the contact area 15 is provided in the area that is held by the emission area 12.

[0097] The emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. On the upper surface of the mesa 61, a contact region 15 may be provided in the area sandwiched between the base regions 14-e and grounded to each base region 14-e. A base region 14 may be provided on the upper surface of the mesa 61 in the area sandwiched by the contact region 15. The base region 14 may be configured over the entire area sandwiched by the contact region 15.

[0098] A contact hole 54 is provided above each mesa. The contact hole 54 is disposed in the region sandwiched by the base region 14-e. In this example, the contact hole 54 is disposed above the contact region 15, the base region 14, and the emitter region 12. In the diode section 80, the contact region 15 may not be provided. The contact hole 54 is not disposed in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed in the center of the mesa 60 in the arrangement direction (X-axis direction).

[0099] In the diode section 80, a cathode region 83 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The cathode region 83 is a region in which an N+ type first cathode region and a P+ type second cathode region are periodically arranged. Figure 2 In this diagram, the first and second cathode regions are omitted. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in an area where the cathode region 83 is not located. The cathode region 83 and the collector region 22 are located between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. The cathode region 83 and the collector region 22 can contact the lower surface 23 of the semiconductor substrate 10. Figure 3 In the diagram, a dashed line is used to represent the boundary 90 between the cathode region 83 and the collector region 22.

[0100] When viewed from the top surface 21 in a top-down view, boundary 90 may coincide with the boundaries of transistor section 70 and diode section 80. The location of boundary 90 may be the boundary between transistor section 70 and diode section 80, determined based on the structure on the top surface 21 side of semiconductor substrate 10. Boundary 90 in the X-axis direction may be located in a trench section, situated between the mesa 60 of transistor section 70 located closest to diode section 80 and the mesa 61 of diode section 80 located closest to transistor section 70. Boundary 90 in the X-axis direction may be located at the center of the trench in the X-axis direction. This trench may be the trench closest to diode section 80 among the trench sections that contact emitter region 12.

[0101] When viewed from the top surface 21 in a top-down view, the boundary 90 in the Y-axis direction can be located further inward than the end of the contact hole 54 in the Y-axis direction of the diode section 80 (in this example, the +Y-axis direction side), and can also be located at a position overlapping with the base region 14 exposed on the top surface 21. When viewed from the top surface 21 in a top-down view, the distance from the end of the contact hole 54 in the Y-axis direction of the diode section 80 to the boundary 90 in the Y-axis direction can be more than half the thickness of the semiconductor substrate 10, more than 75% of the thickness of the semiconductor substrate 10, or more than the thickness of the semiconductor substrate 10.

[0102] The first cathode region included in cathode region 83 is disposed separately from the well region 11 in the Y-axis direction. This ensures a sufficient distance between the P-type region (well region 11), which has a higher doping concentration and is formed deeper, and the N+ type first cathode region, thereby improving the breakdown voltage. In this example, the end of the first cathode region in the Y-axis direction is configured to be further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the first cathode region in the Y-axis direction may also be disposed between the well region 11 and the contact hole 54.

[0103] Figure 2 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 83. The cathode region 83 has an N+ type first cathode region 81 and a P+ type second cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0104] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass with impurities such as boron or phosphorus, a thermally oxidized film, and other insulating films. The interlayer insulating film 38 has a layer of... Figure 3 Contact hole 54 as described in the diagram.

[0105] The emitter electrode 52 is disposed above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0106] The semiconductor substrate 10 has N-type or N-type drift regions 18. The drift regions 18 are respectively provided in the transistor section 70 and the diode section 80.

[0107] On the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region 16 may be disposed on the mesa 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0108] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is grounded to the gate trench portion 40. The emitter region 12 can be connected to the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0109] The base region 14 is located below the transmitter region 12. In this example, the base region 14 is grounded to the transmitter region 12. The base region 14 can be connected to the grooves on both sides of the stage surface 60.

[0110] An accumulation region 16 is disposed below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be improved, and the turn-on voltage can be reduced. The accumulation region 16 can be disposed such that it covers the entire lower surface of the base region 14 in each mesa 60.

[0111] A P-type base region 14 is provided on the mesa 61 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 of the diode section 80 functions as the anode region of the diode section 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided on the mesa 61, below the base region 14.

[0112] In each transistor section 70 and each diode section 80, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 may have a concentration peak with a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 can be the average doping concentration in a region with a roughly flat doping concentration distribution.

[0113] The buffer 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer 20 may be set at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer 20 may function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22 and the cathode region 83.

[0114] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration in the collector region 22 is higher than that in the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptors in the collector region 22 are, for example, boron.

[0115] In the diode section 80, a first cathode region 81 and a second cathode region 82 are provided below the buffer zone 20. Figure 4A In the example, the first cathode region 81 is in contact with the collector region 22, but the second cathode region 82 can also be in contact with the collector region 22.

[0116] The donor concentration in the first cathode region 81 is higher than that in the drift region 18. The donors in the first cathode region 81 are, for example, arsenic, hydrogen, or phosphorus. The acceptors in the second cathode region 82 are, for example, boron, indium, or aluminum. The acceptor concentration in the second cathode region 82 can be higher than that in the base region 14. The acceptor concentration in the second cathode region 82 can be the same as or different from that in the acceptor region of the collector region 22. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above.

[0117] When the acceptor concentrations in the second cathode region 82 and the collector region 22 are the same, and when the second cathode region 82 is in contact with the collector region 22, the groove between the mesa 60 where the emitter region 12 is located and the mesa 61 where the emitter region 12 is not located can be defined as the boundary between the second cathode region 82 and the collector region 22. More specifically, the central position of this groove in the X-axis direction can be defined as the boundary between the second cathode region 82 and the collector region 22.

[0118] The collector region 22 and the cathode region 83 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 can be formed of a metallic material such as aluminum.

[0119] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and extends below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and accumulation region 16 is provided, each trench also extends through these doped regions. The trench extending through the doped regions is not limited to the order in which the trenches are formed after the doped regions are formed. The case where doped regions are formed between the trenches after the trenches are formed is also included in the case where the trench extends through the doped regions.

[0120] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 83 and the collector region 22.

[0121] The gate trench portion 40 includes a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench, at a position further inward than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0122] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0123] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench disposed on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is disposed covering the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0124] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0125] By providing a second cathode region 82 to the diode section 80, holes in the drift region 18 and the like can be extracted via the second cathode region 82. Therefore, hole accumulation in the diode section 80 during the conducting state can be suppressed, reducing losses during reverse recovery. Furthermore, by providing the second cathode region 82, the forward voltage in the diode section 80 during the conducting state changes. By adjusting the arrangement of the first cathode region 81 and the second cathode region 82, characteristics such as reverse recovery loss and forward voltage can be adjusted.

[0126] Figure 4A This is a diagram showing an example of the arrangement of the first cathode region 81 and the second cathode region 82 at the lower surface 23 of the semiconductor substrate 10. Figure 4A The image shows an example of the configuration of a first cathode region 81 and a second cathode region 82 in a diode section 80. All diode sections 80 may have... Figure 4A The configuration shown. In Figure 4A The collector area 22 surrounding the diode section 80 is also shown. Additionally, the location of one of the contact holes 54 provided on the upper surface 21 is shown in dashed lines.

[0127] In this example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in the first direction. Figure 4AIn the example, the first direction is the Y-axis direction. The structure of repeating the first cathode region 81 and the second cathode region 82 in the first direction is called a repeating structure 85. For example, the repeating structure 85 includes only one set of first cathode regions 81 and second cathode regions 82 alternately arranged in the first direction. In the diode section 80, at least two repeating structures 85 are grounded to each other in the first direction. When the first cathode region 81 and the second cathode region 82 are repeated in multiple directions, in the diode section 80, at least two repeating structures 85 are grounded to each other in each direction.

[0128] In this example, the length of the first cathode region 81 contained in the repeating structure 85 in the X-axis direction is greater than its length in the Y-axis direction. The length of the second cathode region 82 contained in the repeating structure 85 in the X-axis direction is also greater than its length in the Y-axis direction.

[0129] Let Xa be the length of a cathode region 83 along the X-axis and Ya be the length along the Y-axis. Let Xr be the length of a repeating structure 85 along the X-axis and Yr be the length along the Y-axis. In this specification, the direction in which the first cathode region 81 and the second cathode region 82 are repeatedly configured (in...) Figure 4A The length of the repeating structure 85 (Yr in this example, denoted as Y-axis) along the Y-axis direction is called the repeating distance P between the first cathode region 81 and the second cathode region 82. When the first cathode region 81 and the second cathode region 82 are repeatedly arranged in multiple directions, the length of the repeating structure 85 in each direction is the repeating distance P. When there are multiple repeating structures 85 with different lengths in one direction, the average length of the multiple repeating structures 85 can also be set as the repeating distance P in that direction.

[0130] Furthermore, the area of ​​the first cathode region 81 contained in a repeating structure 85 is designated as S1, and the area of ​​the second cathode region 82 is designated as S2. In this specification, the ratio (S2 / (S1+S2)) of the area of ​​the second cathode region 82 to the sum of the areas of the first cathode region 81 and the second cathode region 82 contained in a repeating structure 85 is designated as the area ratio R. In the case of multiple repeating structures 85 with different area ratios, the average of the area ratios of the multiple repeating structures 85 contained in the cathode region 83 can also be designated as the area ratio R.

[0131] exist Figure 4A In the example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged along the Y-axis direction. When the first cathode region 81 and the second cathode region 82 are continuously arranged from one end of the cathode region 83 in the X-axis direction to the other end, the length Xa of the cathode region 83 in the X-axis direction is set as the length Xr of the repeating structure 85 in the X-axis direction.

[0132] Cathode region 83 may have a margin region 84. Margin region 84 is the region extending from boundary 90 to the first cathode region 81. Margin region 84 may have the same conductivity type as the second cathode region 82. Margin region 84 may have the same doping concentration distribution as the second cathode region 82. The length of margin region 84 in the X-axis direction is defined as Xm, and the length of margin region 84 in the Y-axis direction is defined as Ym.

[0133] like Figure 4A As shown, when the length of one of the first cathode region 81 and the second cathode region 82 in the X-axis direction is shorter than the length Xa of the cathode region 83 in the X-axis direction, the length Xr of the repeating structure 85 in the X-axis direction is the same as the length of the shorter of the first cathode region 81 and the second cathode region 82 in the X-axis direction. Figure 4A In this example, the length X2 of the second cathode region 82 is less than the length Xa of the cathode region 83. In this case, the length X2 of the second cathode region 82 is set to the length Xr of the repeating structure 85.

[0134] In this example, the Y-axis length Yr of the repeating structure 85 is the sum of the Y-axis length Y1 of the first cathode region 81 and the Y-axis length Y2 of the second cathode region 82. The repeating spacing P in this example is Y1 + Y2. Furthermore, the area ratio R is S2 / (S1 + S2) = Y2 / (Y1 + Y2). By adjusting the repeating spacing P and the area ratio R to predetermined ranges, characteristics such as forward voltage and reverse recovery loss can be adjusted. The ranges within which the repeating spacing P and the area ratio R should be adjusted will be described later.

[0135] A first cathode region 81 of length Xe is disposed in contact with both ends of the second cathode region 82 in the X-axis direction. The length Xe is 0 μm or more. The length Xe can be less than the length Xr, less than the length Y1, or less than the length Y2. The length Xe can be more than 1, 2, 5, 10, or 20 times the width of the mesa 61 in the X-axis direction. The length Xe can be less than 50 or 30 times the width of the mesa 61 in the X-axis direction. By having a first cathode region 81 of length Xe in a manner that is connected to both ends of the second cathode region 82, electrical interference caused by hole inflow between the diode section 80 and the transistor section 70 can be suppressed.

[0136] The length of the first cathode region 81 or the second cathode region 82 in the Y-axis direction, which is located at both ends of the cathode region 83, is defined as Ye. Figure 4BIn the example, the first cathode region 81 is disposed at both ends of the cathode region 83. The length Ye is 0 μm or more. The length Ye can be less than the length Yr, or less than the length Y1, or less than the length Y2. By having a first cathode region 81 or a second cathode region 82 with a length Ye at both ends of the cathode region 83, the movement of charge carriers at the Y-axis end of the diode section 80 can be made more uniform.

[0137] In the Y-axis direction, the length by which the contact hole 54 protrudes beyond the boundary 90 is defined as F. The length F is 0 μm or more. The length F can be less than the length Yr, the length Y1, or the length Y2. By having a length F, it is possible to suppress the concentration of charge carriers at the Y-axis end of the contact hole 54.

[0138] When viewed from above, the corner of the first cathode region 81, located closest to the transistor section 70 in the X-axis direction and outermost in the Y-axis direction, can have a chamfered portion 91. The chamfered portion 91 can be a region of the first cathode region 81 whose width in the Y-axis direction decreases as it approaches the transistor section 70. At the corner of the first cathode region 81 chamfered by the chamfered portion 91, a margin region 84 or a second cathode region 82 can be provided instead of the first cathode region 81. In this example, the portion marked with a dashed line at the corner can be designated as the chamfered portion 91, and this portion can be used as the boundary between the first cathode region 81 and the margin region 84. This effectively prevents the electron current from concentrating at the corner of the first cathode region 81 during reverse recovery.

[0139] Figure 4A This is a diagram illustrating another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83. In this example, [the following is a diagram showing a different configuration example]. Figure 4A The first cathode region 81 and the second cathode region 82 are interchanged. In this example, the repeating interval P is also Y1+Y2, and the area ratio R is also S2 / (S1+S2)=Y2 / (Y1+Y2). Furthermore, the lengths Xe, Ye, and F can be... Figure 4A The same example can also be used with Figure 4C The examples are different. A margin area of ​​84 can be set, or it can be omitted. In this example, the lengths Xm and Ym of the margin area of ​​84 are both 0.

[0140] Figure 4C This is a diagram showing another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83. Figure 4A The difference lies in that, with the Y-axis direction as the long side direction, Figure 4A The first cathode region 81 and the second cathode region 82 are arranged repeatedly along the X-axis. Various dimensions, repeating intervals P, area ratios R, etc., can be... Figure 4C Same. However, Figure 4A In the example, the lengths X1, X2, and Xr are...Figure 4C In the example, the lengths Y1, Y2, and Yr correspond. Additionally, Figure 4A In the example, the lengths Y2 and Yr are... Figure 5A In the example, the lengths X2 and Xr correspond.

[0141] Figure 5A This diagram illustrates another configuration example of the first cathode region 81 and the second cathode region 82 in a diode section 80. In this example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in multiple directions. Figure 4A In this example, the multiple directions are the X-axis and Y-axis directions. In this example, the structure of the first cathode region 81 and the second cathode region 82 repeating in both the X-axis and Y-axis directions is designated as a repeating structure 85. In the diode section 80, at least two repeating structures 85 are grounded to each other in the X-axis direction, and at least two repeating structures 85 are grounded to each other in the Y-axis direction. For example, the repeating structure 85 may be a rectangular shape comprising only one set of alternating first cathode regions 81 and second cathode regions 82 in the X-axis direction, and only one set of alternating first cathode regions 81 and second cathode regions 82 in the Y-axis direction.

[0142] In this example, within the cathode region 83, rectangular second cathode regions 82 are arranged at predetermined intervals in both the X-axis and Y-axis directions. The area outside the second cathode regions 82 within the cathode region 83 is the first cathode region 81.

[0143] Let the length of the second cathode region 82 in the X-axis direction be X2, and the length in the Y-axis direction be Y2. In the X-axis direction, let the length of the first cathode region 81 that is clamped by the second cathode region 82 be X1. In the Y-axis direction, let the length of the first cathode region 81 that is clamped by the second cathode region 82 be Y1.

[0144] In this example, the length Xr of the repeating structure 85 in the X-axis direction is X1+X2, and the length Yr in the Y-axis direction is Y1+Y2. In this example, the first cathode region 81 and the second cathode region 82 are configured in the X-axis direction with a repeating interval Px=Xr, and in the Y-axis direction with a repeating interval Py=Yr. In this specification, when the range or value of the repeating interval is described, it can be that at least one of the repeating intervals Px and Py has that range or value, or both repeating intervals Px and Py can have that range or value. Alternatively, the repeating intervals Px and Py can be the same value. In this example, the area ratio R is (X2×Y2) / (Xr×Yr) = (X2×Y2) / ((X1+X2)×(Y1+Y2)).

[0145] Lengths Xe, Ye, and F can be related to Figure 5BThe examples can be the same or different. In this example, the length Xe can be greater than X² / 2 and less than X¹ / 2. In this example, the length Ye can be greater than Y² / 2 and less than Y¹ / 2.

[0146] Figure 5A This is a diagram illustrating another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83. In this example, [the following is a diagram showing a different configuration example]. Figure 5A The first cathode region 81 and the second cathode region 82 are interchanged. In this example, the repeating interval Px is also X1+X2, and the repeating interval Py is also Y1+Y2. The area ratio R is 1-((X1×Y1) / (Xr×Yr))=1-((X1×Y1) / ((X1+X2)×(Y1+Y2))). Furthermore, the lengths Xe, Ye, and F can be... Figure 5C The examples can be the same or different. In this example, the length Xe can be greater than X² / 2 or less than X¹ / 2. In this example, the length Ye can be greater than Y² / 2 and less than Y¹ / 2.

[0147] Figure 5A This is a diagram illustrating another configuration example of a first cathode region 81 and a second cathode region 82 within a cathode region 83. In this example, Figure 5A The second cathode region 82 extends further toward the transistor portion 70 in the X-axis direction than the first cathode region 81, and extends further outward in the Y-axis direction than the first cathode region 81. Therefore, with... Figure 5A The difference lies in the absence of the corner of the first cathode region 81. Apart from this, it can be compared with... Figure 5C The same applies. All ends of the first cathode region 81 in the X-axis direction can be positioned further inward than the ends of the second cathode region 82. All ends of the first cathode region 81 in the Y-axis direction can be positioned further inward than the ends of the second cathode region 82. "Inner" refers to the side closest to the center of the cathode region 83.

[0148] In this example, the second cathode region 82 protrudes by a length Xe in the X-axis direction and a length Ye in the Y-axis direction from the end of the first cathode region 81. The length Xe can be less than half or less than 1 / 4 of the length X2 of the second cathode region 82. Alternatively, the length Xe can be more than 1 / 10 of the length X2. Similarly, the length Ye can be less than half or less than 1 / 4 of the length Y2 of the second cathode region 82. Alternatively, the length Ye can be more than 1 / 10 of the length Y2.

[0149] like Figure 6AAs shown, the repeating structure 85 disposed on the outer side and the repeating structure 85 disposed on the inner side can have different structures. More specifically, the repeating structure 85 including the end of the first cathode region 81 has a different configuration pattern of the first cathode region 81 compared to the other repeating structures 85. In this example, the repeating structure 85 can be determined based on the pattern of the second cathode region 82 and the regions other than the second cathode region 82 (the margin region 84 and the first cathode region 81). That is, in determining the repeating structure 85, the margin region 84 can be treated as the first cathode region 81.

[0150] The portion of the second cathode region 82 that protrudes further outward than the end of the first cathode region 81 can be treated as a collector region 22. This portion can have the same doping concentration as the collector region 22.

[0151] Figure 5A This is a diagram illustrating another configuration example of the first cathode region 81 and the second cathode region 82 in a diode section 80. In this example, the shape of the second cathode region 82 is similar to... Figure 5A The examples differ. Other structures are different. Figure 5A The same applies. In this example, the second cathode region 82 is circular in shape. It should be noted that the shape of the second cathode region 82 is not limited to rectangular or circular.

[0152] Let the radius of a second cathode region 82 be R2. In the X-axis direction, let the minimum length of the first cathode region 81 that is clamped by the second cathode region 82 be X1. In the Y-axis direction, let the minimum length of the first cathode region 81 that is clamped by the second cathode region 82 be Y1.

[0153] In this example, the length Xr of the repeating structure 85 along the X-axis is X1 + 2 × R2, and the length Yr along the Y-axis is Y1 + 2 × R2. The first cathode region 81 and the second cathode region 82 in this example are arranged along the X-axis with a repeating interval Px = Xr, and along the Y-axis with a repeating interval Py = Yr. The area ratio R in this example is (π × R2). 2 ) / (Xr×Yr)=(π×R2) 2 ) / ((2×R2+X1)×(2×R2+Y1)).

[0154] Lengths Xe, Ye, and F can be related to Figure 5A The same example can also be used with Figure 6B The examples are different. In this example, the length Xe can be greater than X1 and less than R2. In this example, the length Ye can be greater than Y1 and less than R2.

[0155] Figure 6A This is a diagram illustrating another configuration example of a first cathode region 81 and a second cathode region 82 in a cathode region 83. In this example, [the following is a diagram showing a different configuration example]. Figure 6AThe first cathode region 81 and the second cathode region 82 are interchanged. The radius of the first cathode region 81 is set to R1. In this example, the repetition interval Px is X² + 2 × R1, and the repetition interval Py is Y² + 2 × R1. The area ratio R is 1 - (π × R1) / (π × R1). 2 ) / (Xr×Yr)=1-(π×R1) 2 ) / ((2×R1+X2)×(2×R1+Y2)). Additionally, lengths Xe, Ye, and F can be... Figure 6A The same example can also be used with Figure 6C The examples are different. In this example, the length Xe can be greater than X² / 2 and less than R1. In this example, the length Ye can be greater than Y² / 2 and less than R1.

[0156] Figure 6A This is a diagram illustrating another configuration example of a first cathode region 81 and a second cathode region 82 within a cathode region 83. In this example, Figure 6A The second cathode region 82 extends further toward the transistor portion 70 in the X-axis direction than the first cathode region 81, and extends further outward in the Y-axis direction than the first cathode region 81. Therefore, with... Figure 6A The difference lies in the absence of the corner of the first cathode region 81. Apart from this, it can be compared with... Figure 5C The same. The configuration of the end of the first cathode region 81 can be the same as... Figure 5C The example is the same. Furthermore, the determination of the repeating structure 85 can also be related to... Figure 5A The examples are the same.

[0157] exist Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7 In the example, the repeating structure 85 is arranged periodically along a square (or rectangular) grid, but is not limited to this. The repeating structure 85 can also be arranged periodically along a triangular grid, or even along a honeycomb grid.

[0158] Figure 7 This is a graph showing the relationship between the area ratio R and the forward voltage of the diode section 80. The forward voltage is normalized to 1, with the voltage at R=0 as 1. The forward voltage can also be normalized in the same way in other graphs. Figure 4A In the middle, it is shown that Figure 4B The examples shown illustrate the characteristics of samples with repeat intervals P of 10 μm, 20 μm, 40 μm, 80 μm, 160 μm, 320 μm, or 640 μm. It should be noted that... Figure 7 The same properties are also set in the example shown.

[0159] If the area ratio R increases, the area of ​​the second cathode region 82 increases. Consequently, the amount of holes extracted from the cathode region 83 during the conduction state of the diode section 80 increases, and the on-resistance of the diode section 80 increases. Therefore, if the area ratio R increases, the forward voltage increases. In particular, if the area ratio R is greater than 0.8, the forward voltage increases sharply. Therefore, the area ratio R is preferably 0.8 or less. The area ratio R can be 0.7 or less, or 0.6 or less. Furthermore, if the second cathode region 82 is too small, the effect of reducing reverse recovery loss decreases. The area ratio R is preferably 0.1 or more. The area ratio R can be 0.15 or more, or 0.2 or more.

[0160] like Figure 7 As shown, the tendency for the forward voltage to decrease as the repetition spacing P increases from 10 μm to 80 μm is illustrated. If the repetition spacing P is small, the length Y1 of the first cathode region 81 also becomes smaller. If the length Y1 of the first cathode region 81 is small, the distance between the holes present above the first cathode region 81 and the second cathode region 82 cannot be guaranteed, and the holes present above the first cathode region 81 are easily extracted into the second cathode region 82. Therefore, the diode section 80 becomes difficult to conduct, and the forward voltage increases. It is assumed that as the repetition spacing P increases, the diode section 80 becomes easier to conduct, and the forward voltage decreases.

[0161] On the other hand, it is shown that the forward voltage tends to increase if the repetition spacing P increases from 160 μm to 640 μm. When the repetition spacing P is small, since the length Y2 of the second cathode region 82 is also small, electrons injected from the first cathode region 81 easily wind around to the top of the entire second cathode region 82 when the diode section 80 is turned on. Therefore, the region above the second cathode region 82 also functions as a diode. If the repetition spacing P becomes large enough, a region arises above the second cathode region 82 where electrons from the first cathode region 81 cannot wind around. Therefore, a portion of the region above the second cathode region 82 no longer functions as a diode. If the repetition spacing P increases, the region that does not function as a diode also increases, and the forward voltage increases. Therefore, as... Figure 7 As shown, it is believed that the forward voltage increases when the repetition spacing P increases from 160 μm to 640 μm.

[0162] As described above, the forward voltage decreases when the repetition spacing P increases from 10 μm to 80 μm, and increases when the repetition spacing P increases from 160 μm to 640 μm. Therefore, the forward voltage is more stable within the range of 40 μm or more and 200 μm or less for the repetition spacing P. Within the range of 40 μm or more and 200 μm or less for the repetition spacing P, when the carrier lifetime is longer than 1 μs, a balance is achieved between maintaining an appropriate concentration of minority carriers (holes in this example) in the drift region 18 from the first cathode region 81 to the upper surface 21 side and reducing the carrier concentration due to short circuits in the minority carriers in the second cathode region 82. As a result, the forward voltage is considered to be at an appropriate value and more stable. The repetition spacing P is preferably 40 μm or more and 200 μm or less. By setting the repetition spacing P to 40 μm or more and 200 μm or less, deviations in the forward voltage caused by manufacturing deviations of the repetition spacing P can be suppressed. In addition, by adjusting the area ratio R, the forward voltage can be adjusted to a predetermined value.

[0163] The repeat interval P can be greater than 80 μm. The repeat interval P can also be less than 160 μm. For example... Figure 7 As shown, the forward voltage exhibits the same characteristics when the repetition interval P is 80 μm and when the repetition interval P is 160 μm. Therefore, the deviation of the forward voltage can be further reduced. Figure 4A The results shown suggest that the repeat interval P reaches a minimum between 80 μm and 160 μm. The repeat interval P can also be greater than 100 μm. It can also be less than 130 μm.

[0164] When the area ratio R is below 0.6, the forward voltage is almost identical in the examples with a repetition spacing P of 80 μm and 160 μm. The area ratio R can be below 0.6. In this case, the repetition spacing P can be above 80 μm and below 160 μm.

[0165] When the area ratio R is below 0.5, the deviation of the forward voltage becomes smaller within a range where the repetition interval P is above 40 μm. Figure 8 When the first cathode region 81 and the second cathode region 82 in the repeating structure 85 shown each have a long side in a direction different from the first direction (Y-axis direction) (X-axis direction), the area ratio R can be 0.5 or less. The area ratio R can also be 0.4 or less. The repeating spacing P can be 40 μm or more and 200 μm or less.

[0166] In other examples, the repetition interval P can be greater than 40 μm and less than 80 μm. In this region, if the repetition interval P increases, the forward voltage increases. Therefore, the forward voltage can be adjusted by adjusting the repetition interval P.

[0167] Figure 8 This is a graph showing the relationship between forward voltage and reverse recovery loss relative to the area ratio R. Figure 5A The diode section 80 in the middle has Figure 8 The structure shown has a repeating interval P of 80 μm. The forward voltage is applied at a forward current density of 1800 A / cm². 2 In cases where the current density is high.

[0168] like Figure 8 As shown, increasing the area ratio R reduces reverse recovery losses and increases forward voltage. The upper limit of the area ratio R can be determined based on the area ratio-forward voltage characteristic. For example, the upper limit of the area ratio R can be set in a way that keeps the forward voltage below an allowable value (within...). Figure 8 (The lower limit of the area ratio R range can be determined based on the characteristics of the area ratio versus reverse recovery loss. For example, the lower limit of the area ratio R can be set in a way that keeps the reverse recovery loss below an allowable value). Figure 9 (The value is 0.1).

[0169] Figure 9 This is a graph showing the relationship between the forward voltage and the reverse recovery loss relative to the length Y2 in the first direction of the second cathode region 82. Figure 5A The diode section 80 in the middle has Figure 9 The structure shown has a repeating interval P of 80 μm.

[0170] like Figure 10 As shown, if the length Y2 increases, the reverse recovery loss decreases, and the forward voltage increases. The upper limit of the length Y2 can be determined based on the length Y2-forward voltage characteristic. For example, the upper limit of the length Y2 can be set in a way that keeps the forward voltage below an allowable value. The length Y2 can be 65 μm or less, 60 μm or less, or 55 μm or less. The lower limit of the length Y2 can be determined based on the length Y2-reverse recovery loss characteristic. For example, the lower limit of the length Y2 can be set in a way that keeps the reverse recovery loss below an allowable value. The length Y2 can be 10 μm or more, 15 μm or more, or 20 μm or more.

[0171] Figure 10 This shows the relationship between the magnitude of the positive voltage deviation caused by patterning deviations in the manufacturing process and the area ratio R. Figure 5A The diode section 80 in the middle has Figure 10 The structure shown has a repeating interval P of 80 μm.

[0172] exist Figure 7In the example, the patterning deviation is set to ±0.5 μm. That is, the length Y1 of the first cathode region 81 and the length Y2 of the second cathode region 82 each have a deviation of ±0.5 μm. Furthermore, the magnitude of the forward voltage deviation is related to... Figure 10 Similarly, the magnitude of the forward voltage when R=0 is normalized by setting it to 1.

[0173] like Figure 10 As shown, if the area ratio R is greater than 0.8, the deviation of the forward voltage increases sharply. If the area ratio of the second cathode region 82 is large, the area of ​​the first cathode region 81 required for conductivity modulation becomes relatively smaller. Therefore, the influence of the linewidth deviation of the first cathode region 81 is considered to increase. The area ratio R is preferably 0.8 or less. The area ratio R can also be 0.6 or less. This further suppresses the deviation of the forward voltage. Figure 11 As shown, if the area ratio R becomes less than 0.05, the deviation of the forward voltage increases sharply. It is believed that if the area ratio of the second cathode region 82 is too small, the influence of the linewidth deviation of the first cathode region 81 will strongly affect the short-circuit degree of minority carriers in the second cathode region 82. The area ratio R is preferably 0.05 or higher. The area ratio R can be 0.1 or higher, or 0.15 or higher. It is believed that by setting the area ratio of the second cathode region 82 within the above range, even if the linewidth of the first cathode region 81 deviates, the balance between the effect of appropriately maintaining the concentration of minority carriers (holes in this example) and the effect of reducing the carrier concentration due to the short circuit of minority carriers in the second cathode region 82 remains stable, provided the carrier lifetime is relatively long (1 μs or higher).

[0174] Figure 11 The relationship between the magnitude of the deviation in positive voltage caused by patterning deviations in the manufacturing process and the length Y2 of the second cathode region 82 is shown. Figure 5A The diode section 80 in the middle has Figure 11 The structure shown has a repeating interval P of 80 μm. Figure 11 In the example, the patterning deviation is set to ±0.5μm.

[0175] like Figure 11 As shown, if the length Y2 is greater than 65 μm, the deviation of the forward voltage increases sharply. If the length of the second cathode region 82 is long, the area of ​​the first cathode region 81 required for conductivity modulation becomes relatively smaller. Therefore, the influence of the linewidth deviation of the first cathode region 81 is considered to be greater. The length Y2 is preferably 65 μm or less. The length Y2 can be 60 μm or less, or 55 μm or less. This further suppresses the deviation of the forward voltage. Figure 12As shown, if the length Y2 is less than 4 μm, the deviation of the forward voltage increases sharply. It is assumed that if the length of the second cathode region 82 is too short, the linewidth deviation of the first cathode region 81 will strongly affect the degree of short-circuiting of minority carriers in the second cathode region 82. The length Y2 is preferably 4 μm or more. The length Y2 can be 8 μm or more, or 12 μm or more.

[0176] Figure 10 This illustrates the relationship between the magnitude of the forward voltage deviation and the area ratio R when the patterning deviation is set to ±0.2 μm. In this example, the relationship with... Figure 13 The example shown yields the same result.

[0177] Figure 11 This illustrates the relationship between the magnitude of the forward voltage deviation and the length Y2 of the second cathode region 82 when the patterning deviation is set to ±0.2 μm. In this example, the relationship with... Figure 14 The example shown yields the same result.

[0178] Figure 14 This is a graph illustrating another example of the relationship between the area ratio R and the forward voltage of diode section 80. Figure 5A In the middle, it is shown that Figure 5B The examples shown depict the characteristics of samples with repeat intervals Px and Py set to 10 μm, 20 μm, 40 μm, 80 μm, 160 μm, 320 μm, or 640 μm. In each sample, Px = Py. It should be noted that... Figure 7 The example shown also exhibits the same characteristics.

[0179] and Figure 14 Similarly, the area ratio R is preferably 0.8 or less. The area ratio R can be 0.7 or less, or 0.6 or less. Furthermore, if the second cathode region 82 is too small, the effect of reducing reverse recovery loss becomes smaller. The area ratio R is preferably 0.1 or more. The area ratio R can be 0.15 or more, or 0.2 or more.

[0180] exist Figure 14 In the example, if the repetition interval P increases from 10 μm to 160 μm, the positive voltage tends to decrease. On the other hand, if the repetition interval P increases from 160 μm to 640 μm, the positive voltage tends to increase.

[0181] exist Figure 7 In the example, since the second cathode region 82 is surrounded by the first cathode region 81, electrons injected from the first cathode region 81 easily orbit around the entire top of the second cathode region 82 when the diode section 80 is turned on. Therefore, compared with... Figure 14Compared to the previous example, up to the range of the repeating spacing P, the region above the second cathode region 82 is more likely to function as a diode. Therefore, in Figure 14 In the example, it is believed that there is a tendency for the positive voltage to decrease until the repetition interval P is large.

[0182] As described above, the forward voltage decreases as the repetition interval P increases from 10 μm to 160 μm, and increases as the repetition interval P increases from 160 μm to 640 μm. Therefore, the forward voltage is more stable within the range of 40 μm or more and 200 μm or less for the repetition interval P. The repetition interval P is preferably 40 μm or more and 200 μm or less.

[0183] like Figure 5A As shown, with a repetition interval P of 160 μm, the forward voltage is lower compared to other samples. The repetition interval P can also be set to a value close to 160 μm. The repetition interval P can be greater than 80 μm, greater than 100 μm, or greater than 120 μm. The repetition interval P can be less than 200 μm or less than 180 μm.

[0184] In other examples, the repetition interval P can be greater than 40 μm and less than 160 μm. In this region, if the repetition interval P increases, the forward voltage increases. Therefore, the forward voltage can be adjusted by adjusting the repetition interval P.

[0185] The first cathode region 81 and the second cathode region 82 are also repeatedly configured in a second direction (e.g., the X-axis direction) different from the first direction (e.g., the Y-axis direction). Figure 4A In that structural case, with Figure 15 Compared to that structure, the area ratio R can be set slightly larger. The area ratio R can be below 0.8, below 0.7, or below 0.6.

[0186] Figure 15 This is a diagram showing a comparative example of the anode voltage-anode current characteristics of the diode section 80. Figure 4A The diode section 80 has Figure 15 The structure has a repeating interval P of 10 μm. Figure 16The example shows the anode voltage-anode current characteristics when the area ratio R varies from 0.001 to 0.9. If the repetition interval P is small, the variation in the anode voltage-anode current characteristics when varying the area ratio R is large. In particular, the variation in the anode voltage-anode current characteristics when the area ratio R is 0.1 (i.e., when the second cathode region 82 is almost non-existent) is larger than the characteristics when the area ratio R is 0.001. Therefore, if the repetition interval P is too small, it is difficult to precisely adjust the anode voltage-anode current characteristics in regions where the difference from the characteristics when the area ratio R is 0.001 is small.

[0187] Figure 16 This is a diagram showing another example of the anode voltage-anode current characteristics of diode section 80. Figure 4A The diode section 80 has Figure 16 The structure has a repeating interval P of 80 μm. For example... Figure 15 As shown, if the repetition interval P is large, the change in the anode voltage-anode current characteristics is smaller when the area ratio R is varied. In particular, the change in the anode voltage-anode current characteristics when the area ratio R is 0.1 (i.e., with a slight presence of the second cathode region 82) is smaller compared to when the area ratio R is 0.001 (i.e., with almost no second cathode region 82). Figure 17 The examples are small. Therefore, the anode voltage-anode current characteristics can be adjusted with high precision. From this perspective, the repeatability interval P can be 40 μm or more. The repeatability interval P can also be 60 μm or more, and even 80 μm or more.

[0188] Figure 4A This is a diagram showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage. The diode section 80 in this example has… Figure 17 The structure shown has a repeating interval P of 80 μm. For example... Figure 18 As shown, if the length Y2 is greater than 60 μm, the increase in forward voltage becomes abrupt. The length Y2 can be in the region where the forward voltage changes linearly, i.e., below 50 μm. The area ratio R can be below 0.6.

[0189] Figure 18 This is a graph showing the relationship between the forward voltage and reverse recovery loss of diode section 80. (See diagram below.) Figure 4A As shown, there is a trade-off between the forward voltage and reverse recovery loss in the diode section 80. That is, the lower the reverse recovery loss, the higher the forward voltage. If the forward voltage increases, the loss of the diode section 80 when it is turned on increases.

[0190] Comparative Examples 1 and 2 are examples where the cathode region 83 has a first cathode region 81 but does not have a second cathode region 82. Comparative Example 1 shows the relationship between forward voltage and reverse recovery loss when the doping concentration of the anode region (base region 14) of the diode section 80 is varied. Comparative Example 2 shows the relationship between forward voltage and reverse recovery loss when the doping concentration of the cathode region 83 of the diode section 80 is varied.

[0191] Example 1 shows that the diode section 80 has Figures 1-18 The relationship between forward voltage and reverse recovery loss is shown in the example with a structure and a repeating spacing of 80 μm, where the area ratio R is varied. Figure 19 As shown, the compromise characteristics of Example 1 are improved compared to Comparative Examples 1 and 2.

[0192] In Example 1, the doping concentration of the base region 14 (anode region) of the diode portion 80 is the same as the doping concentration of the base region 14 of the transistor portion 70. Therefore, the base region 14 of the diode portion 80 and the base region 14 of the transistor portion 70 can be fabricated by the same ion implantation process. That is, by using a common mask to synchronously implant dopant ions at the same dosage, the base regions 14 of the transistor portion 70 and the diode portion 80 can be formed. In contrast, in Comparative Examples 1 and 2, the manufacturing process is complicated because the doping concentration of the anode region of the diode portion 80 is varied.

[0193] In Embodiment 1, the doping concentration of the second cathode region 82 of the diode section 80 is the same as the doping concentration of the collector region 22 of the transistor section 70. Therefore, the second cathode region 82 of the diode section 80 and the collector region 22 of the transistor section 70 can be fabricated using the same ion implantation process. With this structure, a semiconductor device 100 with improved trade-off characteristics can be manufactured using a simplified manufacturing process. However, the base region 14 of the diode section 80 and the base region 14 of the transistor section 70 can have different doping concentrations. Furthermore, the second cathode region 82 of the diode section 80 and the collector region 22 of the transistor section 70 can also have different doping concentrations.

[0194] The dopant ion dose in the base region 14 (anode region) of the diode section 80 can be 5.0 × 10⁻⁶. 12 / cm 2 Above and 5.0×10 13 / cm 2 The dosage of dopant ions can be determined by adjusting the doping concentration of base region 14 ( / cm²). 3The dose is obtained by integrating along the depth direction. When the base region 14 is in contact with the upper surface 21 and the drift region 18, the dose can be calculated by integrating the doping concentration of the base region 14 from the upper surface 21 to the drift region 18. In other examples, the dose can be obtained by integrating the peak of the doping concentration along the depth direction of the base region 14 over the full width at half maximum (FWHM).

[0195] The dopant ion dose in the second cathode region 82 can be 1.0 × 10⁻⁶. 13 / cm 2 Above and 1.0×10 14 / cm 2 The dosage of dopant ions can be determined by adjusting the doping concentration ( / cm²) of the second cathode region 82. 3 The dose is calculated by integrating along the depth direction. When the second cathode region 82 is in contact with the lower surface 23 and the N-type region, the dose can be calculated by integrating the doping concentration of the second cathode region 82 from the lower surface 23 to the N-type region. In other examples, the dose can also be calculated by integrating the peak of the doping concentration along the depth direction of the second cathode region 82 over the full width at half maximum (FWHM).

[0196] To adjust forward voltage and reverse recovery loss, carrier lifetime inhibitors are sometimes formed in the diode section 80. For example, by forming charged particles such as helium below the anode region of the diode section 80, recombination centers of carriers can be formed in that region, thereby reducing carrier lifetime.

[0197] In this example, the semiconductor device 100 may not require the formation of a carrier lifetime inhibitor in the diode section 80. For example... Figure 19 As explained, the characteristics of the diode section 80 can be adjusted by changing the repeating spacing P and area ratio R of the cathode region 83. The carrier lifetime in the drift region 18 of the diode section 80 can be 1 μs or more throughout the entire drift region 18. This carrier lifetime can be 2 μs or more, or 3 μs or more. This carrier lifetime can be 10 μs or more, or 20 μs or more, or 30 μs or more. This carrier lifetime can be less than 10 ms, less than 1 ms, less than 500 μs, less than 200 μs, or less than 100 μs. Furthermore, helium may not be present in the drift region 18 of the diode section 80. The carrier lifetime in the drift region 18 of the diode section 80 can exhibit a maximum value within the semiconductor substrate 10. Therefore, the process of forming a carrier lifetime inhibitor can be omitted, simplifying the manufacturing process. Furthermore, leakage current caused by carrier recombination centers or generation centers can be prevented.

[0198] Figure 7This is a diagram illustrating the manufacturing method of the semiconductor device 100. Figure 14 The diagram illustrates the process of forming the cathode region 83 in the manufacturing process of the semiconductor device 100. In setting step S1002, the repetition spacing P and area ratio R in the cathode region 83 are set. In setting step S1002, the repetition spacing P and area ratio R are set such that the forward voltage and reverse recovery loss of the diode section 80 are within a predetermined range. In S1002, reference can be made to… Figures 1-18 or Figure 20 The characteristics shown are used to set the repetition spacing P and the area ratio R. In setting step S1002, the repetition spacing P is set to 40 μm or more and 200 μm or less, and the area ratio R is set to 0.1 or more and 0.8 or less. In setting step S1002, the following can be set... Figure 20 The repeating interval P and area ratio R are explained in the text.

[0199] In formation step S1004, a first cathode region 81 and a second cathode region 82 are formed on the semiconductor substrate 10 with a set repeating pitch P and area ratio R. In formation step S1004, the first cathode region 81 and the second cathode region 82 can be formed by implanting dopant ions from the lower surface 23 of the semiconductor substrate 10 and performing heat treatment.

[0200] In formation step S1004, the collector region 22 of the transistor section 70 can be formed using the same process as the second cathode region 82. For example, in formation step S1004, dopant ions are implanted using a mask that exposes the areas where the collector region 22 and the second cathode region 82 should be formed. This simplifies the formation processes of the second cathode region 82 and the collector region 22.

[0201] In formation step S1004, the anode region (base region 14) of the diode section 80 and the base region 14 of the transistor section 70 can be formed using a common process. For example, in formation step S1004, dopant ions are implanted using a mask that exposes the regions where the anode region and base region 14 should be formed. This simplifies the formation process of the anode region and base region 14.

[0202] Figure 20 This is a diagram illustrating an example of design step S1002. Figure 4A The relationship between the forward voltage and reverse recovery loss of diode section 80 is shown. Figure 20 The diagram illustrates a structure in which the cathode region 83 has a first cathode region 81 but no second cathode region 82, showing the forward voltage-reverse recovery loss characteristic 302 when the doping concentration of the anode region of the diode section 80 varies. Furthermore, the doping concentration of the anode region at a predetermined reference point A in characteristic 302 is also shown, illustrating the formation of... Figure 20Characteristic group 304 is shown for the diode section 80 with the structure shown. Characteristic group 304 displays the characteristics of each sample with the repeating pitch P varied from 10 μm to 640 μm. In each characteristic of characteristic group 304, the forward voltage and reverse recovery loss are adjusted by varying the area ratio R.

[0203] In design step S1002, an initial value for the design doping concentration of the anode region is set. The initial value is the doping concentration of the anode region at any point on feature 302. ​ In the example, the doping concentration of the anode region at reference point A is set to the initial value.

[0204] In design step S1002, the forward voltage-reverse recovery loss characteristics of the diode section 80 are obtained for multiple repeating intervals P using the initial value. ​ In the example, feature group 304 is obtained.

[0205] In design step S1002, the design value of the doping concentration of the anode region can be adjusted based on the acquired characteristic group 304. For example, a characteristic that can achieve the desired forward voltage and reverse recovery loss is selected from the characteristics contained in the characteristic group 304, and the repetition spacing P and area ratio R are determined according to this characteristic. However, the characteristic group 304 for reference point A sometimes does not include the desired forward voltage and reverse recovery loss. In this case, in design step S1002, a new reference point B is set in a way that the desired forward voltage and reverse recovery loss can be obtained, and a new characteristic group 304 for reference point B is acquired. For example, if it is desired to shift the range of the reverse recovery loss of the characteristic group 304 in the direction of smaller loss, a reference point B with a smaller forward voltage (and reverse recovery loss) is set for reference point A. By increasing the doping concentration of the anode region, the forward voltage can be reduced. This process can be repeated until the desired forward voltage and reverse recovery loss can be set.

[0206] While the present invention has been described above using embodiments, its technical scope is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or alterations can be made to the above embodiments. As can be seen from the claims, such modifications or alterations can also be included within the technical scope of the present invention.

[0207] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order unless specifically stated as "before" or "beforehand," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, this does not mean that they must be implemented in this order. Claims (as amended under Article 19 of the Treaty) 1. [After correction] A semiconductor device is characterized by comprising a semiconductor substrate having an upper surface and a lower surface, wherein a diode portion is disposed on the semiconductor substrate. The diode section has: A drift region of a first conductivity type is disposed on the semiconductor substrate; and A cathode region of either the first or second conductivity type is disposed in contact with the lower surface of the semiconductor substrate, and has a higher doping concentration than the drift region. The cathode region has: The first cathode region of the first conductivity type; and The second cathode region of the second conductivity type is disposed in contact with the lower surface of the semiconductor substrate. The first cathode region and the second cathode region are repeatedly arranged in a first direction, and the repeating spacing between the first cathode region and the second cathode region in the first direction is less than 200 μm. The area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less. 2. The semiconductor device according to claim 1, characterized in that, The repeat interval is greater than 80 μm and less than 160 μm. 3. The semiconductor device according to claim 2, characterized in that, The area ratio is below 0.6. 4. The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region each have a long side in a direction different from the first direction. The area ratio is less than 0.5. 5. The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region are also repeatedly configured in a second direction different from the first direction. The area ratio is below 0.6. 6. The semiconductor device according to claim 1, characterized in that, The repeat interval is greater than 100 μm and less than 130 μm. 7. [After correction] The semiconductor device according to claim 1, characterized in that, The repeat interval is less than 80 μm. 8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The dose of dopant ions in the anode region is 5.0 × 10⁻⁶. 12 / cm 2 Above and 5.0×10 13 / cm 2 the following. 9. The semiconductor device according to claim 8, characterized in that, The dose of dopant ions in the second cathode region is 1.0 × 10⁻⁶. 13 / cm 2 Above and 1.0×10 14 / cm 2 the following. 10. The semiconductor device according to any one of claims 1 to 7, characterized in that, A transistor section is provided on the semiconductor substrate and is connected in reverse parallel with the diode section. 11. The semiconductor device according to claim 10, characterized in that, The transistor portion has a collector region of a second conductivity type disposed in a manner that is in contact with the lower surface of the semiconductor substrate. The doping concentration of the second cathode region is the same as that of the current collector region. 12. The semiconductor device according to claim 10, characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The transistor section has: The emitter region of the first conductivity type is disposed in a manner that is in contact with the upper surface of the semiconductor substrate; The drift region; and The base region of the second conductivity type is disposed between the emitter region and the drift region. The doping concentration of the anode region is the same as that of the base region. 13. The semiconductor device according to any one of claims 1 to 7, characterized in that, The carrier lifetime in the drift region of the diode is 1 μs or more. 14. [After correction] The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region are also repeatedly configured in a second direction different from the first direction. At least one of the first cathode regions is surrounded by the second cathode region. 15. [After correction] The semiconductor device according to claim 10, characterized in that, The semiconductor device includes the boundary between the transistor portion and the diode portion. The distance between the boundary extending along the first direction and the end of the first cathode region opposite the boundary extending along the first direction is less than the length of the first cathode region in a second direction different from the first direction. 16. [After correction] The semiconductor device according to claim 5, characterized in that, When viewed from above, the end of the contact hole of the diode portion is located outside the boundary extending along the second direction. When viewed from above, the length of the contact hole protruding from the boundary extending along the second direction is less than the length of the repeating structure of the first cathode region and the second cathode region in the first direction. 17. [After correction] The semiconductor device according to claim 1, characterized in that, At least one second cathode region is surrounded by the first cathode region. The diode portion has a margin region of a second conductivity type that is disposed in contact with the lower surface of the semiconductor substrate and surrounds the first cathode region. 18.[Additional] The semiconductor device according to claim 1, characterized in that, A chamfered portion is provided at the outermost corner of one or more first cathode regions. 19.[Additional] The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region are also repeatedly configured in a second direction different from the first direction. The end of the first cathode region in the first direction is positioned further inward than the end of the second cathode region in the first direction. 20.[Additional] The semiconductor device according to claim 19, characterized in that, The end of the first cathode region in the second direction is positioned further inward than the end of the second cathode region in the second direction. 21.[Additional] The semiconductor device according to claim 1 or 7, characterized in that, The repeat interval is greater than 40 μm. 22.[Additional] The semiconductor device according to claim 4, characterized in that, The area ratio is less than 0.4. 23.[Additional] A method for manufacturing a semiconductor device, characterized in that the semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface and a drift region having a first conductivity type, and a diode portion is disposed on the semiconductor substrate. A first cathode region of a first conductivity type and a second cathode region of a second conductivity type are formed. The first cathode region of the first conductivity type is disposed in contact with the lower surface of the semiconductor substrate and has a higher doping concentration than the drift region. The second cathode region of the second conductivity type is disposed in contact with the lower surface of the semiconductor substrate. In the formation of the first cathode region and the second cathode region The first cathode region and the second cathode region are repeatedly arranged in a first direction, and the repeating spacing between the first cathode region and the second cathode region in the first direction is less than 200 μm. The area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less. 24.[Additional] The method for manufacturing a semiconductor device according to claim 23 is characterized in that, The semiconductor device includes a transistor section disposed on the semiconductor substrate and connected in reverse parallel with the diode section. The transistor portion has a collector region of a second conductivity type disposed in a manner that is in contact with the lower surface of the semiconductor substrate. The current collector region is formed using the same process as the second cathode region. 25.[Additional] The method for manufacturing a semiconductor device according to claim 23 is characterized in that, The semiconductor device includes a transistor section disposed on the semiconductor substrate and connected in reverse parallel with the diode section. The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The transistor section has: The emitter region of the first conductivity type is disposed in a manner that is in contact with the upper surface of the semiconductor substrate; The drift region; and The base region of the second conductivity type is disposed between the emitter region and the drift region. The anode region and the base region are formed through a common process. 26.[Additional] The method for manufacturing a semiconductor device according to claim 23 is characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. Set the initial value of the design value of the doping concentration in the anode region. The forward voltage-reverse recovery loss characteristics of the diode section were obtained using the initial value for multiple repetitive intervals. The design value of the doping concentration in the anode region is adjusted based on the forward voltage-reverse recovery loss characteristics for the multiple repeating intervals. 27.[Additional] The method for manufacturing a semiconductor device according to claim 23 is characterized in that, Set the repeat interval to below 80 μm. 28.[Additional] The method for manufacturing a semiconductor device according to claim 27 is characterized in that, Set the repeat interval to 40 μm or more.

Claims

1. A semiconductor device, characterized in that, It comprises a semiconductor substrate having an upper surface and a lower surface, and a diode portion is disposed on the semiconductor substrate. The diode section has: A drift region of a first conductivity type is disposed on the semiconductor substrate; A first cathode region of a first conductivity type is disposed in contact with the lower surface of the semiconductor substrate, and the doping concentration is higher than that of the drift region. as well as The second cathode region of the second conductivity type is disposed in contact with the lower surface of the semiconductor substrate. The first cathode region and the second cathode region are repeatedly arranged in a first direction, and the repeating distance between the first cathode region and the second cathode region in the first direction is more than 40 μm and less than 200 μm. The area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

2. The semiconductor device according to claim 1, characterized in that, The repeat interval is greater than 80 μm and less than 160 μm.

3. The semiconductor device according to claim 2, characterized in that, The area ratio is below 0.

6.

4. The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region each have a long side in a direction different from the first direction. The area ratio is less than 0.

5.

5. The semiconductor device according to claim 1, characterized in that, The first cathode region and the second cathode region are also repeatedly configured in a second direction different from the first direction. The area ratio is below 0.

6.

6. The semiconductor device according to claim 1, characterized in that, The repeat interval is greater than 100 μm and less than 130 μm.

7. The semiconductor device according to claim 1, characterized in that, The repeat interval is greater than 40 μm and less than 80 μm.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The dose of dopant ions in the anode region is 5.0 × 10⁻⁶. 12 / cm 2 Above and 5.0×10 13 / cm 2 the following.

9. The semiconductor device according to claim 8, characterized in that, The dose of dopant ions in the second cathode region is 1.0 × 10⁻⁶. 13 / cm 2 Above and 1.0×10 14 / cm 2 the following.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that, A transistor section is provided on the semiconductor substrate and is connected in reverse parallel with the diode section.

11. The semiconductor device according to claim 10, characterized in that, The transistor portion has a collector region of a second conductivity type disposed in a manner that is in contact with the lower surface of the semiconductor substrate. The doping concentration of the second cathode region is the same as that of the current collector region.

12. The semiconductor device according to claim 10, characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The transistor section has: The emitter region of the first conductivity type is disposed in a manner that is in contact with the upper surface of the semiconductor substrate; The drift region; as well as The base region of the second conductivity type is disposed between the emitter region and the drift region. The doping concentration of the anode region is the same as that of the base region.

13. The semiconductor device according to any one of claims 1 to 7, characterized in that, The carrier lifetime in the drift region of the diode is 1 μs or more.

14. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a semiconductor substrate having an upper surface and a lower surface and a drift region having a first conductivity type, and a diode portion is disposed on the semiconductor substrate. A first cathode region of a first conductivity type and a second cathode region of a second conductivity type are formed. The first cathode region of the first conductivity type is disposed in contact with the lower surface of the semiconductor substrate and has a higher doping concentration than the drift region. The second cathode region of the second conductivity type is disposed in contact with the lower surface of the semiconductor substrate. In the formation of the first cathode region and the second cathode region The first cathode region and the second cathode region are repeatedly arranged in a first direction, and the repeating distance between the first cathode region and the second cathode region in the first direction is more than 40 μm and less than 200 μm. The area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The semiconductor device includes a transistor section disposed on the semiconductor substrate and connected in reverse parallel with the diode section. The transistor portion has a collector region of a second conductivity type disposed in a manner that is in contact with the lower surface of the semiconductor substrate. The current collector region is formed using the same process as the second cathode region.

16. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The semiconductor device includes a transistor section disposed on the semiconductor substrate and connected in reverse parallel with the diode section. The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. The transistor section has: The emitter region of the first conductivity type is disposed in a manner that is in contact with the upper surface of the semiconductor substrate; The drift region; as well as The base region of the second conductivity type is disposed between the emitter region and the drift region. The anode region and the base region are formed through a common process.

17. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The diode portion has a second conductivity type anode region disposed in a manner that is in contact with the upper surface of the semiconductor substrate. Set the initial value of the design value of the doping concentration in the anode region. The forward voltage-reverse recovery loss characteristics of the diode section were obtained using the initial value for multiple repetitive intervals. The design value of the doping concentration in the anode region is adjusted based on the forward voltage-reverse recovery loss characteristics for the multiple repeating intervals.

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