Automatic test method and system for gate embedded MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device

Abstract

The invention relates to the technical field of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device testing, in particular to an automatic testing method and system for a gate embedded MOSFET device. The method comprises the following steps of: corroding a device, acquiring a grid voltage and a grid leakage current of each test point on a corresponding corrosion surface of the device after each corrosion, and analyzing a grid material uniformity coefficient corresponding to each corrosion surface; then analyzing the change of the overall amplitude of the grid voltage of the test points on different corrosion surfaces, and obtaining interlayer voltage stability parameters; further evaluating interlayer isolation stability parameters based on the amplitudes of the gate leakage currents of different test points on different corrosion surfaces; and a device test result is comprehensively obtained. According to the method, the parameter performance and change of the device under different corrosion depths are measured for multiple times, and the material uniformity and isolation performance in the device are quantitatively evaluated, so that the accuracy of the test result of the gate embedded MOSFET device is improved.

Description

Technical Field

[0001] This invention relates to the field of MOSFET device testing technology, and specifically to an automated testing method and system for gate-embedded MOSFET devices. Background Technology

[0002] The buried-gate MOSFET is an innovative design based on the traditional structure. Its core feature is that the gate pattern region (including the buried gate and the connection gate) is completely embedded inside the substrate. Pre-cracked trenches are provided on both sides of the buried gate, and it is isolated from the active layer by the gate oxide layer. Testing the buried-gate MOSFET is crucial during the research and development and production process.

[0003] Currently, the testing of gate-embedded MOSFET devices generally adopts a surface single-point sampling mode, focusing on verifying macroscopic parameters such as on-resistance and threshold voltage. However, due to the layered doping process, the doping concentration and oxide layer thickness in the gate depth direction of gate-embedded MOSFETs are easily affected by process fluctuations. Conventional tests cannot reflect the differences in internal gate control capability and isolation layer insulation, which may lead to the risk that the device passes surface tests but fails in reality, resulting in low accuracy of test results for gate-embedded MOSFET devices. Summary of the Invention

[0004] To address the technical problem of low accuracy in testing gate-embedded MOSFET devices, the present invention aims to provide an automated testing method and system for gate-embedded MOSFET devices. The specific technical solution adopted is as follows: An automated testing method for a gate-embedded MOSFET device, the method comprising: The device is etched, and after each etching, the gate voltage and gate leakage current at a preset drain current are obtained at each test point on the corresponding etched surface. The test point locations on different etched surfaces are consistent. For each etched surface, based on the discrete characteristics of the gate voltage and gate leakage current corresponding to different test points, and the amplitude level of the gate leakage current at all test points, the gate material uniformity coefficient of the corresponding etched surface is obtained; based on the overall amplitude variation of the gate voltage at test points on different etched surfaces, the interlayer voltage stability parameters of the device are obtained. Based on the amplitude variation of the gate leakage current at the same location on different etched surfaces, the deviation of the overall amplitude variation of the gate leakage current at all test points on different etched surfaces, and the deviation of the gate leakage current at each test point on each etched surface relative to the gate leakage current at all test points, the interlayer isolation stability parameters of the device are obtained. The device test results are obtained based on the interlayer voltage stability parameters, the interlayer isolation stability parameters, and the gate material uniformity coefficient of each etched surface.

[0005] Furthermore, the method for etching the device includes: The single etching depth is determined based on the total embedding depth of the device gate and the preset test level, and the single etching time is determined based on the single etching depth and the preset etching rate; during each etching, the device is immersed in the etching solution for the single etching time.

[0006] Furthermore, the method for obtaining the uniformity coefficient of the gate material includes: The coefficient of variation of the gate voltage at all test points on the etched surface is used as the first material inhomogeneity parameter. Based on the range and standard deviation of the gate leakage current corresponding to all test points on the etched surface, the extreme non-uniformity parameter of the leakage current is obtained; the extreme non-uniformity parameter and the mean value of the gate leakage current corresponding to the test points are fused to obtain the second material non-uniformity parameter. By fusing the first material inhomogeneity parameter and the second material inhomogeneity parameter and normalizing them with negative correlation, the gate material uniformity coefficient is obtained.

[0007] Furthermore, the method for obtaining the interlayer voltage stability parameters includes: Based on the distribution characteristics of the gate voltage at all test points on each etched surface, a reference voltage for each etched surface is obtained; based on the discrete characteristics of the variation differences of the reference voltage between adjacent etched surfaces and the variation trend of the reference voltage for different etched surfaces, interlayer voltage stability parameters are obtained.

[0008] Furthermore, based on the discrete characteristics of the variation differences of the reference voltage between adjacent corrosion surfaces, and the variation trends of the reference voltage for different corrosion surfaces, interlayer voltage stability parameters are obtained, including: The difference between each corrosion surface and its adjacent previous corrosion surface corresponding to the reference voltage is taken as the voltage change difference, and the standard deviation of the voltage change difference between all adjacent corrosion surfaces is taken as the voltage change fluctuation parameter; the change curve of the voltage change difference is fitted, and the linear regression coefficient of the change curve is taken as the voltage change trend parameter. By integrating voltage fluctuation parameters and voltage trend parameters and normalizing them with negative correlation, interlayer voltage stability parameters are obtained.

[0009] Furthermore, the method for obtaining the interlayer isolation stability parameters includes: Based on the amplitude variation of the gate leakage current at the same location on different etched surfaces, and the deviation of the overall amplitude variation of the gate leakage current at all test points on different etched surfaces, a first deviation parameter is obtained. On each etched surface, the leakage current deviation of each test point is obtained based on the deviation of the gate leakage current of each test point from the average level of the gate leakage current of all test points; the leakage current deviations of all test points at the same position on all etched surfaces are combined to obtain a second deviation parameter. By fusing the first deviation parameter and the second deviation parameter and normalizing them with negative correlation, the interlayer leakage current similarity parameter at the corresponding test point is obtained; by combining the interlayer leakage current similarity parameters at all test points, the interlayer isolation stability parameter of the device is obtained.

[0010] Furthermore, the method for obtaining the first deviation parameter includes: Based on the distribution characteristics of the gate leakage current at all test points on each etched surface, the reference leakage current of each etched surface is obtained; based on the difference between the reference leakage currents of all adjacent etched surfaces, the overall interlayer leakage current difference is obtained. For all test points at the same location, the interlayer leakage current difference at each test point is obtained based on the difference between the gate leakage currents on adjacent etched surfaces. A first deviation parameter is obtained based on the deviation of the interlayer leakage current difference at all test points at each location relative to the overall interlayer leakage current difference.

[0011] Furthermore, the method for obtaining the device test results includes: Based on the distribution characteristics of the gate material uniformity coefficient of all etched surfaces, the first quality parameter of the device is obtained; the interlayer voltage stability parameter and the interlayer isolation stability parameter are fused to obtain the second quality parameter of the device; the first quality parameter and the second quality parameter are fused and normalized to obtain the device quality coefficient; the device test result is determined based on the device quality coefficient.

[0012] Furthermore, the determination of device test results based on the device quality coefficient includes: When the device quality coefficient is greater than a preset threshold, the device is deemed to have passed the test; otherwise, the device is deemed to have failed the test.

[0013] An automated testing system for a gate-embedded MOSFET device is provided. The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the automated testing method for the gate-embedded MOSFET device.

[0014] The present invention has the following beneficial effects: This invention etches a device to analyze it at different depths, then obtains the gate voltage and gate leakage current at each test point on the etched surface after each etching, providing a data foundation for subsequent analysis. The test points on different etched surfaces are consistently distributed. Based on the discrete characteristics of the gate voltage and gate leakage current at different test points on each etched surface, the invention analyzes the dispersion of device test parameters caused by material doping inhomogeneity at the same depth. Furthermore, it assesses the local damage of the gate isolation layer using the amplitude of the gate leakage current at all test points, obtaining the gate material uniformity coefficient for the corresponding etched surface. Finally, based on the variation characteristics of the gate voltage with device depth, the invention further analyzes... This invention analyzes the overall amplitude variation of the gate voltage at test points on different etched surfaces to obtain the interlayer voltage stability parameters of the device. Then, based on the amplitude variation of the gate leakage current at the same location on different etched surfaces, and the deviation of the gate leakage current amplitude variation relative to the overall amplitude variation of the gate leakage current at all test points on different etched surfaces, combined with the deviation of the gate leakage current at each test point on each etched surface relative to the gate leakage current at all test points, the isolation differences at different test points on different etched surfaces are evaluated, thereby obtaining the interlayer isolation stability parameters of the device. Finally, based on the interlayer voltage stability parameters, interlayer isolation stability parameters, and the gate material uniformity coefficient of each etched surface, the device test results are obtained. This invention quantitatively evaluates the internal material uniformity and isolation performance of the device by repeatedly measuring the parameter performance and changes of the device at different etching depths, thereby improving the accuracy of test results for gate-embedded MOSFET devices. Attached Figure Description

[0015] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart illustrating an automated testing method for a gate-embedded MOSFET device according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a method for obtaining interlayer isolation stability parameters according to an embodiment of the present invention. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of an automated testing method and system for gate-embedded MOSFET devices proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0019] The following description, in conjunction with the accompanying drawings, details the specific scheme of the automated testing method and system for gate-embedded MOSFET devices provided by this invention.

[0020] In order to conduct more comprehensive testing of gate-embedded MOSFET devices, this invention selects chemical etching method to etch the embedded gate of the MOSFET device. By controlling the etching progress and measuring the parameter performance of the device at different etching depths multiple times, the depth performance of the gate-embedded MOSFET device is quantitatively evaluated through the overall performance and changes of the parameters, so as to evaluate the device test results.

[0021] Please see Figure 1 The diagram illustrates a flowchart of an automated testing method for a gate-embedded MOSFET device according to an embodiment of the present invention, specifically including: Step S1: Etch the device, and after each etching, obtain the gate voltage and gate leakage current at a preset drain current for each test point on the corresponding etched surface of the device. The test point locations on different etched surfaces are distributed in the same way.

[0022] It should be noted that in this embodiment of the invention, the gate-embedded MOSFET device (hereinafter referred to as the device) needs to be subjected to corrosion test in order to analyze the doping concentration of the material (such as polysilicon) in the depth direction of the device gate, evaluate the device quality, and provide a reference for subsequent process optimization; if the test is a destructive test, then the device is a sampling test. Meanwhile, in order to eliminate interference from other quality factors, before testing the sampled devices, the embodiments of the present invention also need to perform routine surface inspection on the devices to eliminate the influence of defects such as surface scratches and pin oxidation, so as to avoid interfering with the test results and thus obtain the devices to be tested.

[0023] It should be noted that the testing and analysis methods are consistent for each device. Here, we will only take any one device under test as an example for analysis and description, and will not go into detail about each one.

[0024] In one embodiment of the present invention, the device is first etched multiple times with chemical reagents, and after each etching, the device is subjected to performance testing to obtain the test parameters of each test point on the corresponding etched surface of the device, in order to prepare for subsequent quality assessment. The test points are evenly distributed on each etched surface, for example, in a cross or square shape, with a spacing of 50 μm. A total of 10 test points are distributed on each etched surface. The implementer can also adjust the test point layout scheme according to the device. The test points are distributed in the same location on different (depth) corrosion surfaces, that is, the same location corresponds to multiple test points on different (depth) corrosion surfaces. After each corrosion, the implementer can use photolithography or laser marking to determine the test points at the same location on different corrosion surfaces for subsequent analysis at the depth level, which will not be elaborated further.

[0025] Preferably, in one embodiment of the present invention, the method for etching the device includes: determining the single etching depth based on the total embedding depth of the device gate and a preset test level; determining the single etching time based on the single etching depth and a preset etching rate; and immersing the device in the etching solution for the single etching time during each etching process.

[0026] The specific operations of corrosion are well-known techniques, and the general process is briefly described here: (1) Test preparation: Clean the surface of the device with isopropanol ultrasonically to remove oil and dust, and then put it into a vacuum drying oven for 30 minutes to eliminate the influence of surface moisture on contact resistance; protect the non-test area of ​​the device with photoresist and only expose the edge area where the depth profile needs to be prepared.

[0027] (2) Calibration rate determination: For the substrate material of the device, a mixed etching solution of hydrofluoric acid-nitric acid-deionized water was prepared with a volume ratio of 1:5:20. One device was selected for pre-etching experiment: The device was immersed in the etching solution with the test surface facing down. It was removed after 10 seconds of etching and rinsed with deionized water for 30 seconds. After drying the surface moisture, the etching depth was measured with a step meter. The above operation was repeated 5 times, and the etching time and depth were recorded, such as 10s→0.15μm, 20s→0.31μm, 30s→0.46μm, etc., for linear fitting, and the etching rate v was calculated (a well-known method, which will not be described in detail). (3) Device etching: The gate embedding depth h of the gate-embedded MOSFET is obtained by obtaining the device design parameters, and then the etching number N is set (i.e., the preset test level N is determined) to obtain the single etching depth. Then based on the depth of a single corrosion attack The time required for a single corrosion cycle can be determined by setting a preset corrosion rate v. During each etching process, an automatic clamping device is used to immerse the device in the etching solution for a single etching time t, after which the device is removed, cleaned, and dried in preparation for subsequent testing.

[0028] It should be noted that the corrosion test conditions during device testing should be consistent with the corrosion test conditions when calibrating the corrosion rate to avoid inconsistent corrosion results.

[0029] Considering that the two main test parameters during device testing are threshold voltage and gate-substrate leakage current, the threshold voltage refers to the minimum gate-source voltage required to start conduction, reflecting the channel formation and conduction capability; the gate-substrate leakage current refers to the leakage current of the isolation layer between the gate and the substrate, representing the insulation integrity of the isolation layer between the gate and the substrate. Both are affected by the quality of semiconductor materials and processes; therefore, the test parameters should at least include the gate voltage at a preset drain current and the gate leakage current at a preset voltage. During the test, for each test point on each etched surface, a stepped voltage scan was used (a stepped voltage was applied to the gate, 0-5V, with a step size of 0.1V). The preset drain current was set to 1μA, and the gate voltage was recorded when the drain current first reached the preset drain current, so as to capture the initial state of channel formation more sensitively and earlier. The preset voltage was set to 30V (1.2 times the rated voltage). The preset voltage was applied to the gate, and 0V was applied to the substrate. The source and drain were left floating to avoid interference between the source and drain currents. After each test point was left to stand for 10 seconds, the gate leakage current (gate-substrate leakage current) was recorded.

[0030] It should be noted that the above testing steps are well-known technical methods. The test parameters of the device can be automatically scanned by an automatic testing device, and the obtained test parameters can be uploaded to the data management platform for analysis and calculation. Therefore, they will not be described in detail. The implementer can also adjust the preset drain current and preset voltage, but the preset drain current should not be too large, and the test conditions of all test points should be consistent. The implementer can also collect the gate voltage and gate drain current at each test point multiple times, and take the mode or the average to avoid single random errors.

[0031] It should be noted that, in order to facilitate subsequent analysis and calculation, all test parameters (gate voltage and gate leakage current) need to be standardized after acquisition, such as removing dimensions.

[0032] Step S2: On each etched surface, based on the discrete characteristics of the gate voltage and gate leakage current corresponding to different test points, and the amplitude level of the gate leakage current at all test points, obtain the gate material uniformity coefficient of the corresponding etched surface; based on the overall amplitude variation of the gate voltage at the test points on different etched surfaces, obtain the interlayer voltage stability parameters of the device.

[0033] Considering that all test points on each etched surface are roughly at the same depth, and that material doping and oxidation processes at the same depth are theoretically carried out simultaneously, the test performance of different test points should be similar. The smaller the difference in gate voltage and gate leakage current between different test points, the more stable the material performance of the etched layer. Furthermore, considering that the gate leakage current corresponding to each test point on each etched layer is similar and has a low amplitude, it indicates that the oxidation process of the gate is more uniform and the gate isolation layer is more dense and defect-free. Therefore, in this embodiment of the invention, the gate material uniformity coefficient of each etched surface is obtained based on the discrete characteristics of the gate voltage and gate leakage current corresponding to different test points, as well as the amplitude level of the gate leakage current at all test points. The gate material uniformity coefficient initially reflects the material doping situation or process uniformity at a single depth level, which prepares for the subsequent comprehensive evaluation of device test results by combining the interlayer test performance differences between different etched surfaces.

[0034] Preferably, in one embodiment of the present invention, on each etched surface, considering that the coefficient of variation can help evaluate discrete characteristics, the larger the coefficient of variation of the gate voltage corresponding to different test points, the more uniform the overall doping of the gate material is, which may affect the channel conduction capability; also considering that the range and standard deviation can also help evaluate discrete characteristics, and for gate leakage current, an excessive gate leakage current at any test point will affect device performance, while the range can further reflect extreme abnormal situations, i.e., whether there is local damage to the gate isolation layer, thus affecting device performance, based on the evaluation of discrete characteristics by the standard deviation; at the same time, the smaller the gate leakage current, the better the gate isolation effect, and vice versa, it indicates that there may be damage and uneven gate material; based on this, the method for obtaining the gate material uniformity coefficient includes: The coefficient of variation of the gate voltage corresponding to all test points on the etched surface is used as the first material non-uniformity parameter; the extreme non-uniformity parameter of the leakage current is obtained based on the range and standard deviation of the gate leakage current corresponding to all test points on the etched surface; the extreme non-uniformity parameter and the mean value of the gate leakage current corresponding to the test points are fused to obtain the second material non-uniformity parameter; the first material non-uniformity parameter and the second material non-uniformity parameter are fused and negatively correlated and normalized to obtain the gate material uniformity coefficient.

[0035] Specifically, the calculation of the coefficient of variation is a well-known technique and will not be elaborated further, thus obtaining the first material non-uniformity parameter; then, the standard deviation of the gate leakage current corresponding to all test points on the etched surface is mapped to the exponential function exp(-x) with the natural constant e as the base, and the range of the gate leakage current corresponding to all test points on the etched surface is multiplied by the exponential function value to obtain the extreme non-uniformity parameter of the leakage current; the smaller the standard deviation, the more concentrated the gate leakage current distribution is at different test points, while the larger the range, the more extreme the local anomaly exists, such as local damage to the isolation layer, and the larger the extreme non-uniformity parameter of the leakage current. Then, the mean value of the gate current corresponding to all test points on the etched surface is multiplied by the extreme non-uniformity parameter to obtain the second material non-uniformity parameter. The larger the mean value and the larger the extreme non-uniformity parameter, the more likely the gate isolation layer is damaged. The larger the second material non-uniformity parameter, the less ideal the test results of the etched surface are. Finally, the first material non-uniformity parameter and the second material non-uniformity parameter are multiplied, and the product is mapped to the exponential function exp(-x) with the natural constant e as the base and normalized with negative correlation to obtain the gate material uniformity coefficient.

[0036] In other embodiments of the present invention, the implementer may also use other negative correlation normalization methods, or may use addition or weighted summation to combine the two, which will not be elaborated further.

[0037] Considering that in a vertically downward-extending buried gate structure, ideally, the potential from the source to the substrate is not constant along the gate depth direction, and the source-bulk potential difference of the local channel at different depths increases linearly with depth, resulting in a synchronous increase in the gate voltage required to turn on. Based on this, the interlayer voltage stability parameters of the device can be obtained by observing the overall amplitude variation of the gate voltage at test points on different etched surfaces. These interlayer voltage stability parameters, from the perspective of the interlayer variation of the gate voltage on different etched surfaces, preliminarily reflect the device performance and prepare for subsequent evaluation of test results.

[0038] Preferably, in one embodiment of the present invention, the reference voltage of the etched surface is first comprehensively evaluated based on the gate voltage of all test points on each etched surface, thereby characterizing the gate voltage level at different depths; considering that ideally the gate voltage should increase linearly with depth (the order of etched surfaces), the variation trend of the reference voltage corresponding to different etched surfaces can be analyzed to assess whether it conforms to the ideal variation characteristics; at the same time, the discrete characteristics of the variation difference of the reference voltage corresponding to adjacent etched surfaces reflect the stability of the voltage difference to a certain extent; therefore, the method for obtaining the interlayer voltage stability parameters includes: Based on the distribution characteristics of the gate voltage at all test points on each etched surface, the reference voltage of each etched surface is obtained; based on the discrete characteristics of the variation differences of the corresponding reference voltages between adjacent etched surfaces, and the variation trend of the corresponding reference voltages of different etched surfaces, the interlayer voltage stability parameters are obtained.

[0039] Specifically, the distribution characteristics are characterized by the mean value. The mean value of the gate voltage corresponding to all test points on each etched surface is used as the reference voltage of that etched surface. This characterizes the gate voltage level of each etched surface, which facilitates subsequent analysis of the variation characteristics between different etched surfaces and evaluation of interlayer voltage stability parameters. In particular, considering that ideally, the reference voltage corresponding to an etched surface increases linearly with the etched surface sequence (depth), the difference between the reference voltages corresponding to adjacent etched surfaces should be relatively similar with small fluctuations. The standard deviation can help measure the fluctuations, thereby obtaining the voltage change fluctuation parameter. The voltage change fluctuation parameter can help reflect the stability of the change between the reference voltages corresponding to adjacent etched surfaces, and thus assess whether the reference voltage (gate voltage) changes linearly with depth. Furthermore, considering that fitting the curve of the reference voltage change with the etched surface sequence (depth) can help assess its linear change trend, thereby helping to assess whether the reference voltage (gate voltage) increases linearly with depth; The difference in reference voltage between each corrosion surface and its adjacent previous corrosion surface is taken as the voltage change difference, and the standard deviation of the voltage change difference between all adjacent corrosion surfaces is taken as the voltage change fluctuation parameter. The change curve of the voltage change difference is fitted, and the linear regression coefficient of the change curve is taken as the voltage change trend parameter. The voltage change fluctuation parameter and the voltage change trend parameter are fused and negatively correlated and normalized to obtain the interlayer voltage stability parameter.

[0040] Specifically, the voltage variation difference is measured by the difference, that is, the reference voltage of each corrosion surface is subtracted from the reference voltage of the adjacent previous corrosion surface to obtain the voltage variation difference of each corrosion surface (relative to the previous corrosion surface); the standard deviation of all voltage variation differences is used as the voltage variation fluctuation parameter. Linear fitting of all voltage change differences is performed using the least squares method to obtain change curves. The linear regression coefficients corresponding to the change curves are then mapped to the sigmoid function to obtain voltage change trend parameters. The curve fitting and the acquisition of linear regression coefficients mentioned above are well-known techniques and will not be elaborated further. Finally, the voltage fluctuation parameters are mapped to the exponential function exp(-x) with the natural constant e as the base for negative correlation normalization. Then, the negative correlation normalization result is averaged with the voltage change trend parameters to obtain the inter-layer voltage stability parameters.

[0041] In other embodiments of the present invention, the implementer may also use other negative correlation normalization methods, or may use addition or weighted summation to combine the two, which will not be elaborated further.

[0042] Step S3: Based on the amplitude change of the gate leakage current at the same position on different etched surfaces, the deviation of the overall amplitude change of the gate leakage current at all test points on different etched surfaces, and the deviation of the gate leakage current at each test point on each etched surface relative to the gate leakage current at all test points, the interlayer isolation stability parameters of the device are obtained.

[0043] Considering that the gate leakage current is determined by the tunneling current of the isolation layer, the isolation layers in different layers have the same function, and the thickness and density should not differ with depth. Therefore, the gate leakage current performance corresponding to the test points on different etched surfaces should be similar. Analyzing the amplitude variation of gate leakage current corresponding to test points at the same location on different etched surfaces can help evaluate the consistency of gate leakage current performance at different depths at a single location; analyzing the deviation of the overall amplitude variation of gate leakage current at all test points on different etched surfaces can help evaluate the overall consistency of gate leakage current performance at different depths; analyzing the deviation of gate leakage current at each test point on each etched surface relative to the gate leakage current at all test points can help evaluate the consistency of gate leakage current performance at the same depth. The three analyses, from different perspectives, demonstrate the consistency of gate leakage current performance. This can help assess the consistency of isolation performance of the isolation layer, thereby helping to evaluate the interlayer isolation stability parameters of the device and preparing for subsequent evaluation of device test results.

[0044] Preferably, in one embodiment of the present invention, the method for obtaining the interlayer isolation stability parameter includes: Please see Figure 2 The diagram illustrates a flowchart of a method for obtaining interlayer isolation stability parameters according to an embodiment of the present invention, specifically including: Step S301: Based on the amplitude change of the gate leakage current at the same location on different etched surfaces, and the deviation of the overall amplitude change of the gate leakage current at all test points on different etched surfaces, obtain the first deviation parameter.

[0045] Considering the amplitude variation of gate leakage current at the same location on different etched surfaces, the interlayer difference of gate leakage current at a single test point can be provided; while the overall amplitude variation of gate leakage current at all test points on different etched surfaces can provide the interlayer difference of overall gate leakage current performance on different etched surfaces. Furthermore, considering that analyzing the differences in gate leakage current performance between a single test point and different etched surfaces can help assess the gate leakage current deviation at a single test point, a first deviation parameter can be obtained. The first deviation parameter initially reflects the deviation of the gate leakage current at a single test point relative to the overall performance of all locations, preparing for subsequent evaluation of interlayer isolation stability parameters.

[0046] In a preferred embodiment of the present invention, the method for obtaining the first deviation parameter includes: Based on the distribution characteristics of the gate leakage current at all test points on each etched surface, the reference leakage current of each etched surface is obtained; based on the difference between the reference leakage currents of all adjacent etched surfaces, the overall interlayer leakage current difference is obtained; for all test points at the same location, based on the difference between the corresponding gate leakage currents on adjacent etched surfaces, the interlayer leakage current difference at all test points at each location is obtained; based on the deviation of the interlayer leakage current difference at all test points at each location relative to the overall interlayer leakage current difference, the first deviation parameter is obtained.

[0047] Specifically, the mean value is used to measure the distribution characteristics. The mean value of the gate leakage current of all test points on each etched surface is used as the reference leakage current of its corresponding etched surface to characterize the overall performance. Then, the sum of the absolute values ​​of the differences between the reference currents of all adjacent etched surfaces is used as the overall interlayer leakage current difference. For all test points at any location (test points distributed at the same location, at different depths, or on the etched surface), the sum of the absolute values ​​of the differences between the gate leakage currents corresponding to the test points at that location on all adjacent etched surfaces is taken as the interlayer leakage current difference for all test points at that location. Then, the absolute value of the difference between the interlayer leakage current difference at all test points at each location and the overall interlayer leakage current difference is used as the first deviation parameter at the angle of all test points at that location.

[0048] In step S302, on each etched surface, the leakage current deviation of each test point is obtained based on the deviation of the gate leakage current of each test point from the average level of the gate leakage current of all test points; the leakage current deviations of all test points at the same position on all etched surfaces are combined to obtain the second deviation parameter.

[0049] Considering that the deviation of the gate leakage current of each test point on each etched surface from the average level of the gate leakage current of all test points (reference leakage current) reflects the local deviation of a single test point on a single etched surface, the local deviation of all test points at the same position on all etched surfaces in the depth direction can be combined to comprehensively evaluate the second deviation parameter at the angle of all test points at that position. The second deviation parameter further reflects the deviation of the gate leakage current of a single test point, preparing for the subsequent evaluation of interlayer isolation stability parameters.

[0050] Specifically, on each etched surface, taking any test point as an example, the absolute value of the difference between the gate leakage current of the test point and the reference leakage current is taken as the leakage current deviation of the test point; the sum of the leakage current deviations of all test points on all etched surfaces at the same position as the test point is taken as the second deviation parameter at the angle of all test points at that position.

[0051] Step S303: The first deviation parameter and the second deviation parameter are fused and negatively correlated and normalized to obtain the interlayer leakage current similarity parameter at the corresponding test point; the interlayer isolation stability parameter of the device is obtained by combining the interlayer leakage current similarity parameters at all test points.

[0052] As an example, the first deviation parameter and the second deviation parameter are added together, and the sum is mapped to the exponential function exp(-x) with the natural constant e as the base to adjust the logical relationship, so as to obtain the interlayer leakage current similarity parameter at the corresponding test point. The larger the first deviation parameter and the second deviation parameter are, the greater the difference in interlayer leakage current at the test point, and the smaller the interlayer leakage current similarity parameter at the corresponding test point. Then, the interlayer leakage current similarity parameters at all test points are averaged to obtain the interlayer isolation stability parameter during the period.

[0053] In other embodiments of the present invention, implementers may also use other negative correlation normalization methods, which will not be elaborated further.

[0054] Step S4: Obtain device test results based on interlayer voltage stability parameters, interlayer isolation stability parameters, and gate material uniformity coefficient of each etched surface.

[0055] Considering that interlayer voltage stability parameters, interlayer isolation stability parameters, and gate material uniformity coefficients on each etched surface all reflect the quality or performance of the device from different perspectives, the device test results can be further evaluated.

[0056] Preferably, in one embodiment of the present invention, the method for obtaining device test results includes: Based on the distribution characteristics of the gate material uniformity coefficient of all etched surfaces, the first quality parameter of the device is obtained; the interlayer voltage stability parameter and the interlayer isolation stability parameter are fused to obtain the second quality parameter of the device; the first quality parameter and the second quality parameter are fused and normalized to obtain the device quality coefficient; the device test results are determined based on the device quality coefficient.

[0057] As an example, the average value of the gate material uniformity coefficient of all etched surfaces is used as the first quality parameter; the interlayer voltage stability parameter and the interlayer isolation stability parameter are multiplied and fused to obtain the second quality parameter; then the first quality parameter and the second quality parameter are averaged to obtain the device quality coefficient; finally, the device test results are determined based on the device quality coefficient.

[0058] It should be noted that since the values ​​of the first mass parameter and the second mass parameter are both in the range of 0-1, the mean values ​​of the first mass parameter and the second mass parameter do not need to be further normalized. In a preferred embodiment of the present invention, determining the device test results based on the device quality coefficient includes: When the device quality coefficient is greater than the preset threshold, the device is deemed to have passed the test; otherwise, the device is deemed to have failed the test.

[0059] It should be noted that the preset threshold is set to 0.7, and implementers can adjust it according to actual applications, but it should not be too small. When the device quality coefficient is greater than 0.7, it indicates that the material doping and process of the device in the depth direction are stable, the device performance is also stable, and the device test is qualified. Conversely, it indicates that the device only passes the surface test, and the internal material uniformity and isolation have changed significantly, and the test is unqualified. Implementers can trace the device production and process flow based on the unqualified devices, thereby assisting in optimization.

[0060] The present invention also proposes an automated testing system for gate-embedded MOSFET devices. The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the automated testing method for gate-embedded MOSFET devices described in steps S1-S4 above.

[0061] In summary, this invention etches the device and, after each etching, obtains the gate voltage and gate leakage current at each test point on the corresponding etched surface under a preset drain current and a preset voltage, and analyzes the gate material uniformity coefficient corresponding to each etched surface. Then, it analyzes the overall amplitude variation of the gate voltage at test points on different etched surfaces to obtain the interlayer voltage stability parameters of the device. Furthermore, based on the amplitude of the gate leakage current at different test points on different etched surfaces, it evaluates the interlayer isolation stability parameters of the device. Finally, it integrates the interlayer voltage stability parameters, interlayer isolation stability parameters, and the gate material uniformity coefficient of each etched surface to obtain the device test results. This invention quantitatively evaluates the internal material uniformity and isolation performance of the device by repeatedly measuring the parameter performance and changes of the device at different etching depths, thereby improving the accuracy of test results for gate-embedded MOSFET devices.

[0062] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0063] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. An automated testing method for gate-embedded MOSFET devices, characterized in that, The method includes: The device is etched, and after each etching, the gate voltage and gate leakage current at a preset drain current are obtained at each test point on the corresponding etched surface. The test point locations on different etched surfaces are consistent. For each etched surface, based on the discrete characteristics of the gate voltage and gate leakage current corresponding to different test points, and the amplitude level of the gate leakage current at all test points, the gate material uniformity coefficient of the corresponding etched surface is obtained; based on the overall amplitude variation of the gate voltage at test points on different etched surfaces, the interlayer voltage stability parameters of the device are obtained. Based on the amplitude variation of the gate leakage current at the same location on different etched surfaces, the deviation of the overall amplitude variation of the gate leakage current at all test points on different etched surfaces, and the deviation of the gate leakage current at each test point on each etched surface relative to the gate leakage current at all test points, the interlayer isolation stability parameters of the device are obtained. The device test results are obtained based on the interlayer voltage stability parameters, the interlayer isolation stability parameters, and the gate material uniformity coefficient of each etched surface.

2. The automated testing method for a gate-embedded MOSFET device according to claim 1, characterized in that, The method for etching the device includes: The single etching depth is determined based on the total embedding depth of the device gate and the preset test level, and the single etching time is determined based on the single etching depth and the preset etching rate; during each etching, the device is immersed in the etching solution for the single etching time.

3. The automated testing method for a gate-embedded MOSFET device according to claim 1, characterized in that, The method for obtaining the uniformity coefficient of the gate material includes: The coefficient of variation of the gate voltage at all test points on the etched surface is used as the first material inhomogeneity parameter. Based on the range and standard deviation of the gate leakage current corresponding to all test points on the etched surface, the extreme non-uniformity parameter of the leakage current is obtained; the extreme non-uniformity parameter and the mean value of the gate leakage current corresponding to the test points are fused to obtain the second material non-uniformity parameter. By fusing the first material inhomogeneity parameter and the second material inhomogeneity parameter and normalizing them with negative correlation, the gate material uniformity coefficient is obtained.

4. The automated testing method for a gate-embedded MOSFET device according to claim 1, characterized in that, The method for obtaining the interlayer voltage stability parameters includes: Based on the distribution characteristics of the gate voltage at all test points on each etched surface, a reference voltage for each etched surface is obtained; based on the discrete characteristics of the variation differences of the reference voltage between adjacent etched surfaces and the variation trend of the reference voltage for different etched surfaces, interlayer voltage stability parameters are obtained.

5. The automated testing method for a gate-embedded MOSFET device according to claim 4, characterized in that, Based on the discrete characteristics of the variation differences of the reference voltage between adjacent corrosion surfaces, and the variation trends of the reference voltage for different corrosion surfaces, interlayer voltage stability parameters are obtained, including: The difference between each corrosion surface and its adjacent previous corrosion surface corresponding to the reference voltage is taken as the voltage change difference, and the standard deviation of the voltage change difference between all adjacent corrosion surfaces is taken as the voltage change fluctuation parameter; the change curve of the voltage change difference is fitted, and the linear regression coefficient of the change curve is taken as the voltage change trend parameter. By integrating voltage fluctuation parameters and voltage trend parameters and normalizing them with negative correlation, interlayer voltage stability parameters are obtained.

6. The automated testing method for a gate-embedded MOSFET device according to claim 1, characterized in that, The method for obtaining the interlayer isolation stability parameters includes: Based on the amplitude variation of the gate leakage current at the same location on different etched surfaces, and the deviation of the overall amplitude variation of the gate leakage current at all test points on different etched surfaces, a first deviation parameter is obtained. On each etched surface, the leakage current deviation of each test point is obtained based on the deviation of the gate leakage current of each test point from the average level of the gate leakage current of all test points; the leakage current deviations of all test points at the same position on all etched surfaces are combined to obtain a second deviation parameter. By fusing the first deviation parameter and the second deviation parameter and normalizing them with negative correlation, the interlayer leakage current similarity parameter at the corresponding test point is obtained; by combining the interlayer leakage current similarity parameters at all test points, the interlayer isolation stability parameter of the device is obtained.

7. The automated testing method for a gate-embedded MOSFET device according to claim 6, characterized in that, The method for obtaining the first deviation parameter includes: Based on the distribution characteristics of the gate leakage current at all test points on each etched surface, the reference leakage current of each etched surface is obtained; based on the difference between the reference leakage currents of all adjacent etched surfaces, the overall interlayer leakage current difference is obtained. For all test points at the same location, the interlayer leakage current difference at each test point is obtained based on the difference between the gate leakage currents on adjacent etched surfaces. A first deviation parameter is obtained based on the deviation of the interlayer leakage current difference at all test points at each location relative to the overall interlayer leakage current difference.

8. The automated testing method for a gate-embedded MOSFET device according to claim 1, characterized in that, The methods for obtaining the device test results include: Based on the distribution characteristics of the gate material uniformity coefficient of all etched surfaces, the first quality parameter of the device is obtained; the interlayer voltage stability parameter and the interlayer isolation stability parameter are fused to obtain the second quality parameter of the device; the first quality parameter and the second quality parameter are fused and normalized to obtain the device quality coefficient; the device test result is determined based on the device quality coefficient.

9. The automated testing method for a gate-embedded MOSFET device according to claim 8, characterized in that, The device test results are determined based on the device quality coefficient, including: When the device quality coefficient is greater than a preset threshold, the device is deemed to have passed the test; otherwise, the device is deemed to have failed the test.

10. An automated testing system for a gate-embedded MOSFET device, the system comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the automated testing method for a gate-embedded MOSFET device as described in any one of claims 1 to 9.

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