A method for fabricating an optical waveguide based on a transparent substrate and the optical waveguide thereof.

Abstract

This invention relates to the field of photonic computing, specifically disclosing a method for fabricating an optical waveguide based on a transparent substrate and the optical waveguide itself. The method includes the following steps: S101, depositing a masking layer on a first surface of the transparent substrate; S102, sequentially depositing a waveguide layer and an imprinting adhesive layer on a second surface of the masking layer; S103, imprinting the imprinting adhesive layer using an imprinting soft stencil to form an imprinted pattern on the imprinting adhesive layer; S104, etching the residual layer in the imprinted groove based on the imprinted pattern; S105, over-etching the waveguide layer based on the imprinted pattern to obtain a patterned waveguide layer; S106, removing the imprinting adhesive layer to obtain the patterned waveguide layer; S107, depositing a capping layer on the patterned waveguide layer, such that the capping layer and the masking layer encapsulate the waveguide layer. Further, the masking layers are deposited using different deposition processes to obtain a double-layer structure with a flat surface.

Description

Technical Field

[0001] This invention relates to the field of photonic computing technology, and in particular to a method for fabricating an optical waveguide based on a transparent substrate and an optical waveguide based on a transparent substrate. Background Technology

[0002] The increasing demand for AI chip computing power, driven by the need for high-density computing, machine learning, parallel computing, and HPC applications in fields such as AI, places higher demands on chips. For example, AMD's new generation EPYC processors support up to 384 threads and up to 192 cores, including 16 "Zen 5" CCDs (core composite chips). These CCD chips utilize TSMC's 3nm process, while the central I / O chip (IOD) employs a 4nm process, demonstrating the demand for higher process technologies in the AI ​​era. As AI computing power demands continue to rise and hardware circuits become increasingly complex, traditional PCB organic substrates and TSV technology may become bottlenecks restricting the production of high-performance computing chips like AI chips in the future.

[0003] Glass substrates possess high surface flatness and low roughness, which is beneficial for high-density RDL wiring. They exhibit excellent chemical stability, effectively resisting environmental corrosion from moisture, acids, and alkalis. Glass substrates effectively combat warping issues during the packaging process. Simultaneously, they possess superior electrical properties; high resistivity and low dielectric constant reduce transmission losses, ensuring interconnect density and signal integrity. Furthermore, the size variation of glass substrate packaging brings significant cost benefits. The mismatch between rectangular chips and circular silicon interposers leads to waste at wafer edges and further degrades efficiency as chip size increases. Using large-format rectangular glass as a carrier or ultimately as an interposer allows for accommodating more chips within a single carrier or interposer, significantly improving the efficiency of advanced packaging. Therefore, GCP (Glass Circuit Board), as a new substrate material for the iterative upgrade of organic substrates, has gained worldwide attention due to its advantages such as low CTE value, low dielectric loss, high Young's modulus, high surface flatness, and large-size (510mm*515mm) fabrication capabilities, making it more suitable for realizing large-size, low-power AI computing chips. Based on this, existing technologies have proposed using transparent substrates such as glass substrates as carriers to fabricate various optical devices, such as silicon waveguides.

[0004] The fabrication of existing silicon optical waveguides relies on photolithography. The precision of the photolithography machine directly determines the sidewall roughness of the silicon optical waveguide, ultimately affecting its transmission loss. Nanoimprint lithography (NIL), a method that directly utilizes mechanical contact extrusion to redistribute the imprinted material between a template and a substrate, offers advantages such as simple process, low cost, high yield, and mass production capability. It has become the most promising patterning technology, as its precision is not limited by the physical diffraction limit and eliminates the cost of optical lithography masks and optical imaging equipment. It has wide applications in display, semiconductor, and other fields.

[0005] For example, patent application CN119535884A discloses a nanoimprint master and an optical waveguide, as well as a method for manufacturing the same, which can solve the defects of poor edge quality and uneven residual adhesive in the grating structure region during nanoimprinting. The steps for preparing the optical waveguide include: first preparing a master plate; then using the master plate to imprint a sub-plate substrate to form a nanoimprint sub-plate after curing; and using the nanoimprint sub-plate to imprint a waveguide substrate to form an optical waveguide after curing.

[0006] For example, patent application CN118363259A discloses a method for preparing a nanoimprint template and a method for preparing an optical waveguide. The nanoimprint template preparation method includes the following steps: providing a substrate with a silicon oxide layer formed on its surface; patterning the silicon oxide layer to form a patterned structure with micro- and nano-scale dimensions; and heat-treating the substrate with the patterned structure to prepare the nanoimprint template. Simultaneously, a method for preparing an optical waveguide is also provided, specifically including the steps of: using the nanoimprint template for nanoimprinting and etching to transfer the micro- and nano-scale patterned structure onto a composite waveguide substrate composed of silicon and silicon oxide, thereby obtaining an optical waveguide with the micro- and nano-scale patterned structure.

[0007] However, the above scheme involves depositing waveguides on traditional SOI substrates, which is not suitable for fabricating optical waveguides with large-area waveguide structures on large-area transparent substrates, such as glass substrates. Summary of the Invention

[0008] The purpose of this invention is to provide a method for fabricating optical waveguides based on transparent substrates, which partially solves or alleviates the above-mentioned deficiencies in the prior art. When fabricating optical waveguides on large-area transparent substrates, it can improve the uniformity of the waveguides obtained by etching to a certain extent (i.e., improve device performance). At the same time, it can protect the transparent substrate, thereby preventing damage to the transparent substrate during the etching process, and thus improving the yield of optical waveguides.

[0009] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution:

[0010] A first aspect of the present invention provides a method for fabricating an optical waveguide based on a light-transmitting substrate, comprising the steps of: S101, depositing a masking layer on a first surface of the light-transmitting substrate, the masking layer being used to protect the light-transmitting substrate during subsequent etching and to ensure optical coupling between the light-transmitting substrate and light; S102, sequentially depositing a waveguide layer and an imprinting adhesive layer on a second surface of the masking layer; S103, imprinting the imprinting adhesive layer using a pre-prepared imprinting soft template to form an imprinting pattern on the imprinting adhesive layer; S104, etching the residual layer in the imprinted groove based on the imprinting pattern; S105, over-etching the waveguide layer based on the imprinting pattern using an etching gas with a preset etching selectivity ratio to obtain a patterned waveguide layer; S106, removing the imprinting adhesive layer to obtain a patterned waveguide layer; S107, depositing a capping layer on the patterned waveguide layer, such that the capping layer and the masking layer encapsulate the waveguide layer.

[0011] In some embodiments, step S101 specifically includes: S1011, depositing a silicon dioxide layer with a thickness of H1 and a first morphology on the first surface using a first deposition process as a first protective layer; the first deposition process includes HDP-CVD, SACVD, or FCVD; S1012, depositing a silicon dioxide layer with a thickness of H2 and a second morphology on the upper surface of the first protective layer using a second deposition process as a second protective layer; the second deposition process includes PECVD; wherein the sum of the thickness H2 of the second protective layer and the thickness H1 of the first protective layer is greater than or equal to 1 μm; and the first protective layer with the first morphology and the second protective layer with the second morphology complement each other to form a flat masking layer.

[0012] In some embodiments, the method for fabricating an optical waveguide based on a transparent substrate further includes the step of: S201, depositing a buffer layer with a thickness of H3 between the masking layer and the waveguide layer; the selective etching ratio of the waveguide layer and the buffer layer is less than or equal to 1, and correspondingly, when over-etching the waveguide layer in step S105, the waveguide layer is etched using an etching gas with a low selectivity ratio to the waveguide layer and the buffer layer.

[0013] In some embodiments, the optical waveguide fabrication method based on a transparent substrate further includes the following steps: S401, pre-obtaining the width of the pattern structure (120) corresponding to the waveguide structure (110) on the imprinted soft template; S402, dividing the region into multiple regions with the specified pattern structure as the center point and a first preset side length R1, thereby obtaining multiple partitions, and calculating the pattern duty cycle of each region; S403, determining whether the pattern duty cycle of each region is greater than a first preset duty cycle threshold; if the pattern duty cycle is greater than or equal to the first preset duty cycle threshold, marking the corresponding region as a dense region; if the pattern duty cycle is less than the first preset duty cycle threshold, marking the corresponding region as a sparse region; correspondingly, step S105 specifically includes: over-etching the sparse region based on a first preset etching parameter; and over-etching the dense region based on a second preset etching parameter; wherein, the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power.

[0014] In some embodiments, step S402 calculates not only the graphic duty cycle but also the average width of the graphic structure within each region. Accordingly, step S403 specifically includes: determining whether the graphic duty cycle is greater than or equal to a first preset duty cycle threshold, and whether the average width of the graphic structure within the corresponding region is less than a preset width threshold; if the graphic duty cycle is greater than or equal to the first preset duty cycle threshold, and the average width is less than the preset width threshold, marking the corresponding region as a Level I dense region; if the graphic duty cycle is greater than or equal to the first preset duty cycle threshold, and the average width is greater than the preset width threshold, marking the corresponding region as a Level II dense region; if the graphic duty cycle is less than the first preset duty cycle threshold, and the average width is less than the preset width threshold, marking the corresponding region as a Level II dense region; if the graphic duty cycle is less than the first preset duty cycle threshold, and the average width is less than the preset width threshold... A width threshold is used to mark the corresponding region as a Level I sparse region; if the duty cycle of the pattern is less than a first preset duty cycle threshold and the average width is greater than a preset width value, the corresponding region is marked as a Level II sparse region; accordingly, step S105 specifically includes: for Level I and Level II sparse regions, over-etching is performed based on a first preset etching parameter and a third preset etching parameter, respectively; the third ICP power in the third preset etching parameter is less than the first ICP power in the first preset etching parameter; for Level I and Level II dense regions, over-etching is performed based on a second preset etching parameter and a fourth preset etching parameter, respectively; the fourth ICP power in the fourth preset etching parameter is less than the second ICP power in the second preset etching parameter.

[0015] In some embodiments, the optical waveguide fabrication method based on a transparent substrate further includes the following steps: S501, obtaining the height of each patterned structure in each dense region, and dividing the region with any specified patterned structure as the center and a second preset side length R2 to obtain at least two sub-regions, and calculating the average height of the patterned structure in each sub-region; S502, determining whether the average height in each sub-region is less than or equal to a first preset height threshold and greater than or equal to a second preset height threshold; the first preset height threshold is the maximum value among the average heights of all sub-regions; if the average height is less than or equal to the first preset height threshold and greater than or equal to the second preset height threshold, adjusting the etching time or ICP power in the second preset etching parameters according to a first preset increment; if the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, adjusting the etching time or ICP power in the second preset etching parameters according to a second preset increment; if the average height is less than the third preset height threshold, maintaining the current second preset etching parameters.

[0016] In some embodiments, the shielding layer is deposited using pure SiO2 material, and the waveguide layer (300) is deposited using silicon nitride material or thin-film lithium niobate material.

[0017] In some embodiments, the step of pre-preparing an imprinting flexible template specifically includes the following steps: S301, depositing an electron beam resist layer on a substrate layer and exposing a designated area in the electron beam resist layer; S302, developing the exposed electron beam resist layer to obtain a patterned electron beam resist layer; S303, etching the substrate layer based on the patterned electron beam resist layer to obtain a patterned substrate layer; S304, sequentially depositing a first resist layer and a flexible film layer on the patterned substrate layer; S305, removing the substrate layer to obtain the patterned imprinting flexible template.

[0018] A second aspect of the present invention is to provide an optical waveguide based on a light-transmitting substrate, which is prepared by the above-described optical waveguide preparation method, comprising: a light-transmitting substrate, a masking layer located on the light-transmitting substrate, and a patterned waveguide layer located on the masking layer; the masking layer is deposited on a first surface of the light-transmitting substrate using pure silicon dioxide material, and the thickness of the masking layer is greater than or equal to 1 μm.

[0019] In some embodiments, the masking layer includes a first protective layer having a first morphology located on a first surface of the light-transmitting substrate, and a second protective layer having a second morphology located between the first protective layer and the waveguide layer; wherein the first protective layer with the first morphology and the second protective layer with the second morphology complement each other to form a flat masking layer; wherein the first protective layer is obtained by depositing silicon dioxide with a thickness of H1 using a first deposition process; the second protective layer is obtained by depositing silicon dioxide with a thickness of H2 using a second deposition process; the first deposition process includes HDP-CVD, or SACVD, or FCVD; the second deposition process includes PECVD.

[0020] In some embodiments, the optical waveguide further includes a buffer layer disposed between the shielding layer and the waveguide layer.

[0021] Beneficial effects: Traditional photolithography cannot fabricate large-scale waveguide structures on large-area substrates, while nanoimprint lithography enables large-scale patterned replication. Furthermore, the pre-defined patterns guide the etching process, significantly reducing the high defect rate caused by "blind etching" in traditional photolithography. However, when fabricating large-area patterned optical waveguide structures on transparent substrates, especially using micron- or even meter-sized transparent substrates as the base to integrate a large number of patterned waveguides for large-scale optical computer matrices, two issues arise: firstly, the large-area patterned structure on the nanoimprint stencil may exhibit inhomogeneity and varying density; secondly, the large area makes it impossible to guarantee a uniform etching ratio across the entire transparent substrate. Therefore, to ensure complete isolation between waveguide structures (or patterned structures) and prevent light leakage to adjacent waveguide structures, this application involves over-etching the waveguide layer. By placing a masking layer between the transparent substrate and the waveguide layer, the requirements for the etching process are greatly relaxed: 1) It eliminates the need to precisely calculate the "just enough" etching time to prevent over-etching; as long as the waveguide layer is etched through, the process window is very wide. Furthermore, it avoids the formation of non-volatile etching products during over-etching due to etching the transparent substrate (which contains many additive elements such as Na, B, Ga, and Mg), which can affect the performance of the silicon waveguide. For example, it can significantly increase the scattering loss of light propagating in the waveguide, thereby reducing the optical coupling between the light and the transparent substrate and lowering the waveguide yield. 2) Since the masking layer is deposited using pure silicon dioxide (e.g., 99.9999% purity), it not only protects the transparent substrate but also ensures, and may even improve, the optical coupling between the transparent substrate and the waveguide (e.g., by wrapping the waveguide layer together with the capping layer), thus improving the waveguide yield. 3) Furthermore, using two different deposition processes to obtain a double-layer masking layer not only protects the transparent substrate but also ensures the flatness of the deposited waveguide plane due to the complementary physical morphology between the two protective layers prepared by different processes. This eliminates the need for additional planarization layers or other special treatments, reducing process complexity and improving device performance to some extent. Additionally, because of the significant differences between the transparent substrate and the waveguide system, the masking layer directly deposited on the transparent substrate also acts as an "adhesive" to increase the adhesion between the transparent substrate and the waveguide layer, preventing easy detachment of the transparent substrate from the waveguide layer.

[0022] Furthermore, this application incorporates a buffer layer between the mask layer and the waveguide layer. This ensures that even if some areas of the waveguide layer remain unetched (e.g., 10nm) due to poor process parameter control, the subsequent etching steps will almost instantly remove these residues due to the extremely high etching rate of the buffer layer, quickly exposing the underlying pure silicon dioxide mask layer. This significantly reduces the uniformity requirements for the "etching through the waveguide layer" step, making the process easier to control and resulting in a higher yield. Moreover, this buffer layer, together with the pure silicon dioxide mask layer, can be directly used as the lower cladding layer for "in-situ encapsulation" of the waveguide layer. The minimum thickness requirement (e.g., 1µm) for the silicon dioxide mask layer as the final protective layer is sufficient, eliminating the need to reserve additional thickness for over-etching.

[0023] In summary, this application maximizes the process window and accuracy by precisely controlling the etching selectivity between different layers, thereby reducing the difficulty of etching depth control and ensuring the uniformity and consistency of waveguides etched on large-area transparent substrates as much as possible.

[0024] Furthermore, because different regions within the pattern have different etching rates—for example, denser regions have slower etching rates while sparser regions have faster etching rates—the waveguide in the sparse region may be completely etched through or even over-etched within the same etching time, while the waveguide in the dense region may not yet be etched through. This directly leads to inconsistent performance across different functional areas of the chip. Additionally, if the over-etching time is the same for all regions, etching will continue even if the sparse region is already etched through. If the over-etching time is set too long according to the needs of the dense region, severe lateral etching may occur in the sparse region, increasing the probability of defective products. Therefore, to mitigate the adverse effects of this situation, this application increases the etching parameters for the dense region, such as increasing the ion concentration, to accelerate the etching rate of the dense region. This employs a partitioned etching strategy to avoid setting excessively long over-etching times. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0026] Figure 1A This is a flowchart illustrating the fabrication of the optical waveguide in Embodiment 1 of the present invention; Figure 1BThis is a flowchart illustrating the fabrication of the optical waveguide in Embodiment 2 of the present invention; Figure 2 This is a flowchart of the process for preparing the embossing soft template in this invention; Figure 3 A schematic diagram illustrating the varying density of waveguide structures on the waveguide layer; Figure 4 To reflect the corresponding Figure 3 A schematic diagram of the graphic structure of a mid-waveguide; Figure 5 This is a flowchart of the optical waveguide fabrication method based on a transparent substrate in Embodiment 1 of the present invention; Figure 6 This is a flowchart of the optical waveguide fabrication method based on a transparent substrate in Embodiment 2 of the present invention; Figure 7 This is a flowchart of the optical waveguide fabrication method based on a transparent substrate in Embodiment 5 of the present invention.

[0027] Reference numerals: Transparent substrate 100, masking layer 200, waveguide layer 300, imprinting adhesive layer (i.e., mask layer) 400, imprinting flexible template 500, first adhesive layer 5001, flexible film layer 5002, base layer 600, electron beam adhesive layer 700; cover layer 800. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0029] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" can be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In this document, unless otherwise expressly specified and limited, terms such as "installed," "equipped with," and "connected" should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "and / or" includes any and all combinations of one or more of the listed related items. "Multiple" in this document means two or more, i.e., it includes two, three, four, five, etc. In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, a range description should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within that range. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0030] Optical AI chip: A photonic computing chip, also known as a photonic chip or optical computing chip, is a chip specifically designed for processing optical data and performing artificial intelligence (AI) inference. Based on optical principles, it takes optical signals as input and performs computational operations through a series of optical elements and devices. These optical elements can be components such as lasers, optical fibers, and optical modulators, used to process and transmit optical signals. For example, a photonic computing chip converts the optical signal into a weak photocurrent signal using a light-emitting diode (LED). This photocurrent signal is then converted into a voltage signal U by a transimpedance amplifier (TIA), and finally converted into a digital signal by an analog-to-digital converter (ADC). The digital signal is then output to an FPGA for processing. Simultaneously, the FPGA outputs the processed digital signal to a digital-to-analog converter (DAC) to convert the FPGA's digital signal back into an analog signal and input it back to the photonic computing chip.

[0031] Computational unit: A single computational unit used to perform a calculation. For example, using Mach... A single computational unit for photonic computing can be implemented using a Zeidel interferometer (MZI) or a microring structure (MMR). Other examples include photonic computing units utilizing carrier light absorption effects and photonic computing units based on the absorption effects of phase change materials. Specifically, computational units can be categorized into photonic computing units and hybrid computing units.

[0032] Computational Array: An N*N computational array is constructed based on the above computational units. Each intersection of the input row waveguide and the output column waveguide in this array contains a computational unit. If the computational units are photonic computational units, the computational array can also be called a photonic computational array; if the computational units are optoelectronic hybrid computational units, the computational array can also be called an optoelectronic hybrid computational array.

[0033] Transparent substrate: In this document, a transparent substrate refers to a base substrate with a flat, smooth surface and specific geometric dimensions (such as a disc, square, or panel), and exhibits extremely high transmittance, for example, >99.999%, within the target wavelength range (such as the visible light region 380nm-2µm). It is commonly used as a "foundation" or "canvas" for various functional devices (such as circuits, sensors, and waveguides), providing a support platform for subsequent micro / nano fabrication and functional layer deposition. Examples include interposers or redistribution substrates for system-in-package (SIIP), and the fabrication of electrical interconnect vias and optical waveguide structures (such as gratings) within glass. Preferably, the transparent substrate can be a glass substrate, etc.

[0034] Masking layer: In this paper, the masking layer refers to a layer that protects the next material layer during the etching process, preventing it from being etched during the etching process. It does not need to be removed in subsequent processes. Its refractive index is similar to that of the transparent substrate, thus ensuring the coupling between light and the transparent substrate. Furthermore, it can co-encapsulate the waveguide layer with the capping layer on the waveguide layer. Preferably, this masking layer can be deposited using materials such as pure silicon dioxide.

[0035] Over-etching: In this article, over-etching refers to continuing etching for an additional period of time after the preset time for "just etching to the target depth" has emulsified. For example, ideally, the etching time required to just etch through a waveguide layer of a certain depth is T1 (e.g., 10s), but in actual engineering applications, it is necessary to continue etching for T2 (20s) to ensure that the corresponding area and other areas on the large-area waveguide layer are completely etched through the waveguide layer.

[0036] Fabricating a large number of optical waveguides on large-area transparent substrates, such as glass substrates, to create large-scale computing matrices is challenging due to the etching process. This makes it impossible to guarantee uniform etching ratios across all structures, and the uniformity of the structures after nanoimprinting cannot be guaranteed. Consequently, controlling the etching depth / time is difficult, compromising the uniformity and consistency of the etched waveguide structures. To address this, this application employs over-etching and a multi-layered structure, maximizing the process window and precision by controlling the etching selectivity ratio between different layers. This reduces the difficulty of controlling the etching depth / time, thereby ensuring the uniformity of waveguides etched on large-area transparent substrates. For example, a masking layer, such as a double-layered protective layer, is placed between the transparent substrate and the waveguide layers. By controlling the etching ratio between the upper and lower layers, the process window is maximized, allowing for a longer etching time without damaging the transparent substrate. Furthermore, the masking layer can be directly integrated with the subsequently deposited capping layer to perform in-situ encapsulation of the etched waveguide structures. In addition, the number of layers in the structure affects the miniaturization and integration of the device. Therefore, in order to avoid introducing too many multilayer materials, the etching process parameters are adjusted based on the dense and sparse regions of the patterned waveguide structure in the imprinting process. This reduces the difference in etching time caused by non-uniformity to a certain extent, and then works in synergy with the multilayer structure to ensure the uniformity of the waveguide structure.

[0037] Example 1: See Figure 1A and Figure 5 The above is a flowchart of an embodiment of a method for fabricating an optical waveguide based on a transparent substrate according to the present invention. Specifically, the method includes the following steps:

[0038] S101, a masking layer 200 is deposited on the first surface 101 of the light-transmitting substrate 100.

[0039] In this embodiment, the above-mentioned protective layer 200 is used to protect the light-transmitting substrate 100 during the subsequent etching process to prevent the light-transmitting substrate 100 from being etched during the etching process, and at the same time to ensure or improve the light coupling effect between the light and the light-transmitting substrate 100.

[0040] In some embodiments, the shielding layer 200 may be deposited using a transparent material that does not absorb light, and the higher the etching selectivity ratio between the shielding layer and the waveguide layer material, the better (i.e., the etching rate of the waveguide layer is much higher than the etching rate of the shielding layer 200). Preferably, the shielding layer 200 is made of pure SiO2. More preferably, the refractive index n1 of the shielding layer 200 and the refractive index n2 of the transparent substrate 100 satisfy the relationship: n2 - Δn0 ≤ n1 ≤ n2 = Δn0. Preferably, Δn0 = ±0.01.

[0041] Furthermore, the thickness of the masking layer 200 is greater than or equal to 1 μm. Specifically, the masking layer 200 can be deposited on the light-transmitting substrate 100 using methods such as PECVD or HDPCVD.

[0042] S102, a waveguide layer 300 and an imprinted adhesive layer 400 are sequentially deposited on the second surface 201 of the shielding layer 200.

[0043] In some embodiments, the waveguide layer 300 is deposited using waveguide materials commonly used in the art, such as SiN material or thin-film lithium niobate material.

[0044] In a specific example, if thin-film lithium niobate is used as the waveguide layer 300, the thickness of the shielding layer 200 is greater than or equal to 5 μm. That is, compared to the shielding layer 200 between the waveguide layer 300 and the transparent substrate 100 made of other materials, the thickness of the shielding layer 200 is four times or more. The etching process for the waveguide layer made of thin-film lithium niobate (this is prior art and will not be elaborated here) differs from the etching process for waveguide layers made of other materials (e.g., dry etching or wet etching). Because it is impossible or difficult to clean the solid waste from the etched product in a timely manner during the etching process, the risk of over-etching to the transparent substrate is greater. Therefore, in order to ensure the uniformity of the optical waveguide structure and reduce the risk of etching onto the light-transmitting substrate, a mask layer of a specific thickness is set to provide sufficient space for etching without significantly reducing the longitudinal transmission of light. Furthermore, the micro- and nano-structures (e.g., grooves) formed by over-etching the mask layer actually help reduce light loss.

[0045] S103, the embossing adhesive layer 400 is embossed using the pre-prepared embossing soft template 500, so that an embossing pattern is formed on the embossing adhesive layer 400.

[0046] S104, etch the residual layer in the groove after imprinting based on the imprinting pattern. In some embodiments, the etching process must be highly selective, i.e., it should rapidly etch only the imprinting adhesive while barely etching the underlying waveguide layer 300. For example, reactive ion etching (RIE) can be used to etch the imprinting adhesive layer. Of course, other processes can also be used to remove the residual layer. The process for removing the residual layer is prior art and will not be described in detail here.

[0047] S105, based on the imprinted pattern, the waveguide layer 300 is over-etched using an etching gas with a preset etching selectivity to obtain a patterned waveguide layer 300.

[0048] In this embodiment, over-etching the waveguide layer 300 using an etching gas (such as CF4 or CHF3 for SiN) with a preset etching selectivity ratio (such as an empirical value, 1:5) means that the etching rate of the waveguide layer 300 by the etching gas is much greater than the etching rate of the masking layer 200. Therefore, after the waveguide layer 300 is etched through, micro-etching will continue to be performed on the masking layer 200. However, since the etching rate of the masking layer 200 is low and it has a certain thickness, the etching will stop on the masking layer 200 when the preset etching time (such as 20s) is reached, thereby protecting the light-transmitting substrate 100 from damage.

[0049] In this embodiment, over-etching refers to the slight etching of the masking layer 200 after the optical waveguide 300 is etched according to the preset etching time. Of course, since the optical waveguide layer is over-etched, the final masking layer also has a corresponding pattern. Furthermore, since the etching selectivity is greater than the first preset threshold (which can be an empirical value), the process will not completely etch the masking layer 200, that is, it will not etch the light-transmitting substrate 100.

[0050] S106, Remove the imprinting adhesive layer 400 to obtain a patterned waveguide layer 300. In some embodiments, after pattern transfer is completed, all remaining imprinting adhesive is removed using a wet method (such as solvent, acid) or a dry method (such as O2 plasma ashing) to leave a clean, patterned waveguide structure.

[0051] S107, a capping layer 800 is deposited on the patterned waveguide layer 300, such that the capping layer 800 and the shielding layer 200 enclose the waveguide layer 300.

[0052] In this embodiment, the capping layer 800 and the previous shielding layer 200 together form an almost symmetrical "sandwich" structure, enclosing the high-refractive-index waveguide layer 300 in the middle. Since the waveguide layer 300 is directly deposited on the shielding layer 200, no separate encapsulation process is required, thus achieving "in-situ encapsulation" and reducing the risk of waveguide contamination or exposure. In this embodiment, the capping layer 800 and the shielding layer 200 use the same material, for example, pure SiO2. Preferably, the capping layer 800 is prepared using a deposition process corresponding to that of the shielding layer 200, thereby improving the encapsulation of the waveguide layer 300.

[0053] In some embodiments, the preparation step of the imprinting soft template in step S103 specifically includes: S301, depositing an electron beam resist layer 700 on the substrate layer 600, and exposing a designated area in the electron beam resist layer 700. S302, developing the exposed electron beam resist layer 700 to obtain a patterned electron beam resist layer 700. In some embodiments, the electron beam resist layer 700 is a positive resist layer or a negative resist layer; correspondingly, if there is no positive resist layer, the electron beam resist layer in the exposed area is removed during the developing process in step S302, see [reference]. Figure 2 If there is no negative resist layer, in step S302, when developing the electron beam resist layer, the electron beam resist layer outside the exposure area is removed (not shown in the figure). S303, the substrate layer 600 is etched based on the patterned electron beam resist layer 700 to obtain the patterned substrate layer 600. S304, a first resist layer 5001 and a soft film layer 5002 are sequentially deposited on the patterned substrate layer 600. S305, the substrate layer 600 is removed to obtain the patterned imprinting soft template 500.

[0054] During nanoimprinting, uneven height of the pattern on the template or uneven thickness of the residual layer in the grooves of the imprinting adhesive may occur, increasing the difficulty of controlling the etching depth / etching time of the subsequent optical waveguide. Although a high-performance imprinting film can be designed in advance using high-precision algorithms to ensure the uniformity of the imprinting thickness, redesigning and manufacturing a new high-performance template for existing imprinting films would significantly increase costs, and the waiting process for a new template may result in production stoppages and losses. On the other hand, even with a template with high uniformity, different areas of the imprinting film will experience varying degrees of wear after long-term use, leading to different imprinting thicknesses and consequently, different residual layer thicknesses in the grooves. Therefore, to reduce the risk of unevenness in the etched optical waveguide caused by uneven pattern or residual layer thickness, this embodiment uses over-etching combined with a masking layer 200 to ensure the uniformity of the optical waveguide while protecting the transparent substrate 100, thereby improving the yield of the waveguide device.

[0055] Example 2: This invention also provides another method for fabricating an optical waveguide, which includes the steps of Example 1 above, except that, see [link to example]. Figure 1B and Figure 6 In this embodiment, instead of a single-layer masking layer, a double-layer masking layer is used. For example, two different deposition processes are used to deposit a silicon dioxide double-layer structure with different properties (including etching rate, etching resistance, and morphology). The lower layer near the transparent substrate 100 is dense, while the upper layer near the waveguide layer 300 is sparse (i.e., the lower layer is more etch-resistant than the upper layer). This allows the two layers to complement each other with different morphologies, forming a flat masking layer 200. This ensures both waveguide uniformity and the stability of the connection between the multilayer structures. Specifically, the process includes: S1011, using a first deposition process, such as HDP-CVD, to deposit a silicon dioxide layer with a thickness of H1 and a first morphology on the first surface 101 of the transparent substrate as a first protective layer 202. S1012, using a second deposition process, such as PECVD, to deposit a silicon dioxide layer with a thickness of H2 and a second morphology on the upper surface of the first protective layer 202 as a second protective layer 203.

[0056] In this embodiment, the first morphology refers to the first protective layer 202 comprising: a lower surface in contact with the light-transmitting substrate, and an upper surface for depositing the second protective layer 203 and disposed opposite to the lower surface. The second morphology refers to the second protective layer 203 comprising: a third surface in contact with the upper surface of the first protective layer 202, and a fourth surface for depositing the optical waveguide and disposed opposite to the third surface. Since the first protective layer 202 is deposited directly on the light-transmitting substrate 100, the lower surface of the first protective layer 202 is almost flat, while its upper surface has an uneven morphology due to limitations in the deposition process. Correspondingly, since the second protective layer 203 is deposited directly on the upper surface of the first protective layer 202, the morphology of the third surface is complementary to the upper surface, while the fourth surface is almost flat due to the maturity of the deposition process. This results in the double-layer structure of the masking layer 200 having two flat upper and lower surfaces (i.e., the fourth surface of the second protective layer 203 and the lower surface of the first protective layer 202), and the stress integration effect of the double-layer structure can reduce the risk of warping. In this embodiment, a dense, hard silicon dioxide layer with high image stability is prepared using HDP-VCD. Compared to a sparser silicon dioxide layer prepared using PECVD, its etching rate is slower. Accordingly, even if the thinner second protective layer 203 is etched through during the over-etching process, the etching process will eventually stop on the highly etch-resistant first protective layer 202.

[0057] Generally, to ensure sufficient safety, a sufficiently thick silicon dioxide layer can be provided for protection. However, a thicker layer can affect the vertical stacking during subsequent processes, thus impacting the device size. Therefore, to ensure that the second protective layer 203 is etched through during the over-etching process of the optical waveguide 300 without etching through the first protective layer 202 and damaging the light-transmitting substrate 100, the second protective layer 203 near the waveguide layer 300 is made thinner. Furthermore, during the over-etching process, only the first protective layer 202 is etched, without reaching the light-transmitting substrate 100. Compared to simply increasing the thickness of the silicon dioxide layer, for example, by providing a very thick silicon dioxide layer, it is more beneficial for device miniaturization and integration. Preferably, H1 > H2. More preferably, H1 + H2 ≥ 1 μm. Of course, in other embodiments, other deposition techniques can be used to deposit a denser first protective layer 202, such as SACVD or FCVD.

[0058] Example 3: The present invention also provides another method for fabricating an optical waveguide, which includes the steps of Example 1 or Example 2 above. The difference is that, in the fabrication method of this example, before depositing the waveguide layer 300 on the shielding layer 200 (i.e. before performing step S102), the method further includes step S201, depositing a buffer layer of thickness H3 between the shielding layer 200 and the waveguide layer 300.

[0059] In some scenarios, in addition to considering waveguide patterning, it may be necessary to fabricate some overhang structures to create special devices. Therefore, a buffer layer is first set on the shielding layer 200, and then the waveguide layer 300 is deposited on top of the buffer layer. Furthermore, the selective etching ratio between the waveguide layer 300 and the buffer layer is less than or equal to 1. By setting a buffer layer with an etching selectivity ratio less than or equal to 1, when the waveguide layer 300 is over-etched in step S105, the buffer layer will be etched both laterally and longitudinally simultaneously. Since its etching rate is much faster than or equal to the etching rate of the waveguide layer 300, lateral undercut will occur, resulting in a waveguide structure with overhangs. In one example, the buffer layer is made of amorphous silicon (a-Si), and when etching the waveguide layer 300, the waveguide layer 300 is etched using an etching gas (preferably a fluorocarbon-based gas, such as a mixture of CHF3 + SF6 + He / O2) with an etching selectivity ratio of 1:1 for the waveguide layer 300 and the buffer layer. Of course, after etching, the etching residue needs to be cleaned before depositing the capping layer 800. Preferably, the capping layer 800 fills the suspended space below the waveguide structure caused by etching. Preferably, the thickness H3 of the buffer layer is 20-50 nm; while the thickness of the masking layer 200 is ≥1 μm.

[0060] Example 4: The present invention also provides another method for fabricating an optical waveguide, which includes the steps of Example 1, 2, or 3 above. The difference is that in this example, the cover layer 800 is fabricated in two steps. Specifically, in step S102, before depositing the imprinted adhesive layer 400 on the waveguide layer 300, a first cover layer is deposited, and then the imprinted adhesive layer 400 is deposited on the first cover layer, and step S103 is executed. Correspondingly, in step S104, when removing the residual layer in the groove, a high etching ratio is selected for the residual layer and the first cover layer (e.g., selecting a high etching ratio for the first cover layer). The residual layer is over-etched using a gas with an etching ratio of 10:1 (such as a fluorocarbon chemical gas containing C4F8 and CHF3). Then, the first cover layer is etched (or over-etched) using an etching gas with a high selective etching ratio for both the first cover layer and the waveguide layer 300 (such as CHF3 / CF4 / O2, etc.; since the waveguide layer 300 is etched in step S105, slightly etching away a small portion of the waveguide layer 300 during the first cover layer etching will not have any adverse effects) to expose the waveguide layer 300. Then, steps S105-S107 are executed. In step S107, the second cover layer is deposited. Of course, in this embodiment, the etching of the first cover layer is still pattern-based, that is, only the area corresponding to the residual layer is etched or over-etched to expose the area on the waveguide layer 300 that needs to be over-etched.

[0061] Preferably, in this embodiment, the sum of the thicknesses of the first cover layer and the second cover layer is equal to or greater than the thickness of the cover layer 800 deposited in step S107 of Embodiment 1.

[0062] In one specific example, a silicon dioxide layer is first deposited on the waveguide layer 300 as a first cover layer using the same process as the deposition mask layer 200.

[0063] In this embodiment, the effects of nanoimprinting and over-etching are decoupled. Specifically, a first capping layer is placed between the waveguide layer 300 and the imprinting adhesive layer as a decoupling protective layer. This minimizes the impact of uneven patterns or residual layers on the imprinting adhesive layer, while ensuring high-fidelity replication of the pattern onto the waveguide layer 300. It also reduces or eliminates the risk of rough, non-perpendicular waveguide sidewalls after transfer due to deformation or erosion of the pattern edges on the imprinting adhesive layer during over-etching. Furthermore, since no additional removal step is required, the second capping layer deposited in step S107 forms a single unit encapsulating the waveguide layer 300. In other words, after removing the imprinting adhesive layer, step S107 directly deposits the second capping layer on top of the first capping layer, thus forming a single upper structure encapsulating the waveguide layer 300.

[0064] Example 5: Although Example 4 above uses a multilayer structure to decouple the effects of the imprinting and etching processes, thereby obtaining a high-performance optical waveguide, it significantly increases the fabrication cost and process complexity, making it suitable only for manufacturers with high device requirements and ample funds. Therefore, this invention also provides another method for fabricating an optical waveguide, which includes the steps of Example 1 or 2 above, the difference being... (See below for details). Figure 7 In this embodiment, before over-etching the waveguide layer 300, the method further includes the step: S401, obtaining the width of the pattern structure 120 (i.e., the spacing between waveguide structures 110) based on the pattern structure 120 corresponding to the waveguide structure 110 on the imprinted soft template 500. In some embodiments, the imprinted pattern on the imprinted soft template can be captured in advance by an image acquisition device, such as a high-definition camera, and image analysis can be performed to obtain the spacing L1 or L2 between the waveguide structures 110. See [link to relevant documentation]. Figure 3 That is, the width L1 or L2 of the raised graphic structure 120 on the embossing soft template 500, such as Figure 4 Of course, in other embodiments, the width (or spacing) of the graphic structure 120 can also be obtained directly from the design drawings (such as the GDSII layout) of the imprinted soft template 500, thereby obtaining the spacing between the waveguide structures 110.

[0065] S402, using the specified graphic structure 120 as the center point, divide the area into regions with a first preset side length R1 to obtain multiple regions, thus obtaining multiple partitions; and calculate the graphic duty cycle and the average width of the graphic structure in each region; if the graphic duty cycle is greater than or equal to the first preset duty cycle threshold (e.g., 55%), and the average width of the graphic structure in the corresponding region is less than the preset width threshold, then the region is marked as a Level I dense region; if the graphic duty cycle is greater than the first preset duty cycle threshold, and the average width of the graphic structure in the corresponding region is greater than the preset width threshold, then the region is marked as a Level II dense region; if the graphic duty cycle is less than the first preset duty cycle threshold (e.g., 55%), and the average width of the graphic structure is less than the preset width threshold, then the corresponding region is marked as a Level I sparse region; if the graphic duty cycle is less than the first preset duty cycle threshold, and the average width of the graphic structure is greater than the preset width value, then the corresponding region is marked as a Level II sparse region. That is, first, sparse and dense regions are divided based on the image duty cycle, and then further sparse and dense regions are divided based on width, thus obtaining sparse regions and dense regions of different levels.

[0066] Of course, in other embodiments, the division of dense and sparse regions can also be based solely on the graphic duty cycle. For example, if the graphic duty cycle is greater than or equal to a first preset duty cycle threshold, it is classified as a dense region; if it is less than the first preset duty cycle threshold, it is classified as a sparse region. Accordingly, step S105 specifically includes: for sparse regions, over-etching is performed based on a first preset etching parameter; while for dense regions, over-etching is performed based on a second preset etching parameter; wherein, the first preset etching parameter includes a first particle concentration or a first etching time, and the second preset etching parameter includes a second ion concentration or a second etching time, wherein the second ion concentration is greater than the first particle concentration, or the second etching time is greater than the second etching time. Of course, different preset etching parameters can be preset for different levels of sparse regions and different levels of dense regions. The higher the level of the same type of region, the smaller its corresponding preset etching parameter. For example, the preset etching parameter for a level I dense region is greater than the preset etching parameter for a level II dense region.

[0067] In a specific example, taking the etching of a silicon carbide waveguide layer as an example, the initial etching parameters set in advance according to actual needs include: ICP power: 1000 W (to control plasma ion concentration); etching mixed gas: CHF3 / CF4 / O2; etching time: 20 s. When the duty cycle of a certain region is 70%, which is greater than the first preset threshold of 55%, the ICP power of that dense region is increased to 1200 W to increase the ion concentration. When the duty cycle of a certain region is 35%, which is less than 55%, the ICP power of that sparse region is kept at 1000 W.

[0068] In another specific example, if the duty cycle of a certain region is 70%, which is greater than the first preset duty cycle threshold of 55%, and the average width of the pattern structure 120 is less than or equal to the preset width threshold, the region is marked as a Level I dense region, and the ICP power in the initial preset etching parameters of 1000W is adjusted to 1200W (i.e., the second preset etching parameter). If the average width of the pattern structure 120 is greater than or equal to the preset width threshold, the region is marked as a Level II dense region, and the ICP power in the initial preset etching parameters of 1000W is adjusted to 1100W (i.e., the fourth preset etching parameter).

[0069] Similarly, when the image duty cycle of a certain region is less than 55% (35%) and the average width of the pattern structure is less than a preset width threshold, the ICP power of this Level I sparse region is maintained at 1000W (i.e., the first preset etching parameter). If the average width of the pattern structure is greater than or equal to the preset width threshold, the ICP power of the Level II sparse region is maintained at 900W (i.e., instead of maintaining the first preset etching parameter, the first preset etching parameter is reduced to obtain the third preset etching parameter). In other words, the difference in global waveguide etching time is minimized by adjusting the ion concentration during etching. This means different preset etching parameters are set for different levels of dense regions.

[0070] Preferably, when over-etching is performed by adjusting the ion concentration, a high-end etching machine supporting zone control can be used to set corresponding etching parameters, such as ICP power, for each area. Then, the high-end etching machine is used to over-etch all areas (i.e., the etching time is the same for all areas). When over-etching is performed by adjusting the etching time, traditional occlusion etching can be used, i.e., etching sparse and dense areas separately. Specifically, when etching sparse areas, dense areas are occluded, and vice versa.

[0071] In other embodiments, since the distribution of waveguide structures 110 on waveguide layer 300 is not only dense and sparse in the two-dimensional plane, but also has a height in the three-dimensional direction, which determines the etching depth, the method further includes the step: S501, obtaining the height of each pattern structure 120 in the dense region (preferably obtained from the GDSII layout; this height actually maps the etching depth of the grooves between waveguide structures 110), and further partitioning; specifically, for each dense region, with any specified pattern structure 120 as the center, the region is divided by a second preset side length R2 (R2 is less than R1) to obtain at least two sub-regions (i.e., rectangular regions), and the calculation is performed. Calculate the average height of the graphic structure 120 in each sub-region; if the average height is less than or equal to the first preset height threshold and greater than or equal to the second preset height threshold, adjust the second etching parameters corresponding to the sub-region, such as increasing the initial etching time or increasing the initial ICP power according to the first preset increment, thereby increasing the ion concentration; if the average height is less than the second preset height threshold and greater than or equal to the third preset height threshold, adjust the second etching parameters corresponding to the sub-region, such as increasing the initial etching time or increasing the initial ICP power according to the second preset increment, thereby increasing the ion concentration; if the average height is less than the third preset height threshold, maintain the current second etching parameters.

[0072] Furthermore, if the ion concentration is increased, the thickness of the second protective layer 203 will be increased accordingly.

[0073] In a specific example, following the example above, when the average height of any sub-region within any dense region is equal to or less than a first preset height threshold (preferably, the first preset height threshold is the largest average height among all sub-regions), and greater than or equal to a second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1250W. If the average height is less than the second preset height threshold, but greater than or equal to a third preset height threshold, the ICP power in the corresponding sub-region's second etching parameters is adjusted from 1200W to 1230W. If the average height is less than the third preset height threshold, the current second etching parameters are maintained. Of course, in other embodiments, the preset increments are different for each level of dense region; that is, the level of the dense region is first identified, and then the corresponding preset increments are adjusted based on the average height (for example, the higher the level of the dense region, the smaller the preset increment). For example, when the average height of any sub-region within any Level I dense region is equal to or less than a first preset height threshold and greater than or equal to a second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1250W. When the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, the ICP power in the corresponding sub-region's second etching parameters is adjusted from 1200W to 1230W. Similarly, for any sub-region within any Level II dense region, when the average height is equal to or less than the first preset height threshold and greater than or equal to the second preset height threshold, the ICP power in the second preset etching parameters is adjusted from 1200W to 1240W. When the average height is less than the second preset height threshold and greater than or equal to the third preset height threshold, the ICP power in the corresponding sub-region's second etching parameters is adjusted from 1200W to 1220W.

[0074] Of course, to further reduce the difference, in some other embodiments, each sparse region can also be further divided into sub-regions based on the height of the graphic structure 120, and the division principle is the same as that of the dense region. For example, for each dense region, the region is divided with any specified graphic structure 120 as the center and a fourth preset side length R4 (R4 is greater than R2) to obtain at least two sub-regions (i.e., rectangular regions), and the average height of the graphic structure 120 in each sub-region is calculated; if the average height is less than or equal to the fourth preset height threshold (the fourth preset height threshold is greater than the first preset height threshold), and greater than or equal to the fifth preset height threshold (the fifth preset height threshold is less than the second preset height threshold), the first etching parameter corresponding to the corresponding sub-region is adjusted, such as increasing the ion concentration according to the corresponding preset increment; if the average height is less than the fifth preset height threshold, and greater than or equal to the sixth preset height threshold (the sixth preset height threshold is greater than the third preset height threshold), the first etching parameter corresponding to the corresponding sub-region is adjusted, such as increasing the ICP power according to the corresponding preset increment, thereby increasing the ion concentration; if the average height is less than the sixth preset height threshold, the current first etching parameter is maintained.

[0075] Compared to complex multilayer structures that are more suitable for the experimental stage (e.g., a sandwich structure optical waveguide with a double-layer capping layer 800, a waveguide layer 300, a buffer layer, and a shielding layer 200; or an optical waveguide with a double-layer capping layer 800 and a double-layer shielding layer 200), in this embodiment, the ion concentration in the etching parameters is set based on the sparse and dense regions of the waveguide structure, thereby reducing the difficulty of controlling the etching time of the waveguide layer due to the non-uniformity of the imprinted structure, the non-uniformity of the residual layer thickness, and the difference in etching ratio. It eliminates the need for complex deposition and etching processes, resulting in lower costs and reduced complexity of the entire optical waveguide fabrication process, and is more suitable for industrial application.

[0076] This embodiment analyzes the graphic information of the imprint template to predict the non-uniformity (micro-load effect and depth effect) during the etching process, and applies different process parameters to different areas during etching for dynamic compensation, so as to ensure global uniform etching over a large area as much as possible.

[0077] Example 6: Referring to Figure 1, this is a schematic diagram of an embodiment of an optical waveguide based on a transparent substrate according to the present invention. The optical waveguide is prepared based on the method of Example 1 or Example 5 described above. Specifically, the optical waveguide includes: a transparent substrate 100, a masking layer 200 on the transparent substrate 100, a patterned waveguide layer 300 on the masking layer 200, and a cover layer 800 covering the waveguide layer 300.

[0078] Furthermore, the masking layer 200 located on the light-transmitting substrate 100 is also patterned. Specifically, as described in Embodiment 1, since the optical waveguide has been etched, the masking layer 200 located on the light-transmitting substrate 100 is also patterned.

[0079] In other embodiments, the masking layer 200 has a double-layer structure, specifically comprising: a first protective layer 202 located on the first surface 101 of the light-transmitting substrate 100, and a second protective layer 203 located between the first protective layer 202 and the waveguide layer 300. The first protective layer 202 is obtained by depositing a silicon dioxide layer of thickness H1 on the first surface 101 of the light-transmitting substrate 100 using technologies such as HDP-CVD, SACVD, and FCVD (collectively referred to as the first deposition process); the second protective layer 203 is obtained by depositing a silicon dioxide layer of thickness H2 on the upper surface of the first protective layer 202 using technologies such as PECVD (collectively referred to as the second deposition process). Specifically, this double-layer protective layer is prepared using the method described in Embodiment 2 above. Correspondingly, the second protective layer 203 is also patterned. Preferably, the thickness H2 of the second protective layer 203 is less than the thickness H1 of the first protective layer 201.

[0080] In other embodiments, the optical waveguide further includes a buffer layer located between the shielding layer 200 and the waveguide layer 300. Specifically, the shielding layer 200 may be a single-layer structure (e.g., prepared by the preparation method of Embodiment 1) or a double-layer structure (e.g., prepared by the preparation method of Embodiment 2), while the buffer layer is prepared using the method described in Embodiment 3 above.

[0081] In other embodiments, the cover layer 800 adopts a double-layer structure, which is obtained by the preparation method described in Embodiment 4 above.

[0082] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0083] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for fabricating an optical waveguide based on a transparent substrate, characterized in that, Including the following steps: S101, a masking layer (200) is deposited on the first surface (101) of the light-transmitting substrate (100). The masking layer (200) is used to protect the light-transmitting substrate (100) during subsequent etching and to ensure the light coupling between the light-transmitting substrate (100) and light. S102, a waveguide layer (300) and an imprinted adhesive layer (400) are sequentially deposited on the second surface (201) of the shielding layer (200). S103, the embossing adhesive layer (400) is embossed using a pre-prepared embossing soft template (500) so that an embossing pattern is formed on the embossing adhesive layer (400); S104, based on the imprinted pattern, the residual layer in the groove after imprinting is etched; S105, based on the imprinted pattern, the waveguide layer (300) is over-etched using an etching gas with a preset etching selectivity to obtain the patterned waveguide layer (300). S106, Remove the imprinted adhesive layer (400) to obtain a patterned waveguide layer (300). S107, deposit a capping layer (800) on the patterned waveguide layer (300) such that the capping layer (800) and the shielding layer (200) enclose the waveguide layer (300); Specifically, step S101 includes: S1011, a first protective layer (202) with a thickness of H1 and a first morphology is deposited on the first surface (101) using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD. S1012, a second deposition process is used to deposit a silicon dioxide layer (203) with a thickness of H2 and a second morphology on the upper surface of the first protective layer (202); the second deposition process includes PECVD; Wherein, the sum of the thickness H2 of the second protective layer (203) and the thickness H1 of the first protective layer (202) is greater than or equal to 1 μm; and the first protective layer (202) of the first morphology and the second protective layer (203) of the second morphology complement each other to form the flat shielding layer (200).

2. The method for fabricating an optical waveguide based on a transparent substrate according to claim 1, characterized in that, It also includes the following steps: S201, a buffer layer of thickness H3 is deposited between the shielding layer (200) and the waveguide layer (300); the selective etching ratio of the waveguide layer (300) and the buffer layer is less than or equal to 1, correspondingly, In step S105, when the waveguide layer (300) is over-etched, the waveguide layer (300) is etched using an etching gas with a low selectivity to the waveguide layer (300) and the buffer layer.

3. A method for fabricating an optical waveguide based on a transparent substrate according to claim 1 or 2, characterized in that, It also includes the following steps: S401, the width of the graphic structure (120) corresponding to the waveguide structure (110) on the imprinted soft template is obtained in advance; S402, using the specified graphic structure as the center point, divide the area into regions with a first preset side length R1 to obtain multiple regions, thereby obtaining multiple partitions, and calculate the graphic duty cycle of each region; S403, determine whether the graphic duty cycle of each region is greater than or equal to the first preset duty cycle threshold. If the graphic duty cycle is greater than or equal to the first preset duty cycle threshold, mark the corresponding region as a dense region. If the duty cycle of the graphic is less than the first preset duty cycle threshold, the corresponding region will be marked as a sparse region. Accordingly, step S105 specifically includes: for sparse regions, over-etching is performed based on a first preset etching parameter; while for dense regions, over-etching is performed based on a second preset etching parameter; wherein, the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power.

4. The method for fabricating an optical waveguide based on a transparent substrate according to claim 3, characterized in that, In step S402, not only is the duty cycle of the graphic calculated, but also the average width of the graphic structure (120) in each region is calculated. Accordingly, step S403 specifically includes: Determine whether the duty cycle of the graphic is greater than or equal to a first preset duty cycle threshold, and whether the average width of the graphic structure in the corresponding area is less than a preset width threshold; If the duty cycle of the graphic is greater than or equal to the first preset duty cycle threshold, and the average width is less than the preset width threshold, the corresponding area is marked as a level I dense area. If the duty cycle of the graphic is greater than or equal to the first preset duty cycle threshold, and the average width is greater than the preset width threshold, the corresponding area will be marked as a Level II dense area. If the duty cycle of the graphic is less than the first preset duty cycle threshold and the average width is less than the preset width threshold, the corresponding area will be marked as a level I sparse area. If the duty cycle of the graphic is less than the first preset duty cycle threshold and the average width is greater than the preset width value, the corresponding area will be marked as a Level II sparse area. Accordingly, step S105 specifically includes: for the sparse regions of level I and level II, over-etching is performed based on the first preset etching parameters and the third preset etching parameters, respectively; the third ICP power in the third preset etching parameters is less than the first ICP power in the first preset etching parameters; for the dense regions of level I and level II, over-etching is performed based on the second preset etching parameters and the fourth preset etching parameters, respectively; the fourth ICP power in the fourth preset etching parameters is less than the second ICP power in the second preset etching parameters.

5. The method for fabricating an optical waveguide based on a transparent substrate according to claim 4, characterized in that, It also includes the following steps: S501, obtain the height of each graphic structure (120) in each dense region, and divide the region with any specified graphic structure as the center and the second preset side length R2 to obtain at least two sub-regions, and calculate the average height of the graphic structure (120) in each sub-region; S502, determine whether the average height within each sub-region is less than or equal to a first preset height threshold and greater than or equal to a second preset height threshold; the first preset height threshold is the maximum value among the average heights of all sub-regions; If the average height is less than or equal to the first preset height threshold and greater than or equal to the second preset height threshold, the etching time or ICP power in the second preset etching parameters is adjusted according to the first preset increment. If the average height is less than the second preset height threshold and greater than or equal to the third preset height threshold, adjust the etching time or ICP power in the second preset etching parameters according to the second preset increment. If the average height is less than the third preset height threshold, maintain the current second preset etching parameters.

6. The method for fabricating an optical waveguide based on a transparent substrate according to claim 3, characterized in that, The shielding layer (200) is deposited using pure SiO2 material, and the waveguide layer (300) is deposited using silicon nitride material or thin-film lithium niobate material.

7. The method for fabricating an optical waveguide based on a transparent substrate according to claim 1, characterized in that, The steps for pre-preparing the embossing soft template (500) specifically include the following steps: S301, deposit an electron beam resist layer (700) on the substrate layer (600) and expose a designated area in the electron beam resist layer (700); S302, the exposed electron beam resist layer (700) is developed to obtain the patterned electron beam resist layer (700). S303, the substrate layer (600) is etched based on the patterned electron beam adhesive layer (700) to obtain the patterned substrate layer (600). S304, a first adhesive layer (5001) and a soft film layer (5002) are sequentially deposited on the patterned substrate layer (600). S305, the base layer (600) is removed to obtain a patterned embossing soft template (500).

8. An optical waveguide based on a transparent substrate, characterized in that, The optical waveguide is fabricated using any one of the optical waveguide fabrication methods described in claims 1 to 7, and includes: a light-transmitting substrate (100), a masking layer (200) located on the light-transmitting substrate (100), and a patterned waveguide layer (300) located on the masking layer (200); the masking layer (200) is deposited on the first surface (101) of the light-transmitting substrate (100) using pure silicon dioxide material, and the thickness of the masking layer (200) is greater than or equal to 1 μm; The shielding layer (200) includes a first protective layer (202) located on a first surface (101) of the light-transmitting substrate (100) and having a first morphology, and a second protective layer (203) located between the first protective layer (202) and the waveguide layer (300) and having a second morphology; and the first protective layer (202) with the first morphology and the second protective layer (203) with the second morphology complement each other to form a flat shielding layer (200). The first protective layer (202) is obtained by depositing silicon dioxide with a thickness of H1 using a first deposition process; the second protective layer (203) is obtained by depositing silicon dioxide with a thickness of H2 using a second deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD; the second deposition process includes PECVD. And / or, it also includes a buffer layer disposed between the shielding layer (200) and the waveguide layer (300).

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