Semiconductor structure, pattern design method of mask plate, system and medium thereof

Abstract

The disclosure provides a semiconductor structure, a mask plate pattern design method, a system and a medium, the semiconductor structure comprising: a semiconductor layer including a die having a dummy structure region and a device region; a lithography alignment mark located in the dummy structure region; and an overlay mark located in the dummy structure region and adjacent to the lithography alignment mark, wherein a pattern generation rule of the overlay mark is transitioned from a pattern generation rule of the lithography alignment mark to a pattern generation rule of the device region. Since the lithography alignment mark and the overlay mark in the semiconductor structure are both located in the die, and the pattern generation rule of the overlay mark is transitioned from the pattern generation rule of the lithography alignment mark to the pattern generation rule of the device region, the optical detection environment around the periphery of the overlay mark is closer to the real environment of the device structure in the die, which is beneficial to reduce the overlay error.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure, a method for graphic design of photomasks, and a system and medium thereof. Background Technology

[0002] Photolithography is a process that transfers a pattern from a photomask onto a wafer through a series of steps, including alignment and exposure. In the manufacturing of semiconductor chips, multiple photolithography layers are required to complete the entire process. In addition to forming the device structure for each layer, photolithographic alignment marks and overlay marks are also needed. The alignment marks are used to align the photolithography machine with the wafer before the photolithography process for that layer. The overlay marks are used after the device structure has been formed through photolithography and other steps, allowing a measurement machine to check whether the device pattern in that layer is aligned with the pattern in the previous layer.

[0003] Photolithography alignment marks and overlay marks are typically placed at the edges of the exposure area, such as within the dicing channels of a wafer. Because the two marks are placed in different locations with different surrounding exposure environments, their alignment accuracy varies to varying degrees, reducing the final alignment accuracy. Summary of the Invention

[0004] In view of the above problems, there is a need to propose a new semiconductor structure, a photomask patterning method, and a system and medium thereof.

[0005] According to a first aspect of this disclosure, a semiconductor structure for a photomask is provided, comprising:

[0006] Semiconductor layer, including a die with pseudo-structure region and device region;

[0007] Photolithographic alignment marks are located in the pseudo-structure region; and

[0008] The overlay mark is located in the pseudo-structure region and is adjacent to the photolithographic alignment mark.

[0009] The pattern generation rule for the overlay mark is transitioned from the pattern generation rule for the photolithographic alignment mark to the pattern generation rule for the device area.

[0010] Optionally, the lithography alignment mark includes the standard mark of the lithography machine.

[0011] Optionally, the photolithographic alignment mark and / or the overlay mark are composed of at least a portion of the pseudo-structures of the pseudo-structure region.

[0012] According to a second aspect of this disclosure, a method for patterning a photomask is provided, the photomask being used to form photolithographic alignment marks and overlay marks for a semiconductor layer, the semiconductor layer including a die having a pseudo-structure region and a device region, the photolithographic alignment marks being adjacent to the overlay marks and located in the pseudo-structure region, the patterning method comprising:

[0013] Obtain the region in the mask corresponding to the pseudo-structure region;

[0014] Obtain the pattern generation rules for the photolithographic alignment marks and the pattern generation rules for the overlay marks;

[0015] The pattern generation rules for the overlay marks are modified so that the pattern generation rules for the overlay marks are transitioned from the pattern generation rules for the photolithographic alignment marks to the pattern generation rules for the device area;

[0016] Based on the optical analog signals of the overlay mark and the photolithographic alignment mark, determine whether the offset difference between the overlay mark and the photolithographic alignment mark is within a first preset range. If the determination result is negative, return to the step of correcting the pattern generation rule of the overlay mark.

[0017] If the determination result is yes, then according to the pattern generation rules of the photolithographic alignment mark and the modified pattern generation rules of the overlay mark, the pattern of the photolithographic alignment mark and the pattern of the overlay mark are formed in the region of the mask corresponding to the pseudo-structure region.

[0018] Optionally, after the step of forming the pattern of the photolithographic alignment mark and the pattern of the overlay mark, the pattern design method further includes:

[0019] The photolithographic alignment mark and the overlay mark are formed on the test piece;

[0020] Based on the overprint mark, determine whether the overprint error is within the second preset range. If the determination result is no, return to the step of correcting the graphic generation rule of the overprint mark.

[0021] If the judgment result is yes, then the graphic generation rules of the photolithographic alignment mark and the modified graphic generation rules of the overlay mark will be used as the design rules of the formal product.

[0022] Optionally, the pattern generation rules for the lithography alignment marks include the pattern generation rules for the standard marks of the lithography machine.

[0023] Optionally, the pattern of the photolithographic alignment mark and / or the overlay mark is composed of a combination of patterns of at least a portion of the pseudostructure corresponding to the pseudostructure region.

[0024] Optionally, the ratio of the pattern size in the photomask to the pattern size in the semiconductor layer is greater than 1.

[0025] According to a third aspect of this disclosure, a graphic design system for a photomask is provided for forming a graphic of lithographic alignment marks and a graphic of overlay marks on a photomask according to the method described above.

[0026] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0027] One of the above technical solutions has the following unexpected technical effect:

[0028] Since both the photolithographic alignment mark and the overlay mark in this semiconductor structure are located inside the die, and the pattern generation rule of the overlay mark transitions from the pattern generation rule of the photolithographic alignment mark to the pattern generation rule of the device area, the optical detection environment around the overlay mark is closer to the real environment of the device structure inside the die, which helps to reduce overlay errors.

[0029] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description

[0030] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This diagram illustrates the structure of photolithographic alignment marks and overlay marks on a wafer in the relevant technology;

[0032] Figure 2 It shows Figure 1 A magnified schematic diagram of the alignment marks in the photolithography process;

[0033] Figure 3 It shows Figure 2 A schematic diagram of the cross-sectional structure cut along line AA.

[0034] Figure 4 It shows Figure 1 Enlarged structural diagram of the inset markings;

[0035] Figure 5 It shows Figure 4 A schematic diagram of the cross-sectional structure along line BB.

[0036] Figure 6 A schematic diagram illustrating the steps of a graphic design method for a mask template according to an embodiment of the present disclosure is shown.

[0037] Figure 7 This diagram illustrates the structure of the photolithographic alignment marks and overlay marks on a wafer according to an embodiment of the present disclosure.

[0038] Figure 8 It shows Figure 7 An enlarged structural diagram of the core portion of the tube;

[0039] Figure 9 A schematic diagram illustrating the design and formation stage of an overlay mark according to an embodiment of the present disclosure is shown;

[0040] Figure 10 It shows Figure 9 A schematic diagram of the cross-sectional structure cut along line CC;

[0041] Figure 11 A schematic diagram illustrating another stage of the design and formation of overlay marks according to an embodiment of the present disclosure is shown;

[0042] Figure 12 It shows Figure 11 A schematic diagram of the cross-sectional structure cut along line DD.

[0043] Figure 13 A schematic diagram of an optical analog signal of a marker pattern according to an embodiment of the present disclosure is shown;

[0044] Figure 14 and Figure 15 A schematic diagram showing the offset difference between the overlay mark and the photolithographic alignment mark pattern according to an embodiment of the present disclosure is shown.

[0045] Explanation of reference numerals in the attached figures: 10-cut track; 11-dummy structure; 100-first die; 101-first photolithographic alignment mark; 102-first overlay mark; 110-first semiconductor layer; 20-combination mark; 200-die; 201-device area; 202-dummy structure area; 210-photolithographic alignment mark; 220-overlay mark; 230-semiconductor layer; 300-mask; 301-dummy structure pattern. Detailed Implementation

[0046] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0047] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0048] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0049] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0050] This application may be presented in various forms, some of which will be described below.

[0051] Figure 1 A schematic diagram of the structure of photolithographic alignment marks and overlay marks on a wafer in related technologies is shown, wherein only a part of the wafer structure is shown.

[0052] like Figure 1 As shown, in related technologies, multiple first dies 100 are arranged in an array on a wafer, with dicing channels 10 between adjacent first dies 100. Multiple first photolithographic alignment marks 101 and multiple first set of markings 102 are respectively disposed at different positions on the dicing channels 10, wherein the number of first set of markings 102 is greater than the number of first photolithographic alignment marks 101. However, since the two types of marks occupy different areas of the dicing channels 10, they cause the problem of occupying too much space on the dicing channels, thereby compressing the space of the first dies 100 on the wafer and reducing the yield efficiency of a single wafer.

[0053] Figure 2 It shows Figure 1 A magnified schematic diagram of the alignment marks in the photolithography process. Figure 3 It shows Figure 2 A schematic diagram of the cross-sectional structure cut along line AA. Figure 4 It shows Figure 1 Enlarged structural diagram of the markings in the middle. Figure 5 It shows Figure 4 A schematic diagram of the cross-sectional structure cut along line BB.

[0054] like Figure 2 and Figure 4 As shown, because the design specifications (such as the size of the pattern and the spacing between the patterns) of the first photolithographic alignment mark 101 and the first set of marking marks 102 are different in the photomask, when light shines on the photomask, the patterns with different design specifications will have corresponding interference and diffraction phenomena, which will have different degrees of impact on the lithographic pattern. For example, patterns with larger size and larger spacing will have smaller deformation after lithography, while patterns with smaller size and smaller spacing will have larger deformation after lithography. Moreover, since the pattern of the first photolithographic alignment mark 101 and the first set of marking marks 102 are located in different positions, the peripheral patterns of the two marks are not the same. The interference and diffraction of light passing through the peripheral patterns will also affect the lithographic patterns of the two marks. Therefore, the alignment accuracy of the first photolithographic alignment mark 101 and the first set of marking marks 102 will have different degrees of difference, reducing the final alignment accuracy.

[0055] like Figure 3 and Figure 5 As shown, the structures of the first photolithographic alignment mark 101 and the first set of marking marks 102 are, for example, oxides or nitrides filled in the grooves of the first semiconductor layer 110. After chemical mechanical polishing, due to the different sizes of the first photolithographic alignment mark 101 and the first set of marking marks 102, they suffer different degrees of damage. The degree of damage refers to the extent to which the filling material in the grooves recesses towards the bottom of the grooves. Therefore, when the first photolithographic alignment mark 101 and the first set of marking marks 102 are inspected by the photolithography machine and the measurement machine respectively, the difference in alignment accuracy is further increased.

[0056] Because the first photolithographic alignment mark 101 and the first set of marking marks 102 have different design standards and different surrounding light transmission environments, they have different degrees of differences in various alignment stages. At present, there is no design standard for evaluation marks, which leads to the need to design more comparative reference groups on the product for verification.

[0057] In view of the above problems, this disclosure proposes a new semiconductor structure, a method for graphic design of photomasks, and a system and medium thereof.

[0058] Figure 6 A schematic diagram illustrating the steps of a graphic design method for a mask template according to an embodiment of the present disclosure is shown.

[0059] See Figure 6 The graphic design method for the photomask according to embodiments of this disclosure includes:

[0060] In step S01, the region corresponding to the pseudo-structure area in the mask template is obtained;

[0061] In step S02, the pattern generation rules for the photolithographic alignment marks and the pattern generation rules for the overlay marks are obtained;

[0062] In step S03, the pattern generation rules for the overlay marks are modified so that the pattern generation rules for the overlay marks are transitioned from the pattern generation rules for the photolithographic alignment marks to the pattern generation rules for the device area.

[0063] In step S04, the offset difference between the overlay mark and the photolithography alignment mark is determined based on the optical analog signal of the overlay mark and the photolithography alignment mark. If the determination result is no, the process returns to step S03. If the determination result is yes, the process proceeds to step S05.

[0064] In step S05, the patterns of the photolithographic alignment marks and the overlay marks are formed in the region corresponding to the pseudo-structure area in the photomask according to the pattern generation rules of the photolithographic alignment marks and the modified pattern generation rules of the overlay marks.

[0065] In step S06, photolithographic alignment marks and overlay marks are formed on the test piece;

[0066] In step S07, the overlay error is determined to be within the second preset range based on the overlay mark. If the determination result is no, the process returns to step S03. If the determination result is yes, the process proceeds to step S08.

[0067] In step S08, the pattern generation rules for the photolithographic alignment marks and the pattern generation rules for the modified overlay marks are used as the design rules for the formal product.

[0068] The following will combine Figures 7 to 15 The steps of the graphic design method for the mask template according to the embodiments of this disclosure will be described in detail.

[0069] Figure 7 This diagram illustrates the structure of the photolithographic alignment marks and overlay marks on a wafer according to an embodiment of the present disclosure. Figure 8 It shows Figure 7 An enlarged structural diagram of the core portion of the tube.

[0070] See Figure 7 and Figure 8 In the wafer of this embodiment, multiple dies 200 are arranged in an array on the wafer. Each die 200 has an adjacent device region 201 and a dummy structure region 202. In this embodiment, a combined mark 20 of photolithographic alignment mark 210 and overlay mark 220 is set in the dummy structure region of the die 200. Therefore, the spacing between adjacent dies 200 is relatively... Figure 1 The situation shown is greatly reduced. In this case, the photolithographic alignment mark 210 is adjacent to the overlay mark 220, and the overlay mark 220 is closer to the device region 201.

[0071] Regarding the graphic design method of the photomask, it is first necessary to search for areas without device patterns in the original layout of the photomask. These areas without device patterns originally need to be set with dummy patterns to meet the stress, strength and other conditions in the die 200. After finding the areas without device patterns, these areas are the corresponding dummy pattern areas in the photomask.

[0072] Furthermore, the pattern generation rules of the photolithography alignment mark 210 and the pattern generation rules of the overlay mark 220 are obtained. The pattern generation rules are, for example, design rules, including the shape and size of the pattern, the spacing between patterns, the density of surrounding patterns, the aperture ratio, etc. Different design rules result in different pattern exposure environments.

[0073] The lithography alignment mark 210 includes standard markings for lithography equipment, such as ASML, Nikon, and Canon lithography equipment. In some specific embodiments, the lithography alignment mark 210 adopts the standard markings for Nikon lithography equipment, and its shape is similar to... Figure 2 As shown. In some other embodiments, standard markings provided by lithography machines from other manufacturers may also be used as lithography alignment markings 210.

[0074] Figure 9 This diagram illustrates a design and formation stage of an overlay mark according to an embodiment of the present disclosure, wherein... Figure 9 The upper left part represents a portion of the original pseudo-structure pattern 301 in the mask template 300, the upper right part represents the original pseudo-structure pattern 301 corresponding to the pseudo-structure 11 formed in the first die 100, the lower left part represents the pattern of the overlay mark 220 formed by combining the pseudo-structure pattern 301 in this embodiment, and the lower right part represents the pattern of the overlay mark corresponding to the overlay mark 220 formed in the die 200.

[0075] See Figure 9The pseudo-structure pattern 301 on the photomask 300 is, for example, a small block arranged in an array. The ratio of the pattern size in the photomask 300 to the pattern size in the semiconductor layer is greater than 1. In some specific embodiments, the ratio of the pattern size in the photomask 300 to the pattern size in the semiconductor layer is 4:1. Therefore, when the patterns of the small block overlay marks 220 on the photomask 300 are combined according to the generation rules, the images of the corresponding small block pattern groups formed on the die 200 on the lithography machine and the measurement machine will be fused together to form the overlay marks 220. Specifically, when four small blocks are combined on the photomask 300 but do not contact each other, the corresponding image on the die 200 is a large block pattern; when ten small blocks are combined on the photomask 300 but do not contact each other, the corresponding image on the die 200 is a long strip pattern.

[0076] Figure 10 It shows Figure 9 A schematic diagram of the cross-sectional structure cut along the CC line.

[0077] See Figure 10 Although the small patterns formed on the die 200 will merge together in the lithography and measurement equipment images, the individual small pieces remain separate within the semiconductor layer 230 of the die 200. Corresponding materials are filled into the grooves of the semiconductor layer 230 to form overlay marks 220. Because the size of each separate small piece is very small, the degree to which the filling material sinks into the bottom of the groove is also very small after the chemical mechanical polishing process. Similarly, the lithography alignment mark 210 can also be composed of small pieces. In this way, the degree of damage to the lithography alignment mark 210 and the overlay mark 220 after the chemical mechanical polishing process is nearly identical, thereby reducing measurement errors.

[0078] Figure 11 This diagram illustrates another stage of the design and formation of overlay marks according to an embodiment of the present disclosure. Figure 12 It shows Figure 11 A schematic diagram of the cross-sectional structure cut along line DD.

[0079] See Figure 11 and Figure 12 The pseudo-structural patterns 301 on the photomask 300 are parallel stripes with very small spacing. The corresponding stripe patterns formed on the die 200 will merge together on the lithography and measurement equipment, forming a relatively thick elongated overlay mark 220. However, within the semiconductor layer 230 of the die 200, each stripe remains separate. Similarly, the lithography alignment mark 210 can also be composed of stripes.

[0080] Furthermore, the pattern generation rules for the overlay mark 220 are modified to transition from the pattern generation rules of the lithographic alignment mark 210 to the pattern generation rules of the device area. Since the pattern generation rules for the lithographic alignment mark 210 and the device area differ significantly, to better approximate the environment of the device area with the combination of the lithographic alignment mark 210 and the overlay mark 220, for example, a lithographic alignment mark 210 is first added at the center of the unpatterned area, and then overlay marks 220 are added around the lithographic alignment mark 210. The closer the overlay mark 220 is to the area of ​​the device pattern, the closer its pattern generation rules are to the device pattern; the closer it is to the area of ​​the lithographic alignment mark 210, the closer its generation rules are to the lithographic alignment mark 210. In some specific embodiments, the modification process can employ a computational lithography model.

[0081] Furthermore, based on the optical analog signals of the overlay mark 220 and the photolithographic alignment mark 210, it is determined whether the offset difference between the overlay mark 220 and the photolithographic alignment mark 210 is within a first preset range. The following will combine... Figures 13 to 15 The steps for determining the offset difference in embodiments of this disclosure will be described in detail.

[0082] Figure 13 A schematic diagram of the optical simulation signal of the marking pattern according to an embodiment of the present disclosure is shown, wherein the upper thick and thin stripes represent the photolithographic alignment mark 210 or the overlay mark 220, the lower horizontal axis represents the corresponding position of each pattern in the marking, and the vertical axis represents the light transmission intensity of the simulated pattern.

[0083] See Figure 13 The different thicknesses of the stripes in the marking result in different simulated light transmission intensities. Thinner stripes have weaker light transmission intensity, while thicker stripes have stronger light transmission intensity. Only the signal corresponding to the thicker stripes, i.e., the signal between the two dashed lines, needs to be selected.

[0084] Figure 14 and Figure 15 This diagram illustrates the offset difference between the overlay marks and the photolithographic alignment marks according to an embodiment of the present disclosure. Figure 14 and Figure 15 The horizontal axis represents the number of offsets compared, for example, 12 wafers are selected for comparison in a batch. The vertical axis represents the offset difference, in micrometers (μm).

[0085] See Figure 14First, the optical simulation signals of the two-layer lithographic alignment mark 210 pattern are acquired. Using the first layer as a reference, the offset of the second-layer lithographic alignment mark 210 pattern in the X and Y axes is calculated. This offset is used as the reference offset. The X and Y axes are, for example, the wafer coordinate system. The optical simulation signals are generated, for example, by computer simulation. Then, the optical simulation signals of the two-layer overlay mark 220 pattern are acquired. Using the first layer as a reference, the offset of the second-layer overlay mark 220 pattern in the X and Y axes is calculated. This offset is used as the comparison offset. Finally, the difference between the comparison offset on the X-axis and the reference offset on the X-axis is obtained, for example, by... Figure 14 The white dots in the diagram represent the offset of the Y-axis. The offset difference is obtained by subtracting the Y-axis reference offset from the Y-axis offset. For example, from... Figure 14 The black dots in the text indicate that if the preset value of the specified offset difference is within ±0.01μm, such as... Figure 14 The offset difference between the overlay mark 220 and the photolithographic alignment mark 210 is close to 0, within ±0.01μm. Step S05 can be performed, whereby the photolithographic alignment mark and overlay mark are formed in the region corresponding to the pseudo-structure area in the photomask according to the pattern generation rules of the photolithographic alignment mark and the modified pattern generation rules of the overlay mark. Then, step S06 is performed to form the photolithographic alignment mark 210 and overlay mark 220 on the test wafer. And as... Figure 15 The difference in Y-axis offset between the overlay mark 220 and the photolithographic alignment mark 210 is between -0.01 and -0.02 μm, which is not within the range of ±0.01 μm. Therefore, it is necessary to return to step S03 to further correct the pattern generation rules of the overlay mark 220.

[0086] However, the embodiments disclosed herein are not limited thereto, and those skilled in the art can make other settings for the first preset range according to the needs of the semiconductor process node.

[0087] Further, after forming the photolithographic alignment mark 210 and the overlay mark 220 on the test wafer, the overlay mark 220 on the test wafer is measured by a measuring instrument. Based on the overlay mark 220, it is determined whether the overlay error between the two layers is within a second preset range. If the determination result is yes, step S08 is performed, and the pattern generation rules of the photolithographic alignment mark 210 and the corrected pattern generation rules of the overlay mark 220 are used as the design rules for the formal product. If the determination result is no, it is necessary to return to step S03 to further modify the pattern generation rules of the overlay mark 220. Those skilled in the art can make other settings for the second preset range according to the needs of the semiconductor process node.

[0088] This disclosure also provides a graphic design system for a photomask, which can be used to design the graphic of the photomask according to the graphic design method of this disclosure. The photomask includes, for example, photolithographic alignment mark graphics and overlay mark graphics in the corresponding pseudo-structure region.

[0089] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the graphic design method for a mask template as described above.

[0090] One of the above technical solutions has the following unexpected technical effect:

[0091] Since both the photolithographic alignment mark and the overlay mark in this semiconductor structure are located inside the die, and the pattern generation rule of the overlay mark transitions from the pattern generation rule of the photolithographic alignment mark to the pattern generation rule of the device area, the optical detection environment around the overlay mark is closer to the real environment of the device structure inside the die, which helps to reduce overlay errors.

[0092] The integration of lithographic alignment marks and overlay marks facilitates joint identification by lithography and metrology equipment. Furthermore, since the lithographic alignment marks and overlay marks are composed of smaller pseudo-structural patterns, their resistance to the influence of previous layer processes (such as chemical mechanical polishing) can be improved, further optimizing the quality of the marking signals.

[0093] The offset difference between the photolithography alignment mark and the overlay mark is compared using optical analog signals. This establishes a standard for the deviation between the overlay mark and the photolithography alignment mark (the standard mark provided by the photolithography machine manufacturer) based on the generation (semiconductor process node), making it easy to use in the manufacturing of various types of devices.

[0094] Various photolithography alignment marks and overlay marks can be integrated into a single mark through a combination process, which can effectively reduce the space occupied by the marks on the mask, while uniformly marking the surrounding light-transmitting environment.

[0095] As the process node improves, the number of overlay marks is much greater than that of photolithography alignment marks. After being integrated into a combined mark, the number of photolithography alignment marks will increase with the number of overlay marks, and the photolithography alignment error in the exposure area can be better monitored.

[0096] After determining the qualified markings based on the optical analog signals, actual markings are then formed on the test piece. This ensures better alignment with product design rules and allows for more accurate measurement of the overprinted marking signals. Furthermore, all overprinted markings are linked to photolithographic alignment marks to further reduce alignment errors caused by design variations and the surrounding environment.

[0097] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Furthermore, any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory.

[0098] As described above, these embodiments of the present disclosure do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. The scope of protection of this disclosure should be determined by the scope defined by the claims and their equivalents.

Claims

1. A semiconductor structure, comprising: Semiconductor layer, including a die with pseudo-structure region and device region; Photolithographic alignment marks are located in the pseudo-structure region; as well as Overlay marks are located in the pseudo-structure region and adjacent to the photolithographic alignment marks, with at least a portion of the overlay marks being closer to the device region than the photolithographic alignment marks. The pattern generation rule for the overlay mark is transitioned from the pattern generation rule for the photolithographic alignment mark to the pattern generation rule for the device area.

2. The semiconductor structure according to claim 1, wherein, The lithographic alignment marks include the standard marks of the lithography machine.

3. The semiconductor structure according to claim 1, wherein, The photolithographic alignment mark and / or the overlay mark are composed of at least a portion of the pseudostructure of the pseudostructure region.

4. A method for patterning a photomask, the photomask being used to form photolithographic alignment marks and overlay marks for a semiconductor layer, the semiconductor layer including a die having a dummy structure region and a device region, the photolithographic alignment marks being adjacent to the overlay marks and located in the dummy structure region, at least a portion of the overlay marks being closer to the device region than the photolithographic alignment marks, the patterning method comprising: Obtain the region in the mask corresponding to the pseudo-structure region; Obtain the pattern generation rules for the photolithographic alignment marks and the pattern generation rules for the overlay marks; The pattern generation rules for the overlay marks are modified so that the pattern generation rules for the overlay marks are transitioned from the pattern generation rules for the photolithographic alignment marks to the pattern generation rules for the device area; Based on the optical analog signals of the overlay mark and the photolithographic alignment mark, determine whether the offset difference between the overlay mark and the photolithographic alignment mark is within a first preset range. If the determination result is negative, return to the step of correcting the pattern generation rule of the overlay mark. If the determination result is yes, then according to the pattern generation rules of the photolithographic alignment mark and the modified pattern generation rules of the overlay mark, the pattern of the photolithographic alignment mark and the pattern of the overlay mark are formed in the region of the mask corresponding to the pseudo-structure region.

5. The graphic design method according to claim 4, after the step of forming the graphic of the photolithographic alignment mark and the graphic of the overlay mark, the graphic design method further includes: The photolithographic alignment mark and the overlay mark are formed on the test piece; Based on the overprint mark, determine whether the overprint error is within the second preset range. If the determination result is no, return to the step of correcting the graphic generation rule of the overprint mark. If the judgment result is yes, then the graphic generation rules of the photolithographic alignment mark and the modified graphic generation rules of the overlay mark will be used as the design rules of the formal product.

6. The graphic design method according to claim 4, wherein, The rules for generating the lithographic alignment marks include the rules for generating the standard marks of the lithography machine.

7. The graphic design method according to claim 4, wherein, The patterns of the photolithographic alignment marks and / or the overlay marks are composed of a combination of patterns of at least a portion of the pseudostructure corresponding to the pseudostructure region.

8. The graphic design method according to claim 7, wherein, The ratio of the pattern size in the photomask to the pattern size in the semiconductor layer is greater than 1.

9. A photomask graphic design system for forming a pattern of photolithographic alignment marks and a pattern of overlay marks on a photomask according to the method of any one of claims 4 to 8.

10. A computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the method as claimed in any one of claims 4 to 8.

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