Server management control circuit, system and server

Abstract

The application discloses a kind of server management control circuit, system and server, it is related to server technical field, including: baseboard management unit, programmable control module and first connector;Baseboard management unit is connected with programmable control module and first connector communication;Programmable control module is also connected with first connector communication;Baseboard management unit is used to generate first control instruction and second control instruction, and sends first control instruction to server main circuit by first connector;Programmable control module is used to receive the second control instruction sent by baseboard management unit, and sends second control instruction to server main circuit by first connector, so that the complete management and control to server main circuit are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a server management control circuit, a system and a server. BACKGROUND

[0002] The server management control circuit is a special circuit in the server hardware responsible for remote monitoring, fault diagnosis, power control and other management functions. Due to the size limitation of the server mainboard in the current MGX specification, the size of the server mainboard is increased, which compresses the installation space of the management board corresponding to the server management control circuit. Therefore, by removing some components on the original management board, such as external interfaces, the size of the original management board is reduced.

[0003] In the related art, due to the size reduction and removal of some components of the original management board, the baseboard management unit on the current management board cannot send complete control instructions to the server main circuit as the baseboard management unit of the original management board. Therefore, there is an urgent need for a server management control circuit that can realize the functions of the original management board. SUMMARY

[0004] The present application provides a server management control circuit, a system and a server to at least solve the problem that in the related art, due to the size reduction and removal of some components of the original management board, the baseboard management unit on the current management board cannot send complete control instructions to the server main circuit as the baseboard management unit of the original management board.

[0005] The present application provides a server management control circuit (10), comprising: a baseboard management unit (101), a programmable control module (102) and a first connector (103);

[0006] The baseboard management unit (101) is in communication connection with the programmable control module (102) and the first connector (103); the programmable control module (102) is also in communication connection with the first connector (103); the first connector (103) comprises a low-speed signal transmission interface (1032), which is a common interface for the baseboard management unit (101) and the programmable control module (102) to communicate with the first connector (103);

[0007] The baseboard management unit (101) is configured to generate first control instructions and second control instructions, and send the first control instructions to the server main circuit (20) through the first connector (103);

[0008] The programmable control module (102) is configured to receive the second control instruction sent by the baseboard management unit (101), and send the second control instruction to the server main circuit (20) through the low-speed signal transmission interface (1032).

[0009] The application further provides a server management control system, which comprises the server management control circuit (10) and the server main circuit (20) described above.

[0010] The server management control circuit (10) is configured to control the running state of at least one first component in the server main circuit (20) based on the first control instruction, and control the running state of at least one second component in the server main circuit (20) or an external device connected with the server main circuit based on the second control instruction.

[0011] The application further provides a server comprising the server management control system described above.

[0012] The server management control circuit, system and server provided by the application are based on the baseboard management unit 101, the programmable control module 102 and the first connector 103 to construct the corresponding server management control circuit 10. The baseboard management unit 101 is configured to generate the first control instruction and the second control instruction, and send the first control instruction to the server main circuit 20 through the first connector 103. The programmable control module 102 is configured to receive the second control instruction sent by the baseboard management unit 101, and send the second control instruction to the server main circuit 20 through the low-speed signal transmission interface 1032. Thus, the original management board of the server management control circuit can still send the second control instruction, which cannot be directly sent to the server main circuit through the baseboard management unit, to the server main circuit by means of the programmable control module and the first connector after the external interface is deleted, so as to realize complete management and control of the server main circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0014] Figure 1 The structural schematic diagram of the server management control circuit provided by the embodiments of the application is shown in the figure.

[0015] Figure 2 The structural schematic diagram of the server management control system provided by the embodiments of the application is shown in the figure.

[0016] Figure 3A structure schematic diagram of a first server running circuit provided by an embodiment of the present application is shown in FIG. 1.

[0017] Figure 4 A structure schematic diagram of a second server running circuit provided by an embodiment of the present application is shown in FIG. 2.

[0018] Figure 5 A structure schematic diagram of a third server running circuit provided by an embodiment of the present application is shown in FIG. 3.

[0019] Figure 6 A structure schematic diagram of a second front data transmission circuit provided by an embodiment of the present application is shown in FIG. 4.

[0020] Reference signs:

[0021] 10: server management control circuit;

[0022] 101: baseboard management unit; 1011: baseboard management controller; 1012: memory; 10121: non-volatile memory unit; 10122: random access memory; 10123: long-term memory;

[0023] 102: programmable control module; 1021: programmable control device; multiplexer: 10211; bus slave device: 10212; transmission switch: 10213; 1022: physical slot;

[0024] 103: first connector; 1031: first serial communication interface; 1032: low-speed signal transmission interface; 1033: general-purpose pin; 1034: peripheral component interconnect bus interface; 1035: second serial communication interface; 1036: third serial communication interface; 1037: test interface; 1038: universal serial bus interface; 1039: video graphics array interface; 10310: network controller sideband interface; 10311: enhanced serial peripheral interface; 10312: fourth serial communication interface unit; 10313: serial standard interface;

[0025] 104: physical layer module;

[0026] 105: power module;

[0027] 20: server main circuit;

[0028] 201: second connector;

[0029] 202: first server running circuit; 2021: first multiplexer; 2022: second multiplexer; 2023: first processor; 2024: first interface flash memory; 2025: second interface flash memory; 2026: row pin slot; 2027: first level shifter; 2028: second level shifter; 2029: second programmable control device; 20210: fourth multiplexer;

[0030] 203: second server running circuit; 2031: first serial storage protocol interface; 2032: first programmable control device; 2033: intelligent network card serial port; 2034: expansion interface unit; 2035: edge connector; 2036: data management hardware expansion board; 2037: fifth serial storage protocol interface; 2038: second processor; 2039: third level shifter; 20310: row pin connector;

[0031] 204: third server running circuit; 2041: third multiplexer; 2042: logic processor; 2043: conversion transceiver assembly; 20431: first conversion transceiver; 20432: second conversion transceiver; 20433: third conversion transceiver; 2044: third processor; 2045: fourth processor; 2046: bus expander; 2047: third programmable control device; 2048: test interface physical connector;

[0032] 205: third serial storage protocol interface;

[0033] 30: first front data transmission circuit; 301: second serial storage protocol interface; 302: protocol converter; 303: mobile device interface;

[0034] 40: power distribution board; 401: sixth serial storage protocol interface; 402: power distribution device unit; 4021: multiple power distribution devices; 403: disk array hardware management interface;

[0035] 50: second front data transmission circuit; 501: fourth serial storage protocol interface; 502: front physical layer module; 503: network interface. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0037] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or equipment. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0038] The server management control circuit is a special circuit in the server hardware responsible for remote monitoring, fault diagnosis, power control and other management functions. Due to the size limitation of the server mainboard in the current MGX specification, the size of the server mainboard is increased, which compresses the installation space of the management board corresponding to the server management control circuit. Therefore, by removing some components on the original management board, such as external interfaces, the size of the original management board is reduced. In related technologies, due to the reduction in size of the original management board and the removal of some components, the baseboard management unit on the current management board cannot send complete control instructions to the server main circuit as the baseboard management unit of the original management board does. Therefore, there is an urgent need for a server management control circuit that can realize the functions of the original management board.

[0039] To solve the above technical problems, the present application embodiment proposes the following technical concept: the inventor considers a server management control circuit constructed by a baseboard management unit, a programmable control module and a first connector, generates a first control instruction and a second control instruction based on the baseboard management unit, and sends the first control instruction to the server main circuit through the first connector. The programmable control module sends the second control instruction sent by the baseboard management unit to the server main circuit through the low-speed signal transmission interface in the first connector, so that the original management board corresponding to the server management control circuit can also send the second control instruction that cannot be directly sent to the server main circuit through the baseboard management unit to the server main circuit by means of the programmable control module and the first connector after the external interface is deleted, thereby realizing complete management and control of the server main circuit.

[0040] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0041] Figure 1 The structure diagram of the server management control circuit provided by the present application embodiment is shown.

[0042] As shown in Figure 1 The server management control circuit 10 includes a baseboard management unit 101, a programmable control module 102 and a first connector 103.

[0043] The substrate management unit 101 is in communication connection with the programmable control module 102 and the first connector 103; the programmable control module 102 is also in communication connection with the first connector 103; the first connector 103 comprises a low-speed signal transmission interface 1032, which is a common interface for the substrate management unit 101 and the programmable control module 102 to communicate with the first connector 103.

[0044] Exemplarily, the low-speed signal transmission interface 1032 is an LTPI.

[0045] The first connector 103 is a GF connector, i.e., a GF Connector, which is a key component for realizing efficient interconnection in electronic equipment and is widely used in the fields of communication, calculation, industrial control, etc.

[0046] The substrate management unit 101 is configured to generate a first control instruction and a second control instruction, and send the first control instruction to the server main circuit 20 through the first connector 103.

[0047] The programmable control module 102 is configured to receive the second control instruction sent by the substrate management unit 101, and send the second control instruction to the server main circuit 20 through the low-speed signal transmission interface 1032.

[0048] With reference to Figure 1 , the substrate management unit 101 comprises a substrate management controller 1011 and a memory 1012, and is in communication connection with the first connector; the first connector 103 comprises a test interface 1037.

[0049] The substrate management controller 1011 is in communication connection with the memory 1012 and the first connector 103 through the test interface 1037.

[0050] The substrate management controller 1011, i.e., BMC, is a full name of Baseboard Management Controller, which is an independent management module in the server hardware, has a processor and a memory, and can remotely monitor the server state even if the host is down.

[0051] Exemplarily, the model of the substrate management controller 1011 is AST2600.

[0052] The substrate management controller 1011 is specifically configured to generate a corresponding control instruction, divide the control instruction into a first control instruction and a second control instruction based on the interface type of the substrate management controller 1011 in communication connection with the first connector, and send the first control instruction to the server main circuit 20 through the test interface 1037.

[0053] The substrate management controller 1011 is configured to control the memory 1012 to store operation data of the server.

[0054] In addition, the memory 1012 further includes a non-volatile memory unit 10121, a random access memory 10122, and a long-term memory 10123, which are respectively in communication connection with the substrate management controller 1011.

[0055] The substrate management controller 1011 is configured to control the non-volatile memory unit 10121 to store firmware configuration data of the substrate management unit 101.

[0056] The substrate management controller 1011 is configured to control the random access memory 10122 to store basic information of the server.

[0057] The substrate management controller 1011 is configured to control the long-term memory 10123 to store error information of the server.

[0058] In the embodiment, the non-volatile memory unit 10121 includes one or more non-volatile memories.

[0059] For example, the substrate management controller 1011 is in communication connection with the non-volatile memory unit 10121 through a BMC_FWSPI.

[0060] The BMC_FWSPI is the full name of BMC Firmware SPI, which is a key interface for firmware storage and refreshing in the server motherboard management controller.

[0061] The non-volatile memory is a BMC Flash.

[0062] The random access memory 10122 is a DDR4 SDRAM.

[0063] The long-term memory 10123 is an EMMC.

[0064] With reference to the above description, the programmable control module 102 includes a programmable control device 1021 and a physical slot 1022. Figure 1 The programmable control device 1021 is in communication connection with the physical slot 1022, the substrate management controller 1011, and the first connector 103, respectively.

[0065] The programmable control device 1021 is in communication connection with the physical slot 1022, the substrate management controller 1011, and the first connector 103, respectively.

[0066] In the server management control circuit 10, the programmable control device 1021 is in communication connection with the baseboard management controller 1011 through BMC_JTAG2_TRST, BMC_JTAG2_TMS, BMC_JTAG2_TDI, BMC_JTAG2_TDO and BMC_JTAG2_TCK; the physical slot 1022 is in communication connection with the programmable control device 1021 and the baseboard management controller 1011 respectively through JTAG_TMS_CPU_CONN, JTAG_TCK_CONN_CPU_R, JTAG_TDO_CPU_CONN, JTAG_TDI_CPU_CONN and JTAG_TRST_CPU_CONN_L.

[0067] The baseboard management controller 1011 is in communication connection with the first connector 103 through BMC_JTAG1_TCK, BMC_JTAG1_TDO, BMC_JTAG1_TDI, BMC_JTAG1_TMS and BMC_JTAG1_TRST.

[0068] In the embodiment, the programmable control device 1021 is a CPLD, full name is Complex Programmable Logic Device, and exemplarily, the model is 10M25DAF256.

[0069] In the embodiment, the physical slot 1022 is a JTAG HEADER.

[0070] In the embodiment, the programmable control device 1021 is in communication connection with the baseboard management controller 1011 through 4*UART, 2*3.3V I2C (11, 12), GPIOs and JTAG.

[0071] In the embodiment, the UART, full name is Universal Asynchronous Receiver / Transmitter, is a serial communication interface corresponding to a universal asynchronous receiver / transmitter.

[0072] In the embodiment, the 2*3.3V I2C (11, 12) refers to two groups of 3.3V level I2C buses, which are connected to the 11th and 12th devices respectively.

[0073] In the embodiment, the I2C, full name is Inter-Integrated Circuit, is a two-wire serial synchronous communication protocol, which adopts a half-duplex mode and realizes communication between master and slave devices through a data line and a clock line.

[0074] GPIOs, which is the full name of General Purpose Input / Output, corresponds to the general-purpose pin.

[0075] JTAG, which is the full name of Joint Test Action Group, corresponds to the test interface.

[0076] In addition, the physical slot 1022 is connected with 4*UART, 2*3.3V I2C (11, 12), GPIOs and JTAG respectively.

[0077] The programmable control device 1021 is configured to receive the second control instruction sent by the baseboard management unit 101, and send the second control instruction to the server main circuit 20 through the low-speed signal transmission interface 103.

[0078] The transmission of BMC_JTAG1_TCK, BMC_JTAG1_TDO, BMC_JTAG1_TDI, BMC_JTAG1_TMS and BMC_JTAG1_TRST is performed through the low-speed signal transmission interface 103.

[0079] With reference to Figure 1 The programmable control device 1021 is connected with the baseboard management controller 1011 through the first standard test interface, and the physical slot 1022 is connected on the first standard test interface through the second standard test interface.

[0080] In this embodiment, the first standard test interface corresponds to BMC_JTAG2_TDO, BMC_JTAG2_TCK, BMC_JTAG2_TMS and BMC_JTAG2_TRST.

[0081] In this embodiment, the second standard test interface corresponds to JTAG_TMS_CPU_CONN, JTAG_TCK_CONN_CPU_R, JTAG_TDI_CPU_CONN and JTAG_TRST_CPU_CONN_L, etc.

[0082] The baseboard management controller 1011 is configured to adjust the function of the programmable control device 1021.

[0083] With reference to Figure 1 The programmable control device 1021 comprises a multiplexer 10211 and a bus slave device 10212.

[0084] The multiplexer 10211 is communicatively connected to the substrate management controller 1011 and the first connector 103, respectively; the bus slave device 10212 is communicatively connected to the substrate management controller 1011.

[0085] In addition, the programmable controller 1021 also includes a transmission switch 10213, which is communicatively connected to the multiplexer 10211 and the bus slave device 10212.

[0086] In this embodiment, the multiplexer 10211 is communicatively connected to the board management controller 1011 via UART1_SYS_R_TX, UART1_SYS_R_RX, UART3_BMC_SMART_NIC_R_TX, UART3_BMC_SMART_NIC_R_RX, UART4_BMC_TX, UART4_BMC_RX, UART5_BMC_D_TX, and UART5_BMC_D_RX.

[0087] In this embodiment, the bus slave device 10212 communicates with the baseboard management controller 1011 via ADDR:0x20.

[0088] Among them, the multiplexer 10211 is a MUX, which stands for Multiplexer. It is widely used in the fields of electronic engineering and digital communication. Its core function is to select the corresponding output from multiple inputs through control signals to achieve efficient signal transmission and resource multiplexing.

[0089] Among them, the transmission switch 10213 is a UARTSwitch &detect.

[0090] Among them, the bus slave device 10212 is I2C_slave.

[0091] The baseboard management controller 1011 is used to read the device information corresponding to the bus slave device 10212 and send the data transmission request to the bus slave device 10212 according to the device information.

[0092] Bus slave device 10212 is used to generate a data transmission response based on the data transmission request and send the data transmission response to the board management controller 1011.

[0093] The baseboard management controller 1011 is used to send a preset number of second control commands to the multiplexer 10211 through multiple sets of internal serial communication interfaces based on data transmission response.

[0094] The multiplexer is used to filter each second control command and send the filtered second control commands to the server main circuit 20 through the low-speed signal transmission interface 1032.

[0095] With reference to the foregoing Figure 1 Further comprising: a physical layer module 104.

[0096] The physical layer module 104 is in communication connection with the baseboard management unit 101 and the first connector 103 respectively.

[0097] The physical layer module 104 is a PHY, i.e. Physical Layer; exemplarily, the model is RTL8211FS-CG.

[0098] The physical layer module 104 is configured to convert the network signal in parallel transmission mode sent by the baseboard management unit 101 into a network signal in serial transmission mode, and send the network signal in serial transmission mode to the server main circuit 20 through the first connector 103.

[0099] Exemplarily, the parallel transmission mode is RGMII, and the serial transmission mode is SGMII.

[0100] With reference to the foregoing Figure 1 The baseboard management controller 1011 in the baseboard management unit 101 is in communication connection with the physical layer module 104 through a plurality of internal Ethernet interfaces and a first internal serial interface.

[0101] In the embodiment, the first internal serial interface is an MDC / MDIO1 bus interface.

[0102] The MDC is used for managing data clock; and the MDIO1 is used for managing data input / output.

[0103] The baseboard management controller 1011 is configured to send the network signal in parallel transmission mode to the physical layer module through the plurality of internal Ethernet interfaces.

[0104] In the embodiment, the plurality of internal Ethernet interfaces are BMC_RGMIIRXD0, BMC_RGMIIRXD1, BMC_RGMIIRXD2, BMC_RGMIIRXD3, BMC_RGMIIRXCK, BMC_RGMIIRXCTL, BMC_RGMIITXD0, BMC_RGMIITXD1, BMC_RGMIITXD2, BMC_RGMIITXD3, BMC_RGMIITXCK and BMC_RGMIITXCTL.

[0105] The baseboard management controller 1011 is further configured to control the physical layer module 104 to transmit the network signal to the first connector 103 through the first internal serial interface.

[0106] With reference to the foregoing Figure 1The first connector 103 further comprises a serial standard interface 10313.

[0107] The first connector 103 is in communication connection with the physical layer module 104 and the server main circuit 20 respectively through the serial standard interface 10313.

[0108] The serial standard interface 10313 is configured to transmit the network signal in the serial transmission mode transmitted by the physical layer module 104 to the server main circuit 20.

[0109] Exemplarily, the serial standard interface 10313 is SGMII.

[0110] Continuing to refer to Figure 1 The first connector 103 further comprises a first serial communication interface 1031.

[0111] The first connector 103 is in communication connection with the programmable control module 102 through the first serial communication interface 1031.

[0112] The first serial communication interface 1031 is configured to transmit the internal state information of the programmable control module 102 to the server main circuit 20.

[0113] In the embodiment, the first serial communication interface 1031 can be a UART interface, or can be another interface.

[0114] The UART is a widely used serial communication interface, which realizes full-duplex communication through two signal lines, does not need to share a clock signal, and only needs to agree on the same baud rate to complete data transmission.

[0115] The low-speed signal transmission interface 1032 is configured to control the data flow of the programmable control module 102 transmitted to the server main circuit 20 to be less than a preset data flow threshold.

[0116] In the embodiment, the first serial communication interface 1031 is in communication connection with the programmable control module 102 through 1*UART, and the low-speed signal transmission interface 1032 is in communication connection with the programmable control module 102 through LTPI (2*I2C, 2*UART, GPIOs).

[0117] The LTPI (2*I2C, 2*UART, GPIOs) realizes the corresponding low-speed transmission protocol through two groups of I2C buses, two groups of UARTs and general-purpose pins.

[0118] LTPI, which stands for Low-Voltage Differential Signaling Tunneling Protocol and Interface, is a low-speed transmission protocol based on low-voltage differential signaling.

[0119] The first serial communication interface 1031 is a UART.

[0120] The low-speed signal transmission interface 1032 is an LTPI.

[0121] In addition, the first connector 103 further includes: general-purpose pins 1033, a peripheral component interconnect bus interface 1034, a second serial communication interface 1035, a third serial communication interface 1036, a test interface 1037, a universal serial bus interface 1038, a video graphics array interface 1039, a network controller sideband interface 10310, an enhanced serial peripheral interface 10311, and a fourth serial communication interface unit 10312.

[0122] The general-purpose pins 1033 are GPIOs; the peripheral component interconnect bus interface 1034 is a PCIe; the second serial communication interface 1035 is a QSPI; the third serial communication interface 1036 is an I3C; the test interface 1037 is a JTAG; the universal serial bus interface 1038 is a USB; the video graphics array interface 1039 is a VGA; the network controller sideband interface 10310 is a NCSI; the enhanced serial peripheral interface 10311 is an ESPI; and the fourth serial communication interface unit 10312 is an I2C.

[0123] The general-purpose pins 1033, the peripheral component interconnect bus interface 1034, the second serial communication interface 1035, the third serial communication interface 1036, the test interface 1037, the universal serial bus interface 1038, the video graphics array interface 1039, the network controller sideband interface 10310, the enhanced serial peripheral interface 10311, and the fourth serial communication interface unit 10312 are in communication connection with the baseboard management unit 101; and in communication connection with the server main circuit 20.

[0124] In this embodiment, the peripheral component interconnect bus interface 1034 is in communication connection with the baseboard management unit 101 through P2E_CPU_BMC_EP X1.

[0125] In this embodiment, the second serial communication interface 1035 communicates with the substrate management unit 101 via QSPI (for 2*BIOS Flash).

[0126] Among them, QSPI (for 2*BIOS Flash) is a dual BIOS Flash architecture implemented through the QSPI protocol.

[0127] In this embodiment, the third serial communication interface 1036 is connected to the substrate management unit 101 via 2*I3C (1 for SPD, 1 for DBG and MNG).

[0128] Among them, 2*I3C (1 for SPD, 1 for DBG and MNG) are used in the dual I3C channel design, one channel is dedicated to SPD Hub, and the other is used for debugging and managing DBG & MNG, so as to achieve functional isolation and performance optimization.

[0129] In this embodiment, the test interface 1037 is connected to the substrate management unit 101 via JTAG (for ASD and MB CPLD).

[0130] JTAG (for ASD and MB CPLD) is used to debug and program ASD and MB CPLD using JTAG and boundary scan technology.

[0131] In this embodiment, the Universal Serial Bus interface 1038 communicates with the baseboard management unit 101 via 2*USB2.0 (1 master and 1 slave).

[0132] Among them, 2*USB2.0 (1 master and 1 slave) is a master-slave dual-device configuration of USB 2.0.

[0133] In this embodiment, the video graphics array interface 1039 is connected to the baseboard management unit 101 via VGA.

[0134] In this embodiment, the network controller side interface 10310 communicates with the baseboard management unit 101 via NCSI (for OCP and Smart NIC).

[0135] Among them, NCSI (for OCP and Smart NIC) is designed for out-of-band management of servers, enabling efficient communication between the BMC and the NIC.

[0136] In the embodiment, the enhanced serial peripheral interface 10311 is connected with the baseboard management unit 101 through the ESPI.

[0137] In the embodiment, the fourth serial communication interface unit 10312 is connected with the baseboard management unit 101 through 8*3.3V I2C (5, 6, 7, 10, 13, 14, 15, 16) and 6*1.8V I2C (1, 2, 3, 4, 8, 9).

[0138] The 8*3.3V I2C (5, 6, 7, 10, 13, 14, 15, 16) is an I2C bus with 3.3V level corresponding to the pin numbers 5, 6, 7, 10, 13, 14, 15 and 16.

[0139] The 6*1.8V I2C (1, 2, 3, 4, 8, 9) is an I2C bus with 1.8V corresponding to the pin numbers 1, 2, 3, 4, 8 and 9.

[0140] The general pin 1033 is a GPIO; the peripheral component interconnect bus interface 1034 is a PCIe; the second serial communication interface 1035 is a QSPI; the third serial communication interface 1036 is an I3C; the test interface 1037 is a JTAG; the universal serial bus interface 1038 is a USB; the video graphics array interface 1039 is a VGA; the network controller sideband interface 10310 is a NCSI; the enhanced serial peripheral interface 10311 is an ESPI; and the fourth serial communication interface unit 10312 is an I2C.

[0141] Continuing to refer to Figure 1 The power module 105 is connected with the first connector 103 in circuit, and is configured to regulate the input voltage connected by the first connector 103, so as to provide multiple voltage rails for the server management control circuit 10.

[0142] The power module 105 is connected with the first connector 103 in circuit, and is configured to regulate the input voltage connected by the first connector 103, so as to provide multiple voltage rails for the server management control circuit 10.

[0143] In the embodiment, the input voltage is 12V_STBY.

[0144] Exemplarily, the multiple voltage rails are P3V3_STBY, P2V5_STBY, P1V8_STBY, P3V3_RGM_STBY, P1V2_STBY and P1V0_STBY respectively.

[0145] In addition, the first connector 103 is further configured to output P3V_BAT and PVNN_MAIN_CPU0.

[0146] In summary, the server management control circuit provided in the embodiment is constructed based on the baseboard management unit 101, the programmable control module 102 and the first connector 103. The baseboard management unit 101 is configured to generate a first control instruction and a second control instruction, and send the first control instruction to the server main circuit 20 through the first connector 103. The programmable control module 102 is configured to receive the second control instruction sent by the baseboard management unit 101, and send the second control instruction to the server main circuit 20 through the low-speed signal transmission interface 1032. Thus, the original management board of the server management control circuit can still send the second control instruction that cannot be directly sent to the server main circuit by the baseboard management unit to the server main circuit through the programmable control module and the first connector after the external interface is deleted, so as to realize complete management and control of the server main circuit.

[0147] In addition, the server management control circuit provided in the embodiment can leave more interfaces in the server management control circuit to connect other function signals by multiplexing the low-speed signal transmission interface. For example, considering that the physical layer module needs to be configured through the MDC / MDIO bus, one I2C bus can be selected to be multiplexed with the MDC / MDIO bus.

[0148] In addition, the server management control circuit provided in the embodiment can save the signal space of the first connector by connecting the four groups of UARTs of the original baseboard management controller to the programmable control device.

[0149] In addition, the server management control circuit provided in the embodiment can save the layout space by removing all the IO interfaces on the server management control circuit because the server management control circuit is placed in the server in a vertical plug-in form. Meanwhile, the VGA signal and the USB signal can be connected to the server main circuit through the first connector.

[0150] In addition, the server management control circuit provided in the embodiment can save the signal space of the first connector by connecting the four groups of UARTs of the original baseboard management controller to the programmable control device.

[0151] Figure 2 The structure diagram of the server management control system provided in the embodiment is shown in FIG. 1. Figure 1 The server management control system provided in the embodiment is constructed based on the server management control circuit 10 and the server main circuit 20.

[0152] The server management control circuit 10 is configured to control the running state of at least one first component in the server main circuit 20 based on a first control instruction, and control the running state of at least one second component in the server main circuit 20 or an external device connected with the server main circuit based on a second control instruction.

[0153] In addition, the server management control system further comprises a first front data transmission circuit 30, a power distribution board 40 and a second front data transmission circuit 50.

[0154] The server main circuit 20 is in communication connection with the first front data transmission circuit 30, the power distribution board 40 and the second front data transmission circuit 50 respectively.

[0155] In summary, the server management control system provided by the embodiment can make the original management board corresponding to the server management control circuit still be able to send the second control instruction which cannot be directly sent to the server main circuit through the baseboard management unit to the server main circuit by means of the programming control module and the first connector after the external interface is deleted, so as to realize complete management and control of the server main circuit.

[0156] Figure 3 A structural schematic diagram of the first server running circuit provided by the embodiment is shown in FIG. 1. Figure 2 On the basis of the embodiment, the server main circuit 20 comprises a second connector 201 and a first server running circuit 202.

[0157] The first multiplexer 2021 is in communication connection with the first processor 2023 and the first interface flash memory 2024 respectively, and the second multiplexer 2022 is in communication connection with the first processor 2023 and the second interface flash memory 2025 respectively.

[0158] The first multiplexer 2021 is configured to combine the multiple control signals in the first control instruction into a first single control signal, and store the first single control signal into the first interface flash memory 2024.

[0159] Exemplarily, the first multiplexer 2021 is a MUX, and the first interface flash memory 2024 and the second interface flash memory 2025 are Bios flash respectively.

[0160] In the embodiment, the first multiplexer 2021 is in communication connection with the first processor 2023 through SPI_CPU_FLASH_1V8_IO2, SPI_CPU_FLASH_1V8_IO3; the first multiplexer 2021 is in communication connection with the first interface flash memory 2024 through SPI_BMC_CPU_MUX_IO2 and SPI_BMC_CPU_MUX_IO3.

[0161] The second multiplexer 2022 is used for merging the multiple control signals in the first control instruction into a second single control signal and storing the second single control signal into the second interface flash memory 2025.

[0162] In the embodiment, the second multiplexer 2022 is in communication connection with the first processor 2023 through SPI_CPU_FLASH_1V8_CLK, SPI_CPU_FLASH_1V8_IO0, SPI_CPU_FLASH_1V8_IO1 and SPI_CPU_FLASH_1V8_CS_N; the second multiplexer 2022 is in communication connection with the second interface flash memory 2025 through SPI_CPU_FLASH_MUX_CLK, SPI_CPU_FLASH_MUX_IO0 and SPI_CPU_FLASH_MUX_IO1.

[0163] The first processor 2023 is used for controlling the corresponding running state based on the first single control signal or the second single control signal by the server management control circuit 10.

[0164] With reference to Figure 3 , the first server running circuit 202 further comprises a pin slot 2026. The first processor 2023 is in communication connection with the external device through the pin slot 2026.

[0165] In the embodiment, the first processor 2023 is in communication connection with the pin slot 2026 through SPI_CPU_TPM_CLK, SPI_CPU_TPM_MOSI, SPI_CPU_TPM_MISO and SPI_CPU_TPM_CS_N.

[0166] Exemplarily, the pin slot 2026 is a TPM Header; and the external device is a TPM module.

[0167] In addition, the first server running circuit 202 further comprises a first level shifter 2027, a second level shifter 2028, a second programmable control device 2029 and a fourth multiplexer 20210.

[0168] The first level shifter 2027 is communicatively connected with the second connector 201 and the first multiplexer 2021, respectively; the second level shifter 2028 is communicatively connected with the second connector 201 and the second multiplexer 2022, respectively; the second programmable control device 2029 is communicatively connected with the fourth multiplexer 20210; and the fourth multiplexer 20210 is further communicatively connected with the second multiplexer 2022, the first interface flash memory 2024 and the second interface flash memory 2025, respectively.

[0169] In the embodiment, the first level shifter 2027 is communicatively connected with the second connector 201 through SPI_SCM_BIOS_IO2 and SPI_SCM_BIOS_IO3; and the first level shifter 2027 is communicatively connected with the first multiplexer 2021 through SPI_SCM_BIOS_1V8_IO2 and SPI_SCM_BIOS_1V8_IO3.

[0170] In the embodiment, the second level shifter 2028 is communicatively connected with the second connector 201 through SPI_SCM_BIOS_CLK, SPI_SCM_BIOS_IO0, SPI_SCM_BIOS_IO1 and SPI_SCM_BIOS_CS0_N; and the second level shifter 2028 is communicatively connected with the second multiplexer 2022 through SPI_SCM_BIOS_1V8_CLK, SPI_SCM_BIOS_1V8_IO0, SPI_SCM_BIOS_1V8_IO1 and SPI_SCM_BIOS_1V8_CS0_N.

[0171] In the embodiment, the second programmable control device 2029 is communicatively connected with the fourth multiplexer 20210 through FM_DUAL_BIOS_SEL.

[0172] In the embodiment, the fourth multiplexer 20210 is communicatively connected with the first interface flash memory 2024 through SPI_CPU_FLASH0_MUX_CS_N; and the fourth multiplexer 20210 is communicatively connected with the second interface flash memory 2025 through SPI_CPU_FLASH1_MUX_CS_N.

[0173] The second connector 201 is GEN Z4 C+ CONN.

[0174] Each level shifter is LEVEL SHIFT, and an example model is TXB0304RUTR.

[0175] Wherein, each multiplexer is MUX, and an example model is AIP74CBT.

[0176] Wherein, the first processor 2023 is CPU.

[0177] Wherein, the row pin type slot 2026 is TPM Header.

[0178] Wherein, the second programmable control device 2029 is CPLD.

[0179] Wherein, each interface flash memory is SPI FLASH.

[0180] In summary, the first server running circuit provided by the embodiment, the first multiplexer 2021 is used for merging the multi-channel control signals in the first control instruction into a first single-channel control signal, and storing the first single-channel control signal to the first interface flash memory 2024. The second multiplexer 2022 is used for merging the multi-channel control signals in the first control instruction into a second single-channel control signal, and storing the second single-channel control signal to the second interface flash memory 2025. The first processor 2023 is used for the server management control circuit 10 to control the corresponding running state based on the first single-channel control signal or the second single-channel control signal, so that the complete management and control of the corresponding components on the server main circuit are realized.

[0181] In addition, the first server running circuit provided by the embodiment integrates the first multiplexer 2021, the first interface flash memory 2024 and the second interface flash memory 2025 on the server management control circuit 10 to the first server running circuit, so that the size of the first server running circuit can be reduced, and the length of the wire from the first processor to the first interface flash memory and the second interface flash memory can be reduced.

[0182] In addition, the server management control system provided by the embodiment enables the external device to realize the corresponding function on the server main circuit through external connection by the row pin type slot 2026 of the server main circuit 20.

[0183] Figure 4 The structure schematic diagram of the second server running circuit provided by the embodiment is shown in the figure. Figure 2 On the basis of the embodiment, the server main circuit 20 further includes a second server running circuit 203. The second server running circuit 203 includes a first serial storage protocol interface 2031 and a first programmable control device 2032; the first programmable control device 2032 belongs to the second component.

[0184] The first serial storage protocol interface 2031 is in communication connection with the second connector 201 and the programmable control module 102.

[0185] The multiplexer 10211 in the programmable control module 102 is configured to transmit one or more control signals in the second control instruction to the first serial storage protocol interface 2031 and transmit a clock synchronization signal in the second control instruction to the first programmable control device 2032 through the low-speed signal transmission interface 1032.

[0186] The first serial storage protocol interface 2031 is configured to transmit the control signals to the first front data transmission circuit 30.

[0187] The first programmable control device 2032 is configured to perform timing synchronization under the control of the clock synchronization signal.

[0188] In the embodiment, the first serial storage protocol interface 2031 is in communication connection with the second connector 201 through UART_CPLD_SYS_NIC_BMC_TX and UART_CPLD_SYS_NIC_BMC_RX, and is in communication connection with the first front data transmission circuit 30 through a cable.

[0189] In addition, the second server running circuit 203 further comprises an intelligent network card serial port 2033, an expansion interface unit 2034, an edge connector 2035, a data management hardware expansion board 2036, and a fifth serial storage protocol interface 2037.

[0190] The first programmable control device 2032 is in communication connection with the second connector 201, the intelligent network card serial port 2033, and the expansion interface unit 2034 respectively; the expansion interface unit 2034 is in communication connection with the edge connector 2035 and the fifth serial storage protocol interface 2037 respectively; the edge connector 2035 is in communication connection with the data management hardware expansion board 2036; and the fifth serial storage protocol interface 2037 is in communication connection with the power distribution board 40.

[0191] The first programmable control device 2032 is configured to receive the second control instruction in the second control instruction transmitted by the second connector 201 and transmit the second control instruction to the expansion interface unit 2034.

[0192] The expansion interface unit 2034 transmits the second control instruction to the fifth serial storage protocol interface 2037 and the data management hardware expansion board 2036 through the edge connector 2035 respectively.

[0193] The fifth serial storage protocol interface 2037 transmits the second control instruction to the power distribution board 40.

[0194] In this embodiment, the first programmable control device 2032 is communicatively connected with the second connector 201 through an LVDS bus; the first programmable control device 2032 is communicatively connected with the smart network card serial port 2033 through UART_SMART_NIC_CPLD_R_TX and UART_CPLD_SYS_NIC_BMC_RX; and the first programmable control device 2032 is communicatively connected with the expansion interface unit 2034 through UART_BMC_DMPU_R_TX and UART_BMC_DMPU_R_RX.

[0195] In this embodiment, the expansion interface unit 2034 is communicatively connected with the edge connector 2035; and the expansion interface unit 2034 is communicatively connected with the fifth serial storage protocol interface 2037 through UART_MCU_2_TX, UART_MCU_2_RX, UART_MCU_0_TX, UART_MCU_0_RX, UART_MCU_4_TX, UART_MCU_4_RX, UART_MCU_3_TX, UART_MCU_3_RX, UART_MCU_1_TX and UART_MCU_1_RX.

[0196] In this embodiment, the fifth serial storage protocol interface 2037 is communicatively connected with the power distribution board 40 through a cable.

[0197] Each serial storage protocol interface is a Slim Line SAS x8.

[0198] The first programmable control device 2032 is a CPLD.

[0199] The smart network card serial port 2033 is a Smart NIC.

[0200] The expansion interface unit 2034 includes a plurality of UART Headers, exemplarily five UART Headers.

[0201] The data management hardware expansion board 2036 is a DMPU Board.

[0202] The cable is a Cable.

[0203] In addition, the second server running circuit 203 further includes:

[0204] The second processor 2038, the third level converter 2039 and the pin connector 20310.

[0205] The second processor 2038 is in communication connection with the third level converter 2039, and the third level converter 2039 is in communication connection with the pin connector 20310. The pin connector 20310 is used to connect external devices.

[0206] In this embodiment, the third level converter 2039 is in communication connection with the pin connector 20310 through UART_CPU0_CPLD_R_TX and UART_CPU0_CPLD_R_RX.

[0207] The second processor 2038 is used to regulate the running state of the third level converter 2039.

[0208] The third level converter 2039 is used to interact information with the pin connector 20310.

[0209] In addition, the power distribution board 40 comprises a sixth serial storage protocol interface 401, a power distribution device unit 402, and a disk array hardware management interface 403. The disk array hardware management interface 403 is used to connect external devices.

[0210] The sixth serial storage protocol interface 401 is in circuit connection with the fifth serial storage protocol interface 2037, the power distribution device unit 402, and the disk array hardware management interface 403 respectively.

[0211] In this embodiment, the sixth serial storage protocol interface 401 is in circuit connection with the fifth serial storage protocol interface 2037, the power distribution device unit 402, and the disk array hardware management interface 403 respectively through the UART bus.

[0212] The sixth serial storage protocol interface 401 is Slim line SAS x8.

[0213] The disk array hardware management interface 403 is Header For Raid Card.

[0214] The sixth serial storage protocol interface 401 is used to transmit the second control instruction sent by the fifth serial storage protocol interface 2037 to the power distribution device unit 402 and the disk array hardware management interface 403 respectively.

[0215] The power distribution device unit 402 is used to perform corresponding circuit control according to the second control instruction.

[0216] In addition, the power distribution device unit 402 comprises a plurality of power distribution devices 4021.

[0217] The plurality of power distribution devices 4021 are in communication connection with the sixth serial storage protocol interface 401.

[0218] Each power distribution device 4021 is SW_A.

[0219] A plurality of power distribution devices 4021 are configured to perform corresponding circuit control according to the second control instruction.

[0220] With reference to Figure 4 The first front data transmission circuit 30 comprises a second serial storage protocol interface 301, a protocol converter 302, and a mobile device interface 303.

[0221] The second serial storage protocol interface 301 is in communication connection with the protocol converter 302, and the protocol converter 302 is in communication connection with the mobile device interface 303.

[0222] The protocol converter 302 is in communication connection with the mobile device interface 303 through USB_DP and USB_DN.

[0223] The second serial storage protocol interface 301 is a Slim Line SAS x8.

[0224] The protocol converter 302 is MCP2221, which is configured to perform UART TO USB.

[0225] The mobile device interface 303 is a Micro-USB.

[0226] The second serial storage protocol interface 301 is configured to receive each control signal sent by the first serial storage protocol interface 2031 and send each control signal to the protocol converter 302.

[0227] The protocol converter 302 is configured to perform format conversion on each control signal to obtain each converted control signal and send each converted control signal to the mobile device interface 303 to control the external device.

[0228] In this embodiment, the external device can be an LED, a buzzer, or the like.

[0229] In summary, the second server running circuit provided by the embodiment of the present application cooperates with the first serial storage protocol interface 2031, the first programmable control device 2032, the smart network card serial port 2033, the expansion interface unit 2034, the edge connector 2035, the data management hardware expansion board 2036, the fifth serial storage protocol interface 2037, the second processor 2038, the third level converter 2039, and the pin connector 20310 in the second server running circuit 203 to realize the management and control of the server management control circuit on the second server running circuit.

[0230] In addition, the second server running circuit provided by the embodiment of the application is used for transmitting one or more control signals in the second control instruction to the first serial storage protocol interface 2031 and transmitting a clock synchronization signal in the second control instruction to the first programmable control device 2032 through the multiplexer 10211 in the programmable control module 102 through the low-speed signal transmission interface 1032, so that the server management control circuit can completely transmit the second control instruction to the second server running circuit.

[0231] Figure 5 The third server running circuit provided by the embodiment of the application is shown in the structural schematic diagram. Figure 2 On the basis of the embodiment, the server main circuit 20 further includes a third server running circuit 204. The third server running circuit 204 includes a third multiplexer 2041, a logic processor 2042, a transceiver conversion assembly 2043, a third processor 2044, and a fourth processor 2045. The third processor 2044 and the fourth processor 2045 belong to the first assembly.

[0232] The third multiplexer 2041 is in communication connection with the second connector 201, the logic processor 2042, and the transceiver conversion assembly 2043 respectively. The transceiver conversion assembly 2043 is in communication connection with the third processor 2044 and the fourth processor 2045 respectively.

[0233] The third multiplexer 2041 is in communication connection with the second connector 201 through BMC_JTAG1_TCK, BMC_JTAG1_TDO, BMC_JTAG1_TDI, and BMC_JTAG1_TM. The third multiplexer 2041 is in communication connection with the logic processor 2042 through JTAG_TCK_CPU_BMC. The third multiplexer 2041 is in communication connection with the transceiver conversion assembly 2043 through JTAG_TDI_CPU_BMC and JTAG_TMS_CPU_BMC.

[0234] The transceiver conversion assembly 2043 includes a first transceiver conversion device 20431, a second transceiver conversion device 20432, and a third transceiver conversion device 20433.

[0235] The first transceiver conversion device 20431 is in communication connection with the second transceiver conversion device 20432 through JTAG_DBP_TDI, JTAG_DBP_TMS, JTAG_DBP_CPU_GTL_TCK, and H_DBP_PREQ_BUFF_N.

[0236] In the embodiment, the second conversion transceiver 20432 is communicatively connected with the third processor 2044 through the JTAG_CPU0_TDI, the JTAG_CPU0_TMS, the JTAG_CPU0_TCK and the H_DBP_CPU0_GTL_PREQ_N.

[0237] In the embodiment, the third conversion transceiver 20433 is communicatively connected with the fourth processor 2045 through the JTAG_CPU1_TDI, the JTAG_CPU1_TMS, the JTAG_CPU1_TCK and the H_DBP_CPU1_GTL_PREQ_N.

[0238] The third multiplexer 2041 is MUX, and an example model is AIP74CBLV3257.

[0239] The model of the logic processor 2042 is AIP74LVC1G08.

[0240] The model of each conversion transceiver is CAG94014.

[0241] The third multiplexer 2041 is configured to combine the multiple debug signals in the first control instruction sent by the second connector 201 into one or multiple debug signals to obtain each debug signal, and transmit each debug signal to the logic processor 2042 and the conversion transceiver assembly 2043.

[0242] The logic processor 2042 is configured to perform binary logical operation on the corresponding debug signal to obtain an operated debug signal, and transmit the operated debug signal to the conversion transceiver assembly 2043.

[0243] The conversion transceiver assembly 2043 is configured to convert the operated debug signal and the remaining debug signals from differential signals into digital signals to obtain each converted control signal, and transmit each converted control signal to the third processor 2044 and the fourth processor 2045 to debug the third processor 2044 and the fourth processor 2045.

[0244] With reference to Figure 5 , the third server running circuit 204 further includes a bus expander 2046.

[0245] The bus expander 2046 is communicatively connected with the third multiplexer 2041.

[0246] The bus expander 2046 is configured to perform bus expansion on the server main circuit 20.

[0247] With reference to Figure 5The third server running circuit 204 further comprises a third programmable control device 2047.

[0248] The third programmable control device 2047 is in communication connection with the third multiplexer 2041.

[0249] The third programmable control device 2047 is configured to perform function upgrade according to the corresponding debug signal sent by the third multiplexer 2041.

[0250] For example, the function upgrade is debug and ASD function upgrade.

[0251] In addition, the third programmable control device 2047 is in communication connection with the first transceiver 20431 through DBP_ASD_BMC_PREQ_N.

[0252] In addition, the third server running circuit 204 further comprises a test interface physical connector 2048.

[0253] The test interface physical connector 2048 is in communication connection with the third programmable control device 2047.

[0254] In this embodiment, the third programmable control device 2047 is in communication connection with the test interface physical connector 2048 through JTAG_TCK_CPU_CONN, JTAG_TDO_CONN_CPU_R, JTAG_TDI_CPU_CONN and JTAG_TMS_CPU_CONN.

[0255] In summary, the third server running circuit provided by the embodiment of the present application realizes the management and control of the third server running circuit by the cooperation of the third multiplexer 2041, the logic processor 2042, the first transceiver 20431, the second transceiver 20432, the third transceiver 20433, the third processor 2044, the fourth processor 2045, the bus expander 2046, the third programmable control device 2047 and the test interface physical connector 2048 in the third server running circuit 204.

[0256] In addition, the third server running circuit provided by the embodiment of the present application realizes the function upgrade of the third programmable control device by the debug signal sent by the third multiplexer.

[0257] Figure 6 The structure schematic diagram of the second front data transmission circuit provided by the embodiment of the present application is shown in FIG. 6. Figure 2The second front data transmission circuit 50 comprises a fourth serial storage protocol interface 501, a front physical layer module 502 and a network interface 503.

[0258] The fourth serial storage protocol interface 501 is in communication connection with the third serial storage protocol interface 205 and the front physical layer module 502 respectively.

[0259] The third serial storage protocol interface 205 is in communication connection with the second connector 201 through SGMII_RTL8211_R_P, SGMII_RTL8211_R_N, SGMII_RTL8211_T_P and SGMII_RTL8211_T_N.

[0260] The fourth serial storage protocol interface 501 is in communication connection with the front physical layer module 502 through SGMII_RTL8211_R_P, SGMII_RTL8211_R_N, SGMII_RTL8211_T_P, SGMII_RTL8211_T_N, BMC_MDC_PHY2 and BMC_MDIO_PHY2.

[0261] In the embodiment, the front physical layer module 502 is in communication connection with the network interface 503 through RJ45_MDI0_DP, RJ45_MDI0_DN, RJ45_MDI1_DP, RJ45_MDI1_DN, RJ45_MDI2_DP, RJ45_MDI2_DN, RJ45_MDI3_DP and RJ45_MDI3_DN.

[0262] The fourth serial storage protocol interface 501 is Slimline X8.

[0263] The front physical layer module 502 is PHY, and an example model is RTL8211FS-CG.

[0264] The network interface 503 is RJ45.

[0265] The fourth serial storage protocol interface 501 is configured to transmit the network signal transmitted by the third serial storage protocol interface 205 to the front physical layer module 502.

[0266] The baseboard management controller 1011 is configured to control the front physical layer module 502 to transmit the network signal to the network interface 503 through the second internal serial interface, the third serial storage protocol interface 205 and the fourth serial storage protocol interface 501.

[0267] In the embodiment, the second internal serial interface is an MDC / MDIO2 bus interface.

[0268] In the embodiment, MDC is used for managing a data clock, and MDIO2 is used for managing a data input / output.

[0269] The network interface 503 is configured to transmit the network signal with an external network device.

[0270] In summary, the second front data transmission circuit provided by the embodiment of the application, the fourth serial storage protocol interface 501 is configured to transmit the network signal transmitted by the third serial storage protocol interface 205 to the front physical layer module 502; the baseboard management controller 1011 is configured to control the front physical layer module 502 to transmit the network signal to the network interface 503 through the second internal serial interface, the third serial storage protocol interface 205 and the fourth serial storage protocol interface 501; and the network interface 503 is configured to transmit the network signal with an external network device. Figure 1 In the embodiment, the baseboard management controller controls the physical layer module on the server control circuit to transmit the network signal to the first connector through the first internal serial interface, and the baseboard management controller controls the front physical layer module to transmit the network signal to the network interface through the second internal serial interface, the third serial storage protocol interface and the fourth serial storage protocol interface, so that the network signal control of two levels of physical layer modules is realized, that is, the network information signal output by the baseboard management controller is converted into an SGMII signal with less signal quantity and longer wiring distance, so that the transmission rate is improved.

[0271] The server management control circuit, system and server provided by the application are described in detail above. The principles and implementation manners of the application are described by using specific examples in the text, and the above description of the embodiments is only used to help understand the method of the application and the core idea thereof. It should be noted that, for those skilled in the art, without departing from the principles of the application, the application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims

1. A server management control circuit (10) characterized by, The application relates to a server management control circuit (10) and a server main circuit (20), which are connected through a first connector (103). The server management control circuit (10) comprises a substrate management unit (101), a programmable control module (102) and the first connector (103); the substrate management unit (101) is in communication connection with the programmable control module (102) and the first connector (103); the programmable control module (102) is also in communication connection with the first connector (103); the first connector (103) comprises a low-speed signal transmission interface (1032), which is a shared interface for the communication connection between the substrate management unit (101), the programmable control module (102) and the first connector (103). The substrate management unit (101) is used for generating first control instructions and second control instructions and sending the first control instructions to the server main circuit (20) through the first connector (103). The programmable control module (102) is used for receiving the second control instructions sent by the substrate management unit (101) and sending the second control instructions to the server main circuit (20) through the low-speed signal transmission interface (1032).

2. The server management control circuit (10) according to claim 1, characterized in that The server main circuit (20) comprises a second connector (201) and a first server running circuit (202); the first server running circuit (202) comprises a first multiplexer (2021), a second multiplexer (2022), a first processor (2023), a first interface flash memory (2024) and a second interface flash memory (2025); the first processor (2023) belongs to a first component in the server main circuit (20); the first multiplexer (2021) is in communication connection with the first processor (2023) and the first interface flash memory (2024) respectively; the second multiplexer (2022) is also in communication connection with the first processor (2023) and the second interface flash memory (2025) respectively; the first multiplexer (2021) is used for merging multiple control signals in the first control instructions into first single control signals and storing the first single control signals into the first interface flash memory (2024); the second multiplexer (2022) is used for merging multiple control signals in the first control instructions into second single control signals and storing the second single control signals into the second interface flash memory (2025); and the first processor (2023) is used for controlling corresponding running states based on the first single control signals or the second single control signals. The substrate management unit (101) comprises a substrate management controller (1011) and a memory (1012); the substrate management unit (101) is in communication connection with the first connector (103); and the first connector (103) comprises a test interface (1037). The substrate management controller (1011) is in communication connection with the memory (1012), and is in communication connection with the first connector (103) through a test interface (1037); The substrate management controller (1011) is specifically configured to generate corresponding control instructions, divide the control instructions into first control instructions and second control instructions based on an interface type of the substrate management controller (1011) in communication connection with the first connector, and send the first control instructions to the server main circuit (20) through the test interface (1037). The substrate management controller (1011) is configured to control the memory (1012) to store running data of the server.

3. The server management control circuit (10) according to claim 1, characterized in that The programmable control module (102) comprises a programmable control device (1021) and a physical slot (1022); the physical slot (1022) is configured to connect an external device; The programmable control device (1021) is in communication connection with the physical slot (1022), the substrate management controller (1011) and the first connector (103) respectively; The programmable control device (1021) is configured to receive the second control instructions sent by the substrate management unit (101) and send the second control instructions to the server main circuit (20) through the low-speed signal transmission interface (1032).

4. The server management control circuit (10) according to claim 3, characterized in that The programmable control device (1021) is in communication connection with the substrate management controller (1011) through a first standard test interface; and the physical slot (1022) is connected to the first standard test interface through a second standard test interface; The substrate management controller (1011) is configured to adjust the function of the programmable control device (1021).

5. The server management control circuit (10) according to claim 3, characterized in that The programmable control device (1021) comprises a multiplexer (10211) and a bus slave device (10212); The multiplexer (10211) is in communication connection with the substrate management controller (1011) and the first connector (103) respectively; and the bus slave device (10212) is in communication connection with the substrate management controller (1011); The substrate management controller (1011) is configured to read device information corresponding to the bus slave device (10212), and send a data transmission request to the bus slave device (10212) according to the device information; The bus slave device (10212) is configured to generate a data transmission response according to the data transmission request, and send the data transmission response to the substrate management controller (1011); The substrate management controller (1011) is configured to send a preset number of second control instructions to the multiplexer (10211) through a plurality of internal serial communication interfaces based on the data transmission response; The multiplexer is configured to screen each second control instruction, and send the screened second control instruction to the server main circuit (20) through the low-speed signal transmission interface (1032).

6. The server management control circuit (10) according to claim 1, characterized in that Further comprising: The physical layer module (104); The physical layer module (104) is in communication connection with the baseboard management unit (101) and the first connector (103) respectively; The physical layer module (104) is configured to convert the network signal in parallel transmission mode sent by the baseboard management unit (101) into network signal in serial transmission mode, and send the network signal in serial transmission mode to the server main circuit (20) through the first connector (103).

7. The server management control circuit (10) according to claim 6, characterized in that The baseboard management controller (1011) in the baseboard management unit (101) is in communication connection with the physical layer module (104) through a plurality of groups of internal Ethernet interfaces and a first internal serial interface; The baseboard management controller (1011) is configured to send the network signal to the physical layer module in parallel transmission mode through a plurality of groups of internal Ethernet interfaces; The baseboard management controller (1011) is further configured to control the physical layer module (104) to transmit the network signal to the first connector (103) through the first internal serial interface.

8. The server management control circuit (10) according to claim 7, characterized in that The first connector (103) further comprises a serial standard interface (10313); The first connector (103) is in communication connection with the physical layer module (104) and the server main circuit (20) through the serial standard interface (10313) respectively; The serial standard interface (10313) is configured to transmit the network signal in serial transmission mode sent by the physical layer module (104) to the server main circuit (20).

9. The server management control circuit (10) according to claim 1, characterized in that The first connector (103) further comprises a first serial communication interface (1031); The first connector (103) is in communication connection with the programmable control module (102) through the first serial communication interface (1031); The first serial communication interface (1031) is configured to transmit the internal state information of the programmable control module (102) to the server main circuit (20); The low-speed signal transmission interface (1032) is configured to control the data flow transmitted by the programmable control module (102) to the server main circuit (20) to be less than a preset data flow threshold.

10. The server management control circuit (10) according to claim 1, characterized in that Further comprising: A power module (105); The power module (105) is in circuit connection with the first connector (103), and is configured to regulate the input voltage accessed by the first connector (103) to provide a plurality of voltage rails for the server management control circuit (10) respectively.

11. A server management control system, characterized by, The server management control circuit (10) and the server main circuit (20) according to any one of claims 1 to 8; The server management control circuit (10) is configured to control the running state of at least one first component in the server main circuit (20) based on a first control instruction, and control the running state of at least one second component in the server main circuit (20) or an external device connected with the server main circuit based on a second control instruction; The server main circuit (20) comprises a second connector (201) and a first server running circuit (202); the first server running circuit (202) comprises a first multiplexer (2021), a second multiplexer (2022), a first processor (2023), a first interface flash memory (2024) and a second interface flash memory (2025); the first processor (2023) belongs to the first component; The first multiplexer (2021) is in communication connection with the first processor (2023) and the first interface flash memory (2024) respectively; the second multiplexer (2022) is also in communication connection with the first processor (2023) and the second interface flash memory (2025) respectively; The first multiplexer (2021) is used for merging multiple control signals in a first control instruction into a first single control signal and storing the first single control signal into the first interface flash memory (2024); The second multiplexer (2022) is used for merging multiple control signals in a first control instruction into a second single control signal and storing the second single control signal into the second interface flash memory (2025); The first processor (2023) is used for the server management control circuit (10) to control a corresponding running state based on the first single control signal or the second single control signal.

12. The server management control system of claim 11, wherein, The first server running circuit (202) further comprises a row pin type slot (2026); the first processor (2023) is in communication connection with an external device through the row pin type slot (2026).

13. The server management control system of claim 11, wherein, The server main circuit (20) further comprises a second server running circuit (203); the second server running circuit (203) comprises a first serial storage protocol interface (2031) and a first programmable control device (2032); the first programmable control device (2032) belongs to the second component; The first serial storage protocol interface (2031) is in communication connection with a programmable control module (102) through the second connector (201); the first programmable control device (2032) is in communication connection with the programmable control module (102) through the second connector (201); The multiplexer (10211) in the programmable control module (102) is used for transmitting one or more control signals in a second control instruction to the first serial storage protocol interface (2031) through a low-speed signal transmission interface (1032) and transmitting a clock synchronization signal in the second control instruction to the first programmable control device (2032); The first serial storage protocol interface (2031) is used for transmitting each control signal to a first front data transmission circuit (30); The first programmable control device (2032) is used for performing timing synchronization under the control of the clock synchronization signal.

14. The server management control system of claim 13, wherein, The first front data transmission circuit (30) comprises a second serial storage protocol interface (301), a protocol converter (302) and a mobile device interface (303); the mobile device interface (303) is used for connecting an external device; The second serial storage protocol interface (301) is in communication connection with the protocol converter (302); the protocol converter (302) is in communication connection with the mobile device interface (303); The second serial storage protocol interface (301) is used for receiving each control signal sent by the first serial storage protocol interface (2031) and sending the control signal to the protocol converter (302); The protocol converter (302) is used for performing format conversion on the control signal to obtain each converted control signal and sending the converted control signal to the mobile device interface (303) to control the external device.

15. The server management control system of claim 11, wherein, The server main circuit (20) further comprises a third server running circuit (204); the third server running circuit (204) comprises a third multiplexer (2041), a logic processor (2042), a transceiver conversion assembly (2043), a third processor (2044) and a fourth processor (2045); the third processor (2044) and the fourth processor (2045) belong to the first assembly; The third multiplexer (2041) is in communication connection with the second connector (201), the logic processor (2042) and the transceiver conversion assembly (2043) respectively; the transceiver conversion assembly (2043) is in communication connection with the third processor (2044) and the fourth processor (2045) respectively; The third multiplexer (2041) is used for merging multiple debugging signals in a first control instruction sent by the second connector (201) into one or multiple debugging signals to obtain each debugging signal and transmitting each debugging signal to the logic processor (2042) and the transceiver conversion assembly (2043) respectively; The logic processor (2042) is used for performing binary logic operation on a corresponding debugging signal to obtain an operated debugging signal and transmitting the operated debugging signal to the transceiver conversion assembly (2043); The transceiver conversion assembly (2043) is used for converting the operated debugging signal and each remaining debugging signal from a differential signal into a digital signal to obtain each converted control signal and transmitting each converted control signal to the third processor (2044) and the fourth processor (2045) respectively to debug the third processor (2044) and the fourth processor (2045).

16. The server management control system of claim 15, wherein, The third server running circuit (204) further comprises a bus expander (2046); The bus expander (2046) is in communication connection with the third multiplexer (2041); The bus expander (2046) is configured to perform bus expansion for the server main circuit (20).

17. The server management control system of claim 15, wherein, The third server running circuit (204) further comprises a third programmable control device (2047). The third programmable control device (2047) is in communication connection with the third multiplexer (2041). The third programmable control device (2047) is configured to perform function upgrade according to the corresponding debugging signal sent by the third multiplexer (2041).

18. The server management control system of claim 11, wherein, The server further comprises a second front data transmission circuit (50), wherein the second front data transmission circuit (50) comprises a fourth serial storage protocol interface (501), a front physical layer module (502) and a network interface (503), and the server main circuit (20) further comprises a third serial storage protocol interface (205). The fourth serial storage protocol interface (501) is in communication connection with the third serial storage protocol interface (205) and the front physical layer module (502) respectively, and the front physical layer module (502) is in communication connection with the network interface (503). The fourth serial storage protocol interface (501) is configured to transmit the network signal sent by the third serial storage protocol interface (205) to the front physical layer module (502). The baseboard management controller (1011) is configured to control the front physical layer module (502) to transmit the network signal to the network interface (503) through the second internal serial interface, the third serial storage protocol interface (205) and the fourth serial storage protocol interface (501). The network interface (503) is configured to transmit the network signal with an external network device.

19. A server comprising the server management control system according to any one of claims 11-18.

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