A multi-path server, system power consumption monitoring method, device and storage medium

Abstract

The application discloses a multi-path server, a system power consumption monitoring method, equipment and a storage medium, relates to the field of servers, and comprises at least two single-path mainboards, a switching module and a plurality of power supply units; wherein the switching module comprises a vertical power supply plate and at least two horizontal switching plates, and a plurality of power supply unit interfaces and at least two switching connectors are arranged on the vertical power supply plate; one end of the horizontal switching plate is matched with the switching connector of the vertical power supply plate, and the other end is matched with the power supply unit connector of the single-path mainboard, so that the plurality of power supply units can pass through the vertical power supply plate and the horizontal switching plate, and then, stable power supply of the multi-path server composed of the at least two single-path mainboards is realized; therefore, the application can flexibly combine the single-path mainboards to form a multi-path system, users do not need to simultaneously purchase single-path and multi-path servers to meet different scene requirements, repeated purchase expenditure is reduced, equipment utilization is improved, and cost waste caused by equipment idling is reduced.

Description

Technical Field

[0001] This application relates to the field of servers, and more particularly to a multi-channel server, a system power consumption monitoring method, a device, and a storage medium. Background Technology

[0002] Currently, single-socket and multi-socket systems (such as dual-socket systems) in the server market generally employ independent hardware architectures. This means that single-socket motherboards cannot be flexibly combined into multi-socket systems to improve performance; conversely, dedicated multi-socket motherboards cannot be disassembled into single-socket devices for independent use. This rigid design leads to high procurement costs for users, low equipment utilization, and requires repeated design for different specifications, resulting in long development cycles and high costs.

[0003] Therefore, there is an urgent need for a server solution that can be flexibly configured. Summary of the Invention

[0004] This application provides a multi-channel server, a system power consumption monitoring method, a device, and a storage medium to at least solve the problem of inflexible server configuration in related technologies.

[0005] This application provides a multi-processor server, including: at least two single-processor motherboards, an adapter module, and multiple power supply units;

[0006] The single-channel motherboard is equipped with a power unit connector, which is configured to selectively connect to multiple power units via the adapter module.

[0007] The adapter module includes a vertical power board and at least two horizontal adapter boards. The vertical power board is provided with multiple power unit interfaces and at least two adapter connectors. The power unit interfaces are used to connect the multiple power units, and the adapter connectors are used to connect to the horizontal adapter boards.

[0008] One end of the horizontal adapter board is provided with a first connection interface that matches the adapter connector on the vertical power board, and the other end is provided with a second connection interface that matches the power unit connector of the single-channel motherboard, so that a detachable connection between the horizontal adapter board and the single-channel motherboard can be formed through the second connection interface.

[0009] This application also provides a system power consumption monitoring method, applied to the main processing of a multi-processor server, the method comprising:

[0010] For each of at least two single-channel motherboards, obtain the power level information and power-ready signals of all power units connected to the single-channel motherboard;

[0011] Based on the power level information and power ready signals of all power units connected to the single-channel motherboard, the total number of online power units of the multi-channel server is determined, and the total power consumption data of the multi-channel server is calculated by combining the power level information.

[0012] When the total power consumption exceeds a preset threshold, a frequency reduction instruction is generated and sent to all processors in the multi-channel server, triggering all processors to reduce their frequency simultaneously.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described system power consumption monitoring methods when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described system power consumption monitoring methods.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described system power consumption monitoring methods.

[0016] The multi-socket server in this application includes at least two single-socket motherboards, an adapter module, and multiple power supply units. The adapter module includes a vertical power board and at least two horizontal adapter boards. The vertical power board has multiple power supply unit interfaces and at least two adapter connectors. One end of the horizontal adapter board matches the adapter connector of the vertical power board, and the other end adapts to the power supply unit connector of the single-socket motherboard. This allows multiple power supply units to provide stable power to the multi-socket server composed of at least two single-socket motherboards through the vertical power board and the horizontal adapter boards. Therefore, this application allows for flexible combination of single-socket motherboards to form a multi-socket system. Users do not need to purchase both single-socket and multi-socket servers simultaneously to meet different scenario requirements, reducing redundant procurement expenditures, improving equipment utilization, and reducing cost waste caused by equipment idleness. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 An overall framework diagram of a multi-channel server provided in this application embodiment;

[0019] Figure 2A schematic diagram of the stacked structure of a single motherboard in a multi-way server provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram of a single-socket motherboard in a multi-socket server provided in an embodiment of this application;

[0021] Figure 4 A flowchart illustrating a system power consumption monitoring method provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the structure of a system power consumption monitoring device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0024] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] This application provides a multi-processor server. The embodiments of this application use two single-processor motherboards as an example to illustrate the multi-processor server. Refer to... Figure 1 The diagram shown is the overall architecture of a multi-socket server, including: two single-socket motherboards 11 and 12, an adapter module 13, and multiple power supply units 14; detailed descriptions are as follows:

[0027] (1) Power unit connectors are provided on the single-channel motherboards 11 and 12, and the power unit connectors are configured to selectively connect to multiple power units through the adapter module.

[0028] Specifically, each single-socket motherboard (such as single-socket motherboard 11) is equipped with a power unit connector. This power unit connector is the core interface for the single-socket motherboard to achieve flexible power supply configuration. Its function is to selectively connect to the power unit through an adapter module. That is, when the single-socket motherboard needs to run independently (such as only requiring single-socket computing power and not requiring multi-socket collaboration), the power unit connector can directly connect to the power unit 14 without going through an adapter module, thus achieving independent power supply for the single-socket motherboard.

[0029] When a single-socket motherboard needs to be connected to a multi-socket architecture (such as two single-socket motherboards needing to work together to form dual-socket computing power), the power supply unit connector is indirectly connected to the power supply unit 14 through an adapter module, and the adapter module uniformly distributes power supply to ensure the consistency of power supply for multiple motherboards.

[0030] It should be noted that, in the embodiments of this application, at least two single-channel motherboards are arranged in a stacked structure; each single-channel motherboard is equipped with a processor.

[0031] The processors on each single-channel motherboard are connected via cables.

[0032] Specifically, refer to Figure 2 The diagram shows four single-channel motherboards stacked in a layered configuration, where 21 represents any single-channel motherboard. In this embodiment, at least two single-channel motherboards (single-channel motherboard 11 and single-channel motherboard 12) are also arranged as shown in the diagram. Figure 2 The stacked structure shown is arranged in layers.

[0033] Meanwhile, the vertical spacing between two adjacent single-processor motherboards is controlled within a preset reasonable range, which avoids the upper motherboard blocking the heat dissipation of the lower motherboard (ensuring unobstructed heat dissipation airflow for each motherboard and adapting to the heat dissipation requirements of components such as processors and memory), and also reduces the overall height of multi-processor servers. Compared with the traditional side-by-side layout, the stacked structure can reduce the overall height of the server, adapt to the space limitations of rack-mount installation, and save space.

[0034] In some embodiments, positioning holes can be provided at the four corners of each single-channel motherboard, and connected to the server chassis or adapter module mounting bracket via metal support columns. This ensures that the motherboards do not shift after stacking and can withstand their own weight and external forces when plugging and unplugging horizontal adapter boards (the support column has a load-bearing capacity of ≥5kg to meet the requirements for long-term stable operation). External interfaces such as power unit connectors and heat dissipation interfaces on the single-channel motherboards need to be staggered (e.g., the upper motherboard interfaces are biased to the left and the lower motherboard interfaces are biased to the right) to avoid mutual obstruction between interlayer interfaces and ensure that the plugging and unplugging of components such as horizontal adapter boards and heat dissipation cables is not hindered.

[0035] Furthermore, with the same server chassis width and depth, the stacked structure can accommodate more single-socket motherboards, providing space support for subsequent expansion of multi-socket computing power (such as from dual-socket to quad-socket).

[0036] It should also be noted that each single-socket motherboard is equipped with a processor (i.e., the Central Processing Unit (CPU) is the computing core of the single-socket motherboard, and the model can be adapted according to computing power requirements, such as Intel Xeon series, AMD EPYC series). The processors at each layer establish direct communication connections through cables. Specifically, dedicated communication cables that support high-speed data transmission can be used, such as UPI (Ultra Path Interconnect) cables and PCIe 5.0 cables, with a transmission rate of ≥32GB / s, to meet the high-speed data interaction requirements when multiple processors work together (such as cache synchronization and instruction transmission between dual processors).

[0037] Furthermore, the processors of the at least two single-socket motherboards are divided into a master processor and at least one slave processor; the master-slave relationship between the master processor and the slave processor is configured through any one of hardware jumpers, a basic input / output system, and a baseboard management controller.

[0038] Specifically, in at least two single-socket motherboards, two roles need to be clearly defined: the master processor and the slave processor, so that the master processor can perform specific control processing in the future.

[0039] The main processor can be understood as the central control center of a multi-processor system, responsible for core decisions, such as receiving total power consumption data from all single-processor motherboards and determining whether to trigger global frequency reduction; coordinating the working rhythm of each slave processor to avoid chaotic computing power allocation.

[0040] The processor is primarily responsible for executing specific computational tasks, while simultaneously synchronizing data such as power consumption and load from its motherboard to the main processor. It does not participate in global decision-making and only obeys the scheduling of the main processor.

[0041] It should be noted that the master-slave relationship is not fixed and can be flexibly set through hardware or software means. Specifically, there are three methods:

[0042] Hardware jumper configuration involves a dedicated "jumper cap interface" (a set of pinned hardware interfaces) on single-socket motherboards. By inserting or removing the jumper cap, the pin connection status can be changed to designate a specific processor as the master processor. For example, if the "master / slave jumper" of motherboard A is inserted into the "MASTER" pin, its processor will be the master processor; if the jumper of other motherboards is inserted into the "SLAVE" pin, the corresponding processor will be the slave processor.

[0043] Basic Input / Output System (BIOS) configuration: BIOS is the motherboard's low-level management program. After entering the BIOS interface via a shortcut key during startup, you can directly find the "Processor Master / Slave Settings" option. Simply select the processor of a single-socket motherboard as the "Master Processor" in the interface, save, and restart for the changes to take effect.

[0044] The baseboard management controller (BMC) is configured as a "remote management chip" for the server. Even when the server is not powered on or connected to an operating system, it can connect to the BMC's management interface via network and configure processor master-slave relationships in the background. For example, maintenance personnel can log in to the server's BMC via computer in their office and designate a specific processor as the master processor without needing to go to the data center. This method is suitable for batch management of multiple servers in large data centers, significantly improving operational efficiency.

[0045] (2) The adapter module 13 includes a vertical power board 132 and at least two horizontal adapter boards 131. The vertical power board 132 is provided with multiple power unit interfaces 1321 and at least two adapter connectors 1322. The power unit interfaces 1321 are used to connect the multiple power units 14, and the adapter connectors 1322 are used to connect to the horizontal adapter boards 131.

[0046] Specifically, the adapter module, acting as a connection hub, adopts a modular design consisting of a vertical power board and at least two horizontal adapter boards. The vertical power board integrates two types of interfaces, specifically including the following:

[0047] Power unit interface 1321: The number of power unit interfaces is adapted to the number of power units 14 (e.g., 4 interfaces for 4 power units). Its function is to directly connect to power units 14, receive the power output from the power units, and realize centralized management of multiple power units (e.g., redundant power supply switching, fault detection).

[0048] Adapter Connector 1322: The number of adapter connectors matches the number of single-channel motherboards (e.g., two single-channel motherboards correspond to two adapter connectors). Its function is to establish a reliable connection with the horizontal adapter board, transfer the power collected by the vertical power board to the horizontal adapter board, and at the same time transmit power status signals (e.g., power ready signal, fault signal).

[0049] It should be noted that the multiple power supply units supply power to the single motherboard through the vertical power board and at least two of the horizontal adapter boards.

[0050] Each of the horizontal adapter boards has a connection interface that is connected to a corresponding adapter connector of the vertical power board, and its connection interface is connected to a corresponding power unit connector of a single-channel motherboard.

[0051] Specifically, refer to Figure 1 As shown, based on the above description, the power supply path for each single-channel motherboard is: power supply unit — vertical power board — horizontal adapter board — single-channel motherboard.

[0052] Therefore, in the embodiments of this application, when constructing a multi-channel server, multiple power supply units are not directly connected to a single motherboard. Instead, power is supplied through a combination of a vertical power board and a horizontal adapter board. That is, all power supply units are first connected to the vertical power board, which can be understood as a centralized power supply hub, so that the power is first collected to the vertical power board. Then the vertical power board distributes the power to each single motherboard through the horizontal adapter board, and finally realizes the power supply to the single motherboard.

[0053] It should also be noted that one end of the horizontal adapter board is a connector specifically designed to match a single adapter on the vertical power board (i.e., a horizontal adapter board connects to only one dedicated interface on the vertical power board); the other end of the horizontal adapter board is a connector specifically designed to match the power supply unit connector of a single motherboard (i.e., a horizontal adapter board supplies power to only one single motherboard).

[0054] Therefore, in this embodiment of the application, the one-to-one correspondence between the vertical power board interface, the horizontal adapter board and the single motherboard interface ensures that the power supply link of each single motherboard is independent (does not interfere with each other), while facilitating subsequent maintenance (for example, when replacing a single motherboard, only the corresponding horizontal adapter board needs to be disconnected, without affecting the power supply of other motherboards).

[0055] (3) One end of the horizontal adapter plate 131 is provided with a first connection interface 1311 that matches the adapter connector 1322 on the vertical power board 132, and the other end is provided with a second connection interface 1312 that matches the power unit connector of the single-channel motherboard 11 and 12, so that the horizontal adapter plate and the single-channel motherboard can be detachably connected through the second connection interface 1312.

[0056] The horizontal adapter board can be understood as a communication bridge between the vertical power board and the single-channel motherboard. It has matching connection interfaces at both ends to achieve flexible and detachable connection.

[0057] Specifically, one end of the horizontal adapter board has a first connection interface that perfectly matches the shape and pin definition of the adapter connector on the vertical power board, ensuring stable power and signal transmission after the two are connected; the other end has a second connection interface that is compatible with the pin layout and current carrying capacity of the power unit connector of the single-channel motherboard. The horizontal adapter board and the single-channel motherboard can be detached by plugging and unplugging. Thus, when the single-channel motherboard fails, the horizontal adapter board can be directly removed to replace the single-channel motherboard without disassembling the entire adapter module, which greatly improves maintenance efficiency.

[0058] Furthermore, through the above architecture, when the system is in multi-path operation mode (two single-path motherboards 11 and 12 working together), the connection path of each component is as follows: power supply unit 14 — power supply unit interface 1321 of vertical power supply board 132 — adapter connector 1322 of vertical power supply board 132 — first connection interface 1311 of horizontal adapter board 131 — second connection interface 1312 of horizontal adapter board 131 — power supply unit connector of single-path motherboards 11 and 12 — single-path motherboards 11 and 12.

[0059] Through the above connection path, the vertical power board collects the power from multiple power units and distributes it to two single-path motherboards via the horizontal adapter board, ensuring that the two single-path motherboards receive a stable and consistent power supply to meet the computing power requirements of multi-path collaboration.

[0060] By adapting the connection interface to the power unit connector, and using a standardized pluggable structure (such as the combination of pin header and pin sleeve), the plugging and unplugging process requires no tools, and the interface is equipped with a foolproof design (such as positioning protrusions and grooves) to avoid hardware damage caused by reverse plugging and unplugging; at the same time, the current carrying capacity of the interface is matched with the maximum power consumption of a single motherboard to ensure the reliability of power supply after connection.

[0061] Specifically, the connection interface of the horizontal adapter board is configured as a gold finger, which matches the power unit connector of the single-channel motherboard to form a detachable connection between the horizontal adapter board and the power unit connector of the single-channel motherboard through the gold finger.

[0062] In some embodiments, the gold fingers are gold-plated (e.g., gold plating thickness ≥ 5 μm), and their conductive impedance is much lower than that of ordinary pin interfaces (e.g., impedance ≤ 50 mΩ), which can reduce losses and heat generation during current transmission. When the vertical power board supplies power to a single motherboard through the horizontal adapter board, the gold fingers can stably transmit large currents (e.g., support continuous current ≥ 30 A), ensuring that the single motherboard receives a constant voltage (12V DC voltage fluctuation can be controlled within ±1%), avoiding voltage drops due to excessive interface impedance.

[0063] Meanwhile, because the pin definitions and spacing (e.g., pin spacing 2.54mm) of the gold fingers are perfectly matched with those of the single-channel motherboard power unit connector, and the elastic contact structure of the gold fingers ensures tight contact even after insertion and removal, it avoids poor contact caused by vibration or temperature changes. This reliable connection further enhances the independence of the power supply links of each single-channel motherboard. Based on the precise matching of the gold finger-type connection interface, the horizontal adapter board inserts into the power unit connector of the single-channel motherboard via the gold fingers, achieving both stable contact for power and signal transmission and easy insertion and removal. This detachable connection facilitates installation, maintenance, or component replacement (e.g., in case of a single-channel motherboard failure, simply remove the corresponding horizontal adapter board to remove the motherboard independently without affecting other components). Furthermore, the structural characteristics of the gold fingers (wear-resistant and highly conductive) ensure reliable connection during long-term use.

[0064] The multi-socket server in this application includes at least two single-socket motherboards, an adapter module, and multiple power supply units. The adapter module includes a vertical power board and at least two horizontal adapter boards. The vertical power board has multiple power supply unit interfaces and at least two adapter connectors. One end of the horizontal adapter board matches the adapter connector of the vertical power board, and the other end adapts to the power supply unit connector of the single-socket motherboard. This allows multiple power supply units to provide stable power to the multi-socket server composed of at least two single-socket motherboards through the vertical power board and the horizontal adapter boards. Therefore, this application allows for flexible combination of single-socket motherboards to form a multi-socket system. Users do not need to purchase both single-socket and multi-socket servers simultaneously to meet different scenario requirements, reducing redundant procurement expenditures, improving equipment utilization, and reducing cost waste caused by equipment idleness.

[0065] As an extension and refinement of the above embodiments, refer to Figure 3 The diagram shown is a detailed view of the single-channel motherboards 11 and 12, which are equipped with a system power consumption conversion circuit 31, a voltage regulation controller 32, a processor 33, and a power supply unit connector 34.

[0066] The system power consumption conversion circuit 31 is used to collect system voltage and total system current, and calculate the total power consumption data of the multi-channel server based on the system voltage and total system current.

[0067] Specifically, the system power consumption conversion circuit is directly integrated on the single-channel motherboard. It can collect the system voltage (e.g., 12V input voltage, processor core 1.8V voltage) and total system current (e.g., total input current, processor supply current) of the single-channel motherboard in real time, and directly calculate the real-time power consumption data of the single-channel motherboard using the formula "total power consumption = voltage × current" (calculation error ≤ ±2%). This circuit can directly obtain the actual power consumption of the single-channel motherboard, avoiding inaccurate calculation of the global total power consumption caused by power unit power statistics deviation. For example, a single-channel motherboard obtains 12V / 25A of power from the horizontal adapter board through the gold fingers (power unit feedback power 300W), but the system power consumption conversion circuit collects the actual voltage of 11.8V and the current of 24.5A, calculating the actual power consumption to be 289.1W. In this case, the actual data will be used to ensure a more accurate calculation of the global total power consumption.

[0068] The voltage regulator 32 is connected to the system power consumption conversion circuit and the processor on the single-channel motherboard, and the voltage regulator communicates with the processor through a serial voltage identification protocol to transmit the total power consumption data of the multi-channel server to the processor.

[0069] Specifically, the voltage regulator (VR) can be understood as an intermediate hub on a single motherboard, which needs to connect two key components at the same time to enable data flow.

[0070] Furthermore, its first connection is to the system power consumption conversion circuit, which is the data source responsible for collecting voltage and current, and also correcting the total power consumption based on the power-ready signal (for example, calculating the actual power consumption of a single motherboard as 280W). The voltage regulator controller is connected to the system power consumption conversion circuit to obtain the total power consumption data from it.

[0071] The second connection is to the processor on the single-socket motherboard. Processor 33 is the data receiver; it needs to receive power consumption data and then synchronize it to the main processor so the main processor can determine whether to trigger frequency reduction. The voltage regulator controller is connected to the processor to transmit the received power consumption data to it.

[0072] The voltage regulator controller and the processor can communicate using the industry-standard Serial Voltage Identification (SVID) protocol. This protocol is anti-interference and can filter electromagnetic interference in the power supply link (such as interference caused by changes in the current of the horizontal adapter board), ensuring that power consumption data (such as 280W) is not transmitted as 290W or 270W. At the same time, this protocol is fast, with a transmission delay of less than 1ms, which is much faster than traditional protocols. This allows the processor to obtain the latest power consumption data in a timely manner, avoiding misjudgment of the power consumption status by the main processor due to data delay (for example, the power consumption is clearly exceeded, but the frequency is not reduced in time because the data transmission is slow).

[0073] Furthermore, the accurate power consumption data calculated by the system power consumption conversion circuit is transmitted to the processor via the voltage regulation controller and the SVID protocol channel. Only when the processor receives accurate data can the main processor determine whether to trigger all processors to reduce their frequency simultaneously based on the correct total global power consumption (e.g., the total power consumption of all single-socket motherboards is 580W), thus avoiding incorrect frequency reduction due to data errors or missed frequency reduction due to slow data.

[0074] The processor 33 is used to receive the total power consumption data of the multi-channel server.

[0075] Specifically, after the system power consumption conversion circuit calculates the real-time power consumption data of a single motherboard, it transmits the data via VR through the SVI protocol, and finally receives it uniformly by the processor 33, thus clarifying the destination of the data flow. For example, the power consumption conversion circuit of single motherboard A calculates a power consumption of 280W, which is transmitted to the processor 33 on single motherboard A via the voltage regulation controller 32. The power consumption of single motherboard B is 300W, which is transmitted to the processor 33 on single motherboard B via the voltage regulation controller 32. Each processor 33 then synchronizes the data to the main processor, ensuring that the total power consumption data (580W) obtained by the main processor is complete data that has been accurately received by each node without omission.

[0076] Meanwhile, after receiving the total power consumption data, processor 33 locally caches the three most recent historical data (e.g., updated every 100ms, caching power consumption data within 300ms). When the main processor fails, the new main processor does not need to wait for each individual motherboard to re-collect and transmit data; it can directly read the latest total power consumption data cached from each processor 33 (e.g., 280W cached by processor 33A, 300W cached by processor 33B), quickly completing the global total power consumption recalculation (580W). This local caching design reduces the monitoring recovery time after main processor switching from 500ms to less than 200ms, further avoiding monitoring interruptions.

[0077] The system power consumption conversion circuit 31 is also used to receive the power ready signal output through the power unit connector or the adapter module, and to correct the calculation result of the total power consumption data by combining the power ready signal, the system voltage and the total system current.

[0078] Specifically, the power-ready signal is obtained from the power unit connector (the interface for receiving power from a single motherboard) or the adapter module (vertical power board / horizontal adapter board). This signal is a direct indicator of whether the power supply is working properly. For example, a high level indicates that the power supply is stable, while a low level or interruption indicates power failure, poor contact, or other abnormalities.

[0079] The basic power consumption data is obtained by synchronously collecting system voltage (such as the input voltage of a single motherboard of 12V) and total system current (such as the total current flowing into the motherboard of 25A), which is the basis for calculating the initial power consumption.

[0080] Furthermore, the circuit correlates the power-ready signal with voltage / current data to make judgments, the core of which is to eliminate cases where the data appears normal but the power supply status is abnormal:

[0081] If the power-ready signal is normal (high level), it means that the power supply is stable. At this time, the initial power consumption calculated by "voltage × current" (i.e., 12V × 25A = 300W) is basically accurate and no additional correction is needed.

[0082] If the power-ready signal is abnormal (such as flashing or low level), even if the voltage / current data is normal, it may be due to power fluctuations, temporary power supply, or other situations (such as instantaneous data before a power failure). In this case, the initial power consumption data is unreliable and needs to be corrected.

[0083] Then, depending on the type of anomaly in the power-ready signal, the circuit will use preset logic to adjust the initial power consumption to ensure that the result matches the actual power supply capacity.

[0084] For example, if the power ready signal is interrupted (a power supply unit fails), the initial power consumption is calculated to be 280W. However, if the faulty power supply cannot provide continuous power, the circuit will combine the average power consumption of the three previous faults (e.g., 270W) and the current current decay trend (e.g., current decrease of 10%) to correct it to 243W, so as to avoid mistakenly taking the "instantaneous power consumption that cannot be sustained" as the real data.

[0085] For example, if the power-ready signal flickers (power supply is unstable) and the initial power consumption fluctuates between 290W and 310W, the circuit will take the average voltage / current during the stable period of the signal (such as 295W) as the correction result to eliminate fluctuation interference.

[0086] The final corrected total power consumption data will be transmitted to the voltage regulation controller and the processor, providing a reliable basis for the main processor to determine whether to trigger frequency reduction and adjust the power supply strategy, avoiding misoperation caused by inaccurate data (such as wrong frequency reduction that wastes computing power, or failure to detect overload that leads to hardware overload).

[0087] This application also provides a system power consumption monitoring method applied to a multi-processor server. The multi-processor server consists of at least two single-processor motherboards connected via an adapter module and multiple power supply units. Each single-processor motherboard has a processor, and among the multiple processors, there is one master processor and at least one slave processor. (Refer to...) Figure 4 As shown, the method includes the following steps:

[0088] S41. For each of at least two single-channel motherboards, obtain the power level information and power-ready signals of all power supply units connected to the single-channel motherboard.

[0089] Specifically, after the server starts, each single-channel motherboard control unit immediately starts information collection to ensure that the initial state of the power supply unit is obtained before the system runs. It can collect information periodically according to a preset period (such as 100ms / time), or collect information in real time when events such as power supply unit plugging / unplugging or fault alarm are triggered, and dynamically update the power supply unit status information.

[0090] For each single-channel motherboard, its control unit obtains the power level information of all power supply units connected to the motherboard in the following way: The control unit establishes bidirectional communication with the management chip built into the power supply unit through industry standard communication protocols such as I2C (Inter-Integrated Circuit, IIC) bus and Power Management Bus (PMBus); the power level information collected includes at least: rated power, real-time output power and power load rate;

[0091] Rated power is the maximum designed output power of the power supply unit (e.g., 500W, 800W), serving as a benchmark parameter for calculating power consumption; real-time output power is the actual power output of the power supply unit (e.g., 300W, 450W), reflecting the current power supply load; and power load rate is the ratio of real-time output power to rated power, used as a correction basis for subsequent calculations of global power consumption.

[0092] Then, the power unit management chip transmits the power level information to the single-channel motherboard control unit via the communication bus. The control unit verifies the data and removes abnormal data (such as abnormal values ​​exceeding 120% of the rated power) to ensure the accuracy of the information.

[0093] Specifically, the power-ready signal (such as PWRGD_PSUx_PWROK, where "x" is the power unit number) is a key level signal reflecting whether the power unit is supplying power stably. It is obtained as follows:

[0094] The power-ready signal pin of each power unit is directly connected to the signal detection port of the corresponding single-channel motherboard through the signal link of the adapter module (such as the signal pin of the horizontal adapter board or the signal aggregation circuit of the vertical power board).

[0095] When the signal is high (e.g., 3.3V±5%) and lasts for ≥50ms, the power supply unit is determined to be "ready" (i.e., in a stable power supply state); when the signal is low (e.g., 0V±5%) or the high level lasts for less than 50ms, the power supply unit is determined to be "not ready" (e.g., not powered on, faulty, not properly plugged in).

[0096] S42. Based on the power level information and power ready signals of all power units connected to the single-channel motherboard, determine the total number of online power units of the multi-channel server, and calculate the total power consumption data of the multi-channel server in combination with the power level information.

[0097] After obtaining the power ready signals of each power unit in step S41 above, it is necessary to first deduplicate and verify the validity of the power ready signals of each single motherboard, and count the number of valid signals to determine the total number of online power units.

[0098] Furthermore, to avoid the same power unit being counted repeatedly by multiple single-path motherboards, an independent ready status list of all power units in a multi-path server can be obtained. Specifically, the ready status list can be traversed, and only power units that are "judged as ready" can be counted as "online power units", while power units that are "not ready" (such as faulty or improperly plugged-in power units) can be removed.

[0099] Then, the number of online power units after screening is counted to form the total number of online power units (e.g., if 3 out of 4 power units are ready, the total number is 3), and synchronized to the control unit of all single-channel motherboards through the inter-processor communication link (e.g., UPI link) to ensure that each unit uses a unified total parameter to calculate power consumption.

[0100] Combining the power level information obtained in step S41 with the total number of online power supply units determined in the steps, the total power consumption data is calculated. Specifically, the total power consumption data can be calculated based on the power level information of all power supply units, the total number of online power supply units, the collected system voltage and the total system current.

[0101] Furthermore, the local power consumption of a single motherboard can be calculated first. That is, each single motherboard control unit calculates its local power consumption based on the power unit parameters connected to the board. Then, the local power consumption of all single motherboards is added together to obtain the total power consumption data of the multi-channel server. The calculated total power consumption data provides data support for subsequent threshold judgment.

[0102] S43. When the total power consumption data exceeds a preset threshold, a frequency reduction instruction is generated and sent to all processors in the multi-channel server to trigger simultaneous frequency reduction of all processors.

[0103] Specifically, the preset threshold is determined using a dynamic correlation method, meaning the threshold value is strongly correlated with the number of motherboards per processor in a multi-processor server. For example, when there are 2 motherboards per processor, the preset threshold for total power consumption is 2000W; when there are 3 motherboards per processor, the preset threshold for total power consumption is 3000W. Users can set the corresponding preset threshold according to their needs.

[0104] When the total power consumption exceeds a preset threshold, the main processor generates a frequency reduction instruction and forwards it to other processors in the multi-processor server. After receiving the frequency reduction instruction, each processor executes the frequency reduction operation synchronously.

[0105] By acquiring the power level information and power-ready signal of the connected power unit for each single motherboard, the total number of online power units of the multi-channel server is determined. Combined with the power level information, the total power consumption data of the multi-channel server is calculated, thus providing a reliable data basis for threshold judgment. When the global total power consumption exceeds the preset threshold, all processors are triggered to reduce their frequency simultaneously. This can quickly reduce power consumption from the source of computing power to avoid hardware overload damage, maintain the computing power coordination of each processor, prevent computing power imbalance and data risks caused by asynchronous frequency reduction, and ensure stable system operation.

[0106] It should be noted that the above system power consumption monitoring method also includes the following steps:

[0107] When the total power consumption data exceeds a preset threshold, a preset target frequency and a frequency reduction operation execution timestamp are obtained, and a frequency reduction instruction is generated based on the preset target frequency and the frequency reduction operation execution timestamp, so as to be sent to all processors in the multi-path server in parallel.

[0108] It should be noted that the preset target frequency is not a fixed value, but is dynamically matched based on the extent to which the total global power consumption exceeds the limit. For example, when the total power consumption exceeds the threshold by less than 10%, the preset target frequency is set to 85% of the rated frequency (small frequency reduction to balance power consumption and computing power); when the total power consumption exceeds the threshold by 10%-20%, the preset target frequency is set to 75% of the rated frequency (moderate frequency reduction to quickly suppress power consumption); when the total power consumption exceeds the threshold by more than 20%, the preset target frequency is set to 65% of the rated frequency (deep frequency reduction to urgently avoid hardware risks).

[0109] Furthermore, by obtaining the preset target frequency generation instruction, the problem caused by fixed-amplitude frequency reduction (such as reducing the frequency by 20% regardless of the extent of the over-limit) can be avoided. This prevents excessive frequency reduction when the over-limit is small, thus avoiding the waste of computing power, and also prevents insufficient frequency reduction when the over-limit is large, which still cannot control power consumption. This enables precise control of frequency reduction on demand.

[0110] Meanwhile, the frequency reduction operation execution timestamp sets a unified frequency adjustment start time for all processors (e.g., instruction generation time is T0, execution timestamp is T0+50ms). After receiving the instruction, the processor will calibrate based on its own clock module and the timestamp to ensure that frequency reduction starts at the precise time. Compared to the synchronization method that only relies on the order of instruction issuance (which is prone to some processors receiving instructions late due to transmission delays), the timestamp locking mechanism can control the frequency reduction synchronization error of each processor within ±1ms.

[0111] For example, in a distributed database scenario, multiple processors need to process data write tasks synchronously. If the frequency reduction synchronization error is large, it may cause a processor to reduce its frequency first and then its processing speed to slow down, causing the data write queue to be blocked. Timestamp locking can ensure that all processors reduce their frequency at the same time, maintain a consistent processing speed, and ensure the smoothness of data writing.

[0112] Furthermore, by improving instruction coverage efficiency through a parallel delivery mechanism, the main processor generates downclocking instructions, which can be sent synchronously to all processors using multiple independent communication links (such as allocating a dedicated UPI link to each slave processor, while using the control signal channel of the vertical power board as a backup parallel link). This significantly reduces the total instruction delivery time (serial delivery to 4 slave processors may take 20ms, while parallel delivery only takes 5ms), ensuring that all processors have sufficient time to complete instruction reception and calibration before the execution timestamp. At the same time, it avoids the chain-reaction interruption problem caused by the failure of one slave processor in serial delivery, which prevents subsequent processors from receiving instructions. Each parallel link operates independently, and even if one link fails, other links can still transmit normally. Combined with the instruction backup mechanism, the instruction reception success rate can be increased to 100%, ensuring that all processors can perform the downclocking operation as required.

[0113] Because the preset target frequency can be dynamically adjusted according to the extent of exceeding the limit, when the total power consumption only slightly exceeds the limit, the power consumption can be brought back within the threshold without significant frequency reduction, thus preserving the processor's computing power to the maximum extent. For example, if a multi-processor server is running an AI inference task and the total power consumption only exceeds the threshold by 5%, the preset target frequency can be set to 85% of the rated frequency. The processor can still maintain a relatively high inference speed (only decreasing by 15%), avoiding a significant increase in inference latency due to fixed-amplitude frequency reduction (such as a 20% frequency reduction). When the total power consumption significantly exceeds the limit, deep frequency reduction can quickly control power consumption, ensuring system stability and achieving refined resource management.

[0114] It should also be noted that the above system power consumption monitoring method further includes the following steps:

[0115] When the power ready signal of a certain power supply unit is interrupted, a corresponding power failure notification is generated and sent to the main processor to trigger the recalculation of the total power consumption data, and the power contribution of that power supply unit is deducted from the new total power consumption data.

[0116] Specifically, during actual operation, the power ready signal may be interrupted due to abnormal reasons, which usually means that the corresponding power unit has failed (such as damage to the power unit itself, loose connection with the vertical power board, or interruption of the signal link of the horizontal adapter board). At this time, the power unit can no longer provide stable power to the system. If its power is still included in the global total power consumption calculation, it will lead to an inflated total power consumption data (such as the faulty power supply not actually outputting power, but the system still counts it according to its rated power), which will cause subsequent threshold judgment deviations (such as the actual available power consumption is insufficient, but the calculated value is still within the threshold, and the frequency reduction cannot be triggered; or the actual power consumption has exceeded the limit, but the calculated value is not reflected, delaying the frequency reduction time).

[0117] Furthermore, by generating an anomaly notification and deducting the power contribution of the power supply unit, this application can immediately remove the faulty power supply from the power consumption calculation after the signal is interrupted, ensuring that the new total power consumption data can truly reflect the actual power supply capacity of the currently available power supply units, and providing accurate data support for subsequent power consumption control.

[0118] Meanwhile, the generated power failure notification not only triggers a recalculation of total power consumption, but also carries key fault information (such as the faulty power unit number, the connected single-channel motherboard identifier, and the signal interruption timestamp), and is sent to the main processor. After receiving the notification, the main processor can push the warning information to the administrator through the server management interface (such as the Web UI), and record the fault details in the system log. For example, the notification content is "Power unit PSU-3 readiness signal interrupted, connected to the horizontal adapter board 131 of single-channel motherboard 12". The administrator can directly locate the fault location (the connection link between PSU-3 and single-channel motherboard 12) without having to check all power units and adapter components one by one, which greatly shortens the fault investigation time. At the same time, early warning can prevent further damage to the faulty power unit (such as arc discharge caused by loose connection), or cause other power units to overload due to the spread of the fault (such as after a single power supply fails, other power supplies need to bear more load, and if there is no timely warning, it is easy to cause a chain failure).

[0119] When the power-ready signal is interrupted, causing a decrease in available power supply capacity, the recalculated total global power consumption more accurately reflects the maximum computing power that the current power supply can support. The main processor can dynamically adjust the processor frequency based on the new total power consumption data (rather than simply reducing the frequency when the threshold is exceeded). For example, if the total rated power of the available power supply decreases from 2000W to 1500W, and the recalculated total power consumption is 1400W (close to the new power supply capacity limit), the main processor can actively fine-tune the processor frequency from 3.0GHz to 2.8GHz. This ensures that the power consumption does not exceed the limit while maximizing the preservation of computing power (with a decrease of only about 7%), avoiding the waste of computing power caused by blindly reducing the frequency due to a decrease in power supply capacity (such as directly reducing it to 2.0GHz). This design of "dynamically adapting computing power based on power status" achieves a fine-grained match between power supply resources and computing power requirements. It is especially suitable for scenarios where power supply units need to be frequently plugged and unplugged for maintenance (such as regularly replacing aging power supplies in data centers), ensuring that the system can still operate efficiently during maintenance.

[0120] In this embodiment of the application, the system power consumption monitoring method further includes: maintaining communication between the main processor and at least one slave processor through a heartbeat detection mechanism, and determining a new main processor from at least one of the slave processors when the main processor fails.

[0121] Specifically, the heartbeat detection mechanism is implemented through a dedicated communication link (such as the heartbeat signal channel of the UPI link) between the main processor and each slave processor. The main processor sends heartbeat data packets (containing information such as the current running status of the main processor and power consumption calculation progress) to all slave processors at a preset period (such as 100ms / time). After receiving the data, the slave processor immediately sends back an acknowledgment signal.

[0122] If a slave processor fails to receive heartbeat data packets N times consecutively (e.g., 3 times), or if the received data packets contain verification errors (e.g., CRC check failure), it is determined that the master processor may be malfunctioning (e.g., overload causing a freeze, hardware failure). The processor immediately synchronizes the master processor's abnormality information with other slave processors to avoid misjudgment by a single slave processor. This real-time monitoring design can provide early warning before the master processor completely fails (e.g., during the transition from a freeze to a crash), allowing preparation time for subsequent switching and reducing the risk of monitoring interruptions.

[0123] Once a main processor failure is confirmed, the system will select a new main processor from all slave processors according to preset rules, ensuring seamless continuity of power consumption monitoring tasks. The selection rules can be dynamically adapted based on the real-time status of the slave processors. For example, the slave processor that has "fully received the latest global power consumption data and has the lowest load rate (e.g., ≤30%)" will be prioritized as the new main processor. The former ensures that the new main processor can continue calculations based on the latest power consumption data without re-collecting data; the latter ensures that the new main processor has sufficient computing power to undertake global management tasks (such as generating frequency reduction instructions and handling power failure notifications).

[0124] Furthermore, the switching process needs to be completed quickly. For example, after the original main processor fails, processor A (with a load rate of 25% and the latest power consumption data) is selected as the new main processor. It immediately takes over the power consumption calculation task, re-verifies the total global power consumption based on the existing data, and continuously receives power information from each individual motherboard. This avoids problems such as "power ready signal interruption and failure to process" and "power consumption exceeding the limit without triggering frequency reduction" caused by the main processor failure, thus ensuring the continuity of the monitoring process.

[0125] The master-slave processor heartbeat detection and master processor switching mechanism can further reduce the impact of master processor failure on power consumption control and avoid triggering a chain of risks.

[0126] This is because when the main processor malfunctions during the generation of downclocking instructions (e.g., the total global power consumption has been calculated to exceed the limit, but the instruction has not been issued), the new main processor, after taking over, can quickly complete the downclocking instructions based on cached power consumption data (determining the preset target frequency and downclocking execution timestamp), and transmit them to all processors through a parallel issuance mechanism. This avoids power unit overload caused by power consumption exceeding the limit but no instruction triggering downclocking. For example, if the original main processor malfunctions and the total global power consumption has exceeded the preset threshold by 15%, the new main processor will generate a downclocking instruction within 100ms after taking over, setting the target frequency to 70% of the rated frequency, ensuring that all processors downclock synchronously and power consumption drops in a timely manner. At the same time, the new main processor will also re-verify the execution status of the issued downclocking instructions (e.g., through the current frequency information fed back by the processors). If it finds that a processor has not executed downclocking, it will reissue the instruction to prevent power control loopholes.

[0127] If the main processor is not switched over in time, the power failure notification will go unattended, potentially causing the remaining power supply units to overheat due to excessive load (e.g., other power supplies needing to power PSU-2), or even triggering a chain reaction of failures (e.g., multiple power supply units failing one after another). The rapid takeover by the new main processor can keep the power failure handling delay within 1 second, far below the overload protection trigger time of the power supply units (usually 5-10 seconds), effectively preventing the spread of the fault.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0129] The embodiments of this application also provide a system power consumption monitoring device, which corresponds one-to-one with the method claims. Figure 5 This is a schematic diagram of the system power consumption monitoring device 500 provided in this disclosure, as shown below. Figure 5 As shown, the device 500 of this embodiment includes:

[0130] The acquisition unit 51 is used to acquire, for each of at least two single-channel motherboards, the power level information and power ready signal of all power units connected to the single-channel motherboard.

[0131] The determining unit 52 is used to determine the total number of online power units of the multi-channel server based on the power level information and power ready signals of all power units connected to the single-channel motherboard, and to calculate the total power consumption data of the multi-channel server in combination with the power level information.

[0132] The generation unit 53 is used to generate a frequency reduction instruction and send it to all processors in the multi-channel server when the total power consumption data exceeds a preset threshold, thereby triggering all processors to reduce their frequency simultaneously.

[0133] As an optional implementation of this application, the acquisition unit 51 is specifically used to read the power level information corresponding to each power unit based on the baseboard management controller of each single-channel motherboard; and to receive the power ready signals triggered by all power units through the signal path of the adapter module, so that each processor can acquire the power level information and power ready signals of all power units in the multi-channel server.

[0134] As an optional implementation of this application, the determining unit 52 is specifically used to deduplicate and verify the validity of the power ready signal of each single motherboard, and count the number of valid signals to determine the total number of online power units.

[0135] As an optional implementation of this application, the determining unit 52 is specifically used to calculate the total power consumption data based on the power level information of all power supply units, the total number of online power supply units, the collected system voltage and the total system current.

[0136] As an optional implementation of this application, the generation unit 53 is specifically used to obtain a preset target frequency and a frequency reduction operation execution timestamp when the total power consumption data exceeds a preset threshold, and generate the frequency reduction instruction based on the preset target frequency and the frequency reduction operation execution timestamp, so as to send it to all processors in the multi-path server in parallel.

[0137] As an optional implementation of this application, the generation unit 53 is further configured to generate a corresponding power failure notification and send the power failure notification to the main processor when the power ready signal of a certain power unit is interrupted, so as to trigger the recalculation of the total power consumption data and deduct the power contribution of the power unit from the new total power consumption data.

[0138] As an optional implementation of this application, the determining unit 52 is further configured to maintain communication between the main processor and at least one slave processor through a heartbeat detection mechanism, and to determine a new main processor from at least one of the slave processors when the main processor fails.

[0139] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described system power consumption monitoring method embodiments.

[0140] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described system power consumption monitoring method embodiments when running.

[0141] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0142] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described system power consumption monitoring method embodiments.

[0143] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described system power consumption monitoring method embodiments.

[0144] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0145] The foregoing has provided a detailed description of a multi-channel server, a system power consumption monitoring method, a device, and a storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A multi-path server, characterized in that, include: At least two single-channel motherboards, adapter modules, and multiple power supply units; The single-channel motherboard is equipped with a power unit connector, which is configured to selectively connect to multiple power units via the adapter module. The adapter module includes a vertical power board and at least two horizontal adapter boards. The vertical power board is provided with multiple power unit interfaces and at least two adapter connectors. The power unit interfaces are used to connect the multiple power units, and the adapter connectors are used to connect to the horizontal adapter boards. One end of the horizontal adapter board is provided with a first connection interface that matches the adapter connector on the vertical power board, and the other end is provided with a second connection interface that matches the power unit connector of the single-channel motherboard, so that a detachable connection between the horizontal adapter board and the single-channel motherboard can be formed through the second connection interface. The at least two single-channel motherboards are arranged in a stacked structure; each single-channel motherboard is equipped with a processor; the processors of the at least two single-channel motherboards are divided into a main processor and at least one slave processor; The processors on each single-channel motherboard are connected via cables for communication. The single-channel motherboard is also equipped with a system power consumption conversion circuit; The system power consumption conversion circuit is used to collect system voltage and total system current, and calculate the total power consumption data of the multi-channel server based on the system voltage and total system current. The single-channel motherboard is also equipped with a voltage regulation controller; The voltage regulator controller is connected to both the system power consumption conversion circuit and the processor on the single-channel motherboard, and communicates with the processor via a serial voltage identification protocol to transmit the total power consumption data to the processor. After receiving the total power consumption data, the processor also caches the three most recent total power consumption data, so that in the event of a main processor failure, the cached total power consumption data can be read by a new main processor to complete the global total power consumption recalculation.

2. The multi-channel server according to claim 1, characterized in that, The plurality of power supply units supply power to the single motherboard through the vertical power board and at least two of the horizontal adapter boards; Each of the horizontal adapter boards has a connection interface that is connected to a corresponding adapter connector of the vertical power board, and its connection interface is connected to a corresponding power unit connector of a single-channel motherboard.

3. The multi-channel server according to claim 1, characterized in that, The connection interface of the horizontal adapter board is configured with gold fingers, which are matched with the power unit connector of the single-channel motherboard to form a detachable connection between the horizontal adapter board and the power unit connector of the single-channel motherboard.

4. The multi-channel server according to claim 1, characterized in that, The master-slave relationship between the master processor and the slave processor is configured via any one of hardware jumpers, a basic input / output system, and a baseboard management controller.

5. The multi-channel server according to claim 1, characterized in that, The processor is used to receive the total power consumption data of the multi-channel server.

6. The multi-channel server according to claim 1, characterized in that, The system power consumption conversion circuit is also used to receive the power ready signal output through the power unit connector or the adapter module, and combine the power ready signal, the system voltage and the system total current to correct the calculation result of the total power consumption data.

7. The multi-channel server according to claim 5, characterized in that, The main processor is used to trigger all processors in the multi-channel server to simultaneously reduce their frequency when the total power consumption of the multi-channel server is greater than or equal to a preset threshold.

8. A method for monitoring system power consumption, characterized in that, The method, applied to the main processor in a multi-processor server, includes: For each of at least two single-channel motherboards, obtain the power level information and power-ready signals of all power units connected to the single-channel motherboard; Based on the power level information and power ready signals of all power units connected to the single-channel motherboard, the total number of online power units of the multi-channel server is determined, and the total power consumption data of the multi-channel server is calculated by combining the power level information. When the total power consumption data exceeds a preset threshold, a frequency reduction instruction is generated and sent to all processors in the multi-channel server, triggering all processors to reduce their frequency simultaneously. The multi-channel server includes: at least two single-channel motherboards, a converter module, and multiple power supply units; The single-channel motherboard is equipped with a power unit connector, which is configured to selectively connect to multiple power units via the adapter module. The adapter module includes a vertical power board and at least two horizontal adapter boards. The vertical power board is provided with multiple power unit interfaces and at least two adapter connectors. The power unit interfaces are used to connect the multiple power units, and the adapter connectors are used to connect to the horizontal adapter boards. One end of the horizontal adapter board is provided with a first connection interface that matches the adapter connector on the vertical power board, and the other end is provided with a second connection interface that matches the power unit connector of the single-channel motherboard, so that a detachable connection between the horizontal adapter board and the single-channel motherboard can be formed through the second connection interface. The at least two single-channel motherboards are arranged in a stacked structure; each single-channel motherboard is equipped with a processor; the processors of the at least two single-channel motherboards are divided into a main processor and at least one slave processor; The processors on each single-channel motherboard are connected via cables for communication. The single-channel motherboard is also equipped with a system power consumption conversion circuit; The system power consumption conversion circuit is used to collect system voltage and total system current, and calculate the total power consumption data of the multi-channel server based on the system voltage and total system current. The single-channel motherboard is also equipped with a voltage regulation controller; The voltage regulator controller is connected to both the system power consumption conversion circuit and the processor on the single-channel motherboard, and communicates with the processor via a serial voltage identification protocol to transmit the total power consumption data to the processor. After receiving the total power consumption data, the processor also caches the most recent three historical data, so that in the event of a main processor failure, the cached historical data can be read by the new main processor to complete the global total power consumption recalculation.

9. The system power consumption monitoring method according to claim 8, characterized in that, The step of acquiring the power level information and power-ready signals of all power units connected to the single-channel motherboard includes: The baseboard management controller of each of the single-channel motherboards reads the power level information corresponding to each of the power supply units; Through the signal path of the adapter module, the power ready signals triggered by all power units are received, so that each processor can obtain the power level information and power ready signals of all power units in the multi-channel server.

10. The system power consumption monitoring method according to claim 8, characterized in that, The step of determining the total number of online power units for the multi-channel server based on the power level information and power readiness signals of all power units connected to the single-channel motherboard includes: The power-ready signals of each of the single-channel motherboards are deduplicated and their validity is verified. The number of valid signals is counted to determine the total number of online power units.

11. The system power consumption monitoring method according to claim 8, characterized in that, The calculation of the total power consumption data of the multi-channel server, based on the power level information, includes: The total power consumption data is calculated based on the power level information of all power supply units, the total number of online power supply units, the collected system voltage and total system current.

12. The system power consumption monitoring method according to claim 8, characterized in that, When the total power consumption exceeds a preset threshold, a frequency reduction instruction is generated and sent to all processors in the multi-processor server, including: When the total power consumption data exceeds a preset threshold, a preset target frequency and a frequency reduction operation execution timestamp are obtained, and a frequency reduction instruction is generated based on the preset target frequency and the frequency reduction operation execution timestamp, so as to be sent to all processors in the multi-path server in parallel.

13. The system power consumption monitoring method according to claim 8, characterized in that, The method further includes: When the power ready signal of a certain power supply unit is interrupted, a corresponding power failure notification is generated and sent to the main processor to trigger the recalculation of the total power consumption data, and the power contribution of that power supply unit is deducted from the new total power consumption data.

14. The system power consumption monitoring method according to claim 8, characterized in that, The method further includes: The master processor maintains communication with at least one slave processor via a heartbeat detection mechanism, and a new master processor is determined from at least one of the slave processors when the master processor fails.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the system power consumption monitoring method as described in any one of claims 8 to 14 when executing the computer program.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the system power consumption monitoring method as described in any one of claims 8 to 14.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the system power consumption monitoring method as described in any one of claims 8 to 14.

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