Endpoint detection and response method, electronic device

Abstract

The application discloses an endpoint detection and response method and electronic equipment, and relates to the technical field of server security protection. The method comprises the following steps: detecting whether a first device inserted in a PCIE slot is a trusted device; when the first device is a trusted device, writing endpoint detection and response rule information in an extension configuration space of the first device; using a preset detection circuit, detecting whether the running state of the first device is abnormal according to the endpoint detection and response rule information; when it is detected that the running state of the first device is abnormal, generating an abnormal state signal and triggering a protection response operation. The application can realize real-time detection and response of PCIE devices through a hardware level method, and guarantee the security of a server bottom layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server security protection, and particularly relates to an endpoint detection and response method and an electronic device. BACKGROUND

[0002] With the improvement of server performance requirements, the complexity and device combination diversity of a Peripheral Component Interconnect Express (PCIE) link are significantly increased, and the security risk thereof is also increased.

[0003] Therefore, in the server security protection system, how to better realize real-time detection and response of the PCIE device has become a technical problem to be solved at present. SUMMARY

[0004] The present application provides an endpoint detection and response method and an electronic device, which can realize real-time detection and response of the PCIE device through a hardware level means, and guarantee the server bottom layer security.

[0005] The present application provides an endpoint detection and response method, and the method comprises the following steps:

[0006] Detecting whether a first device inserted in a PCIE slot is a trusted device; when the first device is the trusted device, writing endpoint detection and response rule information in an extended configuration space of the first device; utilizing a preset detection circuit to detect whether a running state of the first device is abnormal according to the endpoint detection and response rule information; and generating an abnormal state signal and triggering a protection response operation when it is detected that the running state of the first device is abnormal.

[0007] The present application further provides an endpoint detection and response device, which comprises:

[0008] A pre-detection module is configured to detect whether a first device inserted in a PCIE slot is a trusted device.

[0009] A configuration module is configured to write endpoint detection and response rule information in an extended configuration space of the first device when the first device is the trusted device.

[0010] A detection module is configured to utilize a preset detection circuit to detect whether a running state of the first device is abnormal according to the endpoint detection and response rule information.

[0011] An alarm module is configured to generate an abnormal state signal and trigger a protection response operation when it is detected that the running state of the first device is abnormal.

[0012] The application further provides an electronic device, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of the endpoint detection and response method.

[0013] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of the endpoint detection and response method.

[0014] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of the endpoint detection and response method.

[0015] The endpoint detection and response method and the electronic device provided by the application can realize real-time detection and protection of attacks through a dedicated register, a hardware circuit and a secure storage area by sinking the core logic of the endpoint detection and response function from a software layer to a PCIE device hardware layer, reduce response delay and enhance tamper resistance. A hardware-level cooperative protection mechanism is constructed between a server root complex and a PCIE device based on a PCIE protocol, and a closed-loop security protection system is formed through link layer register configuration, state reporting and dynamic rule updating. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A flowchart of an endpoint detection and response method provided in an embodiment of the application;

[0018] Figure 2 A sub-flowchart of an endpoint detection and response method provided in an embodiment of the application Figure 1 ;

[0019] Figure 3 A sub-flowchart of an endpoint detection and response method provided in an embodiment of the application Figure 2 ;

[0020] Figure 4 A sub-flowchart of an endpoint detection and response method provided in an embodiment of the application Figure 3 ;

[0021] Figure 1 A structure diagram of an electronic device provided in an embodiment of the application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0023] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0024] The term “and / or” in the embodiments of the present application describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. The character “ / ” generally represents that the associated objects before and after it are in an “or” relationship.

[0025] In modern server architecture, PCIE, as a high-speed bus protocol, widely connects key peripherals such as graphics processing units (GPU), storage devices, network interface cards (NIC), etc., and plays a core role in high-speed data transmission and device communication.

[0026] With the improvement of server performance requirements, the complexity of PCIE link and the diversity of device combination increase significantly, and the security risk also rises. For example, an attacker may initiate a direct memory access (DMA) attack through a PCIE device to directly access system memory by bypassing the operating system; or inject malicious code by tampering with the PCIE device firmware; or even use PCIE protocol vulnerabilities to evade basic input / output system (BIOS) security mechanisms.

[0027] In addition, the underlying hardware (such as BIOS) of the server lacks real-time detection capability for abnormal behavior of PCIE devices, making it difficult to intercept attacks at the hardware level.

[0028] In summary, in the server security protection system, how to realize real-time endpoint detection and response (EDR) of PCIE devices through hardware-level means has become a key requirement for ensuring the security of the server bottom layer.

[0029] In related technologies, the EDR function mainly relies on the operating system (OS) or the device firmware interface to indirectly obtain the PCIE device state. Specifically, the EDR function is usually realized by the following methods:

[0030] Software layer dependence: The EDR module needs to read the PCIE device state through the OS driver or the device firmware interface, such as monitoring device behavior through polling or interrupt mechanism. Since the software layer needs the central processing unit (CPU) to analyze and process data, there is a significant delay (such as milliseconds) in attack response, making it difficult to intercept transient hardware attacks (such as DMA over-privileged access).

[0031] Low utilization of hardware security features: The hardware security modules built-in PCIE devices (such as transaction layer packet (TLP) encryption engine, access control service (ACS)) are not directly called by the EDR function, but only exist as static configuration. For example, the access control rules of ACS need to be initialized by BIOS and fixed, which cannot be dynamically adjusted to respond to new attacks.

[0032] EDR policy disconnection from hardware: The detection rules of EDR (such as abnormal TLP signature, DMA address whitelist) are stored in system memory or firmware, which are easy to be tampered by malicious software. In addition, related solutions do not use the hardware isolation features of PCIE devices (such as one-time programmable (OTP) memory, latch register), resulting in lack of security guarantee for the execution environment of protection logic.

[0033] Insufficient link layer coordination: There is a lack of EDR linkage mechanism based on hardware protocol between the server root complex and the PCIE device, such as the inability to dynamically update EDR rules or report abnormal states in real time through the PCIE link layer protocol, resulting in the need for software layer triggering for protection actions, further increasing the risk of delay.

[0034] In summary, related technologies have significant deficiencies in hardware-level security protection, real-time response capability, and tamper resistance, making it difficult to meet the deep security protection requirements of PCIE devices for servers.

[0035] In the face of the above technical problems, an endpoint detection and response method is provided in the embodiments of the present application. The core logic of the EDR function is lowered from the software layer to the PCIE device hardware layer, real-time detection and protection of attacks are realized through special registers, hardware circuits and secure storage areas, response delay is reduced and tamper resistance is enhanced. A hardware-level cooperative protection mechanism is constructed between the server root complex and the PCIE device based on the PCIE protocol, and a closed-loop security protection system is formed through link layer register configuration, state reporting and dynamic rule updating.

[0036] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Referring to Figure 1 , Figure 2 A flowchart of an endpoint detection and response method provided in the embodiments of the present application is shown in FIG. 1. In some embodiments, the endpoint detection and response method includes the following steps.

[0038] S101, detecting whether a first device inserted in a PCIE slot is a trusted device. If yes, proceed to S102; if no, proceed to S105.

[0039] In some embodiments, the first device is a PCIE device.

[0040] In some embodiments, the server root complex can directly read the first device firmware image using a serial peripheral interface (SPI) flash controller and calculate a hash value (to avoid software tampering risks), and then compare the hash value with a reference value provided by the manufacturer through a hardware encryption engine to determine whether the first device is a trusted device.

[0041] If the calculated hash value matches the reference value provided by the manufacturer, it can be determined that the first device is a trusted device and the EDR function is initialized. If the calculated hash value does not match the reference value provided by the manufacturer, it can be determined that the first device is an untrusted device.

[0042] S102, writing EDR rule information in the extended configuration space of the first device.

[0043] In some embodiments, an extended configuration space can be defined for the first device to store the EDR rule information.

[0044] When it is determined that the first device is a trusted device, the EDR rule information is written in the extended configuration space of the first device.

[0045] S103, detecting whether the running state of the first device is abnormal according to the EDR rule information by using a preset detection circuit. If yes, S104 is executed.

[0046] In some embodiments, a preset hardware detection circuit can be used to detect the running parameter of the first device, match the running parameter with the EDR rule information, and determine whether the running state of the first device is abnormal.

[0047] S104, generating an abnormal state signal and triggering a protection response operation.

[0048] In some embodiments, when the running state of the first device is abnormal, an abnormal state signal can be generated and reported to the PCIE information of the server root complex.

[0049] In addition, when the running state of the first device is abnormal, a protection response operation can also be triggered.

[0050] Optionally, the protection response operation includes cutting off the power supply of the PCIE link or isolating the first device.

[0051] S105, triggering a hardware-level alarm and isolating the first device.

[0052] In some embodiments, when it is determined that the first device is an untrusted device, a hardware-level alarm can be triggered in time and the first device can be isolated.

[0053] Through the hardware-level alarm and isolation mechanism, a microsecond-level response can be realized when an untrusted device is detected, and the attack window is significantly reduced.

[0054] The endpoint detection and response method provided by the embodiments of the application can realize real-time detection and protection of attacks by sinking the core logic of the EDR function from the software layer to the PCIE device hardware layer, through a special register, a hardware circuit and a secure storage area, reduce the response delay and enhance the anti-tampering ability. A hardware-level cooperative protection mechanism is constructed between the server root complex and the PCIE device based on the PCIE protocol, and a closed-loop security protection system is formed through link layer register configuration, state reporting and dynamic rule updating.

[0055] In some embodiments, the detection of whether the first device inserted into the PCIE slot is a trusted device includes:

[0056] reading the firmware image of the first device; calculating a hash value according to the firmware image; obtaining a reference value stored in a preset OTP memory, and determining whether the hash value matches the reference value; when the hash value matches the reference value, determining that the first device is a trusted device.

[0057] Exemplarily, in some embodiments, the PCIE device firmware image can be directly read by the SPI flash controller, the hash value is calculated (to avoid software tampering risk), and compared with the vendor reference value by a hardware encryption engine (such as a Trusted Platform Module (TPM)), and whether the PCIE device is a trusted device is determined according to the comparison result.

[0058] Optionally, the calculated firmware image hash value and the reference value read from the OTP memory can be compared bit by bit. If each bit of the two hash values is the same, they are considered to match; otherwise, they are considered to not match.

[0059] The OTP memory is a memory that can only be written once. Once the data is written, it cannot be modified again, and has high security and reliability.

[0060] If the hash values match, it means that the currently loaded firmware image is consistent with the reference firmware pre-stored in the OTP memory, and the system can consider the firmware to be trusted, allowing it to be normally loaded and run. If the hash values do not match, it means that the firmware image is tampered with or damaged.

[0061] Exemplarily, taking the insertion of a solid state disk (Solid State Disk or Solid State Drive, SSD) into the PCIE slot of a server as an example, referring to Figure 2 , Figure 1 is a sub-process diagram of an endpoint detection and response method provided in an embodiment of the present application Figure 3 .

[0062] In some embodiments, when the SSD is inserted into the PCIE slot of the server, the server root complex can automatically detect whether the SSD is a trusted device through the PCIE link layer protocol, specifically including:

[0063] S201, the server root complex reads the configuration space standard register of the SSD through the PCIE link layer protocol, and obtains the vendor ID and device ID. The vendor ID and device ID can be used to preliminarily identify whether the SSD device is a trusted device. If the SSD device is preliminarily identified as a trusted device, S201 can be continued.

[0064] By verifying the vendor ID and device ID, it can be ensured that the inserted device is the expected SSD.

[0065] S202, the server BIOS or firmware reads the firmware image of the SSD through the SPI hardware interface.

[0066] The reading of the firmware image of the SSD can obtain the firmware information of the device for subsequent verification.

[0067] S203, invoke the hash engine built-in SSD, calculate the hash value of the firmware image.

[0068] Wherein, the hash calculation is used to generate a unique fingerprint of the firmware.

[0069] S204, read the pre-stored reference hash value from the OTP storage of the SSD.

[0070] Wherein, the OTP area stores tamper-proof reference data for verifying the integrity of the firmware.

[0071] S205, compare the calculated firmware image hash value with the reference hash value in the OTP storage. If the hash values match, the SSD is considered a trusted device and S206 can be performed; if the hash values do not match, the SSD is considered an untrusted device and S207 can be performed.

[0072] Wherein, through the hash value comparison, it is ensured that the firmware of the SSD has not been tampered with, and the security and stability of the system can be maintained.

[0073] S206, initialize the EDR function.

[0074] In some embodiments, the execution engine can also be activated, and specific register configuration permissions can be unlocked.

[0075] S207, trigger a hardware-level alarm, including an LED alarm and a temporary disablement of the PCIE link, and the process terminates.

[0076] The endpoint detection and response method provided by the embodiments of the present application provides strong security protection for servers through a hardware-level verification mechanism, ensuring that only authenticated and verified devices can operate normally in the system.

[0077] In some embodiments, the EDR rule information includes exception feature code information and a DMA address whitelist. The extension configuration space includes a TLP exception detection register and a DMA permission control register.

[0078] In some embodiments, the EDR rule information is written into the extension configuration space of the first device, including:

[0079] The exception feature detection code is written into the TLP exception detection register, and the DMA address whitelist is written into the DMA permission control register.

[0080] For example, when it is determined that the inserted SSD is a trusted device, the server root complex can directly write the EDR rule information into the extension configuration space of the SSD through a PCIE configuration transaction, taking the insertion of the SSD into the PCIE slot of the server as an example.

[0081] In some embodiments, the server root complex can write exception feature detection code, such as illegal opcode, to a TLP exception detection register (address 0x200) for filtering malicious TLPs.

[0082] In some embodiments, the server root complex can write a DMA address whitelist to a DMA permission control register (address 0x210) for limiting DMA operations.

[0083] The endpoint detection and response method provided in the embodiments of the present application can complete the configuration process of EDR rule information based on the PCIE protocol by hardware directly without CPU intervention, which can effectively improve the processing speed and system efficiency.

[0084] In some embodiments, after writing the EDR rule information into the extended configuration space of the first device, the TLP exception detection register and the DMA permission control register can be set to a hardware locking state based on a hardware latching mechanism.

[0085] In some embodiments, the hardware circuit can continuously monitor the state of the extended configuration space write operation. When detecting that the EDR rule information is successfully written into the extended configuration space of the first device, the hardware circuit can automatically trigger the hardware latching mechanism.

[0086] When the hardware latching mechanism is triggered, a locking signal can be sent to a specific latching control register. The signal is transmitted to the TLP exception detection register and the DMA permission control register through the hardware circuit. After receiving the locking signal, the locking flag bit in the two registers is set. From then on, software will no longer be able to modify the content of the two registers, unless a specific hardware unlocking operation is performed, such as system reset or through a special security unlocking instruction.

[0087] The hardware latching mechanism can be implemented based on flip-flop, latch and other digital circuit elements. When the locking signal arrives, these elements will lock the current register value and prevent subsequent write operations. For example, using a D-type flip-flop, when the locking signal is valid, the clock input of the flip-flop is masked and its output remains unchanged, thereby realizing the locking of the register value.

[0088] The locking signal can be transmitted through a specific signal path in the hardware circuit. The signal from the latching control register passes through the combination and timing control of the logic gate circuit, and can accurately reach the target register, ensuring the reliable execution of the locking operation.

[0089] Setting the TLP exception detection register and the DMA permission control register to a hardware locking state has the following beneficial effects:

[0090] Prevent tampering of rules: After locking the TLP exception detection register and DMA permission control register, malicious software or attackers cannot modify the rule information in these registers through software means. This ensures the integrity and effectiveness of EDR rules, allowing the system to continuously perform TLP detection and DMA permission control according to the pre-set security rules.

[0091] Enhance system security: The hardware lock state makes the system's security configuration more stable, reducing the occurrence of security vulnerabilities. Even if the system is attacked, attackers will find it difficult to bypass these hardware-locked security rules, effectively protecting the system's data security and stable operation.

[0092] Ensure consistency of security policies: During system operation, the hardware lock ensures the consistency of security policies. Regardless of changes in the system's software state, the rules for TLP detection and DMA permission control remain unchanged, providing reliable security protection for the system.

[0093] For example, after writing EDR rule information into the extended configuration space of the SSD, the register is prevented from being tampered with by software through the hardware latching mechanism (by setting the 0x300 register flag position).

[0094] The endpoint detection and response method provided by the embodiments of the present application sets the TLP exception detection register and the DMA permission control register to a hardware-locked state, combined with the EDR rule information previously written into the extended configuration space, to build a powerful hardware-based security protection system that can effectively deal with various potential security threats.

[0095] In some embodiments, a pre-configured detection circuit can be used to detect whether the running state of the first device is abnormal based on the EDR rule information.

[0096] In some embodiments, the detection circuit includes a TLP filtering circuit and a DMA detection circuit. The TLP filtering circuit and / or DMA detection circuit are integrated into the PCIE link layer.

[0097] In some embodiments, a TLP filtering circuit can be used to detect whether the incoming TLP in the first device contains a feature matching the abnormal feature code information; if the incoming TLP in the first device contains a feature matching the abnormal feature code information, it is determined that the running state of the first device is abnormal.

[0098] For example, when the TLP filtering circuit detects that the TLP contains a feature matching the abnormal feature detection code stored in the TLP exception detection register, it will determine that the TLP is a malicious data packet, and at this time it can be determined that the running state of the first device is abnormal.

[0099] The detection process can be based on the PCIE protocol, and the TLP filtering circuit can directly analyze and match the TLP without the intervention of the CPU, thereby improving the detection efficiency and security and reducing the burden of the CPU.

[0100] In some embodiments, the DMA detection circuit can be used to detect whether the DMA request address of the first device is located in the DMA address whitelist; if the DMA request address of the first device is not located in the DMA address whitelist, it is determined that the running state of the first device is abnormal.

[0101] For example, when the DMA request address of the first device is not located in the DMA address whitelist, it can be considered that the first device wants to access sensitive data in the system memory through DMA, and at this time, it can be determined that the running state of the first device is abnormal.

[0102] Only when the DMA request address of the first device is in the DMA address whitelist stored in the DMA authority control register, the DMA operation is allowed. This can effectively prevent malicious devices from accessing sensitive data in the system memory through DMA, and protect the data security of the system.

[0103] In some embodiments, when it is determined that the running state of the first device is abnormal, an abnormal state signal can be generated and a protection response operation can be triggered.

[0104] For example, when it is determined that the TLP transmitted in the first device is a malicious data packet, the protection response operation includes discarding the TLP and / or triggering a security alarm.

[0105] When it is determined that the DMA request address of the first device is not located in the DMA address whitelist, the protection response operation includes terminating data transmission and setting an error state register.

[0106] For example, taking the case that the SSD is inserted into the PCIE slot of the server as an example, referring to Figure 3 , Figure 2 is a sub-process diagram of an endpoint detection and response method provided in an embodiment of the present application Figure 4 .

[0107] In some embodiments, a preset detection circuit is used to detect whether the running state of the SSD is abnormal according to the EDR rule information, including:

[0108] S301, the TLP filtering circuit reads the abnormal feature detection code stored in the TLP abnormality detection register.

[0109] S302, the TLP filtering circuit detects whether the TLP transmitted in the SSD contains a feature matched with the abnormal feature code information. If yes, S303 is executed; if no, S304 is executed.

[0110] S303, discard the TLP and set the exception flag bit (0x01) of the status register (such as 0x230).

[0111] S304, the TLP is normally forwarded to the SSD internally.

[0112] S305, the DMA detection circuit reads the DMA address whitelist stored in the DMA authority control register.

[0113] S306, the DMA detection circuit detects whether the DMA request address of the SSD is located in the DMA address whitelist. If yes, S307 is executed; if no, S308 is executed.

[0114] S307, immediately terminate the DMA transmission and set the exception flag bit (0x02) of the status register (0x230).

[0115] S308, the DMA request is allowed to normally execute.

[0116] In the embodiments of the present application, the pre-set detection circuit is used to detect whether the running state of the SSD is abnormal according to the EDR rule information, which has the following advantages:

[0117] Real-time: The hardware detection circuit can detect and process TLP packets and DMA requests in real time without software intervention, with fast response speed, which can effectively prevent malicious operations from causing damage to the system in a short time.

[0118] Security: Through accurate feature matching and address range checking, abnormal TLP packets and DMA requests can be accurately identified and prevented, enhancing the system's defense capability against malicious attacks and data theft.

[0119] Reliability: The hardware-implemented detection and processing mechanism is not affected by software vulnerabilities or malicious software, providing stable security protection and ensuring that the system can operate according to the preset rules in various situations.

[0120] In some embodiments, after step S303 or step S307, further comprising:

[0121] S309, triggering PCIE link layer state reporting, including sending exception information to the server root complex.

[0122] For example, after detecting the exception, the above-mentioned detection circuit can encapsulate the exception information according to the format specified by the PCIE protocol. The encapsulated exception information is transmitted to the server root complex through the PCIE physical link.

[0123] The PCIE link layer is responsible for ensuring the reliable transmission of the above-mentioned exception information, including data encoding, error detection and correction, and the like. In the transmission process, the timing and flow control rules of the PCIE protocol are followed to ensure that the information can accurately reach the root complex.

[0124] Optionally, the above-mentioned exception information can include:

[0125] Exception type identification: explicitly indicates whether it is a specific exception type such as TLP exception or DMA privilege violation. For example, a specific code can be used to represent that the TLP packet is discarded due to matching an illegal feature, or the DMA request is terminated due to the address exceeding the DMA whitelist range.

[0126] Related register state: contains register state information related to exception detection, such as the current configuration value of the TLP exception detection register related to TLP filtering and the matching condition at the time of exception occurrence, the setting range of the DMA authority control register related to the DMA whitelist, and the target address of the privilege violation request, etc.

[0127] Timestamp: records the time of exception occurrence, so that subsequent security audits and problem analysis can accurately understand the time sequence of event occurrence.

[0128] In the embodiments of the present application, sending exception information to the server root complex can timely warn of potential security threats in the system. The server management system can quickly respond to these information, such as recording logs, triggering alarms, etc., to remind the administrator to pay attention to the security status of the system.

[0129] In addition, the exception information provides a basis for the server root complex to trigger subsequent EDR responses. The root complex can accurately determine the severity of the threat according to the received exception type and specific information, and select appropriate response measures, such as cutting off the power supply of the PCIE link or isolating the device, thereby effectively protecting the safe and stable operation of the system.

[0130] In some embodiments, the server root complex reads the state register of the first device at a preset time interval (such as 10ms). This periodic reading mechanism ensures that the server can continuously monitor the state of the first device and timely discover possible exceptions.

[0131] When the server root complex detects the presence of an exception flag in the above-mentioned state register, it triggers a protection response operation corresponding to the type of the above-mentioned exception flag according to the type of the above-mentioned exception flag.

[0132] For example, when the type of the above-mentioned exception flag is a TLP exception, a TLP flow isolation measure is triggered to close the TLP receiving function of the PCIE port, thereby effectively preventing further transmission of abnormal TLP packets and preventing them from causing greater impact on the system.

[0133] In the case that the type of the abnormality marker is DMA overreach, a link power-off operation is triggered to cut off the power supply of the first device through the PCIE power management module. The power-off operation can quickly stop the first device from working and avoid illegal access to system memory and other resources by the DMA overreach operation.

[0134] In some embodiments, after triggering the EDR response, the server root complex can read the state register again to confirm whether the abnormality has been resolved. If the abnormality is resolved, the server will resume the normal connection of the PCIE link to enable the first device to work normally again. If the abnormality is not resolved, the protection state is maintained to continuously ensure the safety of the system.

[0135] For example, the SSD is inserted into the PCIE slot of the server, and the state register of the SSD is read. Figure 4 , Figure 3 Figure 2 is a sub-process diagram of an endpoint detection and response method provided in the embodiments of the present application. Figure 5 .

[0136] In some embodiments, the method comprises:

[0137] S401, reading the state register of the SSD.

[0138] S402, detecting whether there is an abnormality marker in the state register. If yes, S403 is executed.

[0139] S403, determining the type of the abnormality marker. In the case that the type of the abnormality marker is TLP abnormality, S404 is executed. In the case that the type of the abnormality marker is DMA overreach, S405 is executed.

[0140] S404, triggering TLP traffic isolation measures to close the TLP receiving function of the PCIE slot.

[0141] S405, triggering a link power-off operation to cut off the power supply of the SSD.

[0142] S406, reading the state register again to confirm whether the abnormality has been resolved. If yes, S407 is executed. If no, S408 is executed.

[0143] S407, resuming the PCIE link where the SSD is located.

[0144] S408, maintaining the protection state.

[0145] In the embodiments of the present application, from state reporting, detection, response to exception release confirmation, a complete closed-loop protection mechanism is formed. This closed-loop mechanism can ensure that security threats are completely handled, prevent the re-emergence of threats, and ensure the long-term stable operation of the system.

[0146] In some embodiments, during the operation of the first device, the security risks faced by the system may evolve over time and in the environment. New attack methods and malicious behaviors may continue to appear, and the original EDR rule information may not be able to effectively respond to new threats. Therefore, the server can dynamically update the EDR rule information based on the current risk situation to ensure that the security protection of the system always remains effective.

[0147] In some embodiments, the hardware locking state of the TLP exception detection register and / or the DMA authority control register can be released through the out-of-band management interface; the exception feature detection code in the TLP exception detection register and / or the DMA address whitelist in the DMA authority control register can be updated through the out-of-band management interface.

[0148] For example, before the EDR rule information is changed and adjusted, the hardware latching register can be unlocked first. By resetting the latching register, the hardware locking state of the related register (such as the TLP exception detection register and the DMA authority control register) is released, so that it can accept new EDR rule information.

[0149] In order to ensure tamper resistance, only the reset operation of the latching register through the out-of-band management interface (such as the physical JTAG interface (Joint Test Action Group) or the baseboard management controller (Baseboard Management Controller, BMC)) is allowed. These out-of-band management interfaces have high security and usually require physical contact or specific management permissions to access, effectively preventing illegal modification by malicious software.

[0150] The endpoint detection and response method provided in the present application can directly configure EDR detection rules through the PCIE device itself hardware register; by calling the built-in detection circuit of the PCIE device, the EDR protection action is executed, which can ensure that the EDR configuration and execution logic are stored in the device hardware security area and cannot be tampered with by malicious software.

[0151] In some embodiments, the state of the Access Control Service (ACS) hardware support bit can be obtained. When the ACS hardware support bit is not turned on, a protection response operation is triggered.

[0152] Among them, ACS is an important PCIE security feature, which can provide fine control of device access, such as controlling peer-to-peer access between devices, isolating different service flows, etc. By reading the support bit, it can be determined whether the hardware has the ability to implement these access control functions.

[0153] In some embodiments, the state register of the TLP encryption engine can also be detected to determine whether the encryption enable of the TLP is turned on.

[0154] Among them, TLP encryption is a key measure to ensure the security of PCIE data transmission, which can prevent data from being stolen or tampered during transmission.

[0155] When it is detected that the encryption enable of the TLP is not turned on, a protection response operation is triggered.

[0156] Optionally, the above protection response operation includes a link isolation operation implemented by a hardware level switch. The hardware level switch has the characteristics of fast response speed and high security, which can quickly cut off the PCIE link connection, isolate the device with security risks, prevent potential security threats from further spreading, and protect the security of the entire system.

[0157] Through the description of the above embodiments, those skilled in the art can clearly understand that the endpoint detection and response method described in the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better implementation.

[0158] The application also provides an endpoint detection and response device, which comprises:

[0159] A pre-detection module is configured to detect whether a first device inserted into a PCIE slot is a trusted device.

[0160] A configuration module is configured to write endpoint detection and response rule information in the extended configuration space of the first device when the first device is a trusted device.

[0161] A detection module is configured to use a preset detection circuit to detect whether the running state of the first device is abnormal according to the endpoint detection and response rule information.

[0162] An alarm module is configured to generate an abnormal state signal and trigger a protection response operation when it is detected that the running state of the first device is abnormal.

[0163] In some embodiments, the pre-detection module is specifically configured to:

[0164] reading a firmware image of the first device by using a serial peripheral interface flash controller; calculating a hash value according to the firmware image; obtaining a reference value stored in a one-time programmable memory, and determining whether the hash value matches the reference value; when the hash value matches the reference value, determining that the first device is a trusted device; when the hash value does not match the reference value, determining that the first device is an untrusted device, and triggering a hardware-level alarm information and / or disabling the first device.

[0165] In some embodiments, the endpoint detection and response rule information includes exception signature information and direct memory access address whitelist; the extended configuration space includes a transaction layer packet exception detection register and a direct memory access permission control register; and the configuration module is specifically configured to:

[0166] write the exception signature detection code into the transaction layer packet exception detection register, and write the direct memory access address whitelist into the direct memory access permission control register.

[0167] In some embodiments, the configuration module is further configured to:

[0168] After writing the endpoint detection and response rule information into the extended configuration space of the first device, set the states of the transaction layer packet exception detection register and the direct memory access permission control register to a hardware lock state.

[0169] The setting of the states of the transaction layer packet exception detection register and the direct memory access permission control register to the hardware lock state includes:

[0170] respectively send a lock signal to the transaction layer packet exception detection register and the direct memory access permission control register, and the lock signal is used to trigger the transaction layer packet exception detection register and the direct memory access permission control register to enter the hardware lock state.

[0171] In some embodiments, the configuration module is further configured to:

[0172] release the hardware lock state of the transaction layer packet exception detection register and / or the direct memory access permission control register through the out-of-band management interface; and update the exception signature detection code in the transaction layer packet exception detection register and / or the direct memory access address whitelist in the direct memory access permission control register by using the out-of-band management interface.

[0173] In some embodiments, the detection circuit includes a transaction layer packet filtering circuit and a direct memory access detection circuit; the transaction layer packet filtering circuit and / or the direct memory access detection circuit are integrated in a high-speed serial expansion bus link layer.

[0174] In some embodiments, the detection module is configured to:

[0175] The transaction layer packet filtering circuit is used to detect whether the incoming transaction layer packet in the first device contains a feature matching the abnormal feature code information; the direct memory access detection circuit is used to detect whether the direct memory access request address of the first device is located in the direct memory access address whitelist; if the incoming transaction layer packet in the first device contains a feature matching the abnormal feature code information and / or the direct memory access request address of the first device is not located in the direct memory access address whitelist, it is determined that the running state of the first device is abnormal.

[0176] In some embodiments, the detection module is further configured to:

[0177] monitoring, at preset time intervals, whether there is an abnormal marker in the status register of the first device; when detecting that there is an abnormal marker in the status register, triggering a protection response operation corresponding to the type of the abnormal marker.

[0178] When the type of the abnormal marker is a transaction layer packet abnormality, the protection response operation includes discarding the incoming transaction layer packet in the first device and / or closing the transaction layer packet receiving function of the high-speed serial expansion bus slot; when the type of the abnormal marker is a direct memory access request overreach, the protection response operation includes terminating the transmission of the direct memory access request of the first device and / or cutting off the power supply of the first device.

[0179] In some embodiments, the pre-detection module is further configured to:

[0180] acquire the state of the access control service hardware support bit; read the status register of the transaction layer packet encryption engine to determine whether the transaction layer packet encryption enable is turned on; when the access control service hardware support bit is not turned on and / or the transaction layer packet encryption enable is not turned on, trigger the protection response operation.

[0181] The endpoint detection and response device provided by the embodiments of the present application stores EDR rules in a special register in the PCIE device expansion configuration space, and uses the built-in hardware circuit (TLP filtering, DMA blocking, hash engine) of the PCIE device to perform detection and protection, and realizes the EDR linkage of the server and the PCIE device based on the PCIE protocol. By sinking the EDR function to the hardware layer of the PCIE device, the response delay can be significantly reduced, the tamper resistance can be improved, and the hardware security features can be fully utilized to realize efficient protection.

[0182] Figure 5 A structural schematic diagram of an electronic device provided in the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the electronic device includes a PCIE device 100 and a server 200. ​As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected through a bus.

[0183] In the implementation process, the at least one processor 501 executes the computer execution instructions stored in the memory 502, so that the at least one processor 501 executes the embodiments corresponding to the above-mentioned endpoint detection and response method.

[0184] The specific implementation process of the processor 501 can refer to the embodiments corresponding to the above-mentioned endpoint detection and response method, which has similar implementation principles and technical effects, and will not be described here in this embodiment.

[0185] In the above embodiments, it should be understood that the processor can be a CPU, and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the endpoint detection and response method disclosed in the application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0186] The memory can contain a random access memory (RAM), and can also include a non-volatile memory (NVM), for example, at least one disk memory.

[0187] The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0188] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is set to execute the steps in any of the above-mentioned endpoint detection and response method embodiments when running.

[0189] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a RAM, a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0190] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program, when executed by a processor, implements the steps in any of the endpoint detection and response method embodiments described above.

[0191] The skilled person can further realize that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0192] The technical solutions provided by the present application are described in detail above. The principles and implementation modes of the present application are described by applying specific examples in this paper. The above description of the examples is only applicable to help understand the technical solutions and core ideas of the present application. It should be noted that, for ordinary skilled persons in the technical field, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An endpoint detection and response method, characterized by, The method comprises: detecting whether a first device inserted in a high-speed serial expansion bus slot is a trusted device; when the first device is a trusted device, writing endpoint detection and response rule information in an expansion configuration space of the first device; using a preset detection circuit, detecting whether a running state of the first device is abnormal according to the endpoint detection and response rule information; when it is detected that the running state of the first device is abnormal, generating an abnormal state signal and triggering a protection response operation; the endpoint detection and response rule information comprises abnormal feature code information and a direct memory access address whitelist; the expansion configuration space comprises a transaction layer data packet abnormality detection register and a direct memory access permission control register; the writing of the endpoint detection and response rule information in the expansion configuration space of the first device comprises: writing abnormal feature detection code into the transaction layer data packet abnormality detection register; writing a direct memory access address whitelist into the direct memory access permission control register.

2. The method of claim 1, wherein, The detection of whether the first device inserted in the high-speed serial expansion bus slot is a trusted device comprises: reading a firmware image of the first device by using a serial peripheral interface flash controller; calculating a hash value according to the firmware image; obtaining a reference value stored in a preset one-time programmable memory and determining whether the hash value matches the reference value; when the hash value matches the reference value, determining that the first device is a trusted device; when the hash value does not match the reference value, determining that the first device is an untrusted device, and triggering hardware-level warning information and / or disabling the first device.

3. The method of claim 1, wherein, The method further comprises: after the writing of the endpoint detection and response rule information into the expansion configuration space of the first device, setting states of the transaction layer data packet abnormality detection register and the direct memory access permission control register to a hardware locking state; the setting of the states of the transaction layer data packet abnormality detection register and the direct memory access permission control register to the hardware locking state comprises: sending a locking signal to the transaction layer data packet abnormality detection register and the direct memory access permission control register respectively, the locking signal being used to trigger the transaction layer data packet abnormality detection register and the direct memory access permission control register to enter the hardware locking state.

4. The method of claim 3, wherein, The method further comprises: removing the hardware locking state of the transaction layer data packet abnormality detection register and / or the direct memory access permission control register through an out-of-band management interface; updating abnormal feature detection code in the transaction layer data packet abnormality detection register and / or a direct memory access address whitelist in the direct memory access permission control register by using the out-of-band management interface.

5. The method of claim 1, wherein, The detection circuit comprises a transaction layer data packet filtering circuit and a direct memory access detection circuit; the transaction layer data packet filtering circuit and / or the direct memory access detection circuit are integrated in a high-speed serial expansion bus link layer.

6. The method of claim 5, wherein, The detection of whether the running state of the first device is abnormal according to the endpoint detection and response rule information by using the preset detection circuit comprises: detecting, by the transaction layer packet filtering circuit, whether the incoming transaction layer packet in the first device contains a feature matching the abnormal signature information; detecting, by the direct memory access detection circuit, whether the direct memory access request address of the first device is located in the direct memory access address whitelist; if the incoming transaction layer packet in the first device contains a feature matching the abnormal signature information, and / or the direct memory access request address of the first device is not located in the direct memory access address whitelist, determining that the running state of the first device is abnormal.

7. The method of claim 1, wherein, The method further comprises: monitoring, at a preset time interval, whether there is an abnormal flag in the status register of the first device; when detecting that there is an abnormal flag in the status register, triggering a protection response operation corresponding to the type of the abnormal flag according to the type of the abnormal flag; wherein, when the type of the abnormal flag is transaction layer packet abnormality, the protection response operation comprises discarding the incoming transaction layer packet in the first device, and / or closing the transaction layer packet receiving function of the high-speed serial expansion bus slot; when the type of the abnormal flag is direct memory access request overreach, the protection response operation comprises terminating the transmission of the direct memory access request of the first device, and / or cutting off the power supply of the first device.

8. The method of claim 1, wherein, The method further comprises: obtaining the state of the access control service hardware support bit; reading the status register of the transaction layer packet encryption engine to determine whether the transaction layer packet encryption is enabled; when the access control service hardware support bit is not enabled, and / or the transaction layer packet encryption is not enabled, triggering a protection response operation.

9. An electronic device, comprising: comprises: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the endpoint detection and response method according to any one of claims 1 to 8.

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