A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises the following steps: providing a substrate, at least one shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure defines an active region; performing a first ion implantation process on the substrate to form a well region in the active region; forming a patterned mask layer on the substrate, the patterned mask layer defines at least one implantation window, and each implantation window exposes part of the substrate surface above the well region; performing a second ion implantation process on the substrate through the implantation window to form a threshold voltage adjusting region in the active region, wherein the depth of the threshold voltage adjusting region in the substrate is less than the depth of the well region in the substrate; and removing the patterned mask layer. The application can flexibly adjust the threshold voltage of the device, and the threshold voltage of different types of devices can be synergistically optimized without additional complex processes, and the fluctuation trend of the threshold voltage with the change of the channel size is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the continuous reduction of the gate size of MOS devices, the length of the conductive channel under the gate is also continuously reduced. When the length of the conductive channel is reduced to a certain range, short channel effects, including drain-induced barrier lowering (DIBL) and punch through, will occur. Lightly doped drain (LDD) and pocket implant drain technologies are usually used to reduce the junction depth of PN junction and DIBL effect, and improve the performance of MOS devices. However, the lightly doped drain and pocket implant drain technologies alone cannot meet the performance requirements of MOS devices. To solve this problem, an injection technology for controlling the threshold voltage of MOS devices is proposed to adjust the threshold voltage (VT). Two important parameters of the injection technology for controlling the threshold voltage of MOS devices are injection dose and injection depth.

[0003] In the related art, in the injection technology for the threshold voltage of MOS devices, shallow injection depth and low dose injection are used to reduce the carrier concentration on the surface of the conductive channel, reduce the penetration of the drain electric field to the potential barrier of the conductive channel, weaken the DIBL effect, and make the Fermi levels of the source and the drain closer to the middle, and the bending degree of the Fermi level is small. However, the reduction of the surface concentration of the conductive channel will increase the difference between the threshold voltages of long channel MOS devices and short channel MOS devices, and ultimately affect the reliability of the devices and cause the performance of the devices to be reduced. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the detailed description section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solutions, and even less to determine the protection scope of the claimed technical solutions.

[0005] To solve the problems, the embodiment of the application provides a preparation method of a semiconductor device, which is characterized by comprising the following steps: providing a substrate, at least one shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure defines an active region; performing a first ion implantation process on the substrate to form a well region in the active region; forming a patterned mask layer on the substrate, the patterned mask layer defines at least one implantation window, and each implantation window exposes part of the substrate surface above the well region; performing a second ion implantation process on the substrate through the implantation window to form a threshold voltage adjusting region in the active region, wherein the depth of the threshold voltage adjusting region in the substrate is smaller than the depth of the well region in the substrate; and removing the patterned mask layer.

[0006] Exemplarily, the substrate comprises a first MOS device region and a second MOS device region, the first MOS device region is used for forming a long-channel MOS device, and the second MOS device region is used for forming a short-channel MOS device; when the second ion implantation process is performed, the patterned mask layer is formed on the substrate of the first MOS device region, and the implantation window exposes part of the substrate surface above the well region of the first MOS device region; the second ion implantation process is performed on the substrate of the first MOS device region and the substrate of the second MOS device region through the implantation window and by taking the patterned mask layer as a mask, so as to form threshold voltage adjusting regions in the active regions of the first MOS device region and the second MOS device region respectively, wherein the impurity doping concentration in the threshold voltage adjusting region of the first MOS device region is lower than the impurity doping concentration in the threshold voltage adjusting region of the second MOS device region.

[0007] Exemplarily, after the well region is formed and before the patterned mask layer is formed on the substrate, the method further comprises: performing a third ion implantation process on the substrate to form a punch-through prevention region in the well region, wherein the depth of the well region in the substrate is greater than the depth of the punch-through prevention region in the substrate, and the depth of the punch-through prevention region in the substrate is greater than the depth of the threshold voltage adjusting region in the substrate.

[0008] Exemplarily, after the patterned mask layer is removed, the method further comprises: forming a gate structure on the substrate, wherein part of the active region below the gate structure is a channel region, the punch-through prevention region is located below the channel region, and the threshold voltage adjusting region is located on the surface of the channel region.

[0009] Exemplarily, the implantation energy of the first ion implantation process is 100 KeV-1000 KeV, and the implantation energy of the third ion implantation process is 50 KeV-500 KeV.

[0010] Exemplarily, the number of the implantation windows is multiple.

[0011] Exemplarily, the multiple implantation windows are arranged equidistantly in the first direction, or the multiple implantation windows are arranged non-equidistantly in the first direction.

[0012] Exemplarily, the size of the implantation window in the first direction is 0.01 um-5 um, and the size of the implantation window in the second direction is 0.2 um-5 um, wherein the first direction is parallel to the surface of the substrate, and the second direction is parallel to the thickness of the substrate.

[0013] Exemplarily, the implantation ions of the second ion implantation process include at least one of carbon, nitrogen, phosphorus, boron, arsenic or indium, and / or the implantation energy of the second ion implantation process is 10 KeV-200 KeV, and the implantation angle is 0 deg-15 deg.

[0014] Another aspect of the present application provides a semiconductor device obtained by the above preparation method.

[0015] The semiconductor device and the preparation method thereof provided by the present application can realize the localization and controllability of the threshold voltage adjustment region by forming a patterned mask layer on the substrate and defining the implantation window by using the mask layer to control the ion implantation process, can accurately regulate the surface doping concentration of different device channel regions, can flexibly adjust the threshold voltage of the device, and can realize the collaborative optimization of the threshold voltage of different types of devices without additional complex processes, improve the fluctuation trend of the threshold voltage with the change of the channel size, and improve the reliability and performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description of embodiments of the present application taken in conjunction with the accompanying drawings. The drawings provided in the present application are used to provide further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, but do not constitute a limitation to the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0017] In the drawings:

[0018] Figure 1 A cross-sectional schematic view of a semiconductor device of an example embodiment of the related art is shown;

[0019] Figure 2A flow chart of a method of fabricating a semiconductor device is shown in accordance with an example embodiment of the present application.

[0020] Figures 3A-3F A cross-sectional view of a semiconductor device is shown in accordance with an example embodiment of the present application.

[0021] Figure 4 A simulation plot of a semiconductor device is shown in accordance with an example embodiment of the present application. DETAILED DESCRIPTION

[0022] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application.

[0023] It should be understood that the present application can be carried out in many different forms without departing from the spirit or essential characteristics of the application. To that end, embodiments disclosed herein should be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can represent like elements throughout.

[0024] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will also be understood that, when an element is referred to as being "connected" or "coupled" to another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0025] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0028] For a thorough understanding of the present application, reference will be made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0029] In the related art, as Figure 1As shown, in the threshold voltage injection process, the formation of the threshold voltage adjustment region usually adopts a global ion implantation manner, that is, the substrate 10 of the MOS device is subjected to ion implantation to form the threshold voltage adjustment region 11 in the channel region. However, for different device regions, such as a long channel device region and a short channel device region, the long channel device region is used to form a long channel MOS device, and the short channel device region is used to form a short channel MOS device. Among them, the long channel MOS device has a long channel length, a weak short channel effect, and a threshold voltage less affected by the change of the implantation concentration, while the short channel MOS device has a short channel length, a strong short channel effect, and a threshold voltage more sensitive to the implantation concentration, thereby causing the difference between the threshold voltages of the long channel MOS device and the short channel MOS device to increase, the roll off trend of the threshold voltage decreasing with the decrease of the channel length to increase, and thereby affecting the reliability of the device and causing the performance of the device to decrease.

[0030] Therefore, in view of the foregoing technical problems, the present application provides a preparation method of a semiconductor device, as shown in the accompanying drawings, Figure 2 which mainly comprises the following steps:

[0031] In step S1, a substrate is provided, and at least one shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure defines an active region;

[0032] In step S2, a first ion implantation process is performed on the substrate to form a well region in the active region;

[0033] In step S3, a patterned mask layer is formed on the substrate, and the patterned mask layer defines at least one implantation window, and each implantation window exposes a part of the substrate surface above the well region;

[0034] In step S4, a second ion implantation process is performed on the substrate through the implantation window with the patterned mask layer as a mask to form a threshold voltage adjustment region in the active region, wherein the depth of the threshold voltage adjustment region in the substrate is less than the depth of the well region in the substrate;

[0035] In step S5, the patterned mask layer is removed.

[0036] The preparation method of the semiconductor device provided by the present application can realize the localization and controllability of the threshold voltage adjustment region by forming a patterned mask layer on the substrate and using the mask layer to define an implantation window to control the ion implantation process, can accurately regulate the surface doping concentration of different device channel regions, can flexibly adjust the threshold voltage of the device, and can realize the coordinated optimization of the threshold voltages of different types of devices without additional complex processes, can improve the fluctuation trend of the threshold voltage with the change of the channel size, and can improve the reliability and performance of the device.

[0037] Embodiment one

[0038] Reference will now be made to the drawings Figure 2 and Figures 3A-3F A method of fabricating a semiconductor device according to the present application will be described in detail herein. Figure 2 A flow chart of a method of fabricating a semiconductor device according to an example embodiment of the present application is shown in FIG. 1. Figures 3A-3F A cross-sectional view of a semiconductor device according to an example embodiment of the present application is shown in FIG. 2.

[0039] An example method of fabricating a semiconductor device according to the present application includes the following steps:

[0040] First, a step S1 is performed to provide a substrate having at least one shallow trench isolation structure formed therein, the shallow trench isolation structure defining an active region.

[0041] In one example, as shown in FIG. 2, a substrate 20 is provided, the substrate 20 being made of at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductor, or silicon-on- insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on- insulator (SiGeOI), or germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrates such as alumina, quartz, or glass substrates, etc. Although several examples of materials that can form the substrate 20 are described herein, any material that can be used as the substrate 20 falls within the spirit and scope of the present application. Figure 3A In one example, as shown in FIG. 2, a substrate 20 is provided, the substrate 20 being made of at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductor, or silicon-on- insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on- insulator (SiGeOI), or germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrates such as alumina, quartz, or glass substrates, etc. Although several examples of materials that can form the substrate 20 are described herein, any material that can be used as the substrate 20 falls within the spirit and scope of the present application.

[0042] In one example, as shown in FIG. 2, a substrate 20 is provided, the substrate 20 being made of at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductor, or silicon-on- insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on- insulator (SiGeOI), or germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrates such as alumina, quartz, or glass substrates, etc. Although several examples of materials that can form the substrate 20 are described herein, any material that can be used as the substrate 20 falls within the spirit and scope of the present application. Figure 3BAs shown, the step of forming the shallow trench isolation structure 21 includes: sequentially forming a liner oxide layer and a patterned photoresist layer on the substrate 20; etching the liner oxide layer and the substrate 20 to form at least one recess extending through the liner oxide layer and into the substrate 20, with the patterned photoresist layer as a mask; and filling the recess with an isolation material to form the shallow trench isolation structure 21. Specifically, the liner oxide layer is first formed on the substrate 20, and the method of forming the liner oxide layer includes but is not limited to thermal oxidation or chemical vapor deposition (CVD), etc., and the material of the liner oxide layer can be silicon oxide, etc., which is not specifically limited. Then, the patterned photoresist layer is formed on the liner oxide layer, which defines the shape and position of the shallow trench isolation structure. The liner oxide layer and the substrate 20 are etched with the patterned photoresist layer as a mask to form at least one recess extending through the liner oxide layer and into the substrate 20, such as two recesses or three recesses. The etching of the liner oxide layer and the substrate 20 can be dry etching, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc. Finally, the isolation material is deposited in the recess, and the method of depositing the isolation material includes but is not limited to physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD), and the isolation material includes but is not limited to silicon dioxide. After the isolation material is filled, chemical mechanical polishing (CMP) can be used to remove the excess isolation material and the liner oxide layer on the substrate 20 to form the shallow trench isolation structure 21. The shallow trench isolation structure 21 defines the active region 201 in the substrate 20, which is used to isolate different MOS devices.

[0043] Then, step S2 is performed to perform a first ion implantation process on the substrate to form a well region in the active region.

[0044] In one example, as Figure 3CAs shown, a first ion implantation process is performed on the substrate 20 to form a well region 202 in the active region 201. Specifically, the first ion implantation process is performed on the substrate 20, and the first ion implantation process is a high-energy and high-concentration ion implantation, in which, for an NMOS device, P-type ions such as boron (B) or boron fluoride (BF2) are implanted, and for a PMOS device, N-type ions such as phosphorus (P) or arsenic (As) are implanted. For example, the implantation energy of the first ion implantation process is 100 KeV-1000 KeV, such as 100 KeV, 200 KeV, 500 KeV, 600 KeV, 800 KeV, or 1000 KeV, etc., to ensure that the ions have sufficient penetration depth to achieve a micron-level longitudinal doping distribution, the implantation dose is a high-concentration implantation to meet the device voltage resistance and isolation requirements, the implantation angle is usually approximately 0 degrees, i.e., vertical implantation, to ensure the symmetry and process controllability of the doping distribution, and to avoid lateral deviation and uneven regions caused by inclined implantation. The well region 202 is a deep-doped region formed in the substrate 20 by high-energy ion implantation, and its core function is to provide an electrically isolated working space for the device to prevent charge leakage or mutual interference between different device source-drain regions, and its depth in the substrate 20 is greater than the depth of the subsequent punch-through prevention region 203, threshold voltage adjustment region 204, etc. in the substrate 20.

[0045] In one example, as shown in FIG. 2B, Figure 3C As shown, after the first ion implantation process, a third ion implantation process is performed on the substrate 20 to form a punch-through prevention region 203 in the well region 202, wherein the depth of the well region 202 in the substrate 20 is greater than the depth of the punch-through prevention region 203 in the substrate 20. Specifically, the third ion implantation process is continued to be performed on the substrate 20, and the third ion implantation process is a medium-energy and medium-concentration ion implantation for suppressing short channel effects and preventing subsequent punch-through between source and drain electrodes, in which, for an NMOS device, P-type ions such as boron (B) or boron fluoride (BF2) are implanted, and for a PMOS device, N-type ions such as phosphorus (P) or arsenic (As) are implanted. For example, the implantation energy of the first ion implantation process is 50 KeV-500 KeV, such as 50 KeV, 80 KeV, 100 KeV, 200 KeV, 300 KeV, or 400 KeV, etc., and the implantation angle can be 0 degrees to 7 degrees. The depth of the punch-through prevention region 203 in the substrate 20 is less than the depth of the well region 202 in the substrate 20, i.e., located below the channel region, so that the punch-through prevention region 203 is formed in the well region 202. For example, the depth of the well region 202 in the substrate is 1 um-3 um, and the depth of the punch-through prevention region 203 in the substrate is 0.1 um-0.3 um.

[0046] Continuing, step S3 is performed to form a patterned mask layer on the substrate. The patterned mask layer defines at least one injection window, and each injection window exposes a portion of the substrate surface above the well region.

[0047] In one example, such as Figure 3B and Figure 3D As shown, a protective layer 22 may also be formed on the surface of the substrate 20 to protect the substrate surface and provide functions such as etching barrier or stress modulation in subsequent process steps. Exemplarily, the method for forming the protective layer 22 includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), and the protective layer 22 may be made of silicon oxide, silicon nitride, or silicon oxynitride, etc. Before performing the second ion implantation process, a patterned mask layer 23 is deposited on the protective layer 22. This mask layer 23 defines at least one implantation window 24, each implantation window 24 exposing a portion of the surface of the protective layer 22 above the well region 202, so that during the subsequent second ion implantation process, ions are precisely implanted into the active region above the well region 202 through these implantation windows, forming a local threshold voltage adjustment region 204. In other examples, the protective layer 22 may not be formed. After forming the well region 202 and the anti-penetration region 203, a patterned mask layer 23 may be formed directly on the surface of the substrate 20. Its implantation window 24 directly exposes the surface of the substrate 20 above the well region 202. Subsequently, the second ion implantation forms a local threshold voltage adjustment region 204 in the exposed area through the implantation window 24, which simplifies the process and reduces costs.

[0048] For example, the number of implantation windows 24 is multiple, and the multiple implantation windows 24 are arranged at equal intervals in the first direction. Specifically, there can be two, three, four or more implantation windows 24, which are arranged at intervals along the first direction parallel to the surface of the substrate 20 and distributed above the corresponding well region 202. This arrangement can control the distribution of ion implantation, realize the regular and periodic doping of the subsequent threshold voltage adjustment region, and help improve the uniformity and matching of electrical characteristics between devices. In other examples, the multiple implantation windows 24 can also be arranged at non-equal intervals in the first direction, which is not specifically limited.

[0049] Exemplarily, each implantation window 24 has a size of 0.01 um to 5 um in a first direction and a size of 0.2 um to 5 um in a second direction, wherein the first direction is parallel to the surface of the substrate 20 and the second direction is parallel to the thickness of the substrate 20. For example, the size of the implantation window 24 in the first direction is 0.01 um, 0.5 um, 1 um, 2 um, 4 um or 5 um. For example, the size of the implantation window 24 in the second direction is 0.2 um, 0.6 um, 1.5 um, 3 um, 4 um or 5 um. The size of the implantation window 24 can achieve accurate control of the implantation region, i.e. directional adjustment of the device channel surface doping concentration, to ensure the stability and consistency of the device threshold voltage.

[0050] Continuing, step S4 is performed to perform a second ion implantation process on the substrate through the implantation window with the patterned mask layer as a mask to form a threshold voltage adjustment region in the active region, wherein the depth of the threshold voltage adjustment region in the substrate is less than the depth of the well region in the substrate.

[0051] In one example, as Figure 3EAs shown, a second ion implantation process is performed on the substrate 20 through the injection window 24 with the patterned mask layer 23 as a mask to form a threshold voltage adjustment region 204 in the active region 201, wherein the depth of the threshold voltage adjustment region 204 in the substrate 20 is less than the depth of the well region 202 in the substrate 20. Specifically, the second ion implantation process is performed on the substrate 20 through the injection window 24 defined by the patterned mask layer 23, so that ions are implanted into the active region 201 corresponding to the exposed region to form a local threshold voltage adjustment region 204. Exemplarily, the implanting ions of the second ion implantation process include at least one of carbon, nitrogen, phosphorus, boron, arsenic or indium. Exemplarily, the implanting energy of the second ion implantation process is 10 KeV-200 KeV, for example, 10 KeV, 20 KeV, 50 KeV, 80 KeV, 150 KeV or 200 KeV, etc., and the implanting angle is 0 deg-15 deg, for example, 0 deg, 7 deg or 15 deg, etc., which is not specifically limited. Since the function of the threshold voltage adjustment region 204 is to accurately regulate the threshold voltage of the device by channel surface doping, the depth thereof in the substrate 20 is controlled to be less than the depth of the well region 202 formed by the first ion implantation process and less than the depth of the punchthrough stop region 203 in the substrate 20, specifically located near the surface of the channel region (above the corresponding gate structure and below the punchthrough stop region 203), corresponding to the upper surface region of the well region 202, so as to ensure that the implanted ions only affect the channel surface carrier concentration, neither interfere with the basic doping environment of the well region 202 nor conflict with the doping distribution of the punchthrough stop region 203, and finally realize accurate adjustment of the threshold voltage of the device. For example, the depth of the threshold voltage adjustment region 204 in the substrate is 0.05 um-0.1 um.

[0052] In one example, the substrate 20 includes a first MOS device region and a second MOS device region, the first MOS device region is used to form a long channel MOS device, and the second MOS device region is used to form a short channel MOS device; when performing the second ion implantation process, a patterned mask layer 23 is formed on the substrate 20 of the first MOS device region, and the injection window 24 exposes part of the substrate surface of the well region 202 of the first MOS device region; taking the patterned mask layer 23 as a mask, the second ion implantation process is performed on the substrate 20 of the first MOS device region through the injection window 24, and at the same time, the second ion implantation process is performed on the substrate 20 of the second MOS device region, so as to form a threshold voltage adjusting region 204 in the active region 201 of the first MOS device region and the second MOS device region, respectively, wherein the impurity doping concentration in the threshold voltage adjusting region 204 of the first MOS device region is lower than the impurity doping concentration in the threshold voltage adjusting region 204 of the second MOS device region. Specifically, first, the substrate 20 is divided into a first MOS device region for forming a long channel MOS device and a second MOS device region for forming a short channel MOS device, both regions are enclosed by the shallow trench isolation structure 21 to form independent active regions 201, and both regions form the well region 202 through the first ion implantation process and form the punch-through prevention region 203 (located in the well region) through the third ion implantation process.

[0053] The long channel MOS device can refer to a MOSFET (metal-oxide-semiconductor field effect transistor) whose channel length (L, i.e., the distance between the source and the drain) is much larger than the width of the depletion layer of the device. The short channel MOS device refers to a MOSFET whose channel length (L) is comparable to or even smaller than the width of the depletion layer of the device.

[0054] Then, when performing the second ion implantation process, a patterned mask layer 23 is formed on the surface of the substrate 20 of the first MOS device region, the mask layer 23 has multiple injection windows 24 opened only above the well region 202 corresponding to the long channel MOS device, the injection window 24 exposes part of the substrate 20 surface above the well region 202, wherein when the substrate 20 surface is formed with a protective layer 22, the injection window 24 exposes part of the protective layer 22 surface above the well region 202, and the multiple injection windows 24 are arranged equidistantly along the first direction parallel to the substrate surface, and in other examples, the multiple injection windows 24 can also be arranged non-equidistantly in the first direction, which is not limited herein. The surface of the substrate of the second MOS device region is not formed with a mask layer (i.e., the mask layer also exposes the substrate surface of the second MOS device region), so that the substrate 20 surface above the well region 202 of the second MOS device region is exposed, or wherein when the substrate 20 surface is formed with a protective layer 22, the protective layer 22 surface above the well region 202 is exposed.

[0055] Subsequently, using the patterned mask layer 23 as a mask, a second ion implantation process is performed on the substrate 20 of the first MOS device region and the substrate 20 of the second MOS device region through the implantation window 24. Since the substrate 20 of the first MOS device region only receives ion implantation through the implantation window (the mask layer 23 blocks part of the area, which reduces the actual effective implantation dose), while the substrate 20 of the second MOS device region is not blocked by the mask (it receives implantation over the entire area, resulting in a higher effective implantation dose), the doping concentration in the threshold voltage adjustment region 204 of the first MOS device region is lower than that in the threshold voltage adjustment region 204 of the second MOS device region. This is to meet the requirements of long-channel devices for low threshold voltage and high carrier mobility, and the requirements of short-channel devices for suppressing short-channel effects such as drain-induced barrier reduction (DIBL) through high concentration doping. This differentiated doping strategy effectively raises the threshold voltage of short-channel MOS devices, suppressing the short-channel effect, while keeping the threshold voltage of long-channel MOS devices relatively stable. This reduces the threshold voltage difference between short-channel and long-channel MOS devices, improves the fluctuation trend of threshold voltage with channel size, and enhances the reliability and performance of the devices.

[0056] Finally, step S5 is performed to remove the patterned mask layer.

[0057] In one example, such as Figure 3F As shown, after forming the threshold voltage adjustment region 204, the patterned mask layer 23 is removed. Specifically, the patterned mask layer 23 can be removed using an ashing or wet resist removal process to expose the surface of the substrate. When a protective layer 22 is formed on the substrate 20, removing the mask layer 23 exposes the surface of the protective layer, providing a clean interface for subsequent process steps.

[0058] It should be noted that an annealing process is performed after the ion implantation process. During annealing, the multiple threshold voltage adjustment regions 204 in the first MOS device region are connected into a continuous threshold voltage adjustment region 204 due to the lateral diffusion of impurities. Since the actual doped area of ​​the first MOS device region is smaller, its final average doping concentration is lower than that of the second MOS device region, thereby achieving differentiated control of the threshold voltage of long-channel and short-channel MOS devices and effectively narrowing the VT difference. In addition, annealing can also repair these damages and activate the implanted ions, thereby improving the device performance.

[0059] In one example, after removing the patterned mask layer 23, further comprising: forming a gate structure on the substrate 20, wherein the active region 201 under the gate structure is a channel region. Specifically, the gate structure at least comprises a gate dielectric layer and a gate electrode layer, which are located above the active region 201, and the method of forming the gate structure can be a method commonly used in the art, which is not specifically described here. The part of the active region 201 directly below the gate structure constitutes the channel region of the MOS device. Exemplarily, the punchthrough prevention region 203 is located below the channel region and within the well region 202, and has a higher doping concentration, which does not interfere with the carrier conduction of the channel region, and can avoid source-drain punchthrough; the threshold voltage adjustment region 204 is located near the surface of the channel region, immediately below the gate dielectric layer, so that when the gate applies a voltage, the electric field can efficiently act on the impurity ions of the threshold voltage adjustment region 204, thereby accurately regulating the threshold voltage of the device.

[0060] As shown in Figure 4 , Figure 4 Fig. (a) is a simulation diagram of a semiconductor device of the prior art, and the result obtained by the simulation diagram is that the threshold voltage of the long-channel MOS device of the prior art is -0.744V, and the threshold voltage of the short-channel MOS device is -0.638V. Figure 4 Fig. (b) is a simulation diagram of a semiconductor device of the present application, and the result obtained by the simulation diagram is that the threshold voltage of the long-channel MOS device of the present application is -0.74V, and the threshold voltage of the short-channel MOS device is -0.75V. It can be seen from the simulation result that the present application can reduce the difference between the threshold voltages of the long-channel MOS device and the short-channel MOS device, and has little effect on the saturation drain current (Idsat) of the long-channel device, from -28uA / um to -30uA / um, which indicates that it basically maintains the performance of the long-channel device. The diffusion of the implanted ions is more uniform through the patterned mask layer and the implantation windows arranged at equal intervals, which further improves the consistency and reliability of the device.

[0061] It is worth mentioning that the above steps are only examples, and the order of the above steps can also be adjusted without conflict.

[0062] At this point, the process steps of the semiconductor device preparation method according to an embodiment of the present application are completed. It can be understood that the semiconductor device preparation method of the present embodiment not only includes the above steps, but also can include other required steps before, during or after the above steps, which are all included in the scope of the preparation method of the present embodiment.

[0063] To sum up, the preparation method of the semiconductor device provided in the application realizes the localization and controllability of the threshold voltage adjustment region by forming a patterned mask layer on the substrate and defining an implantation window by using the mask layer to control the ion implantation process, so that the surface doping concentration of different device channel regions can be accurately regulated, the threshold voltage of the device can be flexibly adjusted, the threshold voltage of different types of devices can be synergistically optimized without additional complex processes, the fluctuation trend of the threshold voltage with the channel size is improved, and the reliability and performance of the device are improved.

[0064] The application also provides a semiconductor device, which can be prepared by the method of the first embodiment or other suitable preparation method.

[0065] The semiconductor device can include a MOS device, for example, the semiconductor device can include a long channel MOS device and a short channel MOS device.

[0066] The application has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and illustration, and are not intended to limit the application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the application is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the application, which all fall within the scope of the application claimed. The scope of protection of the application is defined by the appended claims and their equivalent scope.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substrate is provided in which at least one shallow trench isolation structure is formed, the shallow trench isolation structure defining an active region; A first ion implantation process is performed on the substrate to form a well region in the active region; A patterned mask layer is formed on the substrate, the patterned mask layer defining at least one injection window, each injection window exposing a portion of the substrate surface above the well region, wherein the substrate includes a first MOS device region and a second MOS device region, the first MOS device region being used to form a long-channel MOS device, the second MOS device region being used to form a short-channel MOS device, the patterned mask layer being formed on the substrate of the first MOS device region, and the injection window exposing a portion of the substrate surface above the well region of the first MOS device region; Using the patterned mask layer as a mask, a second ion implantation process is performed on the substrate of the first MOS device region and the substrate of the second MOS device region through the implantation window to form threshold voltage adjustment regions in the active regions of the first MOS device region and the second MOS device region, respectively. The depth of the threshold voltage adjustment region in the substrate is less than the depth of the well region in the substrate, and the impurity doping concentration in the threshold voltage adjustment region of the first MOS device region is lower than the impurity doping concentration in the threshold voltage adjustment region of the second MOS device region. Remove the patterned mask layer.

2. The preparation method according to claim 1, characterized in that, After forming the well region and before forming the patterned mask layer on the substrate, the method further includes performing a third ion implantation process on the substrate to form a punch-through region within the well region, wherein the depth of the well region in the substrate is greater than the depth of the punch-through region in the substrate, and the depth of the punch-through region in the substrate is greater than the depth of the threshold voltage adjustment region in the substrate.

3. The preparation method according to claim 2, characterized in that, After removing the patterned mask layer, the method further includes: forming a gate structure on the substrate, wherein a portion of the active region below the gate structure is a channel region, wherein the anti-penetration region is located below the channel region, and the threshold voltage adjustment region is located on the surface of the channel region.

4. The preparation method according to claim 2, characterized in that, The implantation energy of the first ion implantation process is 100 keV-1000 keV, and the implantation energy of the third ion implantation process is 50 keV-500 keV.

5. The preparation method according to claim 1, characterized in that, The number of injection windows is multiple.

6. The preparation method according to claim 5, characterized in that, The plurality of injection windows are arranged at equal intervals in a first direction; or The multiple injection windows are arranged at non-equal intervals in the first direction.

7. The preparation method according to claim 6, characterized in that, The size of the injection window in the first direction is 0.01um-5um, and the size of the injection window in the second direction is 0.2um-5um. The first direction is parallel to the surface of the substrate, and the second direction is parallel to the thickness of the substrate.

8. The preparation method according to claim 1, characterized in that, The implanted ions in the second ion implantation process include at least one of carbon, nitrogen, phosphorus, boron, arsenic, or indium, and / or The second ion implantation process has an implantation energy of 10 keV-200 keV and an implantation angle of 0-15 degrees.

9. A semiconductor device, characterized in that, The semiconductor device is obtained by the fabrication method according to any one of claims 1 to 8.

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