Modulation and clamping based high-side switch current-mode gate drive circuit and method

Abstract

The application discloses a modulation and clamping based high-side switch current mode gate drive circuit and method, containing a charge pump module, a modulation stage, a clamping stage, a drive stage and a power tube M1, the input end of the charge pump module and the drain of the power tube M1 are connected with a power supply VS, the output end of the charge pump module is connected with the first input end of the modulation stage and generates a signal VCP, the second input end of the modulation stage is connected with a clock signal CLK, the output end of the modulation stage is connected with the first input end of the clamping stage and the first input end of the drive stage and generates a signal HVDD, the second input end of the clamping stage is connected with the output end of the drive stage and the gate of the power tube M1 and generates a signal GATE, the output end of the clamping stage is connected with the second input end of the drive stage, the source of the power tube M1 and one end of a load RL and generates an output signal OUT. The application improves system efficiency, reduces area overhead, improves control accuracy of the switching process and reduces system power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of gate drive circuit and method, in particular, a kind of high-side switch current mode gate drive circuit and method based on modulation and clamping, belong to the technical field of semiconductor integrated circuit. BACKGROUND

[0002] In automotive electronic systems, high-side switches as the core power switching devices connected between the positive and negative of the battery and the load, the design of its gate drive circuit directly determines the reliability, efficiency and anti-interference capability of the system. Unlike low-side switches with source ground reference, the source potential of high-side switches dynamically floats above the ground potential with the load state, resulting in a floating reference for the gate-source drive voltage VGS. This common-mode voltage offset phenomenon makes the traditional fixed ground reference-based drive architecture completely ineffective, and the gate control signal must be generated by relying on floating power supply or level shifting technology, which gives rise to the unique technical bottleneck of high-side drive circuit.

[0003] Current mainstream high-side drive schemes mainly fall into three categories, each with significant limitations:

[0004] Bootstrap capacitor scheme: a temporary floating power supply is established for the high-side drive stage by charging a capacitor during the low-side switch conduction period. Although simple in structure and low in cost, its duty cycle dependency characteristic prevents the system from supporting continuous conduction conditions, and it loses driving capability during the initial power-up phase due to the uncharged capacitor. More seriously, the high-voltage transient generated during the switching process of the power device will induce dV / dt noise coupling through the Miller capacitor, causing the bootstrap diode to reverse breakdown or the gate to be mistakenly triggered, significantly reducing the system robustness.

[0005] Charge pump scheme: an oscillator and capacitor network are used to generate a floating ground power supply, which can break through the duty cycle limit, but the switching loss and output voltage ripple introduced by high-frequency switching operation will degrade the integrity of the gate drive waveform. Excessive ripple voltage not only increases the on-resistance of the power device, but also generates a tail current during the off phase, exacerbating switching loss and thermal stress.

[0006] Isolated drive scheme: based on transformer coupling or optocoupler devices to achieve potential isolation, which can theoretically completely solve the common-mode interference problem. However, the leakage inductance effect of magnetic isolation transformer and the carrier lifetime decay of optocoupler devices will cause propagation delay dispersion, resulting in desynchronization of multi-channel drive signals, which induces bridge arm shoot-through risk in high-frequency switching applications. At the same time, the size and cost disadvantage of isolation elements makes it difficult to scale up in compact power modules.

[0007] Based on the high-side switching gate driving method, current driving methods are mainly divided into two core architectures: voltage-mode driving and current-mode driving. Traditional voltage-mode driving, as the mainstream solution, controls the device by applying a constant voltage. While simple in structure and low in cost, its switching rate depends on the external gate-source resistor, it is sensitive to the Miller effect, and has inherent bottlenecks in optimizing switching losses and suppressing electromagnetic interference (EMI). In contrast, current-mode driving, as a more advanced solution, has the core advantage of revolutionizing traditional control variables: it directly and precisely controls the voltage and current change rate of the device by injecting a constant current into the gate. This "current-centric" control mechanism brings several significant advantages:

[0008] 1. Precise switching behavior control: It can actively shape the optimal switching trajectory to minimize switching losses;

[0009] 2. Inherent Miller effect suppression capability: effectively shortens Miller plateau time, fundamentally reducing the risk of bridge arm crosstalk;

[0010] 3. Excellent EMI performance: Simplifies filter design by suppressing voltage overshoot and ringing;

[0011] 4. Enhanced system robustness: Its insensitivity to parasitic parameters improves drive stability.

[0012] Traditional voltage-type drive schemes based on charge pumps, such as Figure 2 As shown, the charge pump output serves as the driving power supply, directly controlling the gate of the power transistor through a current source and a switch. The magnitudes of the current source IB1 and resistor R1 directly determine the gate-source turn-on voltage of the power transistor, affecting its on-resistance. This scheme has the following drawbacks: its internal high-frequency oscillation significantly increases switching losses, reducing system efficiency; the generated high-amplitude output voltage ripple degrades the integrity of the gate drive waveform, causing gate oscillation of the power transistor and exacerbating switching losses; simultaneously, this scheme is highly sensitive to transient noise, and dV / dt noise can easily interfere with the charging process through parasitic parameter coupling, leading to unstable drive voltage and threatening system robustness; a large voltage difference exists between the charge pump output and the power transistor gate, therefore the current source IB1 and switch SW1 need to withstand high voltage, typically requiring high-voltage transistors, which occupies a large area. Summary of the Invention

[0013] The technical problem to be solved by the present invention is to provide a high-side switching current gate drive circuit based on modulation and clamping to achieve low power consumption and reduce chip area.

[0014] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0015] A kind of modulation and clamping-based high-side switch current mode gate drive circuit, including charge pump module, modulation stage, clamping stage, drive stage and power tube M1, the input end of charge pump module and the drain of power tube M1 are connected power VS, the output end of charge pump module is connected with the first input end of modulation stage and generates signal VCP, the second input end of modulation stage is connected clock signal CLK, the output end of modulation stage is connected with the first input end of clamping stage and the first input end of drive stage and generates signal HVDD, the second input end of clamping stage is connected with the output end of drive stage and the gate of power tube M1 and generates signal GATE, the output end of clamping stage is connected with the second input end of drive stage, the source of power tube M1 and the one end of load RL and generates output signal OUT, the other end of load RL is grounded.

[0016] Further, the modulation stage includes capacitor C1, PMOS tube PM1, PMOS tube PM2 and NMOS tube NM1, one end of capacitor C1 is connected clock signal CLK as the second input end of modulation stage, the other end of capacitor C1 is connected with the drain of PMOS tube PM1 and the source of PMOS tube PM2 and generates signal A1, the gate of PMOS tube PM1 is connected with the source of PMOS tube PM1 and the gate of NMOS tube NM1 and generates signal A2, the drain of NMOS tube NM1 is as the first input end of modulation stage and is connected signal VCP, the source of NMOS tube NM1 is connected with the drain of PMOS tube PM2 and as the output end of modulation stage and generates signal HVDD.

[0017] Further, the clamping stage includes PMOS tube PM3 and clamping module, the source of PMOS tube PM3 is as the input end of clamping stage and is connected signal HVDD, the gate of PMOS tube PM3 is connected signal GATE as the second input end of clamping stage, the drain of PMOS tube PM3 is connected with one end of clamping module, the other end of clamping module is connected output signal OUT as the output end of clamping stage.

[0018] Further, the drive stage includes current source IB1, current source IB2, control switch SW1 and control switch SW2, one end of current source IB1 is as the first input end of drive stage and is connected signal HVDD, the other end of current source IB1 is connected with one end of control switch SW1, the other end of control switch SW1 is connected with one end of control switch SW2 and as the output end of drive stage and generates signal GATE, the other end of control switch SW2 is connected with one end of current source IB2, the other end of current source IB2 is as the second input end of drive stage and is connected output signal OUT.

[0019] Further, the capacitor C1 adopts high-voltage-resistant capacitor.

[0020] Further, the NMOS tube NM1 adopts high-voltage NMOS tube.

[0021] Further, the current source IB1, the current source IB2, the control switch SW1 and the control switch SW2 adopt low-voltage devices.

[0022] A driving method of a high-side switch current-mode gate drive circuit based on modulation and clamping, comprising the following steps:

[0023] When initially enabled, the control switch SW1 is closed, and at the same time, the modulation stage is enabled to work, the amplitude of the clock signal CLK is VS-V1 to VS, the signal A1, the signal A2, the signal HVDD, the signal GATE and the output signal OUT are all started from 0V, and due to the fact that the voltage across the capacitor C1 cannot change abruptly, when the clock signal CLK jumps from low to high in the first clock cycle, the potential of the signal A1 changes from 0V to V1, and since the signal A2 is initially 0V, the PMOS tube PM1 in diode connection mode is turned on, the conduction voltage drop of the PMOS tube in diode connection mode is V2, the potential of the signal A2 changes to V1-V2, and then the NMOS tube NM1 is turned on, the conduction voltage drop of the NMOS tube NM1 is V3, and the HVDD voltage changes to V1-V2-V3, at this time, the signal GATE of the gate of the power tube M1 starts to be charged through the current source IB1 and the control switch SW1;

[0024] When the clock signal CLK jumps from high to low in the first clock cycle, theoretically, due to the fact that the voltage across the capacitor C1 cannot change abruptly, the signal A1 should decrease to 0V, but since the signal HVDD voltage is V1-V2-V3, when the potential of the signal A1 decreases to the conduction voltage drop of the PMOS tube PM2, the PMOS tube PM2 is turned on, the signal A1 is pulled to V1-2*V2-V3, and the PMOS tube PM1 will neither conduct from the signal A1 node to the signal A2 node nor conduct from the signal A2 node to the signal A1 node, and the first charging cycle of the modulation stage ends;

[0025] When the clock signal CLK jumps from low to high in the second cycle, the potential of the signal A1 jumps from V1-2*V2-V3 to 2*V1-2*V2-V3 and is transmitted to the signal A2 node, the potential of the signal A2 jumps from V1-V2 to 2*V1-3*V2-V3, the potential of the signal HVDD jumps from V1-V2-V3 to 2*V1-3*V2-2*V3, and the potential of the signal A1 jumps from 2*V1-4*V2-2*V3 when the clock signal jumps from high to low;

[0026] Through the above two clock cycles, the potentials of the signal A1, the signal A2 and the signal HVDD gradually increase, the signal A2 and the signal HVDD increase V1-2*V2-V3 every cycle, and after several clock cycles, the potential of the signal HVDD will eventually reach the potential of the signal VCP, the signal A1 becomes VCP-V2 during the low level of the clock signal CLK, and the signal A1 jumps to VCP-V2+V1 during the high level of the clock signal CLK, and the potential of the signal A2 becomes VCP-2*V2+V1, and the charging process is completed.

[0027] In the charging process, when GATE<HVDD, the PMOS transistor PM3 of the clamping stage is turned on, the clamping between the signal HVDD and the output signal OUT is triggered, and by setting the clamping voltage <low voltage device withstand voltage, the voltage difference between the signal HVDD and the output signal OUT is limited in the clamping value range during the whole opening charging process.

[0028] When the current source IB1 current set to the gate of the power transistor M1 is no longer needed, the output signal OUT voltage rises to the power supply VS potential, the voltage of the signal GATE continues to be pulled up to the voltage of the signal HVDD, the PMOS transistor PM2 is turned off, the clamping stage does not work, and the devices in the current source IB1 gradually work in the linear region, and finally the potential of the signal GATE is equal to the potential of the signal HVDD.

[0029] Compared with the prior art, the present application has the following advantages and effects:

[0030] 1. The present application provides a high-side switching current type gate drive circuit and method based on modulation and clamping, which significantly reduces switching loss and improves efficiency: due to the adoption of the modulation stage, compared with the traditional charge pump scheme, a modulation stage is introduced between the charge pump and the drive stage, which is equivalent to modulating the charge pump output VCP once, reducing the switching loss and improving the system efficiency.

[0031] 2. The present application saves chip area and reduces cost: due to the existence of the clamping stage, it is ensured that the drive stage (IB1, IB2, SW1, SW2) always works in a low voltage environment, so the drive stage can be realized by low voltage devices, which greatly saves the chip area compared with the traditional scheme which must use high voltage devices.

[0032] 3. The present application has high control precision and superior performance: the current type drive stage is adopted, the switching rate of the power transistor is directly and accurately controlled by controlling the current values of IB1 and IB2, which breaks away from the dependence on the external resistance sensitive to process, voltage and temperature (PVT) changes, and improves the controllability and consistency of the switching behavior.

[0033] 4. The present invention has low static power consumption: Under steady state, the GATE voltage is maintained by the charge pump voltage VCP, and the driver stage only needs to provide a holding current of nanoampere (nA) to microampere (uA). Compared with voltage-type drive, which needs to continuously consume current on the gate resistor (usually tens of uA), the static power consumption is reduced by more than an order of magnitude. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a high-side switching current-type gate drive circuit based on modulation and clamping according to the present invention.

[0035] Figure 2 This is a schematic diagram of a conventional charge pump-based gate drive circuit structure in the prior art. Detailed Implementation

[0036] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0037] like Figure 1 As shown, a high-side switching current-type gate drive circuit based on modulation and clamping according to the present invention includes a charge pump module, a modulation stage, a clamping stage, a drive stage, and a power transistor M1. The input terminal of the charge pump module and the drain of the power transistor M1 are connected to the power supply VS. The output terminal of the charge pump module is connected to the first input terminal of the modulation stage and generates a signal VCP. The second input terminal of the modulation stage is connected to the clock signal CLK. The output terminal of the modulation stage is connected to the first input terminal of the clamping stage and the first input terminal of the drive stage and generates a signal HVDD. The second input terminal of the clamping stage is connected to the output terminal of the drive stage and the gate of the power transistor M1 and generates a signal GATE. The output terminal of the clamping stage is connected to the second input terminal of the drive stage, the source of the power transistor M1, and one end of the load RL and generates an output signal OUT. The other end of the load RL is grounded.

[0038] The modulation stage comprises a capacitor C1, a PMOS transistor PM1, a PMOS transistor PM2 and an NMOS transistor NM1, one end of the capacitor C1 is connected to a clock signal CLK as a second input terminal of the modulation stage, the other end of the capacitor C1 is connected to the drain of the PMOS transistor PM1 and the source of the PMOS transistor PM2 and generates a signal A1, the gate of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM1 and the gate of the NMOS transistor NM1 and generates a signal A2, the drain of the NMOS transistor NM1 is an input terminal of the modulation stage and is connected to a signal VCP, the source of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM2 and is an output terminal of the modulation stage and generates a signal HVDD.

[0039] The clamping stage comprises a PMOS transistor PM3 and a clamping module, the source of the PMOS transistor PM3 is an input terminal of the clamping stage and is connected to a signal HVDD, the gate of the PMOS transistor PM3 is connected to a signal GATE as a second input terminal of the clamping stage, the drain of the PMOS transistor PM3 is connected to one end of the clamping module, the other end of the clamping module is an output terminal of the clamping stage and is connected to an output signal OUT.

[0040] The driving stage comprises a current source IB1, a current source IB2, a control switch SW1 and a control switch SW2, one end of the current source IB1 is a first input terminal of the driving stage and is connected to a signal HVDD, the other end of the current source IB1 is connected to one end of the control switch SW1, the other end of the control switch SW1 is connected to one end of the control switch SW2 and is an output terminal of the driving stage and generates a signal GATE, the other end of the control switch SW2 is connected to one end of the current source IB2, the other end of the current source IB2 is a second input terminal of the driving stage and is connected to an output signal OUT.

[0041] In the initial power-on stage, a large voltage difference exists between the two ends of the first capacitor C1, so the capacitor C1 is a high-voltage capacitor.

[0042] In the initial power-on stage, a large voltage difference exists between the source and the drain of the first NMOS transistor NM1, so the NMOS transistor NM1 is a high-voltage NMOS transistor. At the same time, the current of the driving power transistor M1 all comes from the charge pump and will pass through the NMOS transistor NM1, so the size of the NMOS transistor NM1 needs to be large enough to avoid affecting the overcurrent capability of the signal VCP to the signal HVDD.

[0043] The clamping voltage of the clamping module of the circuit should be set in a reasonable range to protect the driving stage circuit, for example, if the driving stage adopts a 6V voltage-resistant device, the clamping voltage of the clamping module should be ensured to be less than 6V in the full PVT range.

[0044] The current source IB1, the current source IB2, the control switch SW1 and the control switch SW2 can be implemented by low-voltage devices.

[0045] A driving method of a modulation and clamping based high-side switching current mode gate drive circuit, comprising the following steps:

[0046] At initial enablement, the control switch SW1 is closed, and the modulation stage is enabled to work, the amplitude of the clock signal CLK is VS-V1 to VS, the signal A1, the signal A2, the signal HVDD, the signal GATE and the output signal OUT are all started from 0V, and the voltage across the capacitor C1 cannot jump, so when the clock signal CLK jumps from low to high in the first clock cycle, the potential of the signal A1 changes from 0V to V1, the signal A2 is initially 0V, the PMOS PM1 in diode connection mode is turned on, the conduction voltage drop of the PMOS in diode connection mode is V2, the potential of the signal A2 changes to V1-V2, and the NMOS NM1 is turned on, the conduction voltage drop of the NMOS NM1 is V3, and the HVDD voltage changes to V1-V2-V3, at this time, the signal GATE of the gate of the power tube M1 starts to be charged through the current source IB1 and the control switch SW1.

[0047] When the clock signal CLK jumps from high to low in the first clock cycle, theoretically, the voltage across the capacitor C1 cannot jump, so the signal A1 should decrease to 0V, but since the signal HVDD voltage is V1-V2-V3, when the potential of the signal A1 decreases to the conduction voltage drop of the PMOS PM2, the PMOS PM2 is turned on, the signal A1 is pulled to V1-2*V2-V3, the PMOS PM1 cannot conduct from the signal A1 node to the signal A2 node, and cannot conduct from the signal A2 node to the signal A1 node, and the first charging cycle of the modulation stage ends.

[0048] When the clock signal CLK jumps from low to high in the second cycle, the potential of the signal A1 jumps to 2*V1-2*V2-V3 and is transmitted to the signal A2 node, the potential of the signal A2 jumps to 2*V1-3*V2-V3 from V1-V2, the potential of the signal HVDD jumps to 2*V1-3*V2-2*V3 from V1-V2-V3, and the potential of the signal A1 jumps to 2*V1-4*V2-2*V3 when the clock signal CLK jumps from high to low.

[0049] Through the above two clock cycles, the potentials of the signal A1, the signal A2 and the signal HVDD gradually increase, the signal A2 and the signal HVDD increase by V1-2*V2-V3 every cycle, and after several clock cycles, the potential of the signal HVDD will eventually reach the potential of the signal VCP, the potential of the signal A1 changes to VCP-V2 during the low level of the clock signal CLK, and the potential of the signal A1 jumps to VCP-V2+V1 during the high level of the clock signal CLK, the potential of the signal A2 changes to VCP-2*V2+V1, and the charging process is completed.

[0050] In the charging process, when GATE < HVDD, the PMOS transistor PM3 in the clamping stage is turned on, the clamping between the signal HVDD and the output signal OUT is triggered, and the voltage difference between the signal HVDD and the output signal OUT is limited in the clamping value range by setting the clamping voltage < low voltage device withstand voltage, so that the voltage difference between the signal HVDD and the output signal OUT is limited in the clamping value range during the whole opening charging process.

[0051] When the current source IB1 current set to the gate of the power transistor M1 is no longer needed, the output signal OUT voltage rises to the power supply VS potential, the voltage of the signal GATE continues to be gradually pulled up to the voltage of the signal HVDD, the PMOS transistor PM2 is turned off, the clamping stage does not work, and the devices in the current source IB1 gradually work in the linear region, and finally the potential of the signal GATE is equal to the potential of the signal HVDD.

[0052] The above method is further described below through specific examples.

[0053] Taking the charge pump module output signal VCP as an example with power supply VS+5V, during initial enable, control switch SW1 is closed, and the modulation stage is simultaneously enabled. The amplitude of the clock signal CLK is from VS-5V to VS. Signals A1, A2, HVDD, GATE, and output signal OUT all start from 0V. Since the voltage across capacitor C1 does not change abruptly, when the clock signal CLK jumps from low to high in the first clock cycle, the potential of signal A1 changes from 0V to 5V. Since signal A2 is initially 0V, the diode-connected PMOS transistor PM1 is turned on. Taking a PMOS transistor with a diode connection and a forward voltage drop of 0.7V as an example, when the potential of signal A2 becomes 4.3V, NMOS transistor NM1 turns on. Assuming the forward voltage drop of NMOS transistor NM1 is 1V, the voltage of signal HVDD becomes 3.3V. At this time, the gate signal GATE of power transistor M1 begins to charge through current source IB1 and control switch SW1. When the clock signal CLK jumps from high to low in the first clock cycle, theoretically, since the voltage across capacitor C1 cannot change abruptly, signal A1 should drop to 0V. However, since the voltage of signal HVDD is 3.3V... When the potential of signal A1 drops to the on-state voltage drop of PMOS transistor PM2, PMOS transistor PM2 turns on, and signal A1 is pulled to 2.6V. PMOS transistor PM1 will not turn on from A1 to A2, nor from A2 to A1, and the first charging cycle of the modulation stage ends. When the second cycle of clock signal CLK arrives from low to high, the potential of signal A1 jumps from 2.6V to 2.6V+5V, which is transmitted to the signal A2 node. The potential of signal A2 jumps from 4.3V to 6.9V, and the potential of signal HVDD changes from 3.3V to 5.9V. Signal A1 changes to 5.2V when it jumps from high to low during the clock cycle. Through the analysis of the above two clock cycles, the potentials of signals A1, A2, and HVDD gradually increase. After several clock cycles, the potential of signal HVDD will eventually reach the potential of signal VCP. Signal A1 changes to VCP-0.7V during the low level of clock signal CLK, and jumps to VCP-0.7V+5V during the high level of clock signal CLK. The potential of signal A2 changes to VCP-0.7V+5V-0.7V=VCP+3.6V, and the charging process is completed.

[0054] The above analysis process only analyzes the modulation stage independently, generally, the power tube parasitic capacitance is large, in the process of charging the power tube parasitic capacitance by the current source IB1 and the control switch SW1, if the voltage of the signal HVDD is not limited, the voltage of the signal HVDD will soon reach the potential of the signal VCP, at this time, the power tube gate has not been charged (for example, it may be charged to 1V only), a large voltage difference will appear between the signal HVDD and the signal GATE of the power tube M1 gate; therefore, the clamping stage is introduced, in the charging process, when GATE<HVDD, the PMOS tube PM3 of the clamping stage is turned on, the clamping between the signal HVDD and the output signal OUT is triggered (since the clamping circuit design is relatively simple, the clamping module is not the design emphasis of the present application, and therefore will not be described in detail), by setting the clamping voltage <low voltage device withstand voltage, the voltage difference between the signal HVDD and the output signal OUT is limited in the clamping value range in the whole opening charging process, and the current source and the switch of the driving stage are all implemented by using low voltage devices, so that there is no withstand voltage problem; when the current of the current source IB1 is no longer needed to be set for charging the power tube gate, the voltage of the output signal OUT is basically raised to the potential of the power supply VS, the voltage of the signal GATE is continuously pulled up to the voltage of the signal HVDD, the PMOS tube PM2 is turned off, the clamping stage does not work, the devices in the current source IB1 gradually work in the linear region, and finally the potential of the signal GATE is basically equal to the potential of the signal HVDD, which is basically equal to the potential of the signal VCP, and only the maintaining current of the order of nanoampere (nA) to microampere (uA) is needed between the signal HVDD and the signal GATE.

[0055] Through the above working principle analysis, the current type gate driving circuit provided by the present application introduces a simple modulation stage similar to an LDO between the charge pump module and the driving stage, compared with the traditional charge pump scheme, the switching loss caused by the high frequency oscillation of the charge pump can be reduced, and the system efficiency can be improved; by introducing the clamping stage automatically controlled by the power tube gate GATE, the voltage difference between HVDD and OUT is clamped, the dependence of the driving stage on high voltage devices is eliminated, and the area overhead is reduced; by adopting the current type driving scheme, the dependence on external gate-source resistance is eliminated, the charging and discharging only depends on the control of the charging and discharging circuit current sources IB1 and IB2, and the control accuracy of the switching process is improved; only the maintaining current of the order of nanoampere (nA) to microampere (uA) is needed between the signal HVDD and the signal GATE after charging, and the system power consumption is reduced.

[0056] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, as long as it does not deviate from the technical solution of the present application, and is within the spirit and principle of the present application, any simple modification, equivalent replacement and improvement of the above embodiments are still within the protection scope of the technical solution of the present application.

Claims

1. A high-side switching current-type gate drive circuit based on modulation and clamping, characterized in that: It includes a charge pump module, a modulation stage, a clamping stage, a driver stage, and a power transistor M1. The input terminal of the charge pump module and the drain of the power transistor M1 are connected to the power supply VS. The output terminal of the charge pump module is connected to the first input terminal of the modulation stage and generates the signal VCP. The second input terminal of the modulation stage is connected to the clock signal CLK. The output terminal of the modulation stage is connected to the first input terminal of the clamping stage and the first input terminal of the driver stage and generates the signal HVDD. The second input terminal of the clamping stage is connected to the output terminal of the driver stage and the gate of the power transistor M1 and generates the signal GATE. The output terminal of the clamping stage is connected to the second input terminal of the driver stage, the source of the power transistor M1, and one end of the load RL and generates the output signal OUT. The other end of the load RL is grounded. The modulation stage includes a capacitor C1, a PMOS transistor PM1, a PMOS transistor PM2, and an NMOS transistor NM1. One end of the capacitor C1 serves as the second input terminal of the modulation stage and is connected to the clock signal CLK. The other end of the capacitor C1 is connected to the drain of the PMOS transistor PM1 and the source of the PMOS transistor PM2 to generate signal A1. The gate of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM1 and the gate of the NMOS transistor NM1 to generate signal A2. The drain of the NMOS transistor NM1 serves as the first input terminal of the modulation stage and is connected to the signal VCP. The source of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM2 and serves as the output terminal of the modulation stage to generate signal HVDD.

2. The high-side switching current-type gate drive circuit based on modulation and clamping according to claim 1, characterized in that: The clamping stage includes a PMOS transistor PM3 and a clamping module. The source of the PMOS transistor PM3 serves as the input terminal of the clamping stage and is connected to the signal HVDD. The gate of the PMOS transistor PM3 serves as the second input terminal of the clamping stage and is connected to the signal GATE. The drain of the PMOS transistor PM3 is connected to one end of the clamping module, and the other end of the clamping module serves as the output terminal of the clamping stage and is connected to the output signal OUT.

3. The high-side switching current-type gate drive circuit based on modulation and clamping according to claim 1, characterized in that: The driver stage includes a current source IB1, a current source IB2, a control switch SW1, and a control switch SW2. One end of the current source IB1 serves as the first input terminal of the driver stage and is connected to the signal HVDD. The other end of the current source IB1 is connected to one end of the control switch SW1. The other end of the control switch SW1 is connected to one end of the control switch SW2 and serves as the output terminal of the driver stage, generating the signal GATE. The other end of the control switch SW2 is connected to one end of the current source IB2. The other end of the current source IB2 serves as the second input terminal of the driver stage and is connected to the output signal OUT.

4. The high-side switching current-type gate drive circuit based on modulation and clamping according to claim 1, characterized in that: The capacitor C1 is a high-voltage capacitor.

5. The high-side switching current-type gate drive circuit based on modulation and clamping according to claim 1, characterized in that: The NMOS transistor NM1 is a high-voltage NMOS transistor.

6. A high-side switching current-type gate drive circuit based on modulation and clamping according to claim 3, characterized in that: The current source IB1, current source IB2, control switch SW1 and control switch SW2 are low-voltage devices.

7. A driving method for a high-side switching current-type gate driving circuit based on modulation and clamping as described in any one of claims 1-6, characterized in that... Includes the following steps: At initial enabling, control switch SW1 is turned off, and at the same time, the modulation stage is enabled to work. The amplitude of clock signal CLK is from VS - V1 to VS. Signal A1, signal A2, signal HVDD, signal GATE, and output signal OUT all start from 0V. Since the voltage across capacitor C1 cannot change suddenly, when the clock signal CLK jumps from low to high in the first clock cycle, the potential of signal A1 changes from 0V to V1. Since signal A2 is initially 0V, PMOS transistor PM1 in diode connection mode conducts. The conduction voltage drop of PMOS transistor in diode connection mode is V2, and the potential of signal A2 becomes V1 - V2. Then NMOS transistor NM1 conducts. The conduction voltage drop of NMOS transistor NM1 is V3, and the HVDD voltage becomes V1 - V2 - V3. At this time, charging of signal GATE at the gate of power transistor M1 starts through current source IB1 and control switch SW1; When the clock signal CLK jumps from high to low in the first clock cycle, theoretically, since the voltage across capacitor C1 cannot change suddenly, signal A1 should drop to 0V. However, since the HVDD voltage is V1 - V2 - V3, when the potential of signal A1 drops to the conduction voltage drop of PMOS transistor PM2, PMOS transistor PM2 conducts, and signal A1 is pulled to V1 - 2*V2 - V3. PMOS transistor PM1 neither conducts from the signal A1 node to the signal A2 node nor from the signal A2 node to the signal A1 node, and the first charging cycle of the modulation stage ends; When the clock signal CLK jumps from low to high in the second cycle, the potential of signal A1 jumps from V1 - 2*V2 - V3 to 2*V1 - 2*V2 - V3 and is transmitted to the signal A2 node. The potential of signal A2 jumps from V1 - V2 to 2*V1 - 3*V2 - V3. The potential of signal HVDD changes from V1 - V2 - V3 to 2*V1 - 3*V2 - 2*V3. Signal A1 becomes 2*V1 - 4*V2 - 2*V3 when the clock cycle jumps from high to low; Through the above two clock cycles, the potentials of signal A1, signal A2, and signal HVDD gradually increase. The potential of signal A2 and signal HVDD increases by V1 - 2*V2 - V3 per cycle. After several clock cycles, the potential of signal HVDD will finally reach the potential of signal VCP. Signal A1 becomes VCP - V2 during the low level of the clock signal CLK and jumps to VCP - V2 + V1 during the high level of the clock signal CLK. The potential of signal A2 becomes VCP - 2*V2 + V1, and the charging process is completed; During the charging process, when GATE < HVDD, clamping stage PMOS transistor PM3 conducts, and clamping between signal HVDD and output signal OUT is triggered. By setting the clamping voltage < the breakdown voltage of the low - voltage device, the voltage difference between signal HVDD and output signal OUT is limited within the clamping value range during the entire startup charging process; When the gate of power transistor M1 is no longer charged to the point where the current source IB1 is no longer needed, the output signal OUT voltage rises to the power supply VS potential, the signal GATE voltage continues to be gradually pulled up to the signal HVDD voltage, PMOS transistor PM2 turns off, the clamping stage does not work, the devices in current source IB1 gradually work in the linear region, and finally the potential of signal GATE is equal to the potential of signal HVDD.

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