Electronic device

Abstract

An electronic device is provided. The electronic device includes an electronic component and a first set of conductive vias. The electronic component has a first set of terminals disposed on a lower surface of the electronic component and a second set of terminals disposed on an upper surface of the electronic component. The first set of terminals includes a first terminal and a second terminal disposed at different heights. The first set of conductive vias is electrically connected to the first set of terminals.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly, to an electronic device with integrated electronic components configured to receive power via a back-side surface. Background Technology

[0002] The power delivery efficiency of electronic components can be significantly affected by disconnections between the electronic components and the terminals of the circuit structure, which in turn affects the reliability of electronic devices. Therefore, developing new technologies or improving existing technologies is important to enhance the performance of electronic devices. Summary of the Invention

[0003] In some embodiments, the electronic device includes an electronic component and a first set of conductive vias. The electronic component has a first set of terminals disposed on a lower surface of the electronic component and a second set of terminals disposed on an upper surface of the electronic component. The first set of terminals includes a first terminal and a second terminal disposed at different heights. The first set of conductive vias is electrically connected to the first set of terminals.

[0004] In some embodiments, the electronic device includes an electronic component and a first set of conductive vias. The electronic component has a lower surface and a upper surface. The first set of conductive vias is disposed below the lower surface of the electronic component and electrically connected to the electronic component. The first set of conductive vias has different lengths.

[0005] In some embodiments, the electronic device includes a lower circuit structure, an electronic component, and a first interconnect. The lower circuit structure has a generally flat surface. The electronic component is disposed above the generally flat surface of the lower circuit structure. The electronic component has a lower curved surface facing the generally flat surface. The first interconnect is disposed between the generally flat surface of the lower circuit structure and the lower curved surface of the electronic component. Attached Figure Description

[0006] Various aspects of some embodiments of this disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A A cross-sectional view showing an example of an electronic device according to some embodiments of the present disclosure.

[0008] Figure 1B Some embodiments according to this disclosure are shown. Figure 1A A magnified view of a portion of the electronic components.

[0009] Figure 1C Some embodiments according to this disclosure are shown. Figure 1A A partially enlarged view of the electronic device.

[0010] Figure 2 A cross-sectional view showing an example of an electronic device according to some embodiments of the present disclosure.

[0011] Figure 3 A cross-sectional view showing an example of an electronic device according to some embodiments of the present disclosure.

[0012] Figure 4 A perspective view showing an example of an electronic device according to some embodiments of the present disclosure.

[0013] Figure 5 A cross-sectional view showing an example of an electronic device according to some embodiments of the present disclosure.

[0014] Figure 6 A cross-sectional view showing an example of an electronic device according to some embodiments of the present disclosure.

[0015] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G , Figure 7H , Figure 7I , Figure 7J , Figure 7K and Figure 7L Examples of methods for manufacturing electronic devices according to some embodiments of the present disclosure are shown at various stages. Detailed Implementation

[0016] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed on or over a second feature may include instances where the first and second features are formed or disposed in direct contact, and embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Figure 1AA cross-sectional view of an electronic device 1a according to some embodiments of the present disclosure is shown. In some embodiments, the electronic device 1a may include a circuit structure 10, a dielectric structure 20, electronic components 30, interconnects 41, 42, 50, and a circuit structure 60.

[0019] The circuit structure 10 (or lower circuit structure) may include a substrate 11, a conductive layer 12, a conductive layer 13, an interconnect 14, a dielectric layer 15, and an interconnect 16. The circuit structure 10 may have a surface 10s1 (or a lower surface) and a surface 10s2 (or an upper surface) opposite to the surface 10s1. In some embodiments, the surface 10s2 may be a generally flat surface.

[0020] Substrate 11 may be a core substrate. The core substrate may comprise prepreg (PP), Ajinomoto build-up film (ABF), or other suitable materials. In some embodiments, the resin material used in the core substrate may be a fiber-reinforced resin to strengthen the core substrate, and the reinforcing fibers may be, but are not limited to, glass fibers or Kevlar fibers (aramid fibers). The lower surface of substrate 11 may be defined as surface 10s1. The upper surface of substrate 11 may be defined as surface 10s2.

[0021] Conductive layer 12 may be disposed below, within, and / or adjacent to surface 10s1 of circuit structure 10. Conductive layer 12 may be electrically connected to an external device (not shown), such as a printed circuit board (PCB), a power conditioning component (e.g., a power management integrated circuit), or other suitable component. Conductive layer 13 may be disposed above, within, and / or adjacent to surface 10s2 of circuit structure 10. Interconnect 14 may be disposed within substrate 11. Interconnect 14 may electrically connect conductive layer 12 to conductive layer 13. Interconnect 14 may include conductive vias tapering toward surface 10s2 of circuit structure 10. Interconnect 16 may be electrically connected to interconnect 50. Interconnect 16 may include conductive vias tapering toward surface 10s2 of circuit structure 10. Each of conductive layer 12, conductive layer 13, and interconnects 14 and 16 may include a seed layer and conductive material on the seed layer. The seed layer may comprise a metal, metal oxide, metal nitride, metal carbide, metal alloy, or a suitable material. For example, the seed layer may comprise tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, tungsten nitride, etc. The conductive material may comprise copper, aluminum, tungsten, chromium, gold, silver, other suitable materials, or combinations thereof.

[0022] The dielectric layer 15 may be disposed below the surface 10s1 of the circuit structure 10. The dielectric layer 15 may be patterned to expose a portion of the conductive layer 12. The dielectric layer 15 may contain a solder resist, such as a polymeric material containing bismaleimide triazine, polypropylene, or epoxy-based materials.

[0023] In some embodiments, the dielectric structure 20 (or carrier) may be disposed on or above the surface 10s2 of the circuit structure 10. The dielectric structure 20 may be configured to encapsulate the electronic component 30, interconnect 41, interconnect 42, and interconnect 50. The dielectric structure 20 may have a surface 20s1 (or lower surface) that interfaces with the circuit structure 10 and a surface 20s2 (or upper surface) that is opposite to the surface 20s1. In some embodiments, the dielectric structure 20 may include encapsulants 21 and 22.

[0024] In some embodiments, the encapsulation 21 (or bottom encapsulation) may be disposed on the surface 10s2 of the circuit structure 10. In some embodiments, the encapsulation 21 may be in contact with the substrate 11. The encapsulation 21 may comprise an insulating or dielectric material. In some embodiments, the encapsulation 21 may be made of a molding material, which may comprise, for example, a phenolic resin, an epoxy resin, a silicone resin, or other suitable material. In some embodiments, the encapsulation 21 may comprise, for example, organic materials (e.g., molding compounds, bismaleimide triazine, polyimide, polybenzoxazole, polypropylene, or epoxy materials), inorganic materials (e.g., silicon, glass, ceramic, or quartz), liquid and / or dry film materials, or combinations thereof. The lower surface of the encapsulation 21 may be defined as the surface 20s1 of the dielectric structure 20.

[0025] In some embodiments, encapsulation 22 (or top encapsulation) may be disposed on or above encapsulation 21. Encapsulation 22 may be in contact with encapsulation 21. Encapsulations 21 and 22 may have an interface 20u therebetween. In some embodiments, the material of encapsulation 22 may be the same as or similar to the material of encapsulation 21. In some embodiments, the thickness T2 of encapsulation 22 may be greater than the thickness T1 of encapsulation 21. The upper surface of encapsulation 22 may be defined as surface 20s2 of dielectric structure 20.

[0026] In some embodiments, the electronic component 30 may be disposed on or above the surface 10s2 of the circuit structure 10. In some embodiments, a portion of the electronic component 30 may be disposed within an enclosure 21. In some embodiments, a portion of the electronic component 30 may be disposed within an enclosure 22. The electronic component 30 may have a surface 30s1 (or a lower surface), a surface 30s2 (or an upper surface) opposite to surface 30s1, and a surface 30s3 (or a lateral surface or side) extending between surfaces 30s1 and 30s2. In some embodiments, the surface area of ​​the electronic component 30 (e.g., the surface area of ​​surface 30s2) may be equal to or less than 200 mm². 2 For example, 150mm 2 100mm 2 50mm 2 10mm 2 Or smaller. In some embodiments, the electronic component 30 may have a thickness equal to or less than 50 μm, such as 50 μm, 40 μm, 30 μm, 20 μm, 15 μm, 10 μm or smaller. In some embodiments, the electronic component 30 may have a terminal 33 disposed below the surface 30s1 and a terminal 34 disposed above the surface 30s2. Due to the relatively small surface area, thickness and the presence of terminals 33 and 34 on two opposite sides, the profile of the electronic component 30 may become curved or twisted due to warpage.

[0027] In some embodiments, the surface 30s1 of the electronic component 30 may be a curved surface due to warping. In some embodiments, the surface 30s1 of the electronic component 30 may protrude toward the circuit structure 10. For example, the central region of the surface 30s1 has a lower height than the peripheral region of the surface 30s1, which is closer to the surface 30s3, relative to the surface 10s2 of the circuit structure 10. In some embodiments, the surface 30s2 of the electronic component 30 may be a curved surface due to warping. In some embodiments, the surface 30s2 of the electronic component 30 may be recessed. For example, the central region of the surface 30s2 has a lower height than the peripheral region of the surface 30s2, relative to the surface 10s2 of the circuit structure 10 (or relative to the circuit structure 60).

[0028] Please refer to Figure 1B This shows an enlarged view of the electronic component 30. In some embodiments, the electronic component 30 may include a passive component 31 and an active component 32 above the passive component 31. It should be noted that, for the sake of brevity, Figure 1B The electronic component 30 shown has generally flat surfaces 30s1 and 30s2, and this disclosure is not intended to be limiting.

[0029] In some embodiments, the passive component 31 (or carrier) may be configured to consume, store, and transmit energy. In some embodiments, the passive component 31 may be configured to stabilize, regulate, receive, and / or transmit power. In some embodiments, the passive component 31 may comprise a capacitor, an inductor, a resistor, a filter, or a combination of such components. The capacitor may comprise a deep trench capacitor (DTC), a multi-layer ceramic capacitor (MLCC), or other capacitors. The passive component 31 may comprise a substrate 311, a passive element region 312, and a conductive structure 313.

[0030] Substrate 311 may include a semiconductor substrate. Substrate 311 may include silicon or germanium in a single-crystal, polycrystalline, or amorphous form. The lower surface of substrate 311 may serve as surface 30s1 of electronic component 30, and may also be defined as the back surface of electronic component 30.

[0031] Passive component region 312 may be embedded in substrate 311. Passive component region 312 may be mated to active component 32. In some embodiments, passive component region 312 may define one or more capacitors and include a metal-insulator-metal (MIM) structure or other suitable structure.

[0032] The conductive structure 313 may extend between the surface 30s1 and the passive component region 312. The conductive structure 313 may penetrate a portion of the substrate 311. The conductive structure 313 may be electrically connected to the passive component region 312. In some embodiments, the conductive structure 313 may include a through-silicon via (TSV). The conductive structure 313 may be configured to receive and / or transmit power. The conductive structure 313 may comprise copper, aluminum, gold, silver, tungsten, nickel, combinations thereof, or other suitable materials.

[0033] In some embodiments, the active component 32 may be disposed on or above the passive component 31. The active component 32 may be configured to receive power. The active component 32 may be configured to generate and / or process signals. The active component 32 may include semiconductor dies or chips, such as logic dies (e.g., application processor (AP), system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), radio frequency (RF) dies, sensor dies, micro-electro-mechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), or other active components. The upper surface of the active component 32 (e.g., surface 32s2) may serve as surface 30s2 of the electronic component 30, and may also be defined as an active surface. As used herein, the term "active surface" may refer to a surface through which signals (e.g., I / O signals) pass. In some embodiments, the active component 32 may have an integrated circuit (IC) layer 321, a redistribution structure 322, and a redistribution structure 323.

[0034] IC layer 321 may include one or more ICs formed in a substrate such as a semiconductor substrate. IC layer 321 may be configured to receive power (or power signal) and generate signals (or non-power signal), such as input / output (I / O) signals or other signals.

[0035] A redistribution structure 322 (or power delivery network (PDN)) may be disposed below the IC layer 321. In some embodiments, the redistribution structure 322 may be configured to receive power and / or transmit power to the IC layer 321, the power being direct current (DC) or composed thereof. The redistribution structure 322 may include one or more conductive traces and conductive vias embedded within one or more dielectric layers.

[0036] The redistribution structure 323 may be disposed above the IC layer 321. The redistribution structure 323 may be configured to receive and / or transmit signals (e.g., I / O signals), which may include or be composed of alternating current (AC). In some embodiments, the redistribution structure 323 may include one or more conductive traces and conductive vias embedded in one or more dielectric layers.

[0037] Please return to the previous page. Figure 1A A portion of the passive component 31 may be disposed within the encapsulation 21. In some embodiments, a portion of the encapsulation 21 may be disposed within the encapsulation 22. In some embodiments, the active component 32 may be disposed within the encapsulation 22. In some embodiments, the active component 32 may be spaced apart from the encapsulation 21. In some embodiments, the passive component 31 may have a surface 31s1 (or a lower surface), a surface 31s2 (or an upper surface), and a surface 31s3 (or a lateral surface) extending between surfaces 31s1 and 31s2. In some embodiments, a portion of surface 31s1 may contact the encapsulation 21. In some embodiments, a portion of surface 31s1 may contact the encapsulation 22. In some embodiments, surface 31s3 may contact the encapsulation 22. In some embodiments, surface 31s3 may be spaced apart from the encapsulation 21.

[0038] In some embodiments, the active component 32 may have a surface 32s1 (or a lower surface), a surface 32s2 (or an upper surface), and a surface 32s3 (or a lateral surface) extending between surfaces 32s1 and 32s2. In some embodiments, surface 32s3 may contact the encapsulation 22. In some embodiments, surface 32s3 may be spaced apart from the encapsulation 22. In some embodiments, the interface between surface 31s2 and surface 32s1 may be located within the encapsulation 22.

[0039] Interconnector 41 (or a first set of interconnectors) may be disposed on or above surface 10s2 of circuit structure 10. Interconnector 41 may be electrically connected to circuit structure 10. In some embodiments, interconnector 41 may be electrically connected to electronic component 30 via terminal 33. In some embodiments, interconnector 41 may be embedded within encapsulation 21. Interconnector 41 may include a seed layer (e.g., titanium nitride) and a conductive material (e.g., copper) on the seed layer. Interconnector 41 may include conductive vias tapering toward electronic component 30.

[0040] Interconnector 42 (or a second set of interconnectors) may be disposed on or below circuit structure 60. Interconnector 42 may be electrically connected to circuit structure 60. In some embodiments, interconnector 42 may be electrically connected to electronic component 30 via terminal 34. In some embodiments, interconnector 42 may be embedded within encapsulation 22. Interconnector 42 may include a seed layer (e.g., titanium nitride) and a conductive material (e.g., copper) on the seed layer. Interconnector 42 may include conductive vias tapering toward electronic component 30.

[0041] Interconnector 50 may be disposed on or above surface 10s2 of circuit structure 10. In some embodiments, interconnector 50 may be disposed between circuit structure 10 and circuit structure 60. Interconnector 50 may be electrically connected to circuit structure 10. Interconnector 50 may be electrically connected to circuit structure 60. In some embodiments, interconnector 50 may include conductive pillars or conductive vias tapering toward circuit structure 10. In some embodiments, interconnector 50 may penetrate encapsulation 21. In some embodiments, interconnector 50 may penetrate encapsulation 22. In some embodiments, the dimensions (e.g., diameter or width) of interconnector 50 may be larger than the dimensions of interconnector 41 (or interconnector 42). Interconnector 50 may include a seed layer (e.g., titanium nitride) and a conductive material (e.g., copper) on the seed layer.

[0042] In some embodiments, the circuit structure 60 may be disposed on or above the encapsulation 22. In some embodiments, the circuit structure 60 may be electrically connected to interconnects. In some embodiments, the circuit structure 60 may be electrically connected to the electronic component 30 via terminals 34. The circuit structure 60 may include a substrate 61, a conductive layer 62, a conductive layer 63, interconnects 64, and a dielectric layer 65. The circuit structure 60 may have a surface 60s1 (or a lower surface) and a surface 60s2 (or an upper surface) opposite to surface 60s1. The substrate 61 may be a core substrate. The core substrate may contain a prepreg, ABF, or other suitable material. In some embodiments, the resin material used in the core substrate may be a fiber-reinforced resin to reinforce the core substrate, and the reinforcing fibers may be, but are not limited to, glass fibers or Kevlar fibers (aramid fibers). The lower surface of the substrate 61 may be defined as surface 60s1. The upper surface of the substrate 61 may be defined as surface 60s2.

[0043] Conductive layer 62 may be disposed below, within, and / or adjacent to surface 60s1 of circuit structure 60. Conductive layer 63 may be disposed above, within, and / or adjacent to surface 60s2 of circuit structure 60. Conductive layer 63 may be electrically connected to an external device (not shown), such as a printed circuit board or other suitable component. Interconnect 64 may be disposed within substrate 61. Interconnect 64 may electrically connect conductive layer 62 to conductive layer 63. Interconnect 64 may include conductive vias that taper toward surface 60s1 of circuit structure 60. Interconnect 66 may be electrically connected to interconnect 50. Interconnect 66 may include conductive vias that taper toward surface 60s1 of circuit structure 60. Each of conductive layer 62, conductive layer 63, and interconnects 64 and 66 may include a seed layer and conductive material on the seed layer. The seed layer may comprise a metal, metal oxide, metal nitride, metal carbide, metal alloy, or a suitable material. For example, the seed layer may comprise tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, tungsten nitride, etc. The conductive material may comprise copper, aluminum, tungsten, chromium, gold, silver, other suitable materials, or combinations thereof.

[0044] A dielectric layer 65 may be disposed above a surface 60s2 of the circuit structure 60. The dielectric layer 65 may be patterned to expose a portion of the conductive layer 63. The dielectric layer 65 may define an opening for exposing a portion of the conductive layer 63. The dielectric layer 65 may contain a solder resist, such as a polymeric material containing bismaleimide triazine, polypropylene, or an epoxy group material.

[0045] Please refer to Figure 1C This diagram shows a partially enlarged view of the electronic device 1a. In some embodiments, each of the terminals 33 (or the first set of terminals) may be located at a different height relative to the surface 10s2 of the circuit structure 10. The terminals 33 may include a terminal 33a located in the central region of the surface 30s1, and a terminal 33b located in the peripheral region of the surface 30s1 closer to the surface 30s3. In some embodiments, the terminal 33a may be located at a lower height than the terminal 33b relative to the surface 10s2 of the circuit structure 10. In some embodiments, the top of the terminal 33a that contacts the passive component 31 may be located at a lower height than the top of the terminal 33b relative to the surface 10s2 of the circuit structure 10. In some embodiments, the bottom of the terminal 33a that contacts the interconnect 41 may be located at a lower height than the bottom of the terminal 33b relative to the surface 10s2 of the circuit structure 10.

[0046] Interconnector 41 may include interconnector 41a connected to terminal 33a and interconnector 41b connected to terminal 33b. In some embodiments, the top 41at (e.g., top surface or tip) of interconnector 41a, which contacts terminal 33, may be located at a lower height than the top 41bt (e.g., top surface or tip) of interconnector 41b relative to the surface 10s2 of circuit structure 10. In some embodiments, relative to the surface 10s2 of circuit structure 10, the top 41at (e.g., top surface or tip) of interconnector 41a, which contacts terminal 33, may be located at a lower height than the top 41bt (e.g., top surface or tip) of interconnector 41b. Figure 1A The bottom (e.g., bottom surface or bottom end) of the contacting interconnect 41a (shown in the diagram) may be located at the same height as the bottom (e.g., bottom surface or bottom end) of the interconnect 41b. In some embodiments, each of the interconnects 41 may have a different length, defined as the distance between the bottom of the terminal 33 and the surface 10s2 of the circuit structure 10. In some embodiments, the length L1 of the interconnect 41a may be less than the length L2 of the interconnect 41b. In some embodiments, the top 41at of the interconnect 41a may be a generally planar surface or a sloped surface. In some embodiments, the top 41bt of the interconnect 41b may be a sloped surface. In some embodiments, the slope of the top 41bt, i.e., the angle defined by the top 41bt and the direction parallel to the axis L, may be greater than the slope of the top 41at, i.e., the angle defined by the top 41at and the direction parallel to the axis L.

[0047] In some embodiments, each of the terminals 34 (or the second set of terminals) may be located at a different height. Terminal 34 may include a terminal 34a located in the central region of surface 30s2, and a terminal 34b located in the peripheral region of surface 30s2 closer to surface 30s3. In some embodiments, terminal 34a may be located at a lower height than terminal 34b relative to surface 10s2 of circuit structure 10 (or relative to circuit structure 60). In some embodiments, the top of terminal 34a contacting interconnect 42 may be located at a lower height than the top of terminal 34b relative to surface 10s2 of circuit structure 10. In some embodiments, the bottom of terminal 34a contacting active component 32 may be located at a lower height than the bottom of terminal 34b relative to surface 10s2 of circuit structure 10.

[0048] Interconnector 42 may include interconnector 42a connected to terminal 34a and interconnector 42b connected to terminal 34b. In some embodiments, the bottom 42at (e.g., bottom surface or bottom end) of interconnector 42a contacting terminal 34 may be located at a lower height than the bottom 42bt (e.g., bottom surface or bottom end) of interconnector 42b relative to the surface 10s2 of circuit structure 10. In some embodiments, relative to the surface 10s2 of circuit structure 10, and the bottom 42bt (e.g., bottom surface or bottom end) of interconnector 42b contacting terminal 34b may be located at a lower height than the bottom 42bt (e.g., bottom surface or bottom end) of interconnector 42b contacting terminal 34b. Figure 1AThe top (e.g., top surface or tip) of the contacting interconnect 42a (shown in the diagram) may be located at the same height as the top (e.g., top surface or tip) of the interconnect 42b. In some embodiments, each of the interconnects 42 may have a different length, defined as the distance between the top of the terminal 34 and the surface 60s1 of the circuit structure 60. In some embodiments, the length L3 of the interconnect 42a may be greater than the length L4 of the interconnect 42b. In some embodiments, the bottom 42at of the interconnect 42a may be a generally planar surface or a sloped surface. In some embodiments, the bottom 42bt of the interconnect 42b may be a sloped surface. In some embodiments, the slope of the bottom 42bt, i.e., the angle defined by the bottom 42bt and the direction parallel to the axis L, may be greater than the slope of the bottom 42at, i.e., the angle defined by the bottom 42at and the direction parallel to the axis L.

[0049] In some embodiments, the sum of the lengths of one of the interconnects 41 and the corresponding length of the interconnect 42 is substantially constant or uniform. For example, the sum of the length L1 of interconnect 41a and the length L3 of interconnect 42a that vertically overlaps with interconnect 41a is the same as the sum of the length L2 of interconnect 41b and the length L4 of interconnect 42b that vertically overlaps with interconnect 41b.

[0050] In some embodiments, the arrangement of interconnects 41 and 42 relative to the electronic component 30 is asymmetrical. In some embodiments, the arrangement of interconnects 41 and 42 is asymmetrical with respect to an axis L passing through the center (or center of gravity) of the electronic component 30. The axis L may be substantially parallel to the surface 10s2 of the circuit structure 10. For example, the distance between interconnect 41b and axis L is different from the distance between interconnect 42b and axis L. In some embodiments, the arrangement of terminals 33 and 34 is asymmetrical with respect to the axis L passing through the center (or center of gravity) of the electronic component 30. For example, the distance between terminal 34b and axis L is different from the distance between terminal 33b and axis L.

[0051] In this embodiment, electronic component 30 is embedded within encapsulations 21 and 22, which helps mitigate warpage associated with electronic component 30. In this embodiment, interconnects 41 and 42 are formed using a via-last technique, which can create trenches or openings of varying depths based on the height of terminals 33 and 34. In a comparative example, disconnection can occur at the interface between the terminals and interconnects due to warpage of the electronic component. In contrast, in this embodiment, the terminals (e.g., terminal 33) can be connected to the interconnects (e.g., interconnect 41) with greater precision and accuracy. Therefore, the reliability of electronic device 1a can be enhanced.

[0052] Figure 2 A cross-sectional view of an example of an electronic device 1b according to some embodiments of the present disclosure is shown. Electronic device 1b is similar to electronic device 1a, and the differences therebetween are described below.

[0053] In some embodiments, a portion of surface 31s3 may contact encapsulation 21. Surface 31s3 may partially contact encapsulation 22. In some embodiments, the edges of surfaces 31s1 and 31s3 may contact encapsulation 21. In some embodiments, surface 31s3 may contact or intersect with the interface 20u of encapsulations 21 and 22.

[0054] Figure 3 A cross-sectional view of an example of an electronic device 1c according to some embodiments of the present disclosure is shown. Electronic device 1c is similar to electronic device 1a, and the differences therebetween are described below.

[0055] Electronic component 30 may include a surface 30s4 opposite to surface 30s3. Passive component 31 may include a surface 31s4 opposite to surface 31s3. In some embodiments, the height difference D1 between the bottommost point BP1 of surface 31s1 and the edge between surface 31s1 and surface 31s3 may be different from the height difference D2 between the bottommost point BP1 of surface 31s1 and the edge between surface 31s1 and surface 31s4. In some embodiments, the height difference D3 between the surface 10s2 of circuit structure 10 and the edge between surface 31s1 and surface 31s3 of passive component 31 may be different from the height difference D4 between the surface 10s2 of circuit structure 10 and the edge between surface 31s1 and surface 31s4 of passive component 31. In some embodiments, the height difference D3 between the surface 10s2 of circuit structure 10 and the edge between surface 30s1 and surface 30s3 of electronic component 30 may be different from the height difference D4 between the surface 10s2 of circuit structure 10 and the edge between surface 30s1 and surface 30s4 of electronic component 30. In some embodiments, a portion of the interface 20u of the encapsulations 21 and 22 may be below the surface 30s1. In some embodiments, the interface 20u of the encapsulations 21 and 22 may contact or intersect with the surface 30s4.

[0056] Figure 4 A perspective view of an example of an electronic device 1d according to some embodiments of the present disclosure is shown. Electronic device 1d is similar to electronic device 1a, and the differences therebetween are described below.

[0057] Electronic component 30 may be included in surface 30s5 extending between surface 30s3 and surface 30s4. Surface 30s3 may be adjacent to surface 30s5. In some embodiments, the warping (or twisting) of surface 30s3 may be different from the warping of surface 30s5. In some embodiments, the height difference D5 between the lowest point BP2 of the edge between surface 10s2 of circuit structure 10 and surface 30s3 of electronic component 30 and surface 30s1 may be different from the height difference D6 between the lowest point BP3 of the edge between surface 10s2 of circuit structure 10 and surface 30s5 of electronic component 30 and surface 30s1.

[0058] Figure 5 A cross-sectional view of an example of an electronic device 1e according to some embodiments of the present disclosure is shown. Electronic device 1e is similar to electronic device 1a, and the differences therebetween are described below.

[0059] In some embodiments, the encapsulation 21 may include a protrusion 21p1. In some embodiments, the protrusion 21p1 may protrude from the upper surface (not labeled) of the encapsulation 21. In some embodiments, the protrusion 21p1 may connect the electronic component 30 and the upper surface of the encapsulation 21. In some embodiments, the protrusion 21p1 may contact the surface 30s1 or surface 31s3 of the electronic component 30. In some embodiments, the height of the protrusion 21p1 may be greater than the height of a portion of the lower surface of the encapsulation 22 relative to the surface 10s2 of the circuit structure 10.

[0060] Figure 6 A cross-sectional view of an example of an electronic device 1f according to some embodiments of the present disclosure is shown. Electronic device 1f is similar to electronic device 1e, and the differences therebetween are described below.

[0061] In some embodiments, the encapsulation 21 may include a protrusion 21p2. In some embodiments, the protrusion 21p2 may protrude from the upper surface of the encapsulation 21. The protrusion 21p2 may have a curved profile. In some embodiments, the protrusion 21p2 may connect the surface 30s3 of the electronic component 30 and the upper surface of the encapsulation 21. In some embodiments, the protrusion 21p2 may contact the surface 30s3 of the electronic component 30. In some embodiments, the protrusion 21p2 may contact the surface 31s3 of the passive component 31. In some embodiments, the height of the protrusion 21p2 may be greater than the height of a portion of the lower surface of the encapsulation 22 relative to the surface 10s2 of the circuit structure 10.

[0062] Figures 7A to 7L Examples of methods for manufacturing electronic devices according to some embodiments of the present disclosure are shown at various stages.

[0063] See Figure 7AAn electronic component 30 may be provided. The electronic component 30 may be embedded within encapsulations 21 and 22. A conductive material 71 may be formed below the lower surface of encapsulation 21. A conductive material 72 may be formed above the upper surface of encapsulation 22.

[0064] See Figure 7B Conductive material 71 may be patterned to expose the lower surface of encapsulation 21. Conductive material 72 may be patterned to expose the upper surface of encapsulation 22.

[0065] See Figure 7C Encapsulation 21 can be patterned, for example, by laser drilling. Encapsulation 22 can be patterned, for example, by laser drilling. An opening O1 can be formed to expose terminal 33. Opening O1 can have different depths. An opening O2 can be formed to expose terminal 34. Opening O2 can have different depths. An opening O3 can be formed to expose conductive material 71. Opening O3 can be recessed from conductive material 72.

[0066] See Figure 7D Conductive material 73 may be formed above conductive material 71. Conductive material 73 may be formed within opening O1. Conductive material 73 may be formed using electroless plating or other suitable techniques. Conductive material 74 may be formed above conductive material 72. Conductive material 74 may be formed within opening O2. Conductive material 74 may be formed within opening O3. Conductive material 74 may be formed using electroless plating or other suitable techniques.

[0067] See Figure 7E Conductive material 75 may be formed below conductive material 73. Conductive material 75 may be formed within opening O1. Conductive material 75 may be formed by electroplating or other suitable techniques. Conductive material 76 may be formed above conductive material 74. Conductive material 76 may be formed within opening O2. Conductive material 76 may be formed within opening O3. Conductive material 76 may be formed by electroplating or other suitable techniques.

[0068] See Figure 7F Conductive materials 71, 73, and 75 can be patterned to form conductive layer 13. Conductive materials 72, 74, and 76 can be patterned to form conductive layer 62.

[0069] See Figure 7G Substrate 11 may be formed below conductive layer 13. Substrate 61 may be formed above conductive layer 62. Conductive material 77 may be formed below the lower surface of substrate 11. Conductive material 78 may be formed above the upper surface of substrate 61.

[0070] See Figure 7HThe conductive material 77 and the substrate 11 may be patterned to form an opening O4. The conductive material 78 and the substrate 61 may be patterned to form an opening O5.

[0071] See Figure 7I Conductive material 79 may be formed below conductive material 77. Conductive material 79 may be formed within opening O4. Conductive material 79 may be formed using electroless plating or other suitable techniques. Conductive material 80 may be formed above conductive material 78. Conductive material 80 may be formed within opening O5. Conductive material 80 may be formed using electroless plating or other suitable techniques.

[0072] See Figure 7J Conductive material 81 may be formed below conductive material 79. Conductive material 81 may be formed within opening O4. Conductive material 82 may be formed by electroplating or other suitable techniques. Conductive material 82 may be formed above conductive material 80. Conductive material 82 may be formed within opening O5. Conductive material 82 may be formed by electroplating or other suitable techniques.

[0073] See Figure 7K Conductive materials 77, 79, and 81 may be patterned to define conductive layer 12 and interconnects 14 and 16. Conductive materials 78, 80, and 82 may be patterned to define conductive layer 63 and interconnects 64 and 66.

[0074] See Figure 7L Dielectric layer 15 may be formed below conductive layer 12. Dielectric layer 65 may be formed above conductive layer 63. Thus, an electronic device (e.g., electronic device 1a) can be produced.

[0075] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangement.

[0076] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with numerical values, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered "substantially" the same or equal.

[0077] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0078] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural number of indicators.

[0079] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate materials that offer little or no resistance to the flow of electric current. One unit of measurement for conductivity is Siemens per meter (S / m). Generally, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0080] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0081] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. An electronic device comprising: An electronic component having a first set of terminals disposed on a lower surface of the electronic component and a second set of terminals disposed on an upper surface of the electronic component, wherein the first set of terminals includes a first terminal and a second terminal disposed at different heights; as well as The first set of conductive vias is electrically connected to the first set of terminals.

2. The electronic device according to claim 1, further comprising: A dielectric structure that encapsulates the electronic components and the first set of conductive vias.

3. The electronic device of claim 2, wherein the dielectric structure comprises a bottom encapsulation and a top encapsulation stacked above the bottom encapsulation, and the electronic component is embedded within the bottom encapsulation and the top encapsulation.

4. The electronic device of claim 3, wherein the bottom encapsulation includes a protrusion that contacts the lower surface of the electronic component or a lateral surface extending between the upper and lower surfaces of the electronic component.

5. The electronic device of claim 4, wherein the upper surface of the electronic component has a central region closer to the bottom encapsulation and a peripheral region farther from the bottom encapsulation.

6. The electronic device of claim 1, wherein the electronic component includes a logic die and a carrier disposed between the first set of terminals and the logic die, and the logic die is configured to receive power through the carrier.

7. The electronic device of claim 6, wherein the first set of terminals includes a first terminal in a central region of the lower surface and a second terminal in a peripheral region of the lower surface, and the first set of conductive vias has a first via connected to the first terminal and a second via connected to the second terminal, and the length of the first via is less than the length of the second via.

8. The electronic device according to claim 6, further comprising: The second set of conductive vias is connected to the second set of terminals. The second set of conductive vias includes a first via above the central region of the upper surface and a second via above the peripheral region of the upper surface, and the length of the first via is greater than the length of the second via.

9. The electronic device of claim 1, wherein the arrangement of the first set of conductive vias relative to the electronic component and the arrangement of the second set of conductive vias relative to the electronic component are asymmetrical.

10. An electronic device comprising: An electronic component having a lower surface and a upper surface; as well as A first set of conductive vias is disposed below the lower surface of the electronic component and electrically connected to the electronic component. The first group of conductive vias has different lengths.

11. The electronic device of claim 10, further comprising: A first circuit structure supports the first set of conductive vias, wherein the first set of conductive vias includes a first via and a second via, the top of the first via is at a first height relative to the upper surface of the first circuit structure, and the top of the second via is at a second height relative to the upper surface of the first circuit structure, which is higher than the first height.

12. The electronic device of claim 11, wherein, relative to the upper surface of the first circuit structure, the bottom of the first through-hole is at a third height and the bottom of the second through-hole is at a fourth height substantially the same as the third height.

13. The electronic device of claim 10, further comprising: A second set of conductive vias is disposed above the upper surface of the electronic component and electrically connected to the electronic component. The second group of conductive vias has different lengths.

14. The electronic device of claim 13, wherein the sum of the length of one of the first group of conductive vias and the length of one of the second group of conductive vias vertically overlapping the first group of conductive vias is substantially the same as the sum of the length of the other of the first group of conductive vias and the length of the other of the second group of conductive vias directly above the other of the first group of conductive vias.

15. The electronic device according to claim 13, further comprising: A second circuit structure is disposed above and connected to the second group of conductive vias, wherein the second group of conductive vias includes a first via and a second via, the bottom of the first via is at a first height relative to the lower surface of the second circuit structure, and the bottom of the second via is at a second height relative to the lower surface of the second circuit structure, which is higher than the first height.

16. The electronic device of claim 15, wherein the second through-hole is closer to the side surface of the electronic component extending between the upper surface and the lower surface than the first through-hole.

17. The electronic device of claim 15, wherein, relative to the lower surface of the second circuit structure, the top of the first through-hole is at a third height and the top of the second through-hole is at a fourth height substantially the same as the third height.

18. An electronic device comprising: The lower circuit structure has a generally flat surface; An electronic component is disposed above the generally flat surface of the lower circuit structure, wherein the electronic component has a lower curved surface facing the generally flat surface; as well as A first interconnect is disposed between the generally flat surface of the lower circuit structure and the lower curved surface of the electronic component.

19. The electronic device of claim 18, wherein the electronic component has a first side and a second side opposite to the first side, and the bottom of the first side is at a different height from the bottom of the second side relative to the generally flat surface of the lower circuit structure.

20. The electronic device of claim 18, wherein the electronic component has a first side and a second side connected to the first side, and the bottom of the first side is at a different height from the bottom of the second side relative to the generally flat surface of the lower circuit structure.

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