Nondestructive testing method and system for TSV through hole side wall defects in 3DCoWoS packaging

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a nondestructive testing method and system for TSV side wall defects in 3DCoWoS packaging, and the method comprises the steps: firstly constructing a theoretical reference model of an element based on design data, and simulating theoretical resonance parameters; then, acquiring actual resonance parameters of an actual semiconductor element by utilizing an ultrasonic resonance scanner, calculating difference parameters between the theoretical resonance parameters and the actual resonance parameters, if the difference exceeds an allowable difference condition, accurately identifying information such as types, depths and volumes of the defects by utilizing an intelligent analysis model, and for repairable defects meeting a preset condition, determining whether the repairable defects are repairable or not. According to the method, the electrolyte and the probe type electroplating equipment are adopted for accurate repair, and the repaired semiconductor element is detected again. According to the invention, accurate nondestructive testing can be carried out on the side wall of the silicon through hole, and the defects of the side wall of the silicon through hole are repaired.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a non-destructive testing method and system for TSV via sidewall defects in 3DCoWoS packaging. Background Technology

[0002] With the development of the semiconductor industry, semiconductor design has shifted from traditional two-dimensional miniaturization to three-dimensional heterogeneous integration. Under this trend, CoWoS packaging technology achieves high-density interconnection through through-silicon vias (TSVs), resulting in higher bandwidth, lower power consumption, and smaller package size. Therefore, through-silicon via technology has become a core technology in the semiconductor industry.

[0003] However, the manufacturing process of through-silicon vias (TSVs) is complex, and defects such as microcracks and voids are easily generated on the sidewalls. These sidewall defects can seriously affect the integrity of signal transmission and the stability of the power network, and may even lead to the failure of the entire chip. Therefore, it is necessary to perform precise non-destructive testing on the sidewalls of TSVs and repair the defects on the sidewalls of TSVs. Summary of the Invention

[0004] This invention provides a method and system for non-destructive testing of TSV sidewall defects in 3DCoWoS packaging. Its main purpose is to perform accurate non-destructive testing on the sidewalls of TSVs and repair defects in the sidewalls of TSVs.

[0005] To achieve the above objectives, the present invention provides a non-destructive testing method for TSV sidewall defects in a 3DCoWoS package, comprising:

[0006] Acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes, and electroplating repair equipment;

[0007] Based on the packaging design data, construct a component baseline model;

[0008] Simulated ultrasonic resonance testing was performed on the component reference model to obtain the theoretical resonance parameter set.

[0009] The actual ultrasonic resonance test operation of the semiconductor device is performed using an ultrasonic resonance scanner to obtain the actual resonance parameter set, wherein the semiconductor device includes multiple actual TSV vias;

[0010] Based on the theoretical resonance parameter set and the actual resonance parameter set, obtain the difference parameter set;

[0011] Determine whether the set of difference parameters meets the preset allowable difference conditions;

[0012] If the set of difference parameters meets the preset allowable difference conditions, the semiconductor device will be identified as a finished device.

[0013] If the set of difference parameters does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the set of difference parameters to obtain the defect information set;

[0014] Determine whether the defect information set meets the preset repairable conditions;

[0015] If the defect information set meets the repairability criteria, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, a defect repair operation is performed on the repairable element to obtain a repaired semiconductor element. The repaired semiconductor element is then used as the semiconductor element, and the process returns to the step of performing actual ultrasonic resonance detection on the semiconductor element using an ultrasonic resonance scanner.

[0016] Optionally, the step of constructing a component baseline model based on package design data includes:

[0017] Extract the basic geometric parameters from the packaging design data. These basic geometric parameters include: substrate dimensions, TSV via coordinates, and TSV via geometric parameters.

[0018] Based on the substrate dimensions and pre-built 3D software, an original substrate model is constructed.

[0019] Based on the original substrate model, TSV via coordinates, and TSV via geometric parameters, a nominal geometric model is constructed.

[0020] Extract structural parameters from the packaging design data, and divide the nominal geometric model into multiple structural regions based on the structural parameters and the nominal geometric model;

[0021] Extract material physical parameters from the packaging design data, and perform physical parameter setting operations on each structural region based on the material physical parameters to obtain a physical property model;

[0022] The physical property model is subjected to finite element analysis to obtain the component reference model.

[0023] Optionally, the step of using an ultrasonic resonance scanner to perform actual ultrasonic resonance detection on the semiconductor device to obtain an actual resonance parameter set includes:

[0024] The scanning path sequence is obtained based on the TSV via coordinates. Based on the scanning path sequence and the pre-constructed ultrasonic excitation signal, the following operations are performed on each actual TSV via:

[0025] Using a pre-constructed ultrasonic transducer array in an ultrasonic resonator, an ultrasonic excitation signal is applied to an actual TSV through-hole, and the ultrasonic transducer array is used to collect the resonance response signal generated by the actual TSV through-hole to which the ultrasonic excitation signal has been applied.

[0026] The resonant response signal is transformed in the frequency domain to obtain the resonant response spectrum.

[0027] Based on the resonance response spectrum, the actual resonance parameters are obtained, including the actual amplitude, the actual resonance frequency, and the actual quality factor.

[0028] By summarizing the actual resonance parameters, we obtain the actual resonance parameter set.

[0029] Optionally, obtaining the actual resonance parameters based on the resonance response spectrum includes:

[0030] Extract the spectral peak with the largest amplitude from the resonance response spectrum to obtain the main resonance peak;

[0031] The amplitude of the main resonance peak is confirmed as the actual amplitude, and the frequency of the main resonance peak is confirmed as the actual resonance frequency.

[0032] The half-amplitude is obtained based on the actual amplitude, two half-width points are obtained based on the half-amplitude, and the frequency difference between the two half-width points is calculated based on the two half-width points.

[0033] The actual quality factor is obtained by calculating the ratio of the actual resonant frequency to the half-width at half-maximum (WHM) frequency difference.

[0034] Optionally, obtaining the difference parameter set based on the theoretical resonance parameter set and the actual resonance parameter set includes:

[0035] Extract the theoretical resonance parameters from the theoretical resonance parameter set, where the theoretical resonance parameters include: theoretical amplitude, theoretical resonance frequency, and theoretical quality factor;

[0036] Perform the following operation for each theoretical resonance parameter:

[0037] Extract the actual resonance parameters corresponding to the theoretical resonance parameters, and calculate the difference parameters based on the theoretical resonance parameters and the actual resonance parameters. The difference parameters include: resonance frequency offset, amplitude attenuation rate and quality factor change rate.

[0038] Summarize the difference parameters to obtain the difference parameter set.

[0039] Optionally, determining whether the set of difference parameters meets the preset allowable difference conditions includes:

[0040] Extract the allowable difference range from the allowable difference conditions, where the allowable difference range includes: allowable frequency offset range, allowable amplitude attenuation rate, and allowable quality factor change rate;

[0041] Perform the following operation for each difference parameter:

[0042] Determine whether the resonant frequency offset is within the allowable frequency offset range. If the resonant frequency offset is within the allowable frequency offset range, determine whether the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate. If the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate, determine whether the quality factor change rate is less than or equal to the allowable quality factor change rate. If the quality factor change rate is less than or equal to the allowable quality factor change rate, then confirm that the difference parameter is within the allowable difference range.

[0043] Otherwise, the difference parameter will be confirmed as not conforming to the allowable difference range;

[0044] If every difference parameter falls within the allowable difference range, the set of difference parameters is considered to meet the allowable difference condition; otherwise, the set of difference parameters is considered not to meet the allowable difference condition.

[0045] Optionally, determining whether the defect information set meets preset repairable conditions includes:

[0046] Extract the defect information from the defect information set sequentially, and perform the following operations on the defect information:

[0047] Determine whether the defect type belongs to the preset repairable defect type in the repairable conditions. If the defect type belongs to the repairable defect type, determine whether the defect depth is less than or equal to the preset repairable defect depth in the repairable conditions. If the defect depth is less than or equal to the repairable defect depth, determine whether the defect volume is less than or equal to the preset repairable defect volume in the repairable conditions. If the defect volume is less than or equal to the repairable defect volume, confirm the defect information as repairable defect information; otherwise, confirm the defect information as unrepairable defect information.

[0048] If all defect information in the defect information set is repairable, then the defect information set is considered to meet the repairability condition; otherwise, the defect information set is considered not to meet the repairability condition.

[0049] Optionally, the defect repair operation on repairable components based on electrolyte and electroplating repair equipment includes:

[0050] Electrolyte is injected into the repairable component to obtain the component to be repaired;

[0051] The coordinate set of the through holes to be repaired is obtained based on the defect information set, wherein the coordinate set of the through holes to be repaired includes the coordinates of multiple through holes to be repaired;

[0052] For each through-hole coordinate in the component to be repaired, perform the following operation:

[0053] Based on the coordinates of the via to be repaired and the defect depth, the working coordinates of the probe are obtained. Based on the working coordinates of the probe, the repair probe is imported into the via to be repaired corresponding to the coordinates of the via to be repaired. Electroplating repair operation is performed using the repair probe in the via to be repaired. At the same time as the electroplating repair operation, the voltage difference between the repair probe and the via to be repaired is monitored using the voltage sensing unit pre-built in the repair probe to obtain the real-time voltage difference.

[0054] If the real-time voltage difference is less than or equal to the preset filling completion voltage difference, stop the electroplating operation;

[0055] Otherwise, return to the step of performing electroplating repair using the repair probe in the through-hole to be repaired. Optionally, the electroplating repair operation using the repair probe in the through-hole to be repaired includes:

[0056] Obtain electrolyte information, and based on the electrolyte information and the pre-constructed electrolyte limiting current calculation formula, obtain the electrolyte limiting current;

[0057] Based on defect type, defect volume, and intelligent analysis model, the defect limiting current is obtained;

[0058] The maximum allowable current is obtained based on the electrolyte limiting current and the defect limiting current.

[0059] The final operating current is obtained based on the maximum allowable current and the preset safety factor;

[0060] Activate the repair probe to perform electroplating repair operation at the final operating current.

[0061] To achieve the above objectives, the present invention also provides a non-destructive testing system for TSV sidewall defects in a 3DCoWoS package, comprising:

[0062] The basics and modeling module is used to acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes and electroplating repair equipment. Based on the packaging design data, a component reference model is constructed, and the component reference model is subjected to simulated ultrasonic resonance detection to obtain a theoretical resonance parameter set.

[0063] The resonance detection module is used to perform actual ultrasonic resonance detection on semiconductor devices using an ultrasonic resonance scanner to obtain an actual resonance parameter set. The semiconductor device includes multiple actual TSV vias. Based on the theoretical resonance parameter set and the actual resonance parameter set, a difference parameter set is obtained.

[0064] The defect analysis module is used to determine whether the set of difference parameters meets the preset allowable difference conditions. If the set of difference parameters meets the preset allowable difference conditions, the semiconductor component is identified as a finished component. If the set of difference parameters does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the set of difference parameters to obtain a defect information set.

[0065] The electroplating repair module is used to determine whether the defect information set meets the preset repairable conditions. If the defect information set meets the repairable conditions, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, the repairable element is subjected to defect repair operation to obtain a repaired semiconductor element. The repaired semiconductor element is used as the semiconductor element, and the process returns to the step of performing actual ultrasonic resonance detection on the semiconductor element using an ultrasonic resonance scanner.

[0066] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0067] Memory, storing at least one instruction;

[0068] The processor executes the instructions stored in the memory to implement the non-destructive testing method for TSV through-hole sidewall defects in the 3DCoWoS package described above.

[0069] To address the aforementioned issues, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the non-destructive testing method for TSV via sidewall defects in a 3DCoWoS package described above.

[0070] To address the problems described in the background art, this invention provides semiconductor components, packaging design data, an ultrasonic resonance scanner, an intelligent analysis model, electrolyte, and electroplating repair equipment. This invention pre-prepares the necessary physical equipment and data, providing a complete foundation for subsequent processes. Based on the packaging design data, a component baseline model is constructed. Simulated ultrasonic resonance testing is performed on the component baseline model to obtain a theoretical resonance parameter set. This invention obtains ideal resonance parameters unaffected by external environmental interference through an ideal three-dimensional digital model, providing a benchmark for subsequent actual testing. An ultrasonic resonance scanner is used to perform actual ultrasonic resonance testing on the semiconductor component, obtaining an actual resonance parameter set. The semiconductor component includes multiple actual TSV vias. This invention utilizes ultrasonic resonance testing to efficiently obtain the true internal state information of the component without damaging it. Based on the theoretical and actual resonance parameter sets, a difference parameter set is obtained. This invention accurately quantifies the difference between the actual component and the theoretical model using the difference in resonance parameters. It determines whether the difference parameter set meets preset allowable difference conditions. If the difference parameter set meets the preset allowable difference conditions, the semiconductor component is confirmed as a finished product. As can be seen, this invention avoids classifying differences that do not affect the performance of semiconductor components as abnormal by automatically judging them through preset allowable difference conditions, and also improves the efficiency and automation level of defect detection. If the difference parameter set does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the difference parameter set to obtain the defect information set. It can be seen that this invention uses an intelligent analysis model to analyze the difference parameters, which significantly improves the accuracy and efficiency of defect diagnosis and realizes precise analysis of defects. It judges whether the defect information set meets the preset repairable conditions. It can be seen that this invention achieves refined diversion management of defective products by judging through preset repairable conditions, and avoids ineffective repair that wastes resources. If the defect information set meets the repairable conditions, the semiconductor component is identified as a repairable component. Based on the electrolyte and electroplating repair equipment, the repairable component is subjected to defect repair operation to obtain a repaired semiconductor component. The repaired semiconductor component is used as the semiconductor component, and the step of performing actual ultrasonic resonance detection operation on the semiconductor component using an ultrasonic resonance scanner is returned. It can be seen that this invention realizes the electroplating repair of defects on the sidewall of silicon through-holes, and the repaired component is inspected again to realize a closed loop of quality control. Therefore, the present invention can perform precise non-destructive testing on the sidewalls of through-silicon vias and repair defects in the sidewalls of through-silicon vias. Attached Figure Description

[0071] Figure 1 This is a flowchart illustrating a non-destructive testing method for TSV via sidewall defects in a 3DCoWoS package according to an embodiment of the present invention.

[0072] Figure 2This is a functional block diagram of a non-destructive testing system for TSV through-hole sidewall defects in a 3DCoWoS package according to an embodiment of the present invention;

[0073] Figure 3 This is a schematic diagram of an electronic device that implements the non-destructive testing method for TSV through-hole sidewall defects in the 3DCoWoS package, according to an embodiment of the present invention.

[0074] Explanation of reference numerals in the attached figures:

[0075] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0076] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0077] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0078] This application provides a method for non-destructive testing of TSV via sidewall defects in a 3DCoWoS package. The execution subject of this method includes, but is not limited to, at least one of the following electronic devices that can be assigned to execute the method provided in this application: a server, a terminal, etc. In other words, the method for non-destructive testing of TSV via sidewall defects in a 3DCoWoS package can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0079] Reference Figure 1 The diagram shown is a flowchart illustrating a non-destructive testing method for TSV via sidewall defects in a 3DCoWoS package according to an embodiment of the present invention. In this embodiment, the non-destructive testing method for TSV via sidewall defects in a 3DCoWoS package includes:

[0080] S1. Acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes, and electroplating repair equipment.

[0081] Understandably, the semiconductor element refers to a chip unit to be inspected that uses 3DCoWoS packaging and includes TSV vias. The package design data refers to the original design parameters containing data such as element geometry, structure, material, and TSV via coordinates. The ultrasonic resonance scanner refers to a device that uses the principle of ultrasonic resonance to detect the physical state and defects of TSV vias. The intelligent analysis model refers to a computational model based on artificial intelligence algorithms, which can be used to identify specific defect information from data differences and assist in generating repair decisions. It also includes a case library containing a large number of known TSV via defect cases and solutions. The electrolyte refers to a conductive solution containing metal ions, intended as a conductive medium and material source for filling defects. The electroplating repair equipment refers to a device with a repair probe at its core, used to perform electroplating repair operations.

[0082] S2. Based on the package design data, construct the component baseline model.

[0083] It is clear that the component reference model refers to an idealized three-dimensional digital model created based on design data, free from any defects, and its purpose is to serve as a benchmark for judging whether defects exist.

[0084] Furthermore, the construction of a component baseline model based on the package design data includes:

[0085] Extract the basic geometric parameters from the packaging design data. These basic geometric parameters include: substrate dimensions, TSV via coordinates, and TSV via geometric parameters.

[0086] Based on the substrate dimensions and pre-built 3D software, an original substrate model is constructed.

[0087] Based on the original substrate model, TSV via coordinates, and TSV via geometric parameters, a nominal geometric model is constructed.

[0088] Extract structural parameters from the packaging design data, and divide the nominal geometric model into multiple structural regions based on the structural parameters and the nominal geometric model;

[0089] Extract material physical parameters from the packaging design data, and perform physical parameter setting operations on each structural region based on the material physical parameters to obtain a physical property model;

[0090] The physical property model is subjected to finite element analysis to obtain the component reference model.

[0091] Understandably, the basic geometric parameters refer to the most fundamental geometric information of a semiconductor device, including: substrate dimensions, TSV via coordinates, and TSV via geometric parameters. The substrate dimensions refer to the macroscopic dimensions of the substrate, such as length, width, and height. The TSV via coordinates refer to the position coordinates of the TSV via on the substrate. The TSV via geometric parameters refer to information such as the diameter, taper, and depth of the TSV via. The 3D software refers to computer-aided 3D design software, such as AutoCAD. The original substrate model refers to an initial 3D digital model constructed solely based on the substrate dimensions, without the addition of internal structures such as TSV vias. The nominal geometric model refers to a 3D digital model based on the original substrate model, with the TSV via coordinates and all TSV vias precisely added. The structural parameters refer to the detailed design information in the packaging design data used to define the specific layout, layering, and boundaries of different functional regions within the semiconductor device, such as insulating layers and padding layers. The multiple structural regions refer to regions divided according to different components within the semiconductor device, such as insulating layer regions and padding layer regions. The material physical parameters refer to the physical properties of various materials in the model, such as material type, density, Young's modulus, Poisson's ratio, etc. The physical parameter setting operation refers to the operation of assigning physical parameters of different materials to different structural regions. The physical property model refers to a three-dimensional digital model that can be used for physical simulation analysis, formed by assigning the true physical properties of the corresponding material to each structural region based on the nominal geometric model. The finite element meshing operation refers to the process of dividing the continuous physical property model into a large number of simple, tiny, interconnected elements (i.e., finite elements), which is a necessary preparatory step before computer physical simulation calculations.

[0092] S3. Perform simulated ultrasonic resonance testing on the component reference model to obtain the theoretical resonance parameter set.

[0093] It should be explained that the simulated ultrasonic resonance testing operation refers to the operation of applying virtual ultrasonic waves to a defect-free component reference model based on computer simulation technology to simulate the actual testing process. Its purpose is to obtain the theoretical resonance parameter set of the semiconductor component under ideal conditions. The theoretical resonance parameter set refers to the set of theoretical resonance parameters of the simulated TSV via obtained through the simulated ultrasonic resonance testing operation.

[0094] S4. Perform actual ultrasonic resonance testing on the semiconductor device using an ultrasonic resonance scanner to obtain the actual resonance parameter set, wherein the semiconductor device includes multiple actual TSV vias.

[0095] Understandably, the actual ultrasonic resonance detection operation refers to the operation of using a real ultrasonic resonance scanner to scan a physically existing semiconductor device and collect the actual resonance response data of the actual TSV via. The actual resonance parameter set refers to the set of actual resonance parameters of the actual TSV via collected through the actual ultrasonic resonance detection operation on the real semiconductor device. The actual TSV via refers to a physically existing silicon via on the semiconductor device.

[0096] Furthermore, the actual ultrasonic resonance detection operation of the semiconductor device using an ultrasonic resonance scanner to obtain the actual resonance parameter set includes:

[0097] The scanning path sequence is obtained based on the TSV via coordinates. Based on the scanning path sequence and the pre-constructed ultrasonic excitation signal, the following operations are performed on each actual TSV via:

[0098] Using a pre-constructed ultrasonic transducer array in an ultrasonic resonator, an ultrasonic excitation signal is applied to an actual TSV through-hole, and the ultrasonic transducer array is used to collect the resonance response signal generated by the actual TSV through-hole to which the ultrasonic excitation signal has been applied.

[0099] The resonant response signal is transformed in the frequency domain to obtain the resonant response spectrum.

[0100] Based on the resonance response spectrum, the actual resonance parameters are obtained, including the actual amplitude, the actual resonance frequency, and the actual quality factor.

[0101] By summarizing the actual resonance parameters, we obtain the actual resonance parameter set.

[0102] It is clear that the scanning path sequence refers to the pre-planned movement order and path of the ultrasonic transducer array to ensure that the ultrasonic resonance scanner can efficiently and completely detect each actual TSV via. The ultrasonic excitation signal refers to the ultrasonic wave signal with a pre-set frequency and waveform, emitted by the ultrasonic transducer array to cause vibration in the TSV via. The ultrasonic transducer array is the core component in the ultrasonic resonance scanner, composed of multiple cooperating ultrasonic sensors, responsible for both applying ultrasonic waves to the actual TSV via and receiving the resonance response signal. The resonance response signal is the vibration signal generated by the actual TSV via after being excited by ultrasonic waves, reflecting its own physical condition. The frequency domain transformation operation refers to the operation of converting the time-varying resonance response signal into a spectrum diagram that displays the various frequencies and their corresponding amplitudes contained within it, using Fourier transform. The resonance response spectrum diagram is an image showing the changes in signal amplitude and frequency after frequency domain transformation of the resonance response signal, with frequency as the horizontal axis and amplitude as the vertical axis. The actual resonance parameters refer to the set of actual amplitude, actual resonance frequency, and actual quality factor obtained from the actual measured resonance response spectrum. The actual amplitude refers to the maximum amplitude measured at the actual resonance frequency. The actual resonance frequency refers to the frequency corresponding to the actual amplitude of the actual TSV via during actual testing. The actual quality factor is a parameter that measures the energy loss of the actual TSV via under ultrasonic excitation.

[0103] Furthermore, obtaining the actual resonance parameters based on the resonance response spectrum includes:

[0104] Extract the spectral peak with the largest amplitude from the resonance response spectrum to obtain the main resonance peak;

[0105] The amplitude of the main resonance peak is confirmed as the actual amplitude, and the frequency of the main resonance peak is confirmed as the actual resonance frequency.

[0106] The half-amplitude is obtained based on the actual amplitude, two half-width points are obtained based on the half-amplitude, and the frequency difference between the two half-width points is calculated based on the two half-width points.

[0107] The actual quality factor is obtained by calculating the ratio of the actual resonant frequency to the half-width at half-maximum (WHM) frequency difference.

[0108] Specifically, the main resonance peak refers to the spectral peak with the largest amplitude in the resonance response spectrum. The half-amplitude refers to half the peak amplitude of the main resonance peak, used to locate the half-width at half-maximum (HWHM). The two HWHMs refer to two specific frequency points on either side of the peak of the main resonance peak, where the amplitude value equals half-amplitude. The HWHM frequency difference refers to the difference in frequencies corresponding to the two HWHMs. The actual quality factor is calculated as follows:

[0109]

[0110] Where Q represents the actual quality factor, P1 represents the frequency of the half-width at half-maximum (WHM) on one side of the peak of the main resonance peak, P2 represents the frequency of the WHM on the other side of the peak of the main resonance peak, and R represents the actual resonance frequency.

[0111] S5. Obtain the difference parameter set based on the theoretical resonance parameter set and the actual resonance parameter set.

[0112] It should be explained that the set of difference parameters refers to the set of difference parameters calculated by comparing the theoretical resonance parameters with the actual resonance parameters.

[0113] Furthermore, obtaining the difference parameter set based on the theoretical resonance parameter set and the actual resonance parameter set includes:

[0114] Extract the theoretical resonance parameters from the theoretical resonance parameter set, where the theoretical resonance parameters include: theoretical amplitude, theoretical resonance frequency, and theoretical quality factor;

[0115] Perform the following operation for each theoretical resonance parameter:

[0116] Extract the actual resonance parameters corresponding to the theoretical resonance parameters, and calculate the difference parameters based on the theoretical resonance parameters and the actual resonance parameters. The difference parameters include: resonance frequency offset, amplitude attenuation rate and quality factor change rate.

[0117] Summarize the difference parameters to obtain the difference parameter set.

[0118] Specifically, the theoretical resonance parameters refer to the set of theoretical amplitude, theoretical resonance frequency, and theoretical quality factor of the simulated TSV via. The theoretical amplitude refers to the theoretical maximum amplitude value of the simulated TSV via when subjected to ultrasonic excitation, calculated through computer simulation. The theoretical resonance frequency refers to the frequency corresponding to the theoretical amplitude of the simulated TSV via, calculated through computer simulation. The theoretical quality factor refers to a parameter calculated through computer simulation that measures the energy loss of the simulated TSV via under simulated ultrasonic excitation. The difference parameters refer to the set of resonance frequency offset, amplitude attenuation rate, and quality factor change rate, used to accurately describe the degree to which the actual measured value deviates from the theoretical standard value. The resonance frequency offset refers to the difference between the actual resonance frequency and the theoretical resonance frequency. The amplitude attenuation rate refers to the proportion by which the actual amplitude decreases compared to the theoretical amplitude. This is because: the theoretical amplitude is the amplitude under idealized conditions, while in actual measurement, even if the actual TSV via is defect-free, ultrasonic waves will be reflected and refracted at different interfaces (e.g., from the ultrasonic transducer array to the actual TSV via), causing some energy to not be fully transmitted to the actual TSV via, thus reducing the actual amplitude. Furthermore, when the actual TSV via has defects, the defects cause the ultrasonic energy to scatter in all directions, further reducing the actual amplitude. The quality factor change rate refers to the proportion by which the actual quality factor changes compared to the theoretical quality factor.

[0119] S6. Determine whether the set of difference parameters meets the preset allowable difference conditions.

[0120] It is clear that the allowable difference condition refers to the judgment logic and judgment criteria set to determine whether there are any abnormalities in the differences between the various resonance parameters of the actual TSV via and the simulated TSV via.

[0121] Furthermore, determining whether the set of difference parameters meets the preset allowable difference conditions includes:

[0122] Extract the allowable difference range from the allowable difference conditions, where the allowable difference range includes: allowable frequency offset range, allowable amplitude attenuation rate, and allowable quality factor change rate;

[0123] Perform the following operation for each difference parameter:

[0124] Determine whether the resonant frequency offset is within the allowable frequency offset range. If the resonant frequency offset is within the allowable frequency offset range, determine whether the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate. If the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate, determine whether the quality factor change rate is less than or equal to the allowable quality factor change rate. If the quality factor change rate is less than or equal to the allowable quality factor change rate, then confirm that the difference parameter is within the allowable difference range.

[0125] Otherwise, the difference parameter will be confirmed as not conforming to the allowable difference range;

[0126] If every difference parameter falls within the allowable difference range, the set of difference parameters is considered to meet the allowable difference condition; otherwise, the set of difference parameters is considered not to meet the allowable difference condition.

[0127] Explained, the allowable difference range refers to specific thresholds within the allowable difference conditions, including: allowable frequency offset range, allowable amplitude attenuation rate, and allowable quality factor change rate. The allowable frequency offset range refers to a pre-defined, acceptable maximum offset interval between the actual resonant frequency and the theoretical resonant frequency that does not affect the performance of the through-silicon via.

[0128] For example, the allowable frequency offset range of [-0.01GHz, +0.01GHz] means that if the actual resonant frequency decreases or increases by less than or equal to 0.01GHz relative to the theoretical resonant frequency, it can be considered an acceptable and normal offset that does not affect the performance of the through-silicon via.

[0129] Specifically, the allowable amplitude attenuation rate refers to the maximum attenuation ratio of the actual amplitude to the theoretical amplitude, which is a pre-set, acceptable ratio that does not affect the performance of the through-silicon via (TSV). The allowable quality factor change rate refers to the maximum change ratio of the actual quality factor to the theoretical quality factor, which is a pre-set, acceptable ratio that does not affect the performance of the TSV. Otherwise, the difference parameter is considered to be outside the allowable difference range if it does not meet any one or more of the following conditions: the resonant frequency offset is within the allowable frequency offset range, the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate, or the quality factor change rate is less than or equal to the allowable quality factor change rate.

[0130] S7. If the set of difference parameters meets the preset allowable difference conditions, the semiconductor device is confirmed as a finished device.

[0131] It should be explained that the finished component refers to a qualified semiconductor component whose difference parameters are within the allowable difference range and do not require repair.

[0132] S8. If the set of difference parameters does not meet the allowable difference conditions, use the intelligent analysis model to perform defect analysis on the set of difference parameters to obtain the defect information set.

[0133] It is clear that the defect analysis operation refers to the operation of using an intelligent analysis model to analyze the difference parameters in the difference parameter set that do not meet the allowable difference range, to determine whether they are defects, and to predict the type, depth and volume of the defects.

[0134] For example, if a difference parameter A does not meet the allowed difference conditions, the case library in the intelligent analysis model is used to calculate the matching degree between the difference parameter and the cases in the case library to obtain the case B with the highest matching degree. If the matching degree of case B is greater than or equal to 95%, the defect information of case B can be regarded as the defect information of the present invention embodiment. If the matching degree of case B is less than 95%, regression analysis is performed to adjust the defect information of case B based on regression analysis, and the adjusted defect information of case B is output as the defect information of the present invention embodiment.

[0135] Specifically, the defect information set refers to the collection of defect information obtained from defect analysis operations. The defect information refers to the collection of defect types, defect depths, and defect volumes obtained from defect analysis operations.

[0136] S9. Determine whether the defect information set meets the preset repairable conditions.

[0137] Understandably, some defects are too severe to repair, or even impossible. Therefore, repairability criteria are used to determine whether a defect can be repaired, avoiding ineffective repair attempts and saving time and resources. These repairability criteria refer to specific standards used to determine whether a defect is worth repairing, including repairable defect type, repairable defect depth, and repairable defect volume.

[0138] Furthermore, determining whether the defect information set meets the preset repairable conditions includes:

[0139] Extract defect information from the defect information set sequentially. The defect information includes: defect type, defect depth, and defect volume. Then, perform the following operations on the defect information:

[0140] Determine whether the defect type belongs to the preset repairable defect type in the repairable conditions. If the defect type belongs to the repairable defect type, determine whether the defect depth is less than or equal to the preset repairable defect depth in the repairable conditions. If the defect depth is less than or equal to the repairable defect depth, determine whether the defect volume is less than or equal to the preset repairable defect volume in the repairable conditions. If the defect volume is less than or equal to the repairable defect volume, confirm the defect information as repairable defect information; otherwise, confirm the defect information as unrepairable defect information.

[0141] If all defect information in the defect information set is repairable, then the defect information set is considered to meet the repairability condition; otherwise, the defect information set is considered not to meet the repairability condition.

[0142] Specifically, the defect type refers to the classification of defect forms identified by the intelligent analysis model, such as voids, microcracks, and material contamination. The defect depth refers to the depth of the defect relative to the opening end of the TSV via, as identified by the intelligent analysis model. The defect volume refers to the volume of the defect identified by the intelligent analysis model. The repairable defect type refers to the types of defects that can be technically repaired by electroplating, such as voids and microcracks. The repairable defect depth refers to the deepest point that the repair probe can reach. The repairable defect volume refers to the maximum, pre-set, suitable defect volume for repair, because for defects exceeding the repairable defect volume, even after electroplating repair, the reliability of the repaired defect cannot be guaranteed. The repairable defect information refers to the conclusion that a defect is considered repairable after passing the three criteria of repairable defect type, repairable defect depth, and repairable defect volume. The unrepairable defect information refers to the conclusion that a defect is considered unrepairable because it does not meet at least one of the three criteria of repairable defect type, repairable defect depth, or repairable defect volume.

[0143] S10. If the defect information set meets the repairable condition, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, the repairable element is subjected to defect repair operation to obtain a repaired semiconductor element. The repaired semiconductor element is used as the semiconductor element, and the process returns to the step of performing actual ultrasonic resonance detection on the semiconductor element using an ultrasonic resonance scanner.

[0144] Understandably, the repairable component refers to a semiconductor component whose internal defects have been confirmed to meet the repairability criteria. The defect repair operation refers to the operation of electroplating to fill defects in the repairable component using an electrolyte, electroplating repair equipment, and based on a defect information set. The repaired semiconductor component refers to a semiconductor component that has undergone defect repair, but whose final quality status still needs to be verified again.

[0145] Furthermore, the defect repair operation on repairable components based on electrolyte and electroplating repair equipment includes:

[0146] Electrolyte is injected into the repairable component to obtain the component to be repaired;

[0147] The coordinate set of the through holes to be repaired is obtained based on the defect information set, wherein the coordinate set of the through holes to be repaired includes the coordinates of multiple through holes to be repaired;

[0148] For each through-hole coordinate in the component to be repaired, perform the following operation:

[0149] Based on the coordinates of the via to be repaired and the defect depth, the working coordinates of the probe are obtained. Based on the working coordinates of the probe, the pre-constructed repair probe in the electroplating repair equipment is imported into the via to be repaired corresponding to the working coordinates of the probe. Electroplating repair operation is performed using the repair probe in the via to be repaired. At the same time as the electroplating repair operation, the voltage difference between the repair probe and the via to be repaired is monitored using the voltage sensing unit pre-constructed in the repair probe to obtain the real-time voltage difference.

[0150] If the real-time voltage difference is less than or equal to the preset filling completion voltage difference, stop the electroplating operation;

[0151] Otherwise, return to the step of performing electroplating repair using the repair probe in the through hole to be repaired.

[0152] Specifically, the component to be repaired refers to a semiconductor component that has been injected with electrolyte and is ready for electroplating repair. The via coordinate set to be repaired refers to the set of precise position coordinates of all actual TSV vias that need to be repaired. The via coordinates to be repaired refer to the precise position coordinates of the actual TSV vias that need to be repaired. The probe working coordinates refer to the specific three-dimensional spatial points that the repair probe needs to precisely locate after combining the planar coordinates of the actual TSV via and the defect depth. The repair probe refers to a miniature probe integrating electroplating electrodes and voltage sensing functions, whose function is to penetrate deep into the TSV via, perform precise electroplating filling operations, and monitor the voltage in real time. The electroplating repair operation refers to the operation of applying current using the repair probe to precisely precipitate and deposit metal ions in the electrolyte at the defect site on the sidewall of the actual TSV via, thereby achieving defect repair. The voltage sensing unit refers to a miniature voltage sensor inside the repair probe specifically used to measure the potential difference between the probe electrode and the via sidewall in real time. The real-time voltage difference refers to the dynamic voltage value representing the defect filling state, continuously collected by the voltage sensing unit during the electroplating repair operation. The filling completion voltage difference refers to a preset voltage threshold. When the real-time voltage difference reaches or falls below the filling completion voltage difference, it indicates that the defect has been completely filled by the metal. Therefore, it can be used to determine whether the defect has been repaired.

[0153] Furthermore, the electroplating repair operation using a repair probe in the through-hole to be repaired includes:

[0154] Obtain electrolyte information, and based on the electrolyte information and the pre-constructed electrolyte limiting current calculation formula, obtain the electrolyte limiting current;

[0155] Based on defect type, defect volume, and intelligent analysis model, the defect limiting current is obtained;

[0156] The maximum allowable current is obtained based on the electrolyte limiting current and the defect limiting current.

[0157] The final operating current is obtained based on the maximum allowable current and the preset safety factor;

[0158] Activate the repair probe to perform electroplating repair operation at the final operating current.

[0159] In detail, the electrolyte information refers to information describing the physical state of the electrolyte, including chemical composition, metal ion concentration, ion diffusion coefficient, and Nernst diffusion layer thickness. The electrolyte limiting current refers to the theoretical maximum electroplating current determined by the properties of the electrolyte itself. The formula for calculating the electrolyte limiting current is as follows:

[0160]

[0161] Where J represents the electrolyte limiting current, N represents the number of electrons transferred (depending on the metal ions), F represents the Faraday constant, D represents the ion diffusion coefficient, C represents the metal ion concentration, and δ represents the Nernst diffusion layer thickness.

[0162] Specifically, the defect limiting current refers to the maximum current estimated by the intelligent analysis model based on the type and volume of the defect, which enables optimal filling quality in the defect area. The maximum permissible current refers to the absolutely safe current value, the smaller of the electrolyte limiting current and the defect limiting current, chosen to simultaneously ensure electrolyte stability and defect filling quality. The safety factor is a coefficient that allows for a margin of safety beyond the maximum permissible current to ensure process stability and reliability. The final operating current refers to the precise current value that the repair probe will ultimately use in the actual electroplating repair operation, obtained by multiplying the maximum permissible current by the safety factor.

[0163] To address the problems described in the background art, this invention provides semiconductor components, packaging design data, an ultrasonic resonance scanner, an intelligent analysis model, electrolyte, and electroplating repair equipment. This invention pre-prepares the necessary physical equipment and data, providing a complete foundation for subsequent processes. Based on the packaging design data, a component baseline model is constructed. Simulated ultrasonic resonance testing is performed on the component baseline model to obtain a theoretical resonance parameter set. This invention obtains ideal resonance parameters unaffected by external environmental interference through an ideal three-dimensional digital model, providing a benchmark for subsequent actual testing. An ultrasonic resonance scanner is used to perform actual ultrasonic resonance testing on the semiconductor component, obtaining an actual resonance parameter set. The semiconductor component includes multiple actual TSV vias. This invention utilizes ultrasonic resonance testing to efficiently obtain the true internal state information of the component without damaging it. Based on the theoretical and actual resonance parameter sets, a difference parameter set is obtained. This invention accurately quantifies the difference between the actual component and the theoretical model using the difference in resonance parameters. It determines whether the difference parameter set meets preset allowable difference conditions. If the difference parameter set meets the preset allowable difference conditions, the semiconductor component is confirmed as a finished product. As can be seen, this invention avoids classifying differences that do not affect the performance of semiconductor components as abnormal by automatically judging them through preset allowable difference conditions, and also improves the efficiency and automation level of defect detection. If the difference parameter set does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the difference parameter set to obtain the defect information set. It can be seen that this invention uses an intelligent analysis model to analyze the difference parameters, which significantly improves the accuracy and efficiency of defect diagnosis and realizes precise analysis of defects. It judges whether the defect information set meets the preset repairable conditions. It can be seen that this invention achieves refined diversion management of defective products by judging through preset repairable conditions, and avoids ineffective repair that wastes resources. If the defect information set meets the repairable conditions, the semiconductor component is identified as a repairable component. Based on the electrolyte and electroplating repair equipment, the repairable component is subjected to defect repair operation to obtain a repaired semiconductor component. The repaired semiconductor component is used as the semiconductor component, and the step of performing actual ultrasonic resonance detection operation on the semiconductor component using an ultrasonic resonance scanner is returned. It can be seen that this invention realizes the electroplating repair of defects on the sidewall of silicon through-holes, and the repaired component is inspected again to realize a closed loop of quality control. Therefore, the present invention can perform precise non-destructive testing on the sidewalls of through-silicon vias and repair defects in the sidewalls of through-silicon vias.

[0164] like Figure 2 The diagram shown is a functional block diagram of a non-destructive testing system for TSV through-hole sidewall defects in a 3DCoWoS package provided by an embodiment of the present invention.

[0165] The non-destructive testing system 100 for TSV via sidewall defects in the 3DCoWoS package described in this invention can be installed in an electronic device. Depending on the functions implemented, the non-destructive testing system 100 for TSV via sidewall defects in the 3DCoWoS package may include a basic modeling module 101, a resonance detection module 102, a defect analysis module 103, and an electroplating repair module 104. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0166] The foundation and modeling module 101 is used to acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes and electroplating repair equipment, construct component reference models based on packaging design data, perform simulated ultrasonic resonance detection operations on component reference models, and obtain theoretical resonance parameter sets.

[0167] The resonance detection module 102 is used to perform actual ultrasonic resonance detection on the semiconductor device using an ultrasonic resonance scanner to obtain an actual resonance parameter set. The semiconductor device includes multiple actual TSV vias. Based on the theoretical resonance parameter set and the actual resonance parameter set, a difference parameter set is obtained.

[0168] The defect analysis module 103 is used to determine whether the set of difference parameters meets the preset allowable difference conditions. If the set of difference parameters meets the preset allowable difference conditions, the semiconductor element is confirmed as a finished element. If the set of difference parameters does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the set of difference parameters to obtain a defect information set.

[0169] The electroplating repair module 104 is used to determine whether the defect information set meets the preset repairable conditions. If the defect information set meets the repairable conditions, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, the repairable element is subjected to defect repair operation to obtain a repaired semiconductor element. The repaired semiconductor element is used as the semiconductor element, and the process returns to the step of using an ultrasonic resonance scanner to perform actual ultrasonic resonance detection on the semiconductor element.

[0170] In detail, the modules in the 3DCoWoS package TSV through-hole sidewall defect non-destructive testing system 100 described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The method used is the same as the non-destructive testing method for TSV through-hole sidewall defects in the 3DCoWoS package described above, and can produce the same technical effect, so it will not be repeated here.

[0171] like Figure 3The diagram shown is a structural schematic of an electronic device that implements a non-destructive testing method for TSV through-hole sidewall defects in a 3DCoWoS package, according to an embodiment of the present invention.

[0172] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a non-destructive testing method program for TSV through-hole sidewall defects in a 3DCoWoS package.

[0173] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 11 includes both internal and external storage units of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of a non-destructive testing method for TSV through-hole sidewall defects in a 3DCoWoS package, but also to temporarily store data that has been output or will be output.

[0174] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., a non-destructive testing method program for TSV via sidewall defects in a 3DCoWoS package), and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0175] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0176] Figure 3 Only electronic devices with components are shown; those skilled in the art will understand that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0177] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management system, thereby enabling functions such as charging management, discharging management, and power consumption management through the power management system. The power supply may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0178] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0179] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0180] The non-destructive testing method program for TSV through-hole sidewall defects in the 3DCoWoS package stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0181] Acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes, and electroplating repair equipment;

[0182] Based on the packaging design data, construct a component baseline model;

[0183] Simulated ultrasonic resonance testing was performed on the component reference model to obtain the theoretical resonance parameter set.

[0184] The actual ultrasonic resonance test operation of the semiconductor device is performed using an ultrasonic resonance scanner to obtain the actual resonance parameter set, wherein the semiconductor device includes multiple actual TSV vias;

[0185] Based on the theoretical resonance parameter set and the actual resonance parameter set, obtain the difference parameter set;

[0186] Determine whether the set of difference parameters meets the preset allowable difference conditions;

[0187] If the set of difference parameters meets the preset allowable difference conditions, the semiconductor device will be identified as a finished device.

[0188] If the set of difference parameters does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the set of difference parameters to obtain the defect information set;

[0189] Determine whether the defect information set meets the preset repairable conditions;

[0190] If the defect information set meets the repairability criteria, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, a defect repair operation is performed on the repairable element to obtain a repaired semiconductor element. The repaired semiconductor element is then used as the semiconductor element, and the process returns to the step of performing actual ultrasonic resonance detection on the semiconductor element using an ultrasonic resonance scanner.

[0191] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0192] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0193] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0194] Acquire semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolytes, and electroplating repair equipment;

[0195] Based on the packaging design data, construct a component baseline model;

[0196] Simulated ultrasonic resonance testing was performed on the component reference model to obtain the theoretical resonance parameter set.

[0197] The actual ultrasonic resonance test operation of the semiconductor device is performed using an ultrasonic resonance scanner to obtain the actual resonance parameter set, wherein the semiconductor device includes multiple actual TSV vias;

[0198] Based on the theoretical resonance parameter set and the actual resonance parameter set, obtain the difference parameter set;

[0199] Determine whether the set of difference parameters meets the preset allowable difference conditions;

[0200] If the set of difference parameters meets the preset allowable difference conditions, the semiconductor device will be identified as a finished device.

[0201] If the set of difference parameters does not meet the allowable difference conditions, the intelligent analysis model is used to perform defect analysis on the set of difference parameters to obtain the defect information set;

[0202] Determine whether the defect information set meets the preset repairable conditions;

[0203] If the defect information set meets the repairability criteria, the semiconductor element is identified as a repairable element. Based on the electrolyte and electroplating repair equipment, a defect repair operation is performed on the repairable element to obtain a repaired semiconductor element. The repaired semiconductor element is then used as the semiconductor element, and the process returns to the step of performing actual ultrasonic resonance detection on the semiconductor element using an ultrasonic resonance scanner.

[0204] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0205] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0206] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0207] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0208] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A non-destructive testing method for sidewall defects of TSV vias in a 3DCoWoS package, characterized in that, The method comprises: acquiring semiconductor components, packaging design data, ultrasonic resonance scanners, intelligent analysis models, electrolyte and electroplating repair equipment; constructing component reference models based on the packaging design data; performing simulated ultrasonic resonance detection operations on the component reference models to obtain a theoretical resonance parameter set; performing actual ultrasonic resonance detection operations on the semiconductor components using the ultrasonic resonance scanners to obtain an actual resonance parameter set, wherein the semiconductor components include a plurality of actual TSV through holes; acquiring a difference parameter set based on the theoretical resonance parameter set and the actual resonance parameter set; determining whether the difference parameter set meets a preset allowable difference condition; if the difference parameter set meets the preset allowable difference condition, confirming the semiconductor components as finished components; if the difference parameter set does not meet the allowable difference condition, performing defect analysis operations on the difference parameter set using the intelligent analysis models to obtain a defect information set; determining whether the defect information set meets a preset repairable condition; if the defect information set meets the repairable condition, confirming the semiconductor components as repairable components, performing defect repair operations on the repairable components based on the electrolyte and the electroplating repair equipment to obtain repaired semiconductor components, and returning to the step of performing actual ultrasonic resonance detection operations on the semiconductor components using the ultrasonic resonance scanners.

2. The method for non-destructive testing of TSV via sidewall defects in 3D CoWoS package as claimed in claim 1, wherein, The method comprises: extracting basic geometric parameters in the packaging design data, wherein the basic geometric parameters include substrate size, TSV through hole coordinates and TSV through hole geometric parameters; constructing an original substrate model based on the substrate size and a pre-constructed three-dimensional software; constructing a nominal geometric model based on the original substrate model, the TSV through hole coordinates and the TSV through hole geometric parameters; extracting structure parameters in the packaging design data, and dividing the nominal geometric model into a plurality of structure regions based on the structure parameters and the nominal geometric model; extracting material physical parameters in the packaging design data, and performing physical parameter setting operations on each structure region based on the material physical parameters to obtain a physical property model; performing finite element subdivision operations on the physical property model to obtain the component reference model.

3. The method of claim 2, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, The method comprises: based on the TSV through hole coordinates, obtaining a scanning path sequence, and based on the scanning path sequence and a pre-constructed ultrasonic excitation signal, performing the following operations on each actual TSV through hole: applying the ultrasonic excitation signal to the actual TSV through hole using a pre-constructed ultrasonic transducer array in the ultrasonic resonance scanner, and collecting resonance response signals generated by the actual TSV through hole to which the ultrasonic excitation signal is applied using the ultrasonic transducer array; performing frequency domain conversion operations on the resonance response signals to obtain resonance response spectrograms; based on the resonance response spectrograms, obtaining actual resonance parameters, wherein the actual resonance parameters include actual amplitudes, actual resonance frequencies and actual quality factors; summarizing the actual resonance parameters to obtain the actual resonance parameter set.

4. The method of claim 3, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, The method comprises: extracting a spectrum peak with a maximum amplitude in the resonance response spectrum diagram to obtain a main resonance peak; confirming the amplitude of the main resonance peak as an actual amplitude and confirming the frequency of the main resonance peak as an actual resonance frequency; obtaining a half amplitude based on the actual amplitude, obtaining two half-width points based on the half amplitude, and calculating a half-width point frequency difference based on the two half-width points; calculating a ratio of the actual resonance frequency and the half-width point frequency difference to obtain an actual quality factor.

5. The method of claim 4, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, The difference parameter set is obtained based on the theoretical resonance parameter set and the actual resonance parameter set, and includes: extracting a theoretical resonance parameter in the theoretical resonance parameter set, wherein the theoretical resonance parameter includes resonance; for each theoretical resonance parameter, the following operations are performed: extracting an actual resonance parameter corresponding to the theoretical resonance parameter, and calculating a difference parameter based on the theoretical resonance parameter and the actual resonance parameter, wherein the difference parameter includes a resonance frequency offset, an amplitude attenuation rate, and a quality factor change rate; summarizing the difference parameters to obtain the difference parameter set. 6.The method for non-destructive testing of TSV via sidewall defects in 3D CoWoS package of claim 5, wherein, The difference parameter set is determined whether to satisfy a preset allowable difference condition, and includes: extracting an allowable difference range in the allowable difference condition, wherein the allowable difference range includes an allowable frequency offset range, an allowable amplitude attenuation rate, and an allowable quality factor change rate; for each difference parameter, the following operations are performed: determining whether the resonance frequency offset is in the allowable frequency offset range, if the resonance frequency offset is in the allowable frequency offset range, determining whether the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate, if the amplitude attenuation rate is less than or equal to the allowable amplitude attenuation rate, determining whether the quality factor change rate is less than or equal to the allowable quality factor change rate, if the quality factor change rate is less than or equal to the allowable quality factor change rate, the difference parameter is confirmed to be in the allowable difference range; otherwise, the difference parameter is confirmed to be not in the allowable difference range; if each difference parameter is in the allowable difference range, the difference parameter set is confirmed to satisfy the allowable difference condition, otherwise, the difference parameter set is confirmed to not satisfy the allowable difference condition.

7. The method of claim 6, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, The defect information set is determined whether to satisfy a preset repairable condition, and includes: extracting defect information in the defect information set in sequence, wherein the defect information includes a defect type, a defect depth, and a defect volume, and the defect information is operated as follows: determining whether the defect type belongs to a preset repairable defect type in the repairable condition, if the defect type belongs to the repairable defect type, determining whether the defect depth is less than or equal to a preset repairable defect depth in the repairable condition, if the defect depth is less than or equal to the repairable defect depth, determining whether the defect volume is less than or equal to a preset repairable defect volume in the repairable condition, if the defect volume is less than or equal to the repairable defect volume, the defect information is confirmed to be repairable defect information, otherwise, the defect information is confirmed to be non-repairable defect information; if all defect information in the defect information set is repairable defect information, the defect information set is confirmed to satisfy the repairable condition, otherwise, the defect information set is confirmed to not satisfy the repairable condition.

8. The method of claim 7, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, The defect repair operation is performed on the repairable element based on the electrolyte and the electroplating repair equipment, and includes: injecting the electrolyte into the repairable element to obtain a to-be-repaired element; acquire a set of to-be-repaired via hole coordinates based on the set of defect information, wherein the set of to-be-repaired via hole coordinates comprises a plurality of to-be-repaired via hole coordinates; perform the following operation on each to-be-repaired via hole coordinate in the to-be-repaired element: acquire a probe working coordinate based on the to-be-repaired via hole coordinate and the defect depth, introduce a pre-constructed repair probe in the electroplating repair equipment to the to-be-repaired via hole corresponding to the probe working coordinate based on the probe working coordinate, perform an electroplating repair operation by using the repair probe in the to-be-repaired via hole, and monitor a voltage difference between the repair probe and the to-be-repaired via hole by using a pre-constructed voltage sensing unit in the repair probe while performing the electroplating repair operation to obtain a real-time voltage difference; if the real-time voltage difference is less than or equal to a preset filling completion voltage difference, stop the electroplating operation; otherwise, return to the step of performing the electroplating repair operation by using the repair probe in the to-be-repaired via hole.

9. The method of claim 8, wherein the TSV via sidewall defect nondestructive testing method in the 3D CoWoS package is characterized by, the step of performing the electroplating repair operation by using the repair probe in the to-be-repaired via hole comprises: acquire electrolyte information, and acquire an electrolyte limit current based on the electrolyte information and a pre-constructed electrolyte limit current calculation formula; acquire a defect limit current based on the defect type, the defect volume, and the intelligent analysis model; acquire a maximum allowable current based on the electrolyte limit current and the defect limit current; acquire a final working current based on the maximum allowable current and a preset safety factor; start the repair probe to perform the electroplating repair operation at the final working current.

10. A non-destructive testing system for TSV through-hole sidewall defects in a 3DCoWoS package, characterized in that, the system comprises: a base and modeling module configured to acquire a semiconductor element, packaging design data, an ultrasonic resonance scanner, an intelligent analysis model, an electrolyte, and an electroplating repair equipment, construct an element reference model based on the packaging design data, and perform a simulated ultrasonic resonance detection operation on the element reference model to obtain a set of theoretical resonance parameters; a resonance detection module configured to perform an actual ultrasonic resonance detection operation on the semiconductor element by using the ultrasonic resonance scanner to obtain a set of actual resonance parameters, wherein the semiconductor element comprises a plurality of actual TSV vias, and acquire a set of difference parameters based on the set of theoretical resonance parameters and the set of actual resonance parameters; a defect analysis module configured to determine whether the set of difference parameters satisfies a preset allowable difference condition, confirm the semiconductor element as a finished product element if the set of difference parameters satisfies the preset allowable difference condition, and perform a defect analysis operation on the set of difference parameters by using the intelligent analysis model to obtain a set of defect information if the set of difference parameters does not satisfy the allowable difference condition; an electroplating repair module configured to determine whether the set of defect information satisfies a preset repairable condition, confirm the semiconductor element as a repairable element if the set of defect information satisfies the repairable condition, perform a defect repair operation on the repairable element based on the electrolyte and the electroplating repair equipment to obtain a repaired semiconductor element, and return to the step of performing the actual ultrasonic resonance detection operation on the semiconductor element with the repaired semiconductor element as the semiconductor element.

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