Multi-port interferometer device, on-chip optical network structure and photonic integrated circuit

Abstract

The invention provides a multi-port interferometer device, an on-chip optical network structure and a photon integrated circuit. The device comprises a plurality of interferometer units which are connected in sequence; the interferometer unit comprises a first interferometer subunit and a second interferometer subunit, the first interferometer subunit comprises n symmetric interferometers, 2n input ends and output ends, the second interferometer subunit comprises n + 1 symmetric interferometers, 2 (n + 1) input ends and output ends, and the input end of the first interferometer subunit serves as the output end of the interferometer unit; the output end of the first interferometer subunit is connected with the input end of the second interferometer subunit; the output end of the second interferometer subunit is used as the output end of the interferometer unit; the input end of the first interferometer unit is used as the input end of the multi-port interferometer device; and the output end of the last interferometer unit is used as the output end of the multi-port interferometer device. The calibration degree of the on-chip optical network structure is improved, so that the fidelity of the photon integrated circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of optical networks on chip, and in particular to a multi-port interferometer device, an optical network on chip structure and a photonic integrated circuit. BACKGROUND

[0002] Large-scale general photonic integrated circuits require an efficient reconfigurable linear optical network to perform matrix-vector multiplication tasks, or a wide range of applications involving signal transmission and processing. Even the most advanced optical manufacturing technology is inevitably affected by loss and error, which makes it a continuous challenge to accurately map matrix operations in general photonic integrated circuits.

[0003] The existing architecture of the reconfigurable linear optical network on chip generally adopts a triangular and rectangular topology architecture design, and n-order unitary matrix can be achieved by cascading n(n-1) / 2 Mach-Zehnder interferometers to perform matrix-vector multiplication tasks. However, as the scale increases, the loss of photonic integrated circuit links intensifies, and the linear optical network based on the existing architecture is insufficient to meet the fidelity requirements of information processing applications. Although the loss of Mach-Zehnder symmetric interferometers can be reduced to improve the fidelity performance, the inherent existence of differential paths hinders the realization of high fidelity, and simply expanding the existing linear optical network is impractical due to inevitable manufacturing variations and dynamic errors. SUMMARY

[0004] The present application aims to provide a multi-port interferometer device, an optical network on chip structure and a photonic integrated circuit to solve the above technical problems, and to improve the calibration degree of the optical network on chip structure in the present application through the multi-port interferometer device, thereby improving the fidelity of the photonic integrated circuit in the process of processing light source signals.

[0005] In order to solve the above technical problems, the present application provides a multi-port interferometer device, comprising: a plurality of interferometer units connected in sequence; for each of the interferometer units, comprising: a first interferometer sub-unit and a second interferometer sub-unit, the first interferometer sub-unit comprising n symmetric interferometers, 2n input terminals and 2n output terminals, the second interferometer sub-unit comprising n+1 symmetric interferometers, 2(n+1) input terminals and 2(n+1) output terminals, wherein: the 2n input terminals of the first interferometer sub-unit serve as the output terminals of the interferometer unit; the 2n output terminals of the first interferometer sub-unit are connected to the 2(n+1) input terminals of the second interferometer sub-unit; the 2(n+1) output terminals of the second interferometer sub-unit serve as the output terminals of the interferometer unit; the input terminal of the first interferometer unit located at the first position serves as the input terminal of the multi-port interferometer device; and the output terminal of the last interferometer unit serves as the output terminal of the multi-port interferometer device.

[0006] In the above scheme, the amplitude and phase regulation of the light source signal is specifically implemented by the symmetric interferometer in the multi-port interferometer. Through the connection mode of the above interferometer unit, the first interferometer sub-unit, the second interferometer sub-unit and the symmetric interferometer, it can be ensured that each symmetric interferometer in the entire multi-port interferometer has a complete diagonal line to perform the calibration process. Unlike the existing structure design, the symmetric interferometer on the other non-main diagonal line usually needs to be connected in series with an adjacent symmetric interferometer to perform calibration and requires an additional calibration method, which also has the risk of calibration error. In addition, by introducing the symmetric interferometer, the footprint area of a phase shifter is reduced compared to the asymmetric interferometer in the horizontal deployment. In summary, the present application can improve the calibration efficiency and accuracy of the multi-port interferometer, thereby improving the calibration degree of the optical network-on-chip structure, thereby reducing the errors in the processing of the light source signal caused by calibration errors, so that the photonic integrated circuit provided with the optical network-on-chip structure can improve the fidelity during processing of the light source signal.

[0007] The present application also provides an optical network-on-chip structure, comprising a light source input array, a light source output array, a circuit control module and a multi-port interferometer device, wherein:

[0008] The output end of the light source input array is connected to the input end of the multi-port interferometer device;

[0009] The output end of the multi-port interferometer device is connected to the input end of the light source output array;

[0010] The phase end of the multi-port interferometer device is connected to the output end of the circuit control module.

[0011] In the above scheme, the amplitude and phase regulation of the light source signal is specifically implemented by the symmetric interferometer in the multi-port interferometer. The circuit control module can send a control signal to each symmetric interferometer unit for dynamic regulation of the light source signal, thereby controlling the transmission path and interference effect of the light source signal. That is, the input, processing and output of the light source signal are realized by the light source input array, the circuit control module, the multi-port interferometer and the light source output array. In addition, based on the introduction of the multi-port interferometer which can improve the calibration efficiency and accuracy, the calibration degree of the optical network-on-chip structure is improved.

[0012] Further, the multi-port interferometer device comprises a second interferometer sub-unit, the second interferometer sub-unit comprises a symmetric interferometer, and the symmetric interferometer having an unconnected port in the second interferometer sub-unit is used as a calibration interferometer;

[0013] The unconnected ports of the calibration interferometer located on the left side of the multi-port interferometer device extend to the light source input array, and the unconnected ports of the calibration interferometer located on the right side of the multi-port interferometer device extend to the light source output array.

[0014] In the above scheme, the unconnected ports of the calibration interferometer are connected to the light source input / output array through the end face coupler, and the selection of the light source input array and the light source output array is considered. Since the end face coupler can be combined with a fiber array, compared with a grating coupler or a single fiber coupling, the fiber array is more convenient and has better tolerance for coupling conditions. The preset split axis in the multi-port interferometer device as the division standard can prevent the ports from crossing when they are extended.

[0015] Further, the unconnected ports of the calibration interferometer close to the light source input array are connected to the output end of the light source input array through an end face coupler based on a cross waveguide.

[0016] The unconnected ports of the calibration interferometer close to the light source output array are connected to the input end of the light source output array through an end face coupler based on a cross waveguide.

[0017] In the above scheme, since the multi-port interferometer in the existing architecture does not introduce additional interferometers and thus does not have new input / output ports, there is no scheme design for the light source array in this case. By deploying the input ports and output ports on both sides, the left side is for input and the right side is for output, the input and output waveguides will cross, which can be solved by a cross waveguide. The design of introducing a cross waveguide can solve the problem of crossing between the output ports and the input ports of adjacent calibration interferometers, thereby optimizing the routing path of the optical signal, reducing signal interference and loss. This design improves the efficiency and accuracy of optical signal transmission, and simplifies the structure of the optical network.

[0018] Further, the unconnected ports of the calibration interferometer are connected to a grating coupler.

[0019] In the above scheme, connecting all unconnected ports to a grating coupler can provide a unified optical signal input / output interface, simplifying the design and manufacturing process of the optical network. The use of a grating coupler can improve the coupling efficiency of the optical signal and reduce signal loss.

[0020] Further, the symmetric interferometer includes an integrated optical waveguide device, a beam splitter device, and a thermo-optic phase shifter device, wherein:

[0021] The integrated optical waveguide device is connected to the beam splitter device and the thermo-optic phase shifter device in sequence.

[0022] In the above scheme, the transmission of optical signals is realized by integrated optical waveguide devices, the coherent splitting and combining of light is realized by beam splitter devices, and the phase of light waves is precisely controlled by optical phase shifters.

[0023] Further, the integrated optical waveguide device includes a first integrated optical waveguide and a second integrated optical waveguide; the beam splitter device includes a first beam splitter and a second beam splitter; the thermo-optic phase shifter device includes a first thermo-optic phase shifter and a second thermo-optic phase shifter, wherein:

[0024] The first integrated optical waveguide is connected in sequence to the first beam splitter, the first thermo-optic phase shifter, and the second beam splitter;

[0025] The second integrated optical waveguide is connected in sequence to the first beam splitter, the second thermo-optic phase shifter, and the second beam splitter;

[0026] The optical waveguide input end of the first integrated optical waveguide is used as the first input end of the symmetric interferometer, and the optical waveguide output end of the first integrated optical waveguide is used as the first output end of the symmetric interferometer;

[0027] The optical waveguide input end of the second integrated optical waveguide is used as the second input end of the symmetric interferometer, and the optical waveguide output end of the second integrated optical waveguide is used as the second output end of the symmetric interferometer.

[0028] In the above scheme, the structure of the symmetric interferometer is described in detail, including the configuration of integrated optical waveguides, beam splitters, and thermo-optic phase shifters. This structure design can realize precise phase control of optical signals, thereby realizing complex optical signal processing functions.

[0029] Further, the first beam splitter and the second beam splitter are 50:50 beam splitters.

[0030] In the above scheme, the use of 50:50 beam splitters can ensure that optical signals are evenly distributed when splitting, which is crucial for precise optical signal control and interference effects. This design can improve the performance and reliability of optical networks.

[0031] Further, the first thermo-optic phase shifter and the second thermo-optic phase shifter are respectively provided with a phase shifter input end as a phase input end of the symmetric interferometer.

[0032] In the above scheme, the thermo-optic phase shifter is provided with an independent phase shifter input end, which can provide more precise phase control capability. This design allows independent phase adjustment of each interferometer unit, thereby realizing more complex optical signal processing tasks.

[0033] The application also provides a photonic integrated circuit, which is provided with the on-chip optical network structure according to any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A structural block diagram of a multi-port interferometer device provided by an embodiment of the application;

[0035] Figure 2 A structural block diagram of a multi-port interferometer in an on-chip optical network structure taking a 6-order unitary matrix as an example and provided by an embodiment of the application.

[0036] Figure 3 A structural schematic diagram of a symmetric Mach-Zehnder interferometer in an on-chip optical network structure provided by an embodiment of the application.

[0037] Figure 4 A structural block diagram of an interferometer unit in an on-chip optical network structure provided by an embodiment of the application.

[0038] Figure 5 A schematic diagram of a light source input array and a light source output array adopting an end face coupler and provided by an embodiment of the application.

[0039] Figure 6 A schematic diagram of a multi-port interferometer adopting a cross waveguide structure and a light source input array and a light source output array adopting an end face coupler and provided by an embodiment of the application.

[0040] Figure 7 A schematic diagram of a light source input array and a light source output array adopting a grating coupler and provided by an embodiment of the application.

[0041] Figure 8 A schematic diagram of a light source input array and a light source output array partially adopting an end face coupler and partially adopting a grating coupler and provided by an embodiment of the application.

[0042] Figure 9 A comparison diagram of fidelity simulation results of an on-chip optical network structure of the application and an existing on-chip optical network structure and provided by an embodiment of the application.

[0043] REFERENCE SIGNS:

[0044] 1. A light source input array;

[0045] 2. A multi-port interferometer device; 20, an interferometer unit; 201, a first interferometer subunit; 202, a second interferometer subunit; 21, a symmetric interferometer; 211, a first integrated optical waveguide; 212, a second integrated optical waveguide; 213, a first beam splitter; 214, a second beam splitter; 215, a first thermo-optic phase shifter; 216, a second thermo-optic phase shifter.

[0046] 3. an array of light source outputs;

[0047] 4. a circuit control module. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0049] Referring to Figure 1 and Figure 2 The present embodiment provides a multi-port interferometer device 2, comprising:

[0050] a plurality of interferometer units 20 connected in sequence;

[0051] For each of the interferometer units 20, comprising: a first interferometer subunit 201 and a second interferometer subunit 202, the first interferometer subunit 201 comprising n symmetric interferometers 21, 2n input ends and 2n output ends, the second interferometer subunit 202 comprising n+1 symmetric interferometers 21, 2(n+1) input ends and 2(n+1) output ends, wherein:

[0052] The 2n input ends of the first interferometer subunit 201 serve as the output ends of the interferometer unit 20;

[0053] The 2n output ends of the first interferometer subunit 201 are connected with the 2(n+1) input ends of the second interferometer subunit 202;

[0054] The 2(n+1) output ends of the second interferometer subunit 202 serve as the output ends of the interferometer unit 20;

[0055] The input end of the interferometer unit 20 at the first position serves as the input end of the multi-port interferometer device 2;

[0056] The output end of the interferometer unit 20 at the last position serves as the output end of the multi-port interferometer device 2.

[0057] In the above scheme, the amplitude and phase regulation of the light source signal is specifically implemented by the symmetric interferometer 21 in the multi-port interferometer device 2. Through the connection mode of the above interferometer unit 20, the first interferometer sub-unit 201, the second interferometer sub-unit 202, and the symmetric interferometer 21, it can be ensured that each symmetric interferometer 21 in the entire multi-port interferometer device 2 has a complete diagonal line to perform the calibration process. It does not need to be like the existing structure design: for other symmetric interferometers 21 on the non-main diagonal line, it usually needs to be connected in series with an adjacent symmetric interferometer 21 to perform calibration and requires an additional calibration method, and there is also a risk of calibration error. In addition, by introducing the symmetric interferometer 21, compared with the asymmetric interferometer, one phase shifter area is reduced in the horizontal deployment. In summary, the present application can improve the calibration efficiency and accuracy of the multi-port interferometer device 2, and then improve the calibration degree of the optical network-on-chip structure, thereby reducing the errors in the processing of the light source signal caused by the calibration error, so that the photonic integrated circuit provided with the optical network-on-chip structure can improve the fidelity in the process of processing the light source signal.

[0058] Further, the n-order multi-port interferometer device in the prior art includes n(n-1) / 2 interferometers, while the present scheme includes n(n+1) / 2 symmetric interferometers 21 for an n-order multi-port interferometer device. In the present scheme, the additional symmetric interferometers 21 can improve the calibration degree and fidelity of the n-order multi-port interferometer device 2. Then the symmetric interferometer 21 has a more compact structure and provides a loss-independent light regulation function.

[0059] The embodiment also provides an optical network-on-chip structure, which includes a light source input array 1, a light source output array 3, a circuit control module 4, and a multi-port interferometer device, wherein:

[0060] The output end of the light source input array 1 is connected with the input end of the multi-port interferometer device;

[0061] The output end of the multi-port interferometer device is connected with the input end of the light source output array 3;

[0062] The phase end of the multi-port interferometer device is connected with the output end of the circuit control module 4.

[0063] In the above scheme, the amplitude and phase regulation of the light source signals is specifically implemented by the symmetric interferometers in the multi-port interferometer device 2. The circuit control module 4 can send control signals to each symmetric interferometer for dynamic regulation of the light source signals, thereby controlling the transmission path and interference effect of the light source signals. That is, the input, processing and output of the light source signals are collectively realized by the light source input array 1, the circuit control module 4, the multi-port interferometer device 2 and the light source output array 3. In addition, based on the multi-port interferometer device 2 which can improve the calibration efficiency and accuracy, the calibration degree of the optical network-on-chip structure is further improved.

[0064] In the above scheme, the phase regulation of the light source signals is specifically implemented by the symmetric interferometers 21 in the multi-port interferometer device. The circuit control module 4 can send control signals to each symmetric interferometer 21 for dynamic regulation of the light source signals, thereby controlling the transmission path and interference effect of the light source signals. That is, the input, processing and output of the light source signals are collectively realized by the light source input array 1, the circuit control module 4, the multi-port interferometer device 2 and the light source output array 3.

[0065] Further, referring to Figure 3 , the light source input array 1 is connected to the multi-port interferometer device and inputs multiple unit amplitude light source signals in parallel. The multi-port interferometer device includes a plurality of cascaded symmetric Mach-Zehnder interferometers (i.e., symmetric interferometers 21) and a circuit control module 4, which is used to realize reconfigurable matrix multiplication operation and output the operation result to the light source output array 3. The light source output array 3 is connected to the multi-port interferometer device, collects the amplitude light source signals of each symmetric interferometer 21, and obtains the matrix operation result.

[0066] Further, it can be understood that for an n x n multi-port interferometer device, n(n+1) / 2 symmetric interferometers 21 (symmetric Mach-Zehnder interferometers MZIs) are required, compared with n(n-1) / 2 MZIs in the prior art. Here, n additional MZIs are introduced. For example, assuming there are 21 symmetric interferometers 21, i.e., 21 symmetric Mach-Zehnder interferometers, the 21 symmetric Mach-Zehnder interferometers are cascaded to form a 6-order multi-port interferometer device. Among them, 15 main symmetric Mach-Zehnder interferometers are cascaded to basically realize a 6-order unitary matrix transformation, and 6 additional symmetric Mach-Zehnder interferometers are introduced, which are respectively placed on the upper and lower sides of the multi-port interferometer device. It can be understood that the number of additional MZIs introduced is related to the number of ports n, and n / 2 additional MZIs are introduced on the upper and lower sides of the multi-port interferometer device, so there are n in total. The transmission matrix U of the 6-order unitary matrix can be represented as: U=D·θ 21 ·T MZI-15 ·T MZI-13 ·θ20 ·T MZI-14 ·T MZI-12 ·T MZI-10 ·T MZI-8 ·θ 19 ·θ 18 ·T MZI-11 ·T MZI-9 ·T MZI-7 ·T MZI--5 ·T MZI-3 ·θ 17 ·T MZI-6 ·T MZI-4 ·T MZI-2 ·θ 16 ·T MZI-1 .

[0067] Wherein, U is a matrix realized by the multi-port interferometer device, and D is a diagonal matrix for realizing an arbitrary unitary matrix, which is generally required to be added behind the multi-port interferometer device in actual deployment, or can be simplified as a diagonal matrix D with all elements being 1.T MZI-n represents Figure 2 The transmission matrix of the corresponding numbered symmetrical Mach-Zehnder interferometer in n is represented by another 6 additional corresponding numbers introduced into the symmetrical Mach-Zehnder interferometer, and the phase control function of the thermo-optic phase shifter is realized by fixing the differential mode part. It can be understood that the subsequent confirmation of the phase control of the thermo-optic phase shifter is performed after the calibration process is completed, and then the matrix U desired to be realized is decomposed into each MZI in the electrical domain (computer), and then into the configuration of the two phase shifters in each MZI, and the phase control can be completed by controlling the corresponding electrical signal values of the circuit module.

[0068] In another embodiment, the symmetrical interferometer 21 comprises: an integrated optical waveguide device, a beam splitter device, and a thermo-optic phase shifter device, wherein:

[0069] The integrated optical waveguide device is connected to the beam splitter device and the thermo-optic phase shifter device in sequence.

[0070] In another embodiment, with reference to Figure 4 , the integrated optical waveguide device comprises a first integrated optical waveguide 211 and a second integrated optical waveguide; the beam splitter device comprises a first beam splitter and a second beam splitter; and the thermo-optic phase shifter device comprises a first thermo-optic phase shifter and a second thermo-optic phase shifter, wherein:

[0071] The first integrated optical waveguide 211 is connected to the first beam splitter 213, the first thermo-optic phase shifter 215, and the second beam splitter 214 in sequence;

[0072] The second integrated optical waveguide 212 is connected to the first beam splitter 213, the second thermo-optic phase shifter 216 and the second beam splitter 214 in sequence.

[0073] The optical waveguide input end of the first integrated optical waveguide 211 is used as the first input end of the symmetric interferometer 21, and the optical waveguide output end of the first integrated optical waveguide 211 is used as the first output end of the symmetric interferometer 21.

[0074] The optical waveguide input end of the second integrated optical waveguide 212 is used as the second input end of the symmetric interferometer 21, and the optical waveguide output end of the second integrated optical waveguide 212 is used as the second output end of the symmetric interferometer 21.

[0075] In the above embodiment, the symmetric interferometer 21 is a symmetric Mach-Zehnder interferometer, which includes the first integrated optical waveguide 211, the second integrated optical waveguide 212, the first beam splitter 213, the second beam splitter 214, the first thermo-optic phase shifter 215 and the second thermo-optic phase shifter 216, wherein the first integrated optical waveguide 211 or the second integrated optical waveguide 212 is affected by the propagation loss α p and the waveguide length l, the first thermo-optic phase shifter and the second thermo-optic phase shifter based on the thermo-optic effect are affected by the optical loss α m caused by the absorption loss, the first beam splitter 213 and the second beam splitter 214 can be implemented by a directional coupler or a multimode interferometer, which are affected by the coupling loss α DC / MMI . The high-fidelity implementation of the entire on-chip optical network structure is achieved by loss isolation from the single to the entire architecture level, so the analysis of these losses is needed. In order to make the first beam splitter 213 and the second beam splitter 214 both 50:50 beam splitters, so as to accurately divide the light beam input therein into two beams of equal intensity, the transmission matrix of the first beam splitter 213 and the second beam splitter 214 is set as:

[0076]

[0077] wherein i is the imaginary part, when the cross-coupling coefficient k is 0.5 and the coupling loss α DC / MMI is 1, the splitter can be simplified to a perfect 50:50 splitter. The transmission matrix of the first thermo-optic phase shifter and the second thermo-optic phase shifter placed in parallel is set as:

[0078]

[0079] wherein a m is the optical loss caused by the absorption loss of the thermo-optic phase shifter based on the thermo-optic effect, and θ t and θ bare the phase values realized by two phase shifters, generally ∈ [0, 2π], i is imaginary number. t and b mean top and bottom, i.e. the upper arm (the first thermo-optic phase shifter) and the lower arm (the second thermo-optic phase shifter). If the input signal [I1, I2] T to the symmetric Mach-Zehnder interferometer (i.e. the symmetric interferometer 21), where T is the transpose matrix, the output signal [O1, O2] T is obtained, and has:

[0080]

[0081] where k1, k2 are the cross-coupling coefficients of the two beam splitters, generally k1=k2=0.5. a DC / MMI is the coupling loss. i is imaginary part, a m is the thermo-optic phase shifter based on the thermo-optic effect suffers from optical loss caused by absorption loss, θ t and θ b are the phase values realized by two phase shifters, α p is the propagation loss, l is the waveguide length, and Δθ represents the differential mode part of the phase difference between the first thermo-optic phase shifter and the second thermo-optic phase shifter placed in parallel: Δθ=(θ t -θ b ) / 2, and θ m represents the common mode part: θ m =(θ t +θ b) / 2. The first thermo-optic phase shifter 215 and the second thermo-optic phase shifter 216 are respectively provided with a phase shifter input end as a phase input end of the symmetric interferometer 21. The output end of the circuit control module 4 is connected to the phase input end, and the phase information of the thermo-optic phase shifter is adjusted in real time by communicating between the field programmable gate array in the circuit control module 4 and the upper computer, thereby adjusting the voltage of the heater. When the differential mode part Δθ is fixed as π, the 2x2 symmetric Mach-Zehnder interferometer can be degenerated into a phase shifter that inputs from the upper (lower) port and outputs from the upper (lower) port, and the phase information is adjusted through the common mode part. The matrix U to be realized is decomposed into each MZI, and then into the configuration of the two phase shifters in each MZI, and the corresponding electrical signal value is distributed by controlling the circuit module, so that the phase control of the phase shifter can be completed by fixing the differential mode part. It can be understood that the high-fidelity implementation of the entire on-chip optical network structure is realized by loss isolation from the single to the entire architecture level. Among them, the single level loss isolation. From the above formula, it can be found that the letters involved in the straight waveguide loss, the coupler loss and the thermo-optic phase shifter loss are all outside the 2x2 matrix, that is, these parameters do not affect the phase distribution in the matrix, thereby realizing the single level loss isolation. The asymmetric interferometer 21 generally places a thermo-optic phase shifter in the outer arm (for example, the upper) and the inner arm (for example, the lower), respectively. Then, the light that passes through the thermo-optic phase shifter of the outer arm (for example, the upper) after entering the upper input port, passes through the coupler, and then passes through the thermo-optic phase shifter of the inner arm (for example, the lower) and the coupler again, will be affected by the loss of the two thermo-optic phase shifters. The light that enters from the lower input port, passes through the coupler, enters the inner arm (the upper), and then passes through the coupler for output, will only be affected by the loss of the straight waveguide and the coupler. That is, the light source in different paths will have different losses due to the asymmetric distribution of the thermo-optic phase shifters, so the single level loss isolation cannot be realized.

[0082] In another embodiment, the symmetric interferometer 21 in the second interferometer subunit 202 with an unconnected port is used as a calibration interferometer.

[0083] Taking the preset segmentation axis in the multi-port interferometer device as the division standard, the unconnected port of the calibration interferometer located on the left side of the multi-port interferometer device 2 extends to the light source input array 1, and the unconnected port of the calibration interferometer located on the right side of the multi-port interferometer device 2 extends to the light source output array 3.

[0084] It should be noted that in the multi-port interferometer device 2, some ports of the symmetrical interferometers 21 are not connected, so they need to be processed to avoid problems in the multi-port interferometer device 2. Taking a 4th-order linear optical network as an example, after the multi-port interferometer device 2 is configured according to the architecture of the present application, the light source input array 1 and the light source output array 3 can be configured in the manner of end-face couplers, as shown in Figure 5 . Among them, the 8 input ports and the 8 output ports of the multi-port interferometer device are respectively extended to the left and right sides through a plurality of parallel and curved integrated optical waveguides. It can be understood that the left and right sides are distinguished according to the preset division axis, and then connected with 16 end-face couplers to form the light source input array 1 and the light source output array 3. The unconnected ports of the calibration interferometers divided to the left side may have output ports, and by analogy, the unconnected ports of the calibration interferometers divided to the right side may have input ports. It can be understood that, for example, referring to Figure 2 , the symmetrical interferometers numbered 4, 7, 11, 14, 18 and 21 are taken as calibration interferometers. It should be noted that, Figures 1-8 , I is an input port and O is an output port.

[0085] In another embodiment, the unconnected ports of the calibration interferometers close to the output ends of the light source input array 1 are connected to the output ends of the light source input array 1 through end-face couplers based on cross waveguides;

[0086] The unconnected ports of the calibration interferometers close to the input ends of the light source output array 3 are connected to the input ends of the light source output array 3 through end-face couplers based on cross waveguides.

[0087] It should be noted that, as shown in Figure 6 , the light source input array 1 and the light source output array 3 can also be configured in the manner of end-face couplers plus cross waveguides. Among them, 1 cross waveguide is added to the upper and lower sides of the 4th-order multi-port interferometer device 2, solving the cross situation of the output ports of the two Mach-Zehnder interferometers. Then, the light source input array 1 and the light source output array 3 can be configured in this way, which can realize that the 8 input ports are placed on the left side of the 4th-order multi-port interferometer device 2 and the 8 output ports are placed on the right side of the 4th-order multi-port interferometer device 2. Because the multi-port interferometer device 2 in the original architecture does not introduce those additional MZIs and thus does not have those new input and output ports, there is no scheme design for the light source array in this case. Figure 6 The design purpose is to deploy the input ports and the output ports on the two sides respectively, the left side for input and the right side for output, so the cross situation of the input and output waveguides will be encountered, which can be solved by cross waveguides.

[0088] Further, as shown in Figure 7As shown, the light source input array 1 and the light source output array 3 can be configured in the manner of grating couplers. Among them, 16 grating couplers are directly connected with 8 input ports and 8 output ports of the 4-order multi-port interferometer device 2, to form the light source input array 1 and the light source output array 3. Since the end face coupler has a position limitation, the ports need to be parallel to a cross section. The position of the grating coupler can be arbitrary, and therefore the cross waveguide and other conditions do not need to be considered.

[0089] In another embodiment, the unconnected ports of the calibration interferometer are connected with grating couplers.

[0090] It should be noted that the light source input array 1 and the light source output array 3 can be configured in the manner of grating couplers plus end face couplers. Among them, 8 end face couplers are connected with 4 input ports and 4 output ports for performing 4-order unitary matrix transformation, and 8 grating couplers are connected with the remaining 8 ports. Figure 8 For example, the 4x4 multi-port interferometer device 2 is a 4x4 multi-port interferometer device 2, and therefore the ports for 4x4 linear optical network input and output are actually I 3-6 and O 3-6 Therefore, the four input and 4 output ports can be connected with the fiber array by the end face coupler scheme, and the additional ports can be connected only by the grating coupler scheme, since they do not undertake the task of 4x4 linear optical network input and output.

[0091] The application also provides a photonic integrated circuit, which is provided with an on-chip optical network structure as described above.

[0092] It can be understood that the application also provides a signal processing method applied to the photonic integrated circuit as described above, and the method is as follows:

[0093] Inputting a light source signal into the photonic integrated circuit, so that the on-chip optical network structure in the photonic integrated circuit performs matrix vector multiplication calculation on the light source signal to obtain a target signal.

[0094] The existing architecture design takes a rectangular architecture as an example, and the fidelity simulation of random matrix allocation of the architecture design proposed by the application is carried out, and the result is as Figure 9 shown in the following table. Among them, the propagation loss a p of the integrated optical waveguide is set to 0.01 dB / cm, the waveguide length l required by a single symmetric Mach-Zehnder interferometer is 900 μm, the optical loss a m of the thermo-optic phase shifter caused by absorption loss is 0.01 dB, and the coupling loss a MMIThe unit amplitude light source signal is inputted by the light source input array 1 of n ports uniformly and in parallel, and the fidelity between the expected output and the actual output result at the light source output array 3 is configured and distributed through 10000 times of random generation matrix elements. It can be seen that, compared with the average fidelity of the linear optical network based on the existing architecture design, the on-chip optical network structure based on the architecture design of the application can perform high-fidelity matrix vector multiplication tasks, and keep 100% theoretical fidelity as the number of ports n increases. The architecture design of the application makes the linear optical network more compact in the horizontal layout, thereby further reducing the cost.

[0095] The above is the preferred embodiment of the application. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the application, several improvements and refinements can be made, which are also considered within the protection scope of the application.

Claims

1. A multi-port interferometer device, characterized by, Comprising: a plurality of interferometer units connected in sequence; for each of the interferometer units, comprising: a first interferometer subunit and a second interferometer subunit, the first interferometer subunit comprising n symmetric interferometers, 2n input ends and 2n output ends, the second interferometer subunit comprising n+1 symmetric interferometers, 2(n+1) input ends and 2(n+1) output ends, wherein: the 2n input ends of the first interferometer subunit are output ends of the interferometer unit; the 2n output ends of the first interferometer subunit are connected to the 2(n+1) input ends of the second interferometer subunit; the 2(n+1) output ends of the second interferometer subunit are output ends of the interferometer unit; the input end of the first interferometer unit is an input end of the multi-port interferometer device; the output end of the last interferometer unit is an output end of the multi-port interferometer device.

2. An optical network-on-chip structure, characterized by, Comprising a light source input array, a light source output array, a circuit control module and a multi-port interferometer device as claimed in claim 1, wherein: the output end of the light source input array is connected to the input end of the multi-port interferometer device; the output end of the multi-port interferometer device is connected to the input end of the light source output array; the phase end of the multi-port interferometer device is connected to the output end of the circuit control module.

3. An optical network-on-chip structure as claimed in claim 2, characterized in that, The multi-port interferometer device comprises a second interferometer subunit, the second interferometer subunit comprises a symmetric interferometer, and the symmetric interferometer in the second interferometer subunit with an unconnected port is used as a calibration interferometer; Taking a preset division axis in the multi-port interferometer device as a division standard, the unconnected port of the calibration interferometer on the left side of the multi-port interferometer device extends to the light source input array, and the unconnected port of the calibration interferometer on the right side of the multi-port interferometer device extends to the light source output array.

4. An optical network-on-chip structure according to claim 3, wherein, The unconnected port of the calibration interferometer close to the light source input array is connected to the output end of the light source input array through an end face coupler based on a cross waveguide; The unconnected port of the calibration interferometer close to the light source output array is connected to the input end of the light source output array through an end face coupler based on a cross waveguide.

5. The optical network-on-chip structure of claim 3, wherein, The unconnected port of the calibration interferometer is connected to a grating coupler.

6. The optical network-on-chip structure of claim 3, wherein, The symmetric interferometer comprises an integrated optical waveguide device, a beam splitter device and a thermo-optic phase shifter device, wherein: The integrated optical waveguide device is connected to the beam splitter device and the thermo-optic phase shifter device in sequence.

7. An optical network-on-chip structure as claimed in claim 6, characterized in that, The integrated optical waveguide device comprises a first integrated optical waveguide and a second integrated optical waveguide; the beam splitter device comprises a first beam splitter and a second beam splitter; the thermo-optic phase shifter device comprises a first thermo-optic phase shifter and a second thermo-optic phase shifter, wherein: The first integrated optical waveguide is connected to the first beam splitter, the first thermo-optic phase shifter and the second beam splitter in sequence; The second integrated optical waveguide is connected to the first beam splitter, the second thermo-optic phase shifter and the second beam splitter in sequence; the light waveguide input end of the first integrated optical waveguide is used as a first input end of the symmetric interferometer, and the light waveguide output end of the first integrated optical waveguide is used as a first output end of the symmetric interferometer; the light waveguide input end of the second integrated optical waveguide is used as a second input end of the symmetric interferometer, and the light waveguide output end of the second integrated optical waveguide is used as a second output end of the symmetric interferometer.

8. An optical network-on-chip structure according to claim 7, wherein, The first beam splitter and the second beam splitter are 50:50 beam splitters.

9. The optical network-on-chip structure of claim 7, wherein, The first thermo-optic phase shifter and the second thermo-optic phase shifter are respectively provided with a phase shifter input end as a phase end of the symmetric interferometer.

10. A photonic integrated circuit, comprising: The photonic integrated circuit is provided with an on-chip optical network structure as claimed in any one of claims 2-9.

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