Optical correction model, acquisition method thereof and mask pattern correction method

Abstract

The invention discloses an optical correction model and an acquisition method thereof, and a mask pattern correction method, and the mask pattern correction method comprises the steps: providing a to-be-corrected layout which comprises a first to-be-corrected pattern and a second to-be-corrected pattern; providing an optical correction model; performing first optical proximity effect correction on the first to-be-corrected graph by adopting a first correction model to obtain a first corrected graph; performing second optical proximity effect correction on the second to-be-corrected graph by adopting a second correction model to obtain a second corrected graph; a correction layout is obtained, the correction layout comprises a first correction graph and a second correction graph, the first correction graph is in one-to-one correspondence with the first to-be-corrected graph, and the second correction graph is in one-to-one correspondence with the second to-be-corrected graph. According to the correction method, the correction result accuracy of optical proximity correction can be improved, so that the size precision of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to an optical correction model and an acquisition method thereof, and a mask layout correction method. BACKGROUND

[0002] In order to realize the transfer of the pattern from the mask to the surface of the silicon wafer, it is usually necessary to go through the exposure step, the developing step after the exposure step, and the etching step after the developing step. In the exposure step, light is irradiated onto the silicon wafer coated with photoresist through the light-transmitting area of the mask, and the photoresist undergoes a chemical reaction under the irradiation of light; in the developing step, the light-exposed and non-exposed photoresist are used to form a photoresist pattern by taking advantage of the different solubility of the developing agent, so as to realize the transfer of the mask pattern to the photoresist; in the etching step, the silicon wafer is etched based on the photoresist pattern formed by the photoresist layer, so as to further transfer the pattern of the mask to the silicon wafer.

[0003] In semiconductor manufacturing, as the design size is continuously reduced, the design size is closer and closer to the limit of the photoetching imaging system, and the diffraction effect of light becomes more and more obvious, resulting in optical image degradation of the final design pattern, and the actual photoetching pattern is seriously distorted relative to the pattern on the mask, so that the actual pattern formed on the silicon wafer through photoetching is different from the design pattern, which is called optical proximity effect (OPE).

[0004] In order to correct the optical proximity effect, optical proximity correction (OPC) is generated. The core idea of optical proximity correction is to establish an optical proximity correction model based on the consideration of offsetting the optical proximity effect, and to design a photomask pattern according to the optical proximity correction model, so that although the photoetching pattern after photoetching has optical proximity effect relative to the photomask pattern, since the photomask pattern has been designed according to the optical proximity correction model, the photoetching pattern after photoetching is close to the target pattern that the user actually wants to obtain.

[0005] How to improve the correction accuracy of optical proximity correction is a continuous problem to be solved. SUMMARY

[0006] The embodiments of the present application provide an optical correction model and an acquisition method thereof, and a mask layout correction method, so as to improve the correction accuracy of optical proximity correction.

[0007] According to a first aspect of the present application, there is provided a method for obtaining an optical correction model, the optical correction model comprising a first correction model and a second correction model, the first correction model and the second correction model being used for correcting different layout patterns on a same layout, the method comprising: providing a first substrate and a second substrate, the first substrate being different from the second substrate; forming a first photoresist layer on the first substrate and a second photoresist layer on the second substrate by using a first lithography condition; and obtaining a first correction model corresponding to the first substrate and a second correction model corresponding to the second substrate according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first lithography condition.

[0008] Optionally, the first substrate and the second substrate each comprise a substrate and an active region on the substrate; the first substrate further comprises a first dielectric layer on the active region; the second substrate further comprises a gate structure layer on the active region and a second dielectric layer on the gate structure layer; the forming of the first photoresist layer on the first substrate and the second photoresist layer on the second substrate by using the first lithography condition comprises: providing a test mask, the test mask satisfying a minimum size design rule of a mask, the test mask comprising a plurality of test patterns; forming the first photoresist layer on the first dielectric layer by using the test mask, the first photoresist layer comprising a plurality of first lithography patterns, the first lithography patterns exposing part of the first dielectric layer on the active region, and each of the test patterns corresponding to one of the first lithography patterns; and forming the second photoresist layer on the second dielectric layer by using the test mask, the second photoresist layer comprising a plurality of second lithography patterns, the first lithography patterns exposing part of the second dielectric layer on the gate structure layer, and each of the test patterns corresponding to one of the second lithography patterns.

[0009] Optionally, the obtaining of the first correction model corresponding to the first substrate and the second correction model corresponding to the second substrate according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first lithography condition comprises: obtaining a first initial model according to a material of the first substrate, a material of the test mask and the first lithography condition; performing simulation training on the first initial model according to a size relationship between the plurality of test patterns and the plurality of first lithography patterns to obtain the first correction model; obtaining a second initial model according to a material of the second substrate, a material of the test mask and the first lithography condition; and performing simulation training on the second initial model according to a size relationship between the plurality of test patterns and the plurality of second lithography patterns to obtain the second correction model.

[0010] Correspondingly, the present application also provides an optical correction model obtained by the above method, comprising: a first correction model; and a second correction model, wherein the first correction model and the second correction model are used for correcting different patterns of a mask layout.

[0011] Correspondingly, the present application also provides a mask pattern correction method, comprising: providing a to-be-corrected layout, wherein the to-be-corrected layout comprises a first to-be-corrected pattern and a second to-be-corrected pattern; providing an optical correction model; performing first optical proximity effect correction on the first to-be-corrected pattern by using a first correction model to obtain a first corrected pattern; performing second optical proximity effect correction on the second to-be-corrected pattern by using a second correction model to obtain a second corrected pattern; and obtaining a corrected layout, wherein the corrected layout comprises the first corrected pattern and the second corrected pattern, the first corrected pattern corresponds to the first to-be-corrected pattern one by one, and the second corrected pattern corresponds to the second to-be-corrected pattern one by one.

[0012] Optionally, the total number of correction times of the first optical proximity effect correction and the second optical proximity effect correction is an odd number greater than 3, the first odd number of correction is the first optical proximity effect correction, the second even number of correction is the second optical proximity effect correction, or the first odd number of correction is the second optical proximity effect correction, and the second even number of correction is the first optical proximity effect correction.

[0013] Optionally, when the total number of correction times of the first optical proximity effect correction and the second optical proximity effect correction is 3, the correction sequence comprises: first performing the first optical proximity effect correction, then performing the second optical proximity effect correction, and then performing the first optical proximity effect correction again; or first performing the second optical proximity effect correction, then performing the first optical proximity effect correction, and then performing the second optical proximity effect correction again.

[0014] Optionally, the first optical proximity effect correction on the first to-be-corrected pattern by using the first correction model to obtain the first corrected pattern comprises: obtaining a first mask based on the first to-be-corrected pattern and the second to-be-corrected pattern; obtaining a first photoresist pattern on a wafer based on the first mask, wherein the first photoresist pattern corresponds to the first to-be-corrected pattern one by one; obtaining a first etching pattern of the wafer based on the first photoresist pattern; obtaining a first etching deviation of the first photoresist pattern and the first etching pattern; compensating the first to-be-corrected pattern based on the first etching deviation to obtain a first target photoresist pattern; performing the first optical proximity effect correction on the first to-be-corrected pattern or the first target photoresist pattern by using the first correction model, and obtaining the first corrected pattern based on the first target photoresist pattern.

[0015] Optionally, the first optical proximity effect correction is performed on the first to-be-corrected pattern or the first target photoresist pattern by using a first correction model to obtain a first corrected pattern, including: performing simulation exposure on the first to-be-corrected pattern or the first target photoresist pattern to obtain a first simulation exposure pattern; obtaining an edge placement error between the first simulation exposure pattern and the first target photoresist pattern; moving a line segment of the first to-be-corrected pattern or the first target photoresist pattern according to the edge placement error; continuing to perform simulation exposure on the first to-be-corrected pattern or the first target photoresist pattern after the line segment is moved until the edge placement error between the first simulation exposure pattern and the first target photoresist pattern meets a preset range; and obtaining a pattern after the first to-be-corrected pattern or the first target photoresist pattern is moved for multiple times as the first corrected pattern.

[0016] Optionally, the second optical proximity effect correction is performed on the second to-be-corrected pattern by using a second correction model to obtain a second corrected pattern, including: obtaining a first mask according to the first to-be-corrected pattern and the second to-be-corrected pattern; obtaining a second photoresist pattern on a wafer according to the first mask, the second photoresist pattern corresponding to the second to-be-corrected pattern in one-to-one manner; obtaining a second etching pattern of the wafer according to the second photoresist pattern; obtaining a second etching deviation of the second photoresist pattern and the second etching pattern; compensating the second to-be-corrected pattern according to the second etching deviation to obtain a second target photoresist pattern; performing the second optical proximity effect correction on the second to-be-corrected pattern or the second target photoresist pattern by using the second correction model, and obtaining the second corrected pattern based on the second target photoresist pattern.

[0017] Optionally, the second optical proximity effect correction is performed on the second to-be-corrected pattern or the second target photoresist pattern by using a second correction model to obtain a second corrected pattern, including: performing simulation exposure on the second to-be-corrected pattern or the second target photoresist pattern to obtain a second simulation exposure pattern; obtaining an edge placement error between the second simulation exposure pattern and the second target photoresist pattern; moving a line segment of the second to-be-corrected pattern or the second target photoresist pattern according to the edge placement error; continuing to perform simulation exposure on the second to-be-corrected pattern or the second target photoresist pattern after the line segment is moved until the edge placement error between the second simulation exposure pattern and the second target photoresist pattern meets a preset range; and obtaining a pattern after the second to-be-corrected pattern or the second target photoresist pattern is moved for multiple times as the second corrected pattern.

[0018] Compared with the prior art, the technical scheme provided by the present application has the following beneficial effects: The optical correction model acquisition method of the application is based on the same first lithography condition to form a first photoresist layer on the first substrate and a second photoresist layer on the second substrate, respectively, and then based on the first substrate, the first photoresist layer and the first lithography condition to acquire a first correction model, and based on the second substrate, the second photoresist layer and the first lithography condition to acquire a second correction model, so that the first correction model and the second correction model correspond to different structures on the same wafer, and the pattern of different regions on the same wafer can be accurately corrected, the accuracy of the corrected mask pattern is improved, and the size accuracy of the semiconductor structure formed based on the mask pattern is further improved.

[0019] The mask pattern correction method of the application uses different optical correction models to correct the first and second to-be-corrected patterns, which can improve the correction accuracy of the optical proximity effect correction, and further improve the size accuracy of the finally obtained semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 And Figure 2 is a structural schematic diagram of a semiconductor structure; Figure 3 And Figure 4 is a structural schematic diagram of a semiconductor structure in an embodiment of the application; Figures 5 to 7 is a flowchart of the optical correction model acquisition method in an embodiment of the application; Figures 8 to 10 is a flowchart of the mask pattern correction method in an embodiment of the application. DETAILED DESCRIPTION

[0021] As described in the background, improving the correction accuracy of optical proximity correction is a continuous problem to be solved. Now, specific embodiments will be analyzed and described.

[0022] Please refer to Figure 1 , the semiconductor structure comprises: a substrate, the substrate comprises a substrate 100 and an active region 101 on the substrate 100; a gate structure 102 on the active region 101; a dielectric layer 103 on the substrate, the dielectric layer 103 is on the side wall surface and the top surface of the gate structure 102; a second plug 104 and a first plug 105 in the dielectric layer 103, the second plug 104 is electrically connected with the top of the gate structure 102, and the first plug 105 is electrically connected with the surface of the active region 101; a metal layer 106 on the dielectric layer 103, the metal layer 106 is electrically connected with the second plug 104 and the first plug 105.

[0023] The method for forming the second plug 104 and the first plug 105 comprises: forming a patterned photoresist layer on the dielectric layer 103; etching the dielectric layer 103 with the patterned photoresist layer as a mask to form a first recess and a second recess in the dielectric layer 103, the first recess exposing part of the top surface of the gate structure 102, and the second recess exposing part of the surface of the active region 101.

[0024] In the forming of the patterned photoresist layer on the dielectric layer 103, a photoresist material is first formed on the dielectric layer 103, and a mask plate is used to expose and develop the photoresist material to form the patterned photoresist layer. The pattern on the mask plate is a pattern after optical proximity effect correction. In the optical proximity effect correction of the pattern on the mask plate, a correction model needs to be established first, which is obtained after training by collecting parameters. The parameters required for modeling include: film layer material, light source, and patterned photoresist layer corresponding to the mask pattern. The physical conditions of the film layer and the light source are input to construct the optical behavior, and then the correction model is trained according to the correspondence between the mask plate and the patterned photoresist layer. The structure model as shown in Figure 2 is usually used to collect data to obtain the correction model for the optical proximity effect correction of the pattern on the mask plate for forming the second plug 104 and the first plug 105. Figure 2 The structure in the method comprises: a substrate comprising a base 100 and an active region 101 on the base 100; a dielectric layer 103 on the active region 101; and a first plug 105 in the dielectric layer 103.

[0025] However, the depths of the second plug 104 and the first plug 105 are different, the depth of the second plug 104 is smaller than that of the first plug 105, and the underlying film layer structures of the second plug 104 and the first plug 105 are also different, so the optical conditions for forming the second plug 104 and the first plug 105 are not the same. The correction result of the pattern of the second plug 104 by using the correction model established under the condition for forming the first plug 105 is poor. Since the etching depths of the second plug 104 and the first plug 105 are different, the etching deviations of the two are inconsistent. The etching deviation between the photoetching pattern and the etching pattern collected at the etching depth of the position of the first plug 105 is commonly used for the second plug 104 at the position of the gate structure 102, which will cause the size of the second plug 104 at the position of the gate structure 102 after etching to deviate from the etching target, affect the electrical properties, and even possibly cause the plug hole to be unable to open or a bridge defect between the two plug holes.

[0026] In order to solve the above problems, the technical scheme of the present application provides an optical correction model and an acquisition method thereof, and a mask pattern correction method, the first photoresist layer located on the first substrate and the second photoresist layer located on the second substrate are formed based on the same first lithography condition, then the first correction model is acquired based on the first substrate, the first photoresist layer and the first lithography condition, and the second correction model is acquired based on the second substrate, the second photoresist layer and the first lithography condition, so that the first correction model and the second correction model correspond to different structures on the same wafer, the patterns of different regions on the same wafer can be accurately corrected, the accuracy of the corrected mask pattern is improved, and the size accuracy of the semiconductor structure formed based on the mask pattern is further improved.

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0028] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the technical solutions of the present application will be described in detail below with reference to the drawings.

[0029] Figures 5 to 7 is a flowchart of the acquisition method of the optical correction model in the embodiments of the present application.

[0030] Please refer to Figure 5 , the optical correction model can include a first correction model and a second correction model, the first correction model and the second correction model are used to correct different pattern graphics on the same layout, and the method comprises the following steps: Step S1: providing a first substrate and a second substrate, the first substrate is different from the second substrate.

[0031] Step S2: forming a first photoresist layer on the first substrate and a second photoresist layer on the second substrate by using a first photoetching condition.

[0032] Step S3: obtaining a first correction model corresponding to the first substrate and a second correction model corresponding to the second substrate according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first photoetching condition.

[0033] The method for obtaining the optical correction model forms a first photoresist layer on the first substrate and a second photoresist layer on the second substrate based on the same first photoetching condition, and then obtains a first correction model based on the first substrate, the first photoresist layer and the first photoetching condition, and obtains a second correction model based on the second substrate, the second photoresist layer and the first photoetching condition. Therefore, the first correction model and the second correction model correspond to different structures on the same wafer, which can accurately correct the patterns of different regions on the same wafer, improve the accuracy of the corrected mask pattern, and further improve the size accuracy of the semiconductor structure formed based on the mask pattern.

[0034] Next, each step is analyzed and described.

[0035] Please refer to Figure 3 Please refer to Figure 5 Step S1: providing a first substrate and a second substrate, wherein the first substrate is different from the second substrate.

[0036] In this embodiment, the first substrate can include a base 200, an active region 201 on the base 200, and a first dielectric layer 203 on the active region 201.

[0037] The first substrate is used for subsequent formation of a first plug in the first substrate, which is electrically connected to the active region 201.

[0038] In this embodiment, the second substrate can include a base 200, an active region 201 on the base 200, a gate structure layer 202 on the active region 201, and a second dielectric layer 206 on the gate structure layer 202.

[0039] The second substrate is used for subsequent formation of a second plug in the second substrate, which is electrically connected to the gate structure layer 202.

[0040] In this embodiment, the first substrate is different from the second substrate, i.e., the structure and material of the first substrate are different from those of the second substrate.

[0041] In the embodiment, the structure and material of the first substrate are different from the structure and material of the second substrate, i.e., the film layer structure of the first substrate is different, and the film layer material is different.

[0042] In the embodiment, the material of the substrate 200 is silicon, and the material of the active region 201 is silicon.

[0043] In other embodiments, the material of the substrate can include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] In the embodiment, the material of the first dielectric layer 203 can include a dielectric material, which can include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0045] In the embodiment, the material of the first dielectric layer 203 includes silicon oxide.

[0046] In the embodiment, the material of the gate structure layer 202 includes polysilicon or tungsten metal.

[0047] The material of the second dielectric layer 206 can include a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0048] In the embodiment, the material of the second dielectric layer 206 includes silicon oxide.

[0049] Please refer to Figure 3 Continue to refer to Figure 5 , perform step S2: form a first photoresist layer 204 on the first substrate and a second photoresist layer 207 on the second substrate using a first photoetching condition.

[0050] In the embodiment, forming the first photoresist layer on the first substrate by using the first photoetching condition can include: providing a test mask according to a minimum size design rule of a mask, the test mask satisfying the minimum size design rule of the mask, the test mask including a plurality of test patterns; forming the first photoresist layer 204 on the first dielectric layer 203 by using the test mask, the first photoresist layer 204 including a plurality of first photoetching patterns, the first photoetching patterns exposing part of the first dielectric layer 203 on the active region 201, and the plurality of test patterns and the plurality of first photoetching patterns corresponding one by one.

[0051] In the embodiment, forming the first photoresist layer 204 on the first dielectric layer 203 by using the test mask can include: forming a photoresist material layer on the first dielectric layer 203; exposing and developing the photoresist material layer by using the test mask based on the first photoetching condition, to form the first photoresist layer 204 including the first photoetching patterns.

[0052] In the embodiment, the first photoetching condition can include a preset exposure light source and a preset exposure wavelength.

[0053] In the embodiment, forming the second photoresist layer 207 on the second substrate by using the first photoetching condition can include: providing a test mask according to a minimum size design rule of a mask, the test mask satisfying the minimum size design rule of the mask, the test mask including a plurality of test patterns; forming the second photoresist layer 207 on the second dielectric layer 206 by using the test mask, the second photoresist layer 207 including a plurality of second photoetching patterns, the second photoetching patterns exposing part of the second dielectric layer 206 on the active region 201, and the plurality of test patterns and the plurality of second photoetching patterns corresponding one by one.

[0054] In the embodiment, forming the second photoresist layer 207 on the second dielectric layer 206 by using the test mask can include: forming a photoresist material layer on the second dielectric layer 206; exposing and developing the photoresist material layer by using the test mask based on the first photoetching condition, to form the second photoresist layer 207 including the second photoetching patterns.

[0055] In the embodiment, the first photoetching condition includes an exposure light source and an exposure wavelength.

[0056] In the embodiment, the same first photoetching condition is used to construct the first correction model and the second correction model, and the first correction model and the second correction model can be used to correct optical proximity effects of mask patterns corresponding to different structures on the same wafer, which can be used to form photoresist patterns corresponding to different structures on the same wafer under the same photoetching condition, thereby saving masks.

[0057] In the embodiment, the first plug is electrically connected with the active region 201, and the second plug is electrically connected with the gate structure layer 202, the depth of the first plug is greater than the depth of the second plug, and the thickness of the first dielectric layer 203 is greater than the thickness of the second dielectric layer 206.

[0058] Please continue to refer to Figure 5 , execute step S3: according to the first substrate, the second substrate, the first photoresist layer 204, the second photoresist layer 207 and the first lithography condition, obtain the first correction model corresponding to the first substrate and the second correction model corresponding to the second substrate.

[0059] In the embodiment, according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first lithography condition, the first correction model corresponding to the first substrate and the second correction model corresponding to the second substrate can include: according to the material of the first substrate, the material of the test mask and the first lithography condition, obtaining a first initial model; according to the size relationship between the test pattern and the first lithography pattern corresponding to the first initial model, the first initial model is simulated and trained to obtain the first correction model; according to the material of the second substrate, the material of the test mask and the first lithography condition, obtaining a second initial model; according to the size relationship between the test pattern and the second lithography pattern corresponding to the second initial model, the second initial model is simulated and trained to obtain the second correction model.

[0060] Please refer to Figure 6 , in the embodiment, according to the first substrate, the first photoresist layer and the first lithography condition, the first correction model can include: Step S51: according to the material of the first substrate, the material of the test mask and the first lithography condition, obtaining a first initial model.

[0061] Step S52: according to the size relationship between the test pattern and the first lithography pattern corresponding to the first initial model, the first initial model is simulated and trained to obtain the first correction model.

[0062] In the embodiment, according to the material of the first substrate, the material of the test mask and the first lithography condition, the first initial model is obtained, that is, according to the material of the substrate 200, the material of the active region 201, the material of the first dielectric layer 203 and the first lithography condition, a pure optical model is constructed, and the pure optical model is the first initial model.

[0063] In the embodiment, the parameters related to the material of the first substrate participating in the construction of the first initial model include: the material type and the material refractive index of the substrate 200, the material type and the material refractive index of the active region 201, the material type and the material refractive index of the first dielectric layer 203, the thickness of the substrate 200, and the thickness of the active region 201, and the thickness of the first dielectric layer 203.

[0064] In the embodiment, the parameters related to the test mask participating in the construction of the first initial model include: the material and the refractive index of the test mask.

[0065] In the embodiment, the first correction model is obtained by simulating and training the first initial model according to the size relationship between the test patterns and the corresponding first lithography patterns.

[0066] Please refer to Figure 7 In the embodiment, the second correction model can be obtained according to the second substrate, the second photoresist layer, and the first lithography condition. Step S61: obtaining a second initial model according to the material of the second substrate, the material of the test mask, and the first lithography condition.

[0067] Step S62: obtaining a second correction model by simulating and training the second initial model according to the size relationship between the test patterns and the corresponding second lithography patterns.

[0068] In the embodiment, the second initial model is obtained according to the material of the second substrate, the material of the test mask, and the first lithography condition, that is, the material of the substrate 200, the material of the active region 201, the material of the gate structure layer 202, the material of the second dielectric layer 206, and the first lithography condition, to construct a pure optical model, and the pure optical model is the second initial model.

[0069] In the embodiment, the parameters related to the material of the second substrate participating in the construction of the second initial model can include: the material type and the material refractive index of the substrate 200, the material type and the material refractive index of the active region 201, the material type and the material refractive index of the second dielectric layer 206, the material type and the material refractive index of the gate structure layer 202, the thickness of the gate structure layer 202, the thickness of the substrate 200, the thickness of the active region 201, and the thickness of the second dielectric layer 206.

[0070] In the embodiment, the parameters related to the test mask involved in constructing the second initial model can include: material and refractive index of the test mask.

[0071] In the embodiment, the lithography condition involved in constructing the second initial model is the same as that involved in constructing the first initial model.

[0072] In the embodiment, the simulation training of the second initial model according to the size relationship between the test patterns and the corresponding second lithography patterns can include: adjusting the model parameters (such as Gaussian function related parameters) in the second initial model, simulating exposure of the test patterns, and until the difference between the size of the simulated exposure pattern and the size of the second lithography pattern meets the preset range, thereby obtaining the second corrected model.

[0073] Correspondingly, the embodiment of the application further provides an optical correction model, which can include: The first corrected model formed by the method in Figure 5 and Figure 6 The second corrected model formed by the method in The second corrected model formed by the method in Figure 5 and Figure 7 The first corrected model and the second corrected model are used for correcting different patterns of the mask layout.

[0074] Figures 8 to 10 is a flowchart of the mask pattern correction method in the embodiment of the application.

[0075] Please refer to Figure 8 , the mask pattern correction method can include: Step S10: providing a to-be-corrected layout, the to-be-corrected layout including a first to-be-corrected pattern and a second to-be-corrected pattern.

[0076] Step S20: providing an optical correction model, the optical correction model including a first corrected model and a second corrected model, the first corrected model and the second corrected model being used for correcting different patterns of the mask layout.

[0077] Step S30: using the first corrected model to perform first optical proximity effect correction on the first to-be-corrected pattern, and obtaining a first corrected pattern.

[0078] Step S40: using the second corrected model to perform second optical proximity effect correction on the second to-be-corrected pattern, and obtaining a second corrected pattern.

[0079] Step S50: obtaining a corrected mask layout, the corrected mask layout comprising a first corrected pattern and a second corrected pattern, the first corrected pattern corresponding to the first to-be-corrected pattern one by one, and the second corrected pattern corresponding to the second to-be-corrected pattern one by one.

[0080] The mask pattern correction method respectively uses different optical correction models to perform optical proximity effect correction on the first to-be-corrected pattern and the second to-be-corrected pattern, thereby improving the correction accuracy and finally improving the precision of the semiconductor structure size.

[0081] Next, each step will be analyzed and described.

[0082] Please continue to refer to Figure 8 Step S10: providing a to-be-corrected mask layout, the to-be-corrected mask layout comprising a first to-be-corrected pattern and a second to-be-corrected pattern.

[0083] The to-be-corrected mask layout is a pattern formed on a mask after optical proximity effect correction, and the mask is used to form a structure with a first plug and a second plug having different depths on the same wafer.

[0084] In this embodiment, the first to-be-corrected pattern corresponds to the photoresist pattern for forming the first plug 105 in Figure 1 The second to-be-corrected pattern corresponds to the photoresist pattern for forming the second plug 104 in Figure 1 .

[0085] Please continue to refer to Figure 8 Step S20: providing an optical correction model, the optical correction model comprising a first correction model and a second correction model, the first correction model and the second correction model being used to correct different patterns of a mask layout.

[0086] The first correction model is formed by using the method described in Figure 5 and Figure 6 , which will not be described here.

[0087] The second correction model is formed by using the method described in Figure 5 and Figure 7 , which will not be described here.

[0088] Please continue to refer to Figure 8 Step S30: using the first correction model to perform first optical proximity effect correction on the first to-be-corrected pattern to obtain a first corrected pattern.

[0089] Please refer to Figure 9 In this embodiment, using the first correction model to perform first optical proximity effect correction on the first to-be-corrected pattern to obtain a first corrected pattern can include: Step S301: Obtain a first mask based on the first image to be corrected and the second image to be corrected.

[0090] Step S302: Obtain the first photoresist pattern on the wafer according to the first mask, wherein the first photoresist pattern corresponds one-to-one with the first pattern to be corrected.

[0091] Step S303: Obtain the first etching pattern of the wafer based on the first photoresist pattern.

[0092] Step S304: Obtain the first etching deviation between the first photoresist pattern and the first etched pattern.

[0093] Step S305: Compensate the first pattern to be corrected according to the first etching deviation to obtain the first target photoresist pattern.

[0094] Step S306: Apply the first correction model to the first pattern to be corrected or the first target photoresist pattern to perform the first optical proximity effect correction, and obtain the first corrected pattern based on the first target photoresist pattern.

[0095] In this embodiment, in step S301, a first mask is obtained based on the first and second patterns to be corrected. That is, the first and second patterns to be corrected are transferred onto the first mask, where the first and second patterns are mask design patterns that have not undergone optical proximity effect correction.

[0096] In this embodiment, the first mask and Figures 5 to 7 The test mask described herein is the same. Figures 5 to 7 The test mask described above is shared with the first mask in this embodiment, which saves on mask usage, simplifies the correction process, and improves correction efficiency. Furthermore, using the same mask for both modeling and correction reduces the impact of mask differences, further improving correction accuracy. In this case, the test mask includes both the first image to be corrected and the second image to be corrected.

[0097] In other embodiments, the first mask and Figures 5 to 7 The test masks in the image are different masks.

[0098] In this embodiment, the first pattern to be corrected and the second pattern to be corrected correspond to different semiconductor structures on the same wafer. The first pattern to be corrected and the second pattern to be corrected are designed on a photomask, which can save photomasks and thus save manufacturing costs.

[0099] In step S302, a first photoresist pattern on the wafer is obtained according to the first mask. The first photoresist pattern corresponds to the first to-be-corrected pattern. That is, the first photoresist pattern on the wafer is obtained by exposing and developing the photoresist layer on the wafer according to the first mask, and the first to-be-corrected pattern on the first mask is transferred to the photoresist layer on the wafer.

[0100] In step S303, a first etching pattern of the wafer is obtained according to the first photoresist pattern. That is, the first etching pattern is obtained by etching the wafer with the first photoresist pattern as a mask, and the first etching pattern corresponds to the first to-be-corrected pattern.

[0101] In step S304, a first etching deviation of the first photoresist pattern and the first etching pattern is obtained. The deviation of the first photoresist pattern and the first etching pattern is the etching deviation.

[0102] In step S305, the first to-be-corrected pattern is compensated according to the first etching deviation, and a first target photoresist pattern is obtained. The first target photoresist pattern is a photoresist pattern that needs to be formed on the wafer, and the etching pattern formed by etching the wafer based on the first target photoresist pattern is a structure pattern that meets the design rule.

[0103] In step S306, a first optical proximity effect correction is performed on the first to-be-corrected pattern or the first target photoresist pattern using a first correction model, and a first corrected pattern is obtained based on the first target photoresist pattern.

[0104] In this embodiment, the first to-be-corrected pattern is a mask design pattern that has not undergone optical proximity correction, and the first corrected pattern is a pattern obtained by performing a first optical proximity effect correction on the first to-be-corrected pattern or the first target photoresist pattern using a first correction model.

[0105] In this embodiment, the first optical proximity effect correction performed on the first to-be-corrected pattern using the first correction model includes optical proximity effect correction on the first to-be-corrected pattern that has not been compensated, and also includes optical proximity effect correction on the first to-be-corrected pattern that has been compensated, and the first target photoresist pattern is the first to-be-corrected pattern that has been compensated by the first etching deviation.

[0106] In the above embodiment, by correcting the first to-be-corrected pattern that has been compensated by the first etching deviation, the number of correction cycles can be reduced, and the correction efficiency can be improved.

[0107] In an embodiment, the first optical proximity effect correction of the first target photoresist pattern by using the first correction model to obtain the first correction pattern can include: performing a simulation exposure on the first target photoresist pattern to obtain a first simulation exposure pattern; obtaining an edge placement error between the first simulation exposure pattern and the first target photoresist pattern; moving a line segment of the first target photoresist pattern according to the edge placement error; and continuously performing a simulation exposure on the first target photoresist pattern after the line segment is moved until the edge placement error between the first simulation exposure pattern and the first target photoresist pattern meets a preset range, and the pattern obtained after the first target photoresist pattern is moved for multiple times is the first correction pattern.

[0108] In another embodiment, the first optical proximity effect correction of the first target photoresist pattern by using the first correction model to obtain the first correction pattern can include: performing a simulation exposure on the first target photoresist pattern to obtain a first simulation exposure pattern; obtaining an edge placement error between the first simulation exposure pattern and the first target photoresist pattern; moving a line segment of the first target photoresist pattern according to the edge placement error; and continuously performing a simulation exposure on the first target photoresist pattern after the line segment is moved until the edge placement error between the first simulation exposure pattern and the first target photoresist pattern meets a preset range, and the pattern obtained after the first target photoresist pattern is moved for multiple times is the first correction pattern.

[0109] Please continue to refer to Figure 8 , and perform step S40: performing the second optical proximity effect correction of the second target photoresist pattern by using the second correction model to obtain the second correction pattern.

[0110] Please refer to Figure 10 , and in the embodiment, the second optical proximity effect correction of the second target photoresist pattern by using the second correction model to obtain the second correction pattern can include: Step S401: obtaining a first mask plate according to the first target photoresist pattern and the second target photoresist pattern.

[0111] Step S402: obtaining a second photoresist pattern on a wafer according to the first mask plate, and the second photoresist pattern corresponds to the second target photoresist pattern one by one.

[0112] Step S403: obtaining a second etching pattern of the wafer according to the second photoresist pattern.

[0113] Step S404: obtaining a second etching deviation of the second photoresist pattern and the second etching pattern.

[0114] Step S405: compensating the second to-be-corrected pattern according to the second etching deviation, to obtain a second target photoresist pattern.

[0115] Step S406: performing second optical proximity effect correction on the second to-be-corrected pattern or the second target photoresist pattern by using a second correction model, and obtaining a second corrected pattern based on the second target photoresist pattern.

[0116] In this embodiment, in step S401, a first mask plate is obtained according to the first to-be-corrected pattern and the second to-be-corrected pattern. That is, the first to-be-corrected pattern and the second to-be-corrected pattern are transferred to the first mask plate, and the first to-be-corrected pattern and the second to-be-corrected pattern are mask plate design patterns without optical proximity effect correction.

[0117] In step S402, a second photoresist pattern on a wafer is obtained according to the first mask plate. The second photoresist pattern corresponds to the second to-be-corrected pattern one-to-one, that is, the second to-be-corrected pattern on the first mask plate is transferred to the photoresist layer on the wafer by exposing and developing the photoresist layer on the wafer according to the first mask plate.

[0118] In step S403, a second etching pattern of the wafer is obtained according to the second photoresist pattern. That is, the second etching pattern is obtained by etching the wafer with the second photoresist pattern as a mask, and the second etching pattern corresponds to the second to-be-corrected pattern one-to-one.

[0119] In step S404, a second etching deviation of the second photoresist pattern and the second etching pattern is obtained. The deviation of the second photoresist pattern and the second etching pattern is the etching deviation.

[0120] In step S405, the second to-be-corrected pattern is compensated according to the second etching deviation, to obtain a second target photoresist pattern. The second target photoresist pattern is a photoresist pattern that needs to be formed on the wafer, and the etching pattern formed by etching the wafer based on the second target photoresist pattern is a structure pattern that meets the design rules.

[0121] In step S406, second optical proximity effect correction is performed on the second to-be-corrected pattern or the second target photoresist pattern by using a second correction model, and a second corrected pattern is obtained based on the second target photoresist pattern.

[0122] The second to-be-corrected pattern is a mask plate design pattern without optical proximity correction, and the second corrected pattern is a pattern obtained by performing second optical proximity effect correction on the second to-be-corrected pattern or the second target photoresist pattern by using a second correction model.

[0123] In the embodiment, the second to-be-corrected pattern is corrected by using the second correction model to perform optical proximity effect correction, which includes performing optical proximity effect correction on the second to-be-corrected pattern without compensation and performing optical proximity effect correction on the second to-be-corrected pattern after compensation. The second target photoresist pattern is the second to-be-corrected pattern after the second etching deviation compensation.

[0124] The second to-be-corrected pattern after the second etching deviation compensation is corrected, which can reduce the number of correction cycles and improve the correction efficiency.

[0125] In an embodiment, the second target photoresist pattern is corrected by using the second correction model to perform second optical proximity effect correction to obtain a second corrected pattern, which can include: performing simulated exposure on the second target photoresist pattern to obtain a second simulated exposure pattern; obtaining edge placement error between the second simulated exposure pattern and the second target photoresist pattern; moving a line segment of the second target photoresist pattern according to the edge placement error; continuing to perform simulated exposure on the second target photoresist pattern after the line segment is moved until the edge placement error between the second simulated exposure pattern and the second target photoresist pattern meets a preset range; and obtaining a pattern after the second target photoresist pattern is moved multiple times to obtain the second corrected pattern.

[0126] In another embodiment, the second to-be-corrected pattern is corrected by using the second correction model to perform second optical proximity effect correction to obtain a second corrected pattern, which can include: performing simulated exposure on the second to-be-corrected pattern to obtain a second simulated exposure pattern; obtaining edge placement error between the second simulated exposure pattern and the second target photoresist pattern; moving a line segment of the second to-be-corrected pattern according to the edge placement error; continuing to perform simulated exposure on the second to-be-corrected pattern after the line segment is moved until the edge placement error between the second simulated exposure pattern and the second target photoresist pattern meets a preset range; and obtaining a pattern after the second to-be-corrected pattern is moved multiple times to obtain the second corrected pattern.

[0127] In the embodiment, the total number of correction times of the first optical proximity effect correction and the second optical proximity effect correction is an odd number greater than 3. Specifically, the odd-numbered correction is the first optical proximity effect correction, and the even-numbered correction is the second optical proximity effect correction; or the odd-numbered correction is the second optical proximity effect correction, and the even-numbered correction is the first optical proximity effect correction.

[0128] In the embodiment, when the total number of the first optical proximity correction and the second optical proximity correction is 3 times, the correction order comprises: first performing the first optical proximity correction, then performing the second optical proximity correction, and then performing the first optical proximity correction again; or, first performing the second optical proximity correction, then performing the first optical proximity correction, and then performing the second optical proximity correction again.

[0129] The first correction object and the third correction object are the same, and the second correction object is different from the first correction object and the third correction object.

[0130] The first correction object and the third correction object are the same, but because the second correction object is different, the pattern environment in the first correction and the third correction is different, so it is necessary to correct the first correction object again after the second correction to improve the accuracy of the correction result and reduce the influence of the change of the correction result caused by the change of the small environment.

[0131] In other embodiments, when the total number of the first optical proximity correction and the second optical proximity correction is more than 3 times, the number of corrections is adjusted as needed, wherein the correction objects of adjacent two corrections are different, that is, the adjacent two corrections are the first optical proximity correction on the first to-be-corrected pattern and the second optical proximity correction on the second to-be-corrected pattern, respectively. In order to improve the accuracy of the correction result.

[0132] Please continue to refer to Figure 8 , step S50 is performed: obtaining a corrected layout, the corrected layout comprising a first correction pattern and a second correction pattern, the first correction pattern corresponding to the first to-be-corrected pattern one by one, and the second correction pattern corresponding to the second to-be-corrected pattern one by one.

[0133] The corrected layout is the pattern finally formed on the target mask, that is, the first correction pattern obtained by using the first correction model and the second correction pattern obtained by using the second correction model are finally formed on a target mask. Subsequently, the target mask is used to expose the regions corresponding to the first correction pattern and the second correction pattern respectively, and one development or multiple developments are performed, which can save the number of masks.

[0134] In the embodiment, the first correction pattern corresponds to a photoresist pattern for forming a first plug 105 on Figure 1 , and the second target pattern corresponds to a pattern for forming a second plug 106 on Figure 1The photoresist pattern for forming the second plug 104 is formed on the first plug 105, the depth of the first plug 105 is greater than the depth of the second plug 104, the photoresist patterns for forming the first plug 105 and the second plug 104 are corrected by different correction models, and finally the size accuracy of the formed first plug 105 and the second plug 104 is higher, and the defects such as misplacement and bridging are less likely to occur, thereby improving the yield of the semiconductor structure.

[0135] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of obtaining an optical correction model, characterized in that, The optical correction model comprises a first correction model and a second correction model, the first correction model and the second correction model are used for correcting different layout patterns on the same layout, and the method comprises: providing a first substrate and a second substrate, the first substrate being different from the second substrate; forming a first photoresist layer on the first substrate and a second photoresist layer on the second substrate by using a first lithography condition; obtaining a first correction model corresponding to the first substrate and a second correction model corresponding to the second substrate according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first lithography condition.

2. The method of claim 1, wherein the optical correction model is obtained by: The first substrate and the second substrate each comprise a substrate and an active region on the substrate; the first substrate further comprises a first dielectric layer on the active region; and the second substrate further comprises a gate structure layer on the active region and a second dielectric layer on the gate structure layer; The first photoresist layer on the first substrate and the second photoresist layer on the second substrate are formed by using the first lithography condition, comprising: providing a test mask, the test mask satisfying a mask minimum size design rule, and the test mask comprising a plurality of test patterns; forming a first photoresist layer on the first dielectric layer by using the test mask, the first photoresist layer comprising a plurality of first lithography patterns, the first lithography patterns exposing part of the first dielectric layer on the active region, and the plurality of test patterns and the plurality of first lithography patterns corresponding to each other in a one-to-one manner; forming a second photoresist layer on the second dielectric layer by using the test mask, the second photoresist layer comprising a plurality of second lithography patterns, the first lithography patterns exposing part of the second dielectric layer on the gate structure layer, and the plurality of test patterns and the plurality of second lithography patterns corresponding to each other in a one-to-one manner.

3. The method of claim 2, wherein the optical correction model is obtained by: The first correction model corresponding to the first substrate and the second correction model corresponding to the second substrate are obtained according to the first substrate, the second substrate, the first photoresist layer, the second photoresist layer and the first lithography condition, comprising: obtaining a first initial model according to the material of the first substrate, the material of the test mask and the first lithography condition; performing simulation training on the first initial model according to the size relationship between the plurality of test patterns and the plurality of first lithography patterns to obtain the first correction model; obtaining a second initial model according to the material of the second substrate, the material of the test mask and the first lithography condition; performing simulation training on the second initial model according to the size relationship between the plurality of test patterns and the plurality of second lithography patterns to obtain the second correction model.

4. An optical correction model obtained by the method of any one of claims 1 to 3, characterized in that, comprising: a first correction model; a second correction model, the first correction model and the second correction model being used for correcting different patterns of a mask layout.

5. A method of mask pattern correction, the method comprising: comprising: providing a to-be-corrected layout, the to-be-corrected layout comprising a first to-be-corrected pattern and a second to-be-corrected pattern; providing the optical correction model according to claim 4; performing first optical proximity effect correction on the first to-be-corrected pattern by using the first correction model to obtain a first corrected pattern; and performing second optical proximity effect correction on the second to-be-corrected pattern by using the second correction model to obtain a second corrected pattern. The second optical proximity effect correction is performed on the second to-be-corrected pattern by using a second correction model to obtain a second corrected pattern. The corrected pattern includes the first corrected pattern and the second corrected pattern, the first corrected pattern corresponds to the first to-be-corrected pattern one-to-one, and the second corrected pattern corresponds to the second to-be-corrected pattern one-to-one.

6. The method of claim 5, wherein the mask pattern is modified by: The total number of correction times of the first optical proximity effect correction and the second optical proximity effect correction is an odd number greater than 3. The first optical proximity effect correction is the first odd-number correction, and the second optical proximity effect correction is the second even-number correction, or the first optical proximity effect correction is the first even-number correction, and the second optical proximity effect correction is the second odd-number correction.

7. The method of claim 5, wherein the mask pattern is modified by: The first optical proximity effect correction is performed on the first to-be-corrected pattern by using a first correction model to obtain a first corrected pattern, including: A first mask is obtained according to the first to-be-corrected pattern and the second to-be-corrected pattern; A first photoresist pattern on a wafer is obtained according to the first mask, the first photoresist pattern corresponding to the first to-be-corrected pattern one-to-one; A first etching pattern of the wafer is obtained according to the first photoresist pattern; A first etching deviation of the first photoresist pattern and the first etching pattern is obtained; The first to-be-corrected pattern is compensated according to the first etching deviation to obtain a first target photoresist pattern; The first optical proximity effect correction is performed on the first to-be-corrected pattern or the first target photoresist pattern by using the first correction model, and the first corrected pattern is obtained based on the first target photoresist pattern.

8. The method of claim 7, wherein the mask pattern is modified by: The first optical proximity effect correction is performed on the first to-be-corrected pattern or the first target photoresist pattern by using the first correction model to obtain the first corrected pattern, including: A first simulated exposure pattern is obtained by performing simulated exposure on the first to-be-corrected pattern or the first target photoresist pattern; An edge placement error between the first simulated exposure pattern and the first target photoresist pattern is obtained; A line segment of the first to-be-corrected pattern or the first target photoresist pattern is moved according to the edge placement error; The first to-be-corrected pattern or the first target photoresist pattern after the line segment is moved is continuously subjected to simulated exposure until the edge placement error between the first simulated exposure pattern and the first target photoresist pattern meets a preset range, and the pattern obtained by moving the line segment of the first to-be-corrected pattern or the first target photoresist pattern for multiple times is the first corrected pattern.

9. The method of claim 5, wherein the mask pattern is modified by: The second correction model is used for performing second optical proximity effect correction on the second to-be-corrected pattern, to obtain a second correction pattern, including: obtaining a first mask plate according to the first to-be-corrected pattern and the second to-be-corrected pattern; obtaining a second photoresist pattern on a wafer according to the first mask plate, the second photoresist pattern corresponding to the second to-be-corrected pattern in a one-to-one manner; obtaining a second etching pattern of the wafer according to the second photoresist pattern; obtaining a second etching deviation of the second photoresist pattern and the second etching pattern; compensating the second to-be-corrected pattern according to the second etching deviation, to obtain a second target photoresist pattern; and performing second optical proximity effect correction on the second to-be-corrected pattern or the second target photoresist pattern by using the second correction model, to obtain the second correction pattern based on the second target photoresist pattern.

10. The method of claim 9, wherein the mask pattern is modified by: The second correction model is used for performing second optical proximity effect correction on the second to-be-corrected pattern or the second target photoresist pattern, to obtain a second correction pattern, including: performing simulation exposure on the second to-be-corrected pattern or the second target photoresist pattern, to obtain a second simulation exposure pattern; obtaining an edge placement error between the second simulation exposure pattern and the second target photoresist pattern; moving a line segment of the second to-be-corrected pattern or the second target photoresist pattern according to the edge placement error; and continuing to perform simulation exposure on the second to-be-corrected pattern or the second target photoresist pattern after the line segment is moved, until the edge placement error between the second simulation exposure pattern and the second target photoresist pattern meets a preset range, and obtaining a pattern of the second to-be-corrected pattern or the second target photoresist pattern after the line segment is moved for multiple times as the second correction pattern.

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