Event mechanism-based processor five-stage pipeline structure and control method

Abstract

The application discloses a processor five-stage pipeline structure and a control method based on an event mechanism, and relates to the technical field of processors.The processor five-stage pipeline structure comprises a fetch module, a decoding module, an execution module, a memory access module and a write-back module, and events and data are transmitted between the modules through asynchronous event control elements, wherein a conditional waiting structure is connected to the output lines of the fetch module, the decoding module, the execution module and the memory access module.The application removes a clock tree, reduces dynamic power consumption, adopts a communication protocol based on the event mechanism to overcome problems caused by clock deviation and jitter, and realizes pipeline flushing through an event walk trap to avoid the flipping of a large number of pipeline registers, effectively save dynamic power consumption and improve the speed of processing instructions in the pipeline.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of processor pipeline control, and particularly relates to a processor five-stage pipeline structure based on an event mechanism and a control method thereof. BACKGROUND

[0002] In a traditional processor architecture, a synchronous pipeline control technology coordinates operations of stages of a pipeline through a global clock signal, and represented by a classic RISC five-stage pipeline (instruction fetch IF, decode ID, execution EX, memory access MEM, and write back WB), has become one of core technologies of modern CPU design. The core idea is to divide pipeline stages through clock-driven registers, to ensure that instruction flow is sequentially pushed forward within a fixed clock period, thereby improving throughput and simplifying timing control.

[0003] However, with the miniaturization of process and the complication of multi-task scenarios, the traditional synchronous pipeline design method gradually exposes the following problems:

[0004] 1. High clock tree power consumption

[0005] The synchronous pipeline relies on a global clock network to drive registers of stages, and the power consumption of the clock tree accounts for 30%-50% of the total power consumption of a chip. The clock tree needs to cover global wiring of hundreds of millions of transistors, and the parasitic capacitance and high-frequency flip (such as 3GHz or more) cause dynamic power consumption to rise exponentially. Taking a 7nm process as an example, the clock tree power consumption of a single-core processor can reach 2.5W, far exceeding the energy consumption of the operation unit itself;

[0006] 2. Timing bottleneck limits the development of maximum performance of the pipeline

[0007] With the synchronous design method, when the process enters the 5nm node, the control difficulty of clock deviation and jitter increases dramatically, which leads to difficulty in timing convergence and limits the space for frequency improvement. For example, the clock period of the traditional pipeline is limited by the delay of the longest flow section, resulting in a large amount of waste of timing margin of short path stages (such as ID decoding), which is difficult to dynamically adapt to the differences in instruction characteristics.

[0008] 3. Insufficient dynamic resource adaptation

[0009] The static timing division of the synchronous pipeline needs to avoid errors by inserting bubbles or pausing the pipeline when facing dynamic events such as branch prediction failure, data hazards (such as RAW, WAR, and WAW), which leads to performance loss. For example, in a load-use (Load-Use) data hazard scenario, the synchronous design needs to forcibly insert a one-cycle delay to realize data synchronization. SUMMARY

[0010] In view of the problems in the prior art, the present application aims to provide a five-stage pipeline structure of a processor based on an event mechanism and a control method.

[0011] To achieve the above object, the present application adopts the following technical scheme:

[0012] The five-stage pipeline structure of the processor based on the event mechanism comprises a fetch module, a decoding module, an execution module, a memory access module and a write-back module, events and data bound by asynchronous event control elements are transmitted between the modules, the asynchronous event control elements comprise cFifo, pmtfifo, eventSource, eventTrap, mutexMerge, waitMerge, arbMerge, cSplitter and cSelector, the output lines of the fetch module, the decoding module, the execution module and the memory access module are all connected with a conditional waiting structure, the conditional waiting structure comprises waitMerge, cSelector and eventTrap, the output lines of the modules are connected with the input ends of waitMerge, the output end of waitMerge is connected with the input end of cSelector, one output end of cSelector is connected with the input end of eventTrap, the other output end of cSelector is connected with the input end of the next module, the output end of eventTrap transmits events and data bound to waitMerge through eventSource, the output end of the decoding module is connected with the conditional waiting structure through an Ld use module, the Ld use module is used for detecting load use correlation, the output end of the execution module is connected with the conditional waiting structure through a first cSplitter, the output end of the memory access module is connected with the conditional waiting structure through a third cSplitter, one output end of the fetch module and the write-back module is connected with an interrupt exception module, one output end of the interrupt exception module is connected with the input end of the fetch module, the other output end of the interrupt exception module and the other output end of the write-back module are both connected with the input end of a fifth waitMerge, the output end of the fifth waitMerge transmits events and data bound to each stage of the pipeline through a fourth cSplitter.

[0013] Further, in the asynchronous event control elements:

[0014] cFifo: used for transmitting events, one event is input and one event is output, a pulse signal is generated as an excitation for saving data in a register during the process;

[0015] pmtfifo: an enable mechanism is added on the basis of cFifo, an enable signal is generated, and the enable signal is effective in a high level;

[0016] eventSource: used to provide initial event driving to drive other modules to start work;

[0017] eventTrap: used as the end point of event delivery;

[0018] mutexMerge: a multiple-input single-output structure, any event input will be output by mutexMerge, and multiple events input into mutexMerge are mutually exclusive;

[0019] waitMerge: a multiple-input single-output structure, an event output can be generated only when all events are input;

[0020] arbMerge: a multiple-input single-output structure, parallel event inputs are converted into serial event outputs;

[0021] cSplitter: a single-input multiple-output structure, an input event is copied into multiple events, and the number of output events is hardware configurable. For data bound to the output event, it can be a split of the data bound to the input event, or a copy of the data bound to the input event;

[0022] cSelector: a single-input multiple-output structure, each input event is output from a certain direction, and the data bound to the input event needs to contain control information of the specified output direction.

[0023] Further, the output end of the interrupt exception module is connected with the input end of the fifth waitMerge through a countable event trap.

[0024] Further, in the conditional wait structure on the output line of the instruction fetch module, the output end of the instruction fetch module is connected with the input end of the first waitMerge, the output end of the first eventTrap is connected with the input end of the first eventSource, the output end of the first countable event source and the input end of the first mutexMerge are respectively connected with the output end of the first eventSource, the output end of the first countable event source is connected with the input end of the first waitMerge, the output end of the first mutexMerge is connected with the input end of the instruction fetch module; and the Ld use module is connected with the input end of the first mutexMerge.

[0025] Further, in the conditional waiting structure on the output line of the decoding module, the output end of the decoding module is connected with the input end of the second waitMerge through the Ld use module, the output end of the second eventTrap is connected with the input end of the second eventSource, the output end of the second eventSource is connected with the input end of the second countable event source and the second mutexMerge respectively, and the output end of the second countable event source and the second mutexMerge are both connected with the input end of the second waitMerge.

[0026] Further, in the conditional waiting structure on the output line of the execution module, the output end of the execution module is connected with the input end of the third waitMerge through the first cSplitter, the output end of the third eventTrap is connected with the input end of the third eventSource, the output end of the third eventSource is connected with the input end of the third countable event source, the output end of the third countable event source is connected with the input end of the third waitMerge and the third mutexMerge through the second cSplitter respectively, the output end of the third mutexMerge is connected with the input end of the second waitMerge in the conditional waiting structure on the output line of the decoding module, one output end of the third cSplitter is connected with the input end of the third mutexMerge, and one output end of the first cSplitter is connected with the input end of the second mutexMerge.

[0027] Further, in the conditional waiting structure on the output line of the memory module, the output end of the memory module is connected with the input end of the fourth waitMerge through the third cSplitter, the output end of the fourth eventTrap is connected with the input end of the fourth eventSource, the output end of the fourth eventSource is connected with the input end of the fourth mutexMerge, and the output end of the fourth mutexMerge is connected with the input end of the fourth waitMerge.

[0028] Further, in the conditional waiting structure on the output line of the instruction fetching module, the output end of the first eventTrap is also connected with the input end of the fifth eventSource and the countable event trap respectively, the output end of the fifth eventSource is connected with the input end of the fifth mutexMerge through the fourth countable event source, the output end of the fifth mutexMerge is connected with the input end of the interrupt exception module, and the output end of the write-back module is connected with the input end of the interrupt exception module through the fifth mutexMerge.

[0029] The application further provides a five-stage pipeline control method based on an event mechanism, which is realized by using the five-stage pipeline structure based on the event mechanism.

[0030] The instruction fetch module fetches instructions from the memory and sends the instructions to the waitMerge and the interrupt exception module in the conditional waiting structure on the instruction fetch module output line, and when the conditional waiting structure on the instruction fetch module output line meets the condition, the instructions and events are transmitted to the decoding module;

[0031] After decoding, the events bound by the instructions are sent to the waitMerge in the conditional waiting structure on the decoding module output line, and when the conditional waiting structures on the decoding module and the execution module output lines meet the condition at the same time, the instructions and events are transmitted to the execution module;

[0032] After the execution module completes the operation, the events bound by the instructions are sent to the waitMerge in the conditional waiting structure on the execution module output line, and when the conditional waiting structure on the execution module output line meets the condition, the instructions and events are transmitted to the memory access module;

[0033] After the memory access is completed, the events bound by the instructions are sent to the waitMerge in the conditional waiting structure on the memory access module output line, and when the conditional waiting structure on the memory access module output line meets the condition, the instructions and events are transmitted to the write-back module;

[0034] After the write-back module is completed, the events bound by the instructions are transmitted to the fifth waitMerge, and the control data is transmitted according to whether the instructions have an exception, and at the same time, the write-back module transmits the instructions and events to the interrupt exception module;

[0035] The interrupt exception module judges whether an interrupt occurs, and after the processing is completed, the interrupt exception module transmits the events bound by the instructions to the fifth waitMerge and further transmits the events to the asynchronous event control elements of each stage of the pipeline, which are used to determine whether the cross-pipeline and transmission of the next instruction need to be discarded; at the same time, the interrupt exception module sends the instructions and events to the instruction fetch module to drive the instruction fetch module to continue fetching instructions and generating events.

[0036] Compared with the defects and deficiencies of the prior art, the application has the following beneficial effects:

[0037] 1. The five-stage pipeline structure based on the event mechanism of the application adopts an asynchronous circuit design method in the circuit mechanism, removes the clock tree, and stops each module as needed during the pipeline operation, thereby avoiding the empty flip of the module, eliminating the power consumption of the clock tree, and greatly reducing the dynamic power consumption;

[0038] 2. The application adopts a communication protocol based on an event mechanism, and there is no problem caused by clock deviation and jitter, and an asynchronous handshake signal only needs to meet the timing of the operation unit itself, and does not need to leave a large design margin for design stability. The whole pipeline can adjust the delay according to the type of different instructions, better adapt to the difference of different instruction characteristics, and under the same process background, it is beneficial to design a higher speed processor;

[0039] 3. The five-stage pipeline control method of the event mechanism-based processor of the application, under the dynamic events such as branch prediction failure and interruption exception, the flushing of the pipeline is realized by the event walk trap, the flip of a large number of pipeline registers is avoided, and the dynamic power consumption is effectively saved. In the application of load use correlation detection, only one event needs to be sent when filling the empty instruction, and the later stage of the pipeline can work immediately, unnecessary time waste is avoided, and the speed of processing instructions of the pipeline is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is the control block diagram of the five-stage pipeline structure of the event mechanism-based processor provided by the embodiment of the application;

[0041] Figure 2 is the symbolic description schematic diagram of the asynchronous event control element provided by the embodiment of the application;

[0042] Figure 3 is the conditional waiting structure schematic diagram provided by the embodiment of the application;

[0043] Figure 4 is the pipeline flushing structure schematic diagram provided by the embodiment of the application;

[0044] Figure 5 is the event source and complex event source structure schematic diagram provided by the embodiment of the application;

[0045] Figure 6 is the CET module and Int&Exp module flushing pipeline control structure schematic diagram provided by the embodiment of the application;

[0046] Figure 7 is the processing method schematic diagram of data hazard in the five-stage pipeline of the processor provided by the embodiment of the application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below in combination with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and are not used to limit the application.

[0048] Event mechanism refers to asynchronous two-phase handshake mechanism at circuit level. The sender needs to send data to the receiver. Since the time of initiating transmission is arbitrary, handshake signal is needed to control the timing to ensure that the receiver can correctly receive the data. The sender needs to ensure that the handshake signal and the data to be transmitted have a specific timing relationship. When the receiving module receives the data, it should respond to the sending module with a pulse to indicate the completion of this transmission. In addition, the sender should ensure that the next transmission cannot be initiated before the previous transmission is completed. The data of the sender should be maintained until the receiver returns the response signal. The request signal and the response signal are usually called events. The request signal, the response signal and the data signal are bound as a group, which is called event-bound data.

[0049] The control block diagram of the five-stage pipeline structure of the processor based on the event mechanism is shown in Figure 1 , which includes an instruction fetch (IF) module, a decoding (ID) module, an execution (EX) module, a memory access (MEM) module and a write back (WB) module. The modules are connected through asynchronous event control elements to transmit the bound events and data.

[0050] The basic functions of the asynchronous event control element include generating events, transmitting events and ending events. The symbol description schematic diagram of the asynchronous event control element is shown in Figure 2 , which includes:

[0051] cFifo: used for transmitting events, inputting an event and outputting an event, during which a pulse signal is generated as a register to save data;

[0052] pmtfifo: based on cFifo, an enable mechanism is added to generate an enable signal, which is active at high level; when the enable is invalid, the module will not generate output after inputting the event, but will save the event internally until the output event is generated when the pmt is valid;

[0053] eventSource: used for providing initial event driving to drive other modules to start work, which is usually run only once;

[0054] eventTrap: used as the terminal point of event transmission; when the event does not need to continue to be transmitted, eventTrap can be used to terminate the event;

[0055] mutexMerge: a multi-input single-output structure, which can connect multiple event inputs. Any event input will be output by mutexMerge. The multiple events input into mutexMerge are mutually exclusive, i.e. only one event is input into the module at a time;

[0056] waitMerge: a multiple-input single-output structure, which generates an event output only when all the input events are received;

[0057] arbMerge: a multiple-input single-output structure, but different input events can arrive simultaneously, and the parallel input events are converted into serial event output;

[0058] cSplitter: a single-input multiple-output structure, the input event is copied into multiple events, and the number of output events is configurable. For the data bound to the output event, it can be the split of the data bound to the input event, or the copy of the data bound to the input event;

[0059] cSelector: a single-input multiple-output structure, each input event is output from a certain direction, and the data bound to the input event needs to contain control information for specifying the output direction.

[0060] Figure 1 The ES is an event source eventSource, the CES is a countable event source, which can generate a specified number of events after each activation, and the CET is a countable event sink, which can make a specified number of events terminate after each activation. The Ld use module is used to detect load use correlation, and the RAW module is used to detect instruction true dependence. The remaining modules are instruction fetch (IF) module, decode (ID) module, execution (EX) module, memory (MEM) module, write back (WB) module and interrupt exception (Int & Exp) module. The output lines of the IF module, the ID module, the EX module and the MEM module are all connected with a conditional waiting structure (such as Figure 3The shown), including waitMerge, cSelector and eventTrap, the output line of each module is connected to the input end of waitMerge, the input end of waitMerge can input multiple events such as Wait event 1, Wait event 2, and waitMerge realizes the conditional waiting when each stage of pipelining passes the data to the next stage, that is, when all the events that waitMerge waits for arrive at the input end of the module, waitMerge will generate event output, and the output data information is the splicing of all input data information. The output end of waitMerge is connected to the input end of cSelector, one output end of cSelector is connected to the input end of eventTrap, and the other output end of cSelector is connected to the input end of the next stage module. cSelector selects one way to output according to the control information in the data sent by waitMerge, if the event trap is selected, the event will disappear here and will not be passed on; if the other port output is selected, the event can be passed on smoothly, indicating that the data bound to it will also be passed on. Therefore, Figure 3 The design realizes that one instruction can pass through and cannot pass through the asynchronous pipeline, and the flushing function of the asynchronous pipeline is realized by using the structure of Figure 3 The output end of eventTrap sends the bound events and data to waitMerge through eventSource. The output end of the ID module is connected to the conditional waiting structure through the Ld use module; the output end of the EX module is connected to the conditional waiting structure through the first cSplitter, the output end of the MEM module is connected to the conditional waiting structure through the third cSplitter, one output end of the IF module and the WB module is connected to the Int&Exp module, one output end of the Int&Exp module is connected to the input end of the IF module, and the other output end of the Int&Exp module and the other output end of the WB module are both connected to the input end of the fifth waitMerge, wherein the output end of the Int&Exp module and the input end of the fifth waitMerge are connected with CET. The output end of the fifth waitMerge passes the bound events and data to each stage of the pipelining through the fourth cSplitter.

[0061] The five-stage pipeline control method based on the event mechanism relies on the five-stage pipeline structure of the processor to realize, and the pipeline control module coordinates the work of other core modules, controls the start and stop of the pipeline, flushes the pipeline, handles data hazards, controls hazards, and structural hazards. Figure 1Each of the directed arrows in the figure represents a set of bound events and data transfer, and the work of each stage of the pipeline depends on the driving of all input events, i.e. for any stage of the pipeline, its work depends on the events and data represented by all the arrows pointing to the stage, when all conditions are met, the stage works once and produces an output. The IF module is special, under normal circumstances, each time the instruction fetch runs, it needs to meet two conditions, one is the event from Int&Exp, and the other is the event from the Ld use module. But at the beginning of the power-on of the chip, the first time the instruction fetch works, the first condition is replaced by an internally self-set event source of the IF module. The signal driving the event source of the IF module is the chip start signal, which comes from the outside of the processor core, usually after the completion of some initialization work of the SOC, the start signal is generated.

[0062] The five-stage pipeline control process of the event mechanism-based processor is described in detail below:

[0063] At the beginning of the pipeline start, the external control signal is flipped to drive Figure 1 all event source modules, and an event is generated at the same time.

[0064] In the conditional waiting structure on the output line of the IF module, the output end of the IF module is connected with the input end of waitMerge1, the output end of the first eventTrap is connected with the input end of ES1, the output end of ES1 is connected with the input end of CES1 and mutexMerge1 respectively, the output end of CES1 is connected with the input end of waitMerge1, and the output end of mutexMerge1 is connected with the input port of the IF module; and the input end of the Ld use module is connected with mutexMerge1. The IF module needs two conditions to transfer a instruction to the ID module, one condition is that the IF module itself issues the instruction to be transferred, and the other condition is the control information transferred by the WB module, which controls whether there is a flush pipeline in this transfer. The IF module has an internal event source module, which will generate an event to drive the IF module to fetch instructions from the memory. The IF module fetches the first batch of instructions, and sends the bound events of the instructions to waitMerge1 and Int&Exp module. At the same time, ES1 sends events to CES1, and CES1 sends events to waitMerge1. At this time, the two conditions are met, and waitMerge1 sends events to cSelector1. The first instruction and event are transferred to the ID module.

[0065] In the conditional waiting structure on the output line of the ID module, the output end of the ID module is connected with the input end of the waitMerge2 through the Ld use module, the output end of the second eventTrap is connected with the input end of the ES2, the output end of the ES2 is connected with the input end of the CES2 and the mutexMerge2 respectively, and the output ends of the CES2 and the mutexMerge2 are connected with the input end of the waitMerge2. When the ID module transmits the instruction to the EX module, four conditions are needed, which are: ① the ID module has output an instruction, ② the WB module has transmitted the control information whether to flush the pipeline, ③ the EX module has output an instruction, and ④ the MEM module has output an instruction. The transmission condition of the ID module to the EX module is the most complex, and the reason is the data hazard phenomenon in the pipeline. After decoding, the instruction-bound event is sent to the waitMerge2, the event is transmitted to the CES2 by the ES2 at the beginning of power-on, the event is transmitted to the waitMerge2 by the CES2, the event is transmitted to the waitMerge2 by the ES3 through the CES3, the cSplitter2 and the mutexMerge3 in turn, the waitMerge2 can transmit the instruction-bound event to the cSelector2, and then the instruction and the event are transmitted to the EX module;

[0066] In the conditional waiting structure on the output line of the EX module, the output end of the EX module is connected with the input end of the waitMerge3 through the cSplitter2, the output end of the third eventTrap is connected with the input end of the ES3, the output end of the ES3 is connected with the input end of the CES3, the output end of the CES3 is connected with the input end of the waitMerge3 and the mutexMerge3 through the cSplitter2 respectively, the output end of the mutexMerge3 is connected with the input end of the waitMerge2, one output end of the cSplitter3 is connected with the input end of the mutexMerge3, and one output end of the cSplitter1 is connected with the input end of the mutexMerge2. When the EX module transmits the instruction to the MEM module, two conditions are needed, which are that the EX module outputs an instruction and the control information transmitted by the WB module controls whether to flush the pipeline. After the EX module completes the operation, the instruction-bound event is transmitted to the cSplitter1, the event is transmitted to the waitMerge3 by the cSplitter1, an event is transmitted to the waitMerge3 by the CES3 through the cSplitter2, the waitMerge3 can transmit the instruction-bound event to the cSelector3, and then the instruction and the event are transmitted to the MEM module.

[0067] In the conditional waiting structure on the output line of the MEM module, the output end of the MEM module is connected with the input end of the waitMerge4 through the cSplitter3, the output end of the fourth eventTrap is connected with the input end of the ES4, the output end of the ES4 is connected with the input end of the mutexMerge4, and the output end of the mutexMerge4 is connected with the input end of the waitMerge4. Two conditions are needed when the MEM module delivers the instruction to the WB module, which are that the MEM module outputs an instruction and the WB module delivers the control information. After the memory access is completed, the instruction-bound event is delivered to the waitMerge4 through the cSplitter3, and the ES4 delivers the event to the waitMerge4 through the mutexMerge4 at the beginning of power-on. Thus, the waitMerge4 can deliver the instruction-bound event to the cSelector4, and then deliver the instruction and the event to the WB module.

[0068] After the WB module is completed, the instruction-bound event is delivered to the waitMerge5, and the control data is delivered according to whether the instruction has an exception. Meanwhile, the output end of the WB module delivers the instruction and the event to the Int&Exp module through the mutexMerge5. The output end of the WB module is also connected with the input end of the waitMerge5, the output end of the waitMerge5 is connected with the cSplitter4, and the output end of the cSplitter4 is connected with the CES1, the CES2, the CES3 and the mutexMerge4 respectively.

[0069] In the conditional waiting structure on the output line of the IF module, the output end of the first eventTrap is also connected with the input end of the ES5 and the CET respectively, the output end of the ES5 is connected with the input end of the mutexMerge5 through the CES4, and the output end of the mutexMerge5 is connected with the input end of the Int&Exp module.

[0070] The Int&Exp module judges whether the interrupt occurs, and after the processing is completed, the Int&Exp module delivers the event to the waitMerge5 through the CET. Thus, the waitMerge5 can further deliver the event to each stage of the flow asynchronous event control element through the cSplitter4, for deciding whether the cross-flow and delivery of the next instruction need to be discarded. Meanwhile, the Int&Exp module delivers the instruction and the event to the IF module, for driving the IF module to continue fetching the instruction and generating the event.

[0071] Figure 4Fig. 3 is a schematic diagram of a pipeline flush structure, which implements the generation of pipeline flush information. In fact, the control information is jointly issued by the WB module and the Int & Exp module. The WB module gives the control information according to whether there is abnormal information (or whether it is a WFI instruction), so as to determine whether to flush the pipeline. The Int & Exp module gives the control information according to whether there is an interrupt, so as to determine whether to flush the pipeline. The control information of the two modules comprehensively determines whether the pipeline needs to be flushed. That is, when there is an interrupt or an exception (including a WFI instruction), the pipeline will be flushed, and the instructions of each stage of the pipeline can be normally transmitted to the next stage of the vector under other circumstances.

[0072] Figure 5 Fig. 4 is a schematic diagram of an event source and a complex event source structure, which implements the filling of the pipeline from an empty load state to a full load state. Taking the asynchronous pipeline between the IF module and the ID module as an example, two conditions are required for the IF module to deliver information to the ID module. One of the conditions is from the WB module. At the beginning of the power-on of the processor, the WB module has no event input, and thus cannot generate output. Therefore, the CES needs to be used to replace the WB module to give the first few events. Since the processor as a whole is a five-stage pipeline, the WB module can generate the first event only when the first instruction reaches the WB module, that is, after the fourth instruction is sent to the decoding stage from the instruction fetching stage. Therefore, the first four instructions are transmitted from the instruction fetching stage to the write-back stage, and the condition needs to be met four times. The CES between the IF module and the ID module needs to cyclically generate four events. After that, the event generation depends on the write-back stage. The write-back stage generates an event every time an instruction is processed, and the event is sent to the Int & Exp module to promote its work. The work of the Int & Exp module in turn drives the work of the IF module, and the cycle does not stop. The pipeline is completely started.

[0073] It is worth noting that when the pipeline flush occurs, the event cycle in the pipeline is broken, and the pipeline returns to a similar state as at the beginning of the power-on. The pipeline needs to be filled again. Here, the eventTrap is utilized, that is, the event that goes to the trap is also delivered to the ES, which is used to start the next filling of the pipeline.

[0074] Figure 6The control structure diagram of the CET module and the Int&Exp module flushing pipeline, corresponding to the countable event source, on the path of the Int&Exp module output control pipeline flushing, there is a CET, when the CET is started each time, it will guide the first specified number of events to the event sink, and after exceeding the specified number, it will directly output the input events and the data carried by the events. At the beginning of power-on, the CET is automatically started, when the pipeline flushing occurs, the events in the event sink between the IF module and the ID module are reused as Restart signals, which are transmitted to the CET module, and the CET is reactivated. At the beginning of power-on, the WB module does not work immediately, but the Int&Exp module works immediately, which means that the Int&Exp module produces the events of the control pipeline flushing first, and the WB module cannot match the Int&Exp module to produce events. Therefore, the CET is needed to guide the events produced by the Int&Exp module to the event sink, and after exceeding the count number, the events produced by the Int&Exp module are directly output.

[0075] Under the RISC-V instruction set architecture, data hazards in a five-stage pipeline are usually divided into three types: RAW, WAR and WAW. Figure 7 The five-stage pipeline of the processor of the application how to handle data hazards is simply explained, that is, the data forwarding technology is used to allow the processor to directly deliver the result to the subsequent instruction in the execution stage without waiting for the Write Back stage. In order to handle data hazards, in the application, when the add instruction calculates the value of x1 in the Execute stage, the value can be directly delivered to the sub and lw instructions, corresponding to the data forwarding path Bypass1 in Figure 7 , without waiting for the add instruction to enter the Write Back stage. Similarly, when the lw instruction reads the value of x6 in the Memory Access stage, the value can be directly delivered to the add x7, x6, x8 instruction, corresponding to the data forwarding path Bypass2 in Figure 7 .

[0076] The above only describes the preferred embodiments of the application and is not used to limit the application, any modification, equivalent replacement and improvement made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A five-stage pipelined architecture for a processor based on an event mechanism, characterized in that, include: The system comprises an instruction fetch module, a decoding module, an execution module, a memory access module, and a write-back module. These modules communicate with each other via asynchronous event control elements, including cFifo, pmtfifo, eventSource, eventTrap, mutexMerge, waitMerge, arbMerge, cSplitter, and cSelector. Each of the instruction fetch, decoding, execution, and memory access modules has a conditional wait structure connected to its output line. This conditional wait structure includes waitMerge, cSelector, and eventTrap. The output lines of each module are connected to the input of waitMerge, and the output of waitMerge is connected to the input of cSelector. One output of cSelector is connected to the input of eventTrap, and the other output of cSelector is connected to the input of the next-level module. The output of eventTrap sends the bound events and data to waitMerge via eventSource. The output of the decoding module is connected to the conditional wait structure via an Ld use module, which is used to detect load. Use relatedness; the output of the execution module is connected to the condition wait structure through the first cSplitter, the output of the memory access module is connected to the condition wait structure through the third cSplitter, one output of the instruction fetch module and the write-back module are both connected to the interrupt exception module, one output of the interrupt exception module is connected to the input of the instruction fetch module, the other output of the interrupt exception module and the other output of the write-back module are both connected to the input of the fifth waitMerge, and the output of the fifth waitMerge transmits the bound events and data to each stage of the pipeline through the fourth cSplitter; In the asynchronous event control element: cFifo: Used to transmit events, inputting one event and outputting another, while generating pulse signals as excitation for registers to store data; pmtfifo: Based on cFifo, an enable mechanism is added to generate an enable signal, which is active high. eventSource: Used to provide the initial event driver to start other modules and enable them to work; eventTrap: Used as the endpoint for event propagation; mutexMerge: This is a multi-input single-output structure. Any event input will be output by mutexMerge, and multiple events input to mutexMerge are mutually exclusive. waitMerge: This is a multi-input single-output structure. An event will be output only if all events have been input. arbMerge: This is a multi-input single-output structure where parallel event inputs are converted into serial event outputs. cSplitter: This is a single-input multiple-output structure. Input events are copied into multiple events, and the number of output events is hardware-configurable. cSelector: This is a single-input multiple-output structure. Each input event will only be output from one direction. The data bound to the input event needs to contain control information specifying the output direction.

2. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 1, characterized in that, A countable event trap is connected between the output of the interrupt exception module and the input of the fifth waitMerge.

3. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 1, characterized in that, In the conditional wait structure on the output line of the instruction fetch module, the output of the instruction fetch module is connected to the input of the first waitMerge, the output of the first eventTrap is connected to the input of the first eventSource, the output of the first eventSource is connected to the input of the first countable event source and the first mutexMerge, the output of the first countable event source is connected to the input of the first waitMerge, and the output of the first mutexMerge is connected to the input port of the instruction fetch module; and the Lduse module is connected to the input of the first mutexMerge.

4. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 1, characterized in that, In the conditional wait structure on the output line of the decoding module, the output of the decoding module is connected to the input of the second waitMerge through the Ld use module, the output of the second eventTrap is connected to the input of the second eventSource, the output of the second eventSource is connected to the input of the second countable event source and the second mutexMerge respectively, and the outputs of the second countable event source and the second mutexMerge are both connected to the input of the second waitMerge.

5. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 1, characterized in that, In the conditional wait structure on the output line of the execution module, the output of the execution module is connected to the input of the third waitMerge via the first cSplitter, the output of the third eventTrap is connected to the input of the third eventSource, the output of the third eventSource is connected to the input of the third countable event source, the output of the third countable event source is connected to the inputs of the third waitMerge and the third mutexMerge via the second cSplitter, and the output of the third mutexMerge is connected to the input of the second waitMerge in the conditional wait structure on the output line of the decoding module; one output of the third cSplitter is connected to the input of the third mutexMerge; and one output of the first cSplitter is connected to the input of the second mutexMerge.

6. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 1, characterized in that, In the conditional wait structure on the output line of the memory access module, the output of the memory access module is connected to the input of the fourth waitMerge through the third cSplitter, the output of the fourth eventTrap is connected to the input of the fourth eventSource, the output of the fourth eventSource is connected to the input of the fourth mutexMerge, and the output of the fourth mutexMerge is connected to the input of the fourth waitMerge.

7. The five-stage pipelined architecture of the processor based on an event mechanism as described in claim 2, characterized in that, In the conditional wait structure on the output line of the instruction fetch module, the output of the first eventTrap is also connected to the input of the fifth eventSource and the countable event trap, respectively. The output of the fifth eventSource is connected to the input of the fifth mutexMerge through the fourth countable event source. The output of the fifth mutexMerge is connected to the input of the interrupt exception module, and the output of the write-back module is connected to the input of the interrupt exception module through the fifth mutexMerge.

8. A five-stage pipeline control method for processors based on an event mechanism, characterized in that, The implementation using the event-based processor five-stage pipeline architecture as described in any one of claims 1-7 includes the following steps: The instruction fetch module fetches instructions from memory and sends them to the waitMerge and interrupt exception modules in the conditional wait structure on the output line of the instruction fetch module. When the conditional wait structure on the output line of the instruction fetch module meets the conditions, the instruction is passed to the decoding module. After decoding, the event bound to the instruction is sent to the waitMerge conditional wait structure on the output line of the decoding module. When the conditional wait structures on the output lines of both the decoding module and the execution module meet the conditions, the instruction and the event are passed to the execution module. After the execution module completes its operation, it sends the event bound to the instruction to the waitMerge conditional wait structure on the execution module's output line. When the conditional wait structure on the execution module's output line meets the condition, the instruction and the event are passed to the memory access module. After the memory access is completed, the event bound to the instruction is sent to the waitMerge in the conditional wait structure on the output line of the memory access module. When the conditional wait structure on the output line of the memory access module meets the condition, the instruction and the event are passed to the write-back module. After the write-back module completes, the event bound to the instruction is passed to the fifth waitMerge module. Depending on whether an exception occurred in the instruction, control data is passed. At the same time, the write-back module passes the instruction and event to the interrupt exception module. The interrupt exception module determines whether an interrupt has occurred. After processing, the interrupt exception module passes the event bound to the instruction to the fifth waitMerge, and further passes it to the asynchronous event control elements of each pipeline level to determine whether the next instruction needs to be discarded when crossing the pipeline. At the same time, the interrupt exception module sends the instruction and event to the instruction fetch module, driving the instruction fetch module to continue fetching instructions and generating events.

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