CPU and FPGA virtual-real combination simulation verification method and system

Abstract

The invention provides a CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) virtuality and reality combined simulation verification method and system. The method comprises the following steps: creating a CPU simulation model and loading a CPU-side binary executable file; based on the CPU simulation model, FPGA codes are deployed through FPGA acceleration hardware; dynamically configuring a connection relation and a connection interface between the CPU simulation model and FPGA hardware, and converting a calling interface of an FPGA code into a network interface for receiving and transmitting; the running speed of the CPU simulation model and the running speed of the FPGA acceleration hardware are matched, then the external test equipment is run, and a test result is obtained. According to the method, by means of software and hardware cooperative adjustment and the data caching technology, it is guaranteed that the simulation time sequence is relatively unified, the credibility and correctness of joint verification are improved, and simulation deduction of the system is effectively supported.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of hardware simulation and co-verification, and particularly relates to a CPU and FPGA virtual-real combined simulation verification method and system. BACKGROUND

[0002] In embedded system design, the heterogeneous architecture of "CPU+FPGA" has become a common choice to meet the demand of high-performance computing. The corresponding simulation verification technology is a key link. At present, the simulation for this architecture usually uses software to simulate FPGA logic, and the specific methods include manually writing C / C++ models or converting existing FPGA codes into C / C++ codes. However, when the FPGA logic becomes complex, these methods expose obvious shortcomings: the manual conversion work is heavy, and errors are easily introduced in the conversion process, leading to inconsistent functions between the software model and the original hardware design, which seriously restricts the efficiency and reliability of verification.

[0003] Therefore, the core problems faced by the prior art are as follows: firstly, the manual conversion is inefficient and prone to errors, which becomes a bottleneck in the development process; secondly, it is difficult to ensure the functional consistency of the model and the source code, which reduces the reliability of the simulation results and buries the integration risk. These problems together lead to the current verification method having deficiencies in accuracy and efficiency, and there is an urgent need for a solution that can automatically and accurately realize the connection between FPGA hardware logic and software model.

[0004] Patent document CN120529032A discloses a real-time video processing system based on an FPGA, which includes an SD card, an FPGA board card and an HDMI display. The SD card is used to store raw video data in Bayer format; the FPGA board card includes an FPGA end and an ARM end, wherein the FPGA end includes an SD card reading control module, an image cache FIFO module, a Bayer to RGB module, a 7-in-1 image processing module, an SDRAM read-write control module and an HDMI display control module, and the connection relationship between the modules is as follows: the first four modules are connected in order, and the SDRAM read-write control module is connected with the Bayer to RGB module, the 7-in-1 image processing module and the HDMI display control module; wherein the ARM end includes a Cortex M0 processor core, an AHBLite Interconnect data bus and various peripheral interfaces, and the modules are connected in order; the FPGA board card completes all video processing functions; and the HDMI display outputs the processed video. This scheme has good video processing effect, small resource consumption, high flexibility, strong stability, low hardware cost, and 100% hardware localization. However, it does not reduce the risk of code rewriting introduction, and does not improve the simulation verification efficiency and shorten the delivery cycle.

[0005] This technical problem needs to be solved urgently. SUMMARY

[0006] In view of the defects in the prior art, the purpose of the present application is to provide a CPU and FPGA virtual-real combined simulation verification method and system.

[0007] According to the CPU and FPGA virtual-real combined simulation verification method provided by the present application, the following steps are included: S1: creating a CPU simulation model and loading a CPU-side binary executable file; Step S2: deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; Step S3: dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; Step S4: matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain test results.

[0008] Preferably, the FPGA acceleration hardware is an FPGA acceleration server; the FPGA acceleration server includes an FPGA array acceleration board card; the FPGA array acceleration board card includes a VU13P core board; The FPGA array acceleration board card is connected to a physical single machine; The external interface of the FPGA acceleration server includes PXIE, GTH, LVDS, GPIO, and SMA; The FPGA acceleration server converts network protocol packets into internal protocols of the physical single machine; the internal protocols of the physical single machine include GTH, LVDS, and EMIF; In the step S2, the FPGA code is deployed through the FPGA array acceleration board card.

[0009] Preferably, the interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and the external connection is a gigabit network; the external interface of the physical single machine is an SMA intermediate frequency signal; the digital end of the physical single machine is a digital timing of AD / DA, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.

[0010] Preferably, in the step S3, the network interface is an Ethernet interface; the Ethernet interface is converted into a timing interface corresponding to the physical single machine through the FPGA acceleration hardware; the timing interface of the physical single machine is determined according to the internal protocol of the physical single machine, that is, dynamically configured; the timing interface includes an LVDS timing interface.

[0011] Preferably, in the step S4, the running speed of the CPU simulation model and the FPGA acceleration hardware is synchronized by a clock signal provided by the DDS.

[0012] According to the application, a CPU and FPGA virtual-real combined simulation verification system is provided, comprising: Module M1: creating a CPU simulation model and loading a CPU-side binary file; Module M2: deploying FPGA code based on the CPU simulation model through FPGA acceleration hardware; Module M3: dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface for receiving and sending; Module M4: matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain test results.

[0013] Preferably, the FPGA acceleration hardware is an FPGA acceleration server; the FPGA acceleration server comprises an FPGA array acceleration board card; and the FPGA array acceleration board card comprises a VU13P core board. The FPGA array acceleration board card is connected to a physical single machine. The external interface of the FPGA acceleration server comprises PXIE, GTH, LVDS, GPIO, and SMA. The FPGA acceleration server converts a network protocol packet into a protocol inside the physical single machine; and the protocol inside the physical single machine comprises GTH, LVDS, and EMIF. In the module M2, the FPGA code is deployed through the FPGA array acceleration board card.

[0014] Preferably, the interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and the external connection is a gigabit network; the external interface of the physical single machine is an SMA intermediate frequency signal; and the digital end of the physical single machine is a digital timing of AD / DA, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.

[0015] Preferably, in the module M3, the network interface is an Ethernet interface; the Ethernet interface is converted into a timing interface corresponding to the physical single machine through the FPGA acceleration hardware; the timing interface of the physical single machine is determined according to the protocol inside the physical single machine, that is, dynamically configured; and the timing interface comprises an LVDS timing interface.

[0016] Preferably, in the module M4, the running speed of the CPU simulation model and the FPGA acceleration hardware is synchronized by a clock signal provided by the DDS.

[0017] Compared with the prior art, the present application has the following beneficial effects: 1、The present application guarantees the binary program directly loaded on the CPU to run, guarantees the consistency of the CPU side with the real hardware, saves the hardware cost, and can develop development and commissioning before the real hardware is in place, thereby improving delivery efficiency.

[0018] 2、The present application completes the direct loading of FPGA code through general FPGA acceleration hardware, reduces the functional deviation risk caused by FPGA code rewriting, reduces the time and labor consumption of FPGA code rewriting, shortens the verification period, and improves delivery efficiency.

[0019] 3、The present application guarantees the relative uniformity of the timing of simulation through software and hardware cooperative regulation and data caching technology, improves the credibility and correctness of joint verification, and effectively supports the simulation deduction of the system. BRIEF DESCRIPTION OF DRAWINGS

[0020] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings: Figure 1 The system structure schematic diagram provided by the present application is shown in the figure; Figure 2 The FPGA acceleration hardware structure schematic diagram provided by the present application is shown in the figure; Figure 3 The use flow schematic diagram provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0021] The present application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present application. These all belong to the protection scope of the present application.

[0022] For the CPU+FPGA simulation scene, digital CPU modeling is now used, which is realized by manual coding or FPGA code conversion to C / C++ code. For complex FPGA logic functions, the rewriting workload is large, and the function consistency of the rewritten code cannot be guaranteed.

[0023] The virtual-real simulation verification system using the CPU and the FGPA can effectively solve the problem, the digital CPU is used to load the CPU binary program, the general FPGA hardware acceleration equipment is used to directly load the FPGA, the consistency of the CPU side and the FPGA side with the hardware is maintained, the risk of the code rewriting introduction problem is reduced, the credibility of the test verification is improved, the FPGA conversion C / C++ coding and the functional test verification time are reduced, the simulation verification efficiency is improved, and the delivery cycle is shortened.

[0024] According to the CPU and FPGA virtual-real combined simulation verification method provided by the application, the method comprises the following steps: Step 1: using a domestic digital simulation platform to complete the modeling of the hardware board system of the CPU side and directly loading the binary executable file of the CPU side.

[0025] Specifically, the step 1 comprises the following steps: Step 1.1: according to the actual CPU hardware board structure diagram, the corresponding instruction set, SOC target board and peripheral interface are selected by building a platform through a graphical digital simulation environment to complete the digital CPU building; Step 1.2: according to the hardware running parameters, the corresponding running configuration parameters are set in the digital simulation component; Step 1.3: loading the binary executable file of the CPU side to the specified path, and switching to the operation mode, and waiting for the running control command.

[0026] The binary executable file of the CPU side is loaded, and the user target code program running on the simulation CPU is simulated. The purpose of the operation is to keep the simulation consistent with the real hardware.

[0027] Step 2: using general FPGA acceleration hardware, that is, FPGA acceleration hardware to complete the deployment of the FPGA code.

[0028] The step 2 comprises the following steps: Step 2.1: the general FPGA acceleration hardware, the basic main chip adopts a super large scale FPGA VU13P, a plurality of VU13Ps are used as basic chips to constitute an FPGA array acceleration board card, and a plurality of FPGA array acceleration board cards constitute a general FPGA acceleration server, and the general FPGA acceleration server is externally connected with a gigabit network and can access other standard server networks; Step 2.2: the external interface is a gigabit network, and data interaction can be performed with other servers, and the internal interface can be flexibly configured by the FPGA logic to realize the conversion from the gigabit network interface to the internal interface.

[0029] Step 2.3: using the DDS protocol to interact with the digital CPU through the network transmission protocol package, and the general FPGA acceleration hardware can flexibly convert the network protocol package.

[0030] Step 2.4: converting the received network protocol packet into a single machine internal protocol such as GTH, LVDS, EMIF, etc. by FPGA.

[0031] Specifically, the step 2.4 includes the following steps: Step 2.4.1: the external interface of the general FPGA acceleration hardware includes a network port, PXIE, GTH, LVDS, GPIO and SMA.

[0032] Step 2.4.2: providing a network port interface, which can access the server network port of the CPU simulation system, and realize communication with other servers.

[0033] Step 2.4.3: providing a PXIE interface, which can access the general FPGA acceleration hardware chassis backplane, realize communication or cascade with other boards; providing a GTH interface, which can communicate with other single machines and general FPGA boards; providing an LVDS interface, which can communicate with other single machines and general FPGA boards; providing a GPIO interface, which can communicate with other single machines and general FPGA boards; providing an SMA interface, which is reserved for accessing intermediate frequency signals, and can access physical devices.

[0034] Step 2.5: selecting a corresponding number of FPGA board cards to complete the deployment of FPGA code; Step 2.6: the interface between the general FPGA acceleration hardware and the digital CPU simulation system is designed as an Ethernet interface, which can be directly connected with different digital CPU simulation systems using DDS protocol. The external interface of the single machine is an SMA intermediate frequency signal, and the digital end is the digital timing of AD / DA, which is connected with the FPGA of the single machine through the LVDS digital timing interface. The Ethernet interface needs to be converted to the LVDS interface.

[0035] Step 3: referring to the actual hardware connection relationship of CPU and FPGA, using FPGA connection configuration software to complete the conversion of FPGA code calling interface to network interface transceiver.

[0036] The step 3 includes the following steps: Step 3.1: referring to the actual hardware connection relationship of CPU and FPGA, opening the FGPA connection configuration software to complete the dynamic connection configuration of FPGA and FPGA, FPGA and CPU to network interface; that is, according to the real hardware connection, flexibly configuring the communication interface between CPU and FPGA, which is convenient for the reuse of different hardware configurations.

[0037] Specifically, the FPGA connection configuration software provides multiple connection configurations, which can dynamically adjust the connection between the FPGA simulation hardware, the FPGA simulation hardware and the CPU according to the connection interface and the connection relationship, so that one set of FPGA hardware can simulate multiple connection modes of user scenarios; Step 3.2: The built-in interface conversion program can complete the conversion of interface data to network data according to the configuration; Step 3.3: The general FPGA acceleration hardware sets the corresponding equal-speed reduction running frequency according to the difference between the running speed of the FPGA and the running speed of the simulation CPU, and caches the result data of the FPGA running to make equivalent simulation time synchronization adjustment; Specifically, the running speed of the simulation CPU is calculated according to the speed ratio of the FPGA hardware simulation speed, and the FPGA hardware is set to run at a reduced speed according to the speed ratio, so that the simulation time of the entire system can be matched.

[0038] As an example, through the clock signal provided by the DDS, the running speed of the CPU simulation model and the FPGA acceleration hardware is matched and synchronized.

[0039] Step 3.4: The data processed by the FPGA is sent to the corresponding digital CPU through the DDS using the data conversion function; Step 3.5: The general FPGA acceleration hardware is adapted to access the Ethernet interface, and through interface conversion processing, it is converted to a corresponding interface timing interface inside the FPGA, and data interaction is performed with the single FPGA program deployed in the general FPGA acceleration board through the timing interface.

[0040] Step 4: Run the cooperative simulation control software to complete the cooperative simulation of the CPU side software and the FPGA code.

[0041] The step 4 includes the following steps: Step 4.1: Complete the running control of the digital CPU and the general FPGA acceleration hardware through the packaged unified control interface; Step 4.2: Use the DDS beat synchronization mechanism to complete the timing control of the simulation cooperative running, match the running speed of the FPGA acceleration hardware with the running speed of the digital CPU, and ensure the relative timing uniformity of the simulation running; Specifically, the DDS beat refers to receiving the waiting or running of the simulation body through the DDS to provide a synchronization signal.

[0042] Step 4.3: Run the external test equipment to complete the test excitation injection, test data monitoring and test result analysis.

[0043] The application further provides a CPU and FPGA virtual-real combined simulation verification system, which can be realized by executing the process steps of the CPU and FPGA virtual-real combined simulation verification method, that is, the CPU and FPGA virtual-real combined simulation verification method can be understood as the preferred embodiment of the CPU and FPGA virtual-real combined simulation verification system by those skilled in the art.

[0044] According to the application, a CPU and FPGA virtual-real combined simulation verification system is provided, which comprises: Module M1: creating a CPU simulation model and loading a CPU-side binary file; Module M2: deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; Module M3: dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; Module M4: matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain a test result.

[0045] Those skilled in the art know that, in addition to implementing the system provided by the application and each device, module and unit thereof in a pure computer readable program code manner, the system provided by the application and each device, module and unit thereof can also be realized in the form of logic gates, switches, special integrated circuits, programmable logic controllers and embedded microcontrollers, etc. by logically programming the method steps to achieve the same functions. Therefore, the system provided by the application and each device, module and unit thereof can be considered as a hardware component, and the devices, modules and units included therein for achieving various functions can also be considered as structures in the hardware component; the devices, modules and units for achieving various functions can also be considered as both software modules for realizing methods and structures in the hardware component.

[0046] The specific embodiments of the application are described above. It should be understood that the application is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the application. The embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily without conflict.

Claims

1. A method for virtual-real combination simulation and verification of a CPU and an FPGA, characterized in that, Comprising: Step S1: creating a CPU simulation model and loading a CPU-side binary executable file; Step S2: deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; Step S3: dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; Step S4: matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain test results. 2.The CPU and FPGA virtual-real combination emulation verification method according to claim 1, characterized in that, The FPGA acceleration hardware, namely the FPGA acceleration server; the FPGA acceleration server comprises an FPGA array acceleration board card; the FPGA array acceleration board card comprises a VU13P core board; The FPGA array acceleration board card is connected to a physical single machine; The external interface of the FPGA acceleration server comprises PXIE, GTH, LVDS, GPIO and SMA; The FPGA acceleration server converts network protocol packets into internal protocols of the physical single machine; the internal protocols of the physical single machine comprise GTH, LVDS and EMIF; In the step S2, the FPGA code is deployed through the FPGA array acceleration board card. 3.The CPU and FPGA virtual-real combination emulation verification method according to claim 2, characterized in that, The interface of the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and is connected to a gigabit network externally; the external interface of the physical single machine is an SMA intermediate frequency signal; the digital end of the physical single machine is an AD / DA digital time sequence, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital time sequence interface.

4. The CPU and FPGA virtual-real combination emulation verification method according to claim 1, characterized in that, In the step S3, the network interface is an Ethernet interface; the Ethernet interface is converted into a time sequence interface corresponding to the physical single machine through the FPGA acceleration hardware; the time sequence interface of the physical single machine is determined according to the internal protocol of the physical single machine, that is, dynamically configured; the time sequence interface comprises an LVDS time sequence interface.

5. The CPU and FPGA virtual-real combination emulation verification method according to claim 1, characterized in that, In the step S4, the running speed of the CPU simulation model and the FPGA acceleration hardware is synchronized through a clock signal provided by DDS.

6. A CPU and FPGA virtual-real combined simulation verification system, characterized in that, Comprising: Module M1: creating a CPU simulation model and loading a CPU-side binary file; Module M2: deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; Module M3: dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; Module M4: matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain test results.

7. The CPU and FPGA virtual-real combined simulation verification system according to claim 6, characterized in that, The FPGA acceleration hardware, namely the FPGA acceleration server; the FPGA acceleration server comprises an FPGA array acceleration board card; the FPGA array acceleration board card comprises a VU13P core board; The FPGA array acceleration board card is connected to a physical single machine; The external interface of the FPGA acceleration server comprises PXIE, GTH, LVDS, GPIO and SMA; The FPGA acceleration server converts network protocol packets into the protocol inside the entity single machine; the protocol inside the entity single machine includes GTH, LVDS and EMIF; In the module M2, FPGA code is deployed through an FPGA array acceleration board card.

8. The CPU and FPGA virtual-real combined simulation verification system according to claim 7, characterized in that, The interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and is connected to a gigabit network externally; the external interface of the entity single machine is an SMA intermediate frequency signal; the digital end of the entity single machine is an AD / DA digital time sequence, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital time sequence interface.

9. The CPU and FPGA virtual-real combined simulation verification system according to claim 6, characterized in that, In the module M3, the network interface is an Ethernet interface; the Ethernet interface is converted into a time sequence interface corresponding to the entity single machine through the FPGA acceleration hardware; the time sequence interface of the entity single machine is determined according to the protocol inside the entity single machine, i.e. dynamically configured; the time sequence interface includes an LVDS time sequence interface.

10. The CPU and FPGA virtual-real combined simulation verification system according to claim 6, characterized in that, In the module M4, the running speed of the CPU simulation model and the FPGA acceleration hardware is synchronized through a clock signal provided by DDS.

Images