A reprogrammable memory cell and memory array

Abstract

This application provides a reproducible programmable memory cell and memory array, relating to the field of semiconductor technology, to solve the problem of high power consumption in existing reproducible programmable memory cells. The reproducible programmable memory cell comprises, from bottom to top, a first antiferromagnetic layer, a free layer, a barrier layer, a reference layer, a coupling layer, a fixed layer, and a second antiferromagnetic layer stacked sequentially. By applying a write current to the first antiferromagnetic layer, and under the synergistic effect of the asymmetric stray field generated by the reference layer and the fixed layer and the write current, low-power data writing of the reproducible programmable memory cell can be achieved. No additional write control or additional transistors are required; unidirectional writing can be achieved solely through the physical structure of the device itself, and the written data cannot be changed by current alone, thus improving write reliability. Data erasure is achieved by applying an erase current and an external magnetic field of a specific intensity, effectively solving the problem of excessive power consumption during the erasure process in current reproducible programmable memory cells.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a multiple programmable memory cell and memory array. Background Technology

[0002] Multiple-Time Programmable Non-Volatile Memory (MTP NVM) is an integrated circuit device that can be programmed and erased multiple times throughout its lifespan and retains stored data long-term after power loss. This technology combines the data stability advantages of one-time programmable memory with the reprogrammability flexibility of electrically erasable programmable read-only memory (EEPROM) and flash memory, achieving an optimized balance between cost and functionality. It is particularly suitable for applications with few write cycles and many read cycles, such as configuration parameter storage, calibration data recording, and firmware code persistence.

[0003] Currently, the mainstream technologies for realizing MTP functionality mainly include floating-gate, charge-trapping, and resistive random-access memory (RRAM). Floating-gate technology, based on quantum tunneling or hot carrier injection, injects electrons into a conductive polysilicon floating gate for programming. To achieve quantum tunneling or hot carrier injection, this programming process must generate and consume high voltage within the chip; therefore, floating-gate technology inherently suffers from high power consumption. Charge-trapping technology, on the other hand, traps electrons in a silicon nitride equipotential well layer through quantum tunneling. Although the structure is simplified, its programming method still relies on electron injection or removal, and it still faces problems such as high operating voltage and relatively high power consumption. Furthermore, while simplifying the memory cell to a structure of a floating-gate transistor and an integrated capacitor, and employing a mirrored shared array design, significantly reducing the size of the memory cell, does not change the fundamental nature of floating-gate technology; its programming process still suffers from high power consumption.

[0004] Therefore, there is an urgent need to develop new storage mechanisms and device structures to address the many challenges faced by existing MTP technology in further reducing power consumption. Summary of the Invention

[0005] To address the aforementioned issues, embodiments of this application provide a multiple programmable memory cell and a memory array. By introducing an asymmetric stray field, the writing and erasing methods of the multiple programmable memory cell are optimized to reduce its power consumption during the writing and erasing processes.

[0006] In a first aspect, embodiments of this application provide a multiple programmable memory cell, comprising, from bottom to top, a first antiferromagnetic layer, a free layer, a barrier layer, a reference layer, a coupling layer, a fixed layer, and a second antiferromagnetic layer stacked sequentially; wherein, an asymmetric stray field is generated based on the reference layer and the fixed layer; the initial state is set to a first resistive state, a write current is applied to the first antiferromagnetic layer, and the multiple programmable memory cell is written to a second resistive state under the action of the asymmetric stray field; an erase current is applied to the first antiferromagnetic layer, and simultaneously, an external magnetic field opposite to the direction of the asymmetric stray field is applied to the multiple programmable memory cell to clear the data stored in the multiple programmable memory cell, wherein the strength of the external magnetic field is greater than the strength of the asymmetric stray field.

[0007] According to some embodiments, the reference layer and the fixed layer generate stray fields respectively, and the stray fields generated by the two layers have opposite directions and different intensities to form an asymmetric stray field.

[0008] According to some embodiments, the asymmetric stray field causes the magnetic moment of the free layer to tend to flip to a certain direction, which represents a second resistance state; as the write current is continuously increased, the magnetic moment of the free layer stabilizes in a certain direction, and the multiple programmable memory cell stabilizes in the second resistance state.

[0009] According to some embodiments, the reference layer and the fixed layer have different thicknesses or different cross-sectional areas.

[0010] According to some embodiments, a target write voltage is applied to the first antiferromagnetic layer to short-circuit the barrier layer or to open-circuit the first antiferromagnetic layer, thereby forming a one-time programmable memory cell.

[0011] The multiple programmable memory unit provided in this application has at least the following advantages:

[0012] The multiple programmable memory cell in this embodiment comprises, from bottom to top, a first antiferromagnetic layer, a free layer, a barrier layer, a reference layer, a coupling layer, a fixed layer, and a second antiferromagnetic layer stacked sequentially; an asymmetric stray field is generated based on the reference layer and the fixed layer. By introducing the asymmetric stray field, the magnetic moment of the free layer tends to the direction of the asymmetric stray field. During the writing process, the synergistic effect of the asymmetric stray field and the writing current reduces the writing voltage of the multiple programmable memory cell, thereby reducing its writing power consumption. After data is written, due to the presence of the asymmetric stray field, applying the writing voltage again will not change its resistance state, making data storage stable, thus achieving low-power, high-reliability unidirectional writing. During the erasure process, the combined effect of the erasure current, the external magnetic field, and the asymmetric stray field effectively reduces the erasure voltage, thereby reducing the erasure power consumption of the multiple programmable memory cell. In addition, the cell structure does not require the introduction of an additional high-voltage power supply and additional transistors, which can effectively save layout area and increase storage density.

[0013] Secondly, this application also provides a storage array, including a data area and a reference area, both of which include multiple programmable memory cells arranged in the above embodiments; at least one multiple programmable memory cell in the reference area is in a first resistive state, and at least one multiple programmable memory cell is written to a second resistive state.

[0014] According to some embodiments, the data area also includes an array of magnetic storage cells consisting of multiple magnetic storage cells that do not have asymmetric stray fields.

[0015] According to some embodiments, the multiple programmable memory cell and the magnetic memory cell film stack have the same structure but different dimensions.

[0016] According to some embodiments, the multiple programmable memory cells in the reference region have the same first and second resistance states as the magnetic memory cells, and are used as reference bits for the magnetic memory cell array.

[0017] This application also provides another storage array, including a data area and a reference area. The data area is composed of a plurality of magnetic storage cells that do not have asymmetric spurious fields. The reference area includes at least two multiple programmable storage cells as described in the above embodiments, wherein the multiple programmable storage cells and the magnetic storage cells have the same first and second resistance states, at least one multiple programmable storage cell is in the first resistance state, and at least one multiple programmable storage cell is written to the second resistance state.

[0018] The storage array in this application embodiment has at least the following advantages:

[0019] In this embodiment of the storage array, both the data area and the reference area include multiple programmable memory cells (MPMCs) arranged in the array as described in the previous embodiment. These MPMCs generate an asymmetric stray field based on the reference layer and the fixed layer. By introducing the asymmetric stray field, the magnetic moment of the free layer tends towards the direction of the asymmetric stray field. During the writing process, the synergistic effect of the asymmetric stray field and the write current reduces the write voltage of the MPMC, thereby reducing its write power consumption. After data is written, due to the presence of the asymmetric stray field, applying the write voltage again will not change its resistance state, ensuring stable data storage. This achieves a low-power, high-reliability unidirectional write storage array. During the erasure process, the combined effect of the erase current, the external magnetic field, and the asymmetric stray field effectively reduces the erase voltage, thereby reducing the erase power consumption of the MPMC. Based on the unidirectional write characteristics of the MPMCs, they can be used as reference bits to form the data area in the storage array, wherein at least one... The multiple programmable memory cell is in a first resistive state, and at least one multiple programmable memory cell is written to a second resistive state. The reference bit in the memory array of this application can be integrated with only structural differences, and it can be compatible with the fabrication process of other magnetic memory cells without asymmetric spurious fields, effectively improving manufacturing efficiency. Furthermore, by designing the multiple programmable memory cell in the reference area to have the same first and second resistive states as the magnetic memory cell without asymmetric spurious fields, the multiple programmable memory cell can be used as a substitute reference bit for the aforementioned magnetic memory cell, thereby increasing the flexibility of memory array design. In addition, no additional high-voltage power supply and additional transistors are required for the multiple programmable memory cell in the array layout, which can also effectively save layout area and increase memory array density. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a multiple programmable memory cell in its initial state according to an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of the structure of a multiple programmable memory cell after a write current is applied in one embodiment of this application.

[0022] Figure 3 This is a schematic diagram of a structure in one embodiment of the present application, showing the application of an external magnetic field during the data erasure process of a multiple programmable memory cell.

[0023] Figure 4 This is a schematic diagram of a storage array according to one embodiment of this application.

[0024] Figure 5 This is a schematic diagram of another storage array in one embodiment of this application.

[0025] Figure 6This is a schematic diagram of another multiple programmable memory cell in one embodiment of this application.

[0026] Figure 7 This is a schematic diagram of yet another storage array according to an embodiment of this application.

[0027] Figure 8 This is a schematic diagram of another storage array in one embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 10 - Multiple programmable memory cell; 20 - Magnetic memory cell; 30 - Data area; 40 - Reference area; 11 - First antiferromagnetic layer; 21 - Free layer; 31 - Barrier layer; 41 - Reference layer; 51 - Coupling layer; 61 - Fixed layer; 71 - Second antiferromagnetic layer; 81 - First spurious field; 91 - Second spurious field. Detailed Implementation

[0030] Multiple-programmable non-volatile memory (MTP-NVM) is an integrated circuit device that can be programmed and erased multiple times during its lifespan and retains stored data for a long time after power loss. Currently, the mainstream technologies for implementing MTP functionality mainly include floating-gate, charge-trapping, and resistive random-access memory (RRAM). Floating-gate technology, based on quantum tunneling or hot carrier injection, injects electrons into a conductive polysilicon floating gate to achieve programming. To achieve quantum tunneling or hot carrier injection, this programming process must generate and consume high voltage inside the chip; therefore, floating-gate technology has the inherent disadvantage of high power consumption. Charge-trapping technology traps electrons in a silicon nitride equipotential well layer through quantum tunneling. Although the structure is simplified, its programming method still relies on electron injection or removal, and still faces problems such as high operating voltage and high power consumption. Furthermore, while simplifying the memory cell to a structure of a floating-gate transistor and an integrated capacitor, and using a mirrored shared array design, significantly reducing the size of the memory cell, does not change the essence of floating-gate technology; its programming process still suffers from high power consumption. Therefore, there is an urgent need to develop new storage mechanisms and device structures to address the many challenges faced by existing MTP technology in further reducing power consumption.

[0031] The multiple programmable memory cell in this embodiment comprises, from bottom to top, a first antiferromagnetic layer, a free layer, a barrier layer, a reference layer, a coupling layer, a fixed layer, and a second antiferromagnetic layer stacked sequentially; an asymmetric stray field is generated based on the reference layer and the fixed layer. By introducing the asymmetric stray field, the magnetic moment of the free layer tends to the direction of the asymmetric stray field. During the writing process, the synergistic effect of the asymmetric stray field and the write current reduces the write voltage of the multiple programmable memory cell, thereby reducing its write power consumption. After data is written, due to the presence of the asymmetric stray field, applying the write current again will not change its resistance state, making data storage stable, thus achieving low power consumption and high reliability unidirectional writing. During the erasure process, the synergistic effect of the erase current, the external magnetic field, and the asymmetric stray field effectively reduces the erase voltage, thereby reducing the erase power consumption of the multiple programmable memory cell. In addition, the cell structure does not require the introduction of an additional high-voltage power supply and additional transistors, which can effectively save layout area and increase storage density.

[0032] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described in this application are merely some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Figure 1 This is a schematic diagram of a multiple programmable memory cell 10 provided in an embodiment of the present application. The multiple programmable memory cell 10 includes, from bottom to top, a first antiferromagnetic layer 11, a free layer 21, a barrier layer 31, a reference layer 41, a coupling layer 51, a fixed layer 61, and a second antiferromagnetic layer 71 stacked sequentially; wherein, an asymmetric stray field is generated based on the reference layer 41 and the fixed layer 61.

[0034] The free layer 21, the barrier layer 31, and the reference layer 41 constitute the basic unit of the magnetic tunnel junction. When the magnetic moment direction of the free layer 21 is parallel to the magnetic moment direction of the reference layer 41, the magnetic tunnel junction is in a low-resistance state; when their magnetic moment directions are antiparallel, the magnetic tunnel junction is in a high-resistance state. The two resistance states of the magnetic tunnel junction are used to represent binary data; typically, the low-resistance state is defined as "0", and the high-resistance state is defined as "1". The shape of the magnetic tunnel junction can be circular, elliptical, rectangular, square, triangular, polygonal, etc., and this embodiment does not limit this.

[0035] The free layer 21, the reference layer 41, and the fixed layer 61 can be made of ferromagnetic metals or ferromagnetic alloys, such as Fe, Co, Ni, CoFe, NiFe, CoB, FeB, CoFeB, CoFeBTa, CoFeSiB, FeSi, etc., or any combination of two or more; the barrier layer 31 is a metal oxide, including MgO and Al2O3, etc.

[0036] An exchange bias field is formed between the antiferromagnetic layer and the magnetic layer to pin the magnetic moment of the magnetic layer. In the embodiments of this application, the first antiferromagnetic layer 11 and the second antiferromagnetic layer 71 form exchange bias fields with the free layer 21 and the fixed layer 61, respectively, which can pin the magnetic moment directions of the free layer 21 and the fixed layer 61.

[0037] The first antiferromagnetic layer 11 and the second antiferromagnetic layer 71 can be made of materials such as IrMn, FeMn, PtMn, NiMn, CoTb, GdFeCo, etc. The materials of the two can be the same or different, and the element ratio in each material is not limited to the listed forms, such as IrMn or IrMn3, etc.

[0038] The reference layer 41, coupling layer 51, and fixed layer 61 constitute a synthetic antiferromagnetic structure. The magnetic moment direction of the fixed layer 61 is opposite to that of the reference layer 41. This antiparallel arrangement of magnetic moments is achieved by the coupling layer 51 through RKKY (Ruderman-Kittel-Kasuya-Yosida, RKKY) coupling. This coupling mechanism makes the magnetic moments of the fixed layer 61 and the reference layer 41 exhibit an antiparallel configuration. The material of the coupling layer 51 can be Ru, Ir, etc.

[0039] Since the reference layer 41 and the fixed layer 61 are magnetic layers with in-plane magnetic anisotropy, their magnetization intensity will abruptly change at the edges of the film layers, resulting in unavoidable magnetic field leakage in the surrounding space. This magnetic field leakage is called a stray field. The main component of the stray field at the free layer 21 is located in the plane of the film layer, and its direction is macroscopically opposite to the magnetic moment direction of the reference layer 41 or the fixed layer 61 itself. When the free layer 21 experiences this in-plane stray field, the stray field is equivalent to an equivalent bias field applied to the free layer 21, which tends to stabilize the magnetic moment direction of the free layer 21 in a state parallel to the direction of the stray field.

[0040] In the embodiments of this application, since the magnetic moments of the fixed layer 61 and the reference layer 41 are in opposite directions, the stray fields generated by them at the free layer 21 are in opposite directions. Based on the difference in the intensity of the stray fields generated by the reference layer 41 and the fixed layer 61, an asymmetric stray field can be formed, which makes the magnetic moment of the free layer 21 more inclined to flip to a certain direction under the bias of the asymmetric stray field. This specific direction is parallel or antiparallel to the reference layer 41, thereby realizing the writing or erasure of data.

[0041] One method for generating an asymmetric stray field is to adjust the film structure of the reference layer 41 and the fixed layer 61 so that the thickness of the reference layer 41 and the fixed layer 61 are different or their cross-sectional areas are different. The larger the film thickness or the smaller the cross-sectional area, the stronger the stray field. Therefore, the thickness of the reference layer 41 can be designed to be greater than that of the fixed layer 61, or its cross-sectional area can be smaller than that of the fixed layer 61, so that the stray field generated by the reference layer 41 is greater than that generated by the fixed layer 61, thereby generating an asymmetric stray field at the free layer 21, and the direction of the asymmetric stray field is opposite to the direction of the magnetic moment of the reference layer 41. Alternatively, the thickness of the reference layer 41 can be designed to be smaller than that of the fixed layer 61, or its cross-sectional area can be larger than that of the fixed layer 61, so that the stray field generated by the reference layer 41 is smaller than that generated by the fixed layer 61, thereby generating an asymmetric stray field at the free layer 21, and the direction of the asymmetric stray field is opposite to that of the magnetic moment of the fixed layer 61.

[0042] In this embodiment, the data writing and erasing process of the multiple programmable memory cell 10 is as follows: First, the initial state of the multiple programmable memory cell 10 is set to the first resistive state; during data writing, a write current is applied to the first antiferromagnetic layer 11. The synergistic effect of the write current and the asymmetric stray field is equivalent to a magnetic field-assisted thermal annealing process for the first antiferromagnetic layer 11, causing the magnetic moment of the free layer 21 to be flipped, and the multiple programmable memory cell 10 is written to the second resistive state; during data erasure, an erasure current and an external magnetic field are applied to the first antiferromagnetic layer 11, and the direction of the external magnetic field is opposite to the direction of the asymmetric stray field and its intensity is greater than that of the asymmetric stray field. The synergistic effect of the erasure current, the external magnetic field, and the asymmetric stray field is equivalent to another magnetic field-assisted thermal annealing process for the first antiferromagnetic layer 11, causing the magnetic moment of the free layer 21 to be flipped again, the resistance of the multiple programmable memory cell 10 to change, and the data erasure is completed.

[0043] It is understood that in the multiple programmable memory unit 10 of this application embodiment, the initial first resistance state can be either a high resistance state or a low resistance state, and the second resistance state is a resistance state with the opposite resistance value to the first resistance state. For example, the first resistance state is a high resistance state and the second resistance state is a low resistance state. In the initial state, the magnetic moments of the reference layer 41 and the free layer 21 are antiparallel. By designing the structure of the reference layer 41 and the fixed layer 61, the direction of the asymmetric stray field is designed so that its biasing effect on the free layer 21 tends to cause the magnetic moment direction of the free layer 21 to flip to a direction parallel to the reference layer 41. Thus, after applying a write current, the programmable memory cell 10 is written to a low resistance state. Similarly, if the first resistance state can be a low resistance state, then the second resistance state is a high resistance state. In the initial state, the magnetic moments of the reference layer 41 and the free layer 21 are parallel. By designing the direction of the asymmetric stray field, its biasing effect on the free layer 21 tends to cause the magnetic moment direction of the free layer 21 to flip to a direction antiparallel to the reference layer 41. Thus, after applying a write current, the programmable memory cell 10 is written to a high resistance state.

[0044] The following example uses the first resistance state as the high resistance state, combined with... Figures 1 to 3 As shown, the write and erase processes of the multiple programmable memory cell 10 and the related mechanisms are explained in detail. Figure 1 In the multiple programmable memory cell 10, the arrows inside each film layer represent the magnetic moment direction of each film layer. The first stray field 81 is the stray field generated by the fixed layer 61, and the second stray field 91 is the stray field generated by the reference layer 41. The thickness of the lines represents the strength of the stray field.

[0045] refer to Figure 1 As shown, the first stray field 81 and the second stray field 91 are in opposite directions, and the intensity of the first stray field 81 is greater than that of the second stray field 91. The asymmetric stray field formed by the two causes the magnetic moment of the free layer 21 to tend to flip to a direction parallel to the magnetic moment of the reference layer 41.

[0046] First, an initial state is set. By performing multiple thermal annealing processes on the programmable memory cell 10, the magnetic moments of the free layer 21 and the reference layer 41 are pinned in opposite directions by the first antiferromagnetic layer 11 and the second antiferromagnetic layer 71, resulting in a high-resistivity first state. At this time, the intensity of the asymmetric stray field is insufficient to counteract the pinning effect of the first antiferromagnetic layer 11 on the free layer 21, so the resistance state remains a high-resistivity state.

[0047] Combination Figure 2As shown, during the data writing process, a write current is applied to the first antiferromagnetic layer 11. The Joule heat generated by the write current raises the temperature of the first antiferromagnetic layer 11 above its magnetic ordering temperature (such as the Curie temperature), causing its magnetic moments to change from an ordered fixed state to a disordered superparamagnetic state. This releases the pinning effect on the free layer 21. During the cooling process after the write current is removed, the multiple programmable memory cell 10 is not cooled freely. Instead, under the guidance of the asymmetric stray field, the magnetic moments of the first antiferromagnetic layer 11 rearrange into a definite orientation. Therefore, when the temperature drops below the magnetic ordering temperature, the magnetic moments of the first antiferromagnetic layer 11 will rearrange in order according to the direction of the asymmetric stray field, pinning the magnetic moment direction of the free layer 21 to be parallel to the magnetic moment direction of the reference layer 41. The multiple programmable memory cell 10 is written into a low-resistivity state.

[0048] During this process, the synergistic effect of the write current and the asymmetric stray field is equivalent to a magnetic field-assisted thermal annealing of the first antiferromagnetic layer 11. That is, the Joule heating generated by the write current temporarily eliminates the pinning effect of the first antiferromagnetic layer 11 on the free layer 21. Under the guidance of the asymmetric stray field, the magnetic moment direction of the first antiferromagnetic layer 11 is accurately reset during the cooling process. This mechanism allows the magnetic moment of the free layer 21 to be changed with a lower write current, thereby significantly reducing write power consumption. Furthermore, no additional high-voltage power supply and additional transistors are required in the memory cell structure, effectively saving layout area and increasing storage density.

[0049] After data is written, due to the presence of the asymmetric stray field, the magnetic moment direction of the free layer 21 is always biased in the same direction as that of the reference layer 41. Applying a forward or reverse write current or continuously increasing the write current will not change its resistance state, thus achieving low power consumption and high reliability unidirectional writing. Moreover, the greater the intensity of the asymmetric stray field, the less interference from the external magnetic field is experienced by the multiple programmable memory cell 10 during data writing, and the more stable the data is.

[0050] During the data erasure process, refer to Figure 3An erasure current is applied to the first antiferromagnetic layer 11. The Joule heat generated by the erasure current will also raise the temperature of the first antiferromagnetic layer 11 to above its magnetic order temperature (such as the Curie temperature), causing its magnetic moment to change from an ordered fixed state to a disordered superparamagnetic state, thereby releasing the pinning effect on the free layer 21. During the cooling process after the write current is removed, when the temperature drops below the magnetic order temperature, since the external magnetic field is opposite to the direction of the asymmetric stray field but the strength of the external magnetic field is greater than the strength of the asymmetric stray field, it is possible to break through the direction restriction of the asymmetric stray field, so that the magnetic moment of the first antiferromagnetic layer 11 is rearranged in order according to the direction of the external magnetic field, and the direction of the magnetic moment of the free layer 21 is pinned in the opposite direction again. At this time, the direction of the magnetic moment of the free layer 21 is antiparallel to the direction of the magnetic moment of the reference layer 41. The programmable memory cell 10 is written back to the high-resistivity state, completing the data erasure.

[0051] During this process, the synergistic effect of the erasure current, the external magnetic field, and the asymmetric stray field is equivalent to performing a magnetic field-assisted thermal annealing process on the first antiferromagnetic layer 11 again. That is, the Joule heating generated by the erasure current temporarily eliminates the pinning effect of the first antiferromagnetic layer 11 on the free layer 21. During the cooling process, under the combined guidance of the external magnetic field and the asymmetric stray field, the magnetic moment direction of the first antiferromagnetic layer 11 is accurately reset, thereby enabling the magnetic moment of the free layer 21 to be changed with a lower erasure current, thus significantly reducing the erasure power consumption.

[0052] In the above embodiments, the directions of the write current and the erase current are both in-plane directions along the magnetic moment of the free layer 21, such as the positive x direction, negative x direction, positive y direction, negative y direction, etc., which can generate Joule heating in the first antiferromagnetic layer 11. There are no special restrictions on the specific directions, and the current directions of the two can be the same or different.

[0053] In some possible implementations, the initial state can be set to a low-resistance state. An asymmetric stray field is designed to bias the free layer 21, causing its magnetic moment to tend to flip to an antiparallel state with the reference layer 41. During data writing, a write current is applied to the first antiferromagnetic layer 11. Under the influence of the asymmetric stray field, the multiple programmable memory cell 10 is written to a high-resistance state. During data erasure, an erase current is applied to the first antiferromagnetic layer 11. Simultaneously, an external magnetic field opposite in direction to the asymmetric stray field is applied to the multiple programmable memory cell 10. The strength of the external magnetic field is greater than that of the asymmetric stray field, thus erasing the data stored in the multiple programmable memory cell 10. The writing process, erasure process, and related mechanisms of this implementation are similar to those described in the previous implementations and will not be repeated here.

[0054] In some possible implementations, the multiple programmable storage unit 10 can also be converted into a one-time programmable storage unit to permanently store data, making the data difficult to tamper with and improving the security of the storage device.

[0055] After multiple initial states or second resistive states of the programmable memory cell 10 are written, a target write voltage is applied to the first antiferromagnetic layer 11, causing either a short circuit in the barrier layer 31 or an open circuit in the first antiferromagnetic layer 11, thereby forming a primary programmable memory cell. This permanently writes the data and prevents it from being altered. The target write voltage can be greater than the breakdown voltage of the barrier layer 31 to short-circuit it, or it can be greater than the open circuit voltage of the first antiferromagnetic layer 11 to open it. The data write path of the formed primary programmable memory cell is disrupted, allowing for the storage of fixed data and effectively protecting the data from tampering. This can be used for device authentication and device key storage.

[0056] This application embodiment also provides a storage array, including a data area and a reference area, both of which include multiple programmable memory cells arranged in the array as described in the above embodiments; at least one multiple programmable memory cell in the reference area is in a first resistive state, and at least one multiple programmable memory cell is written to a second resistive state.

[0057] In this storage array, the data area is used to store data, and the reference area is used to verify the accuracy of the data stored in the data area. The reference area needs to include at least two multiple programmable memory cells, whose resistance states correspond to the first and second resistance states of the multiple programmable memory cells in the data area, respectively, to serve as reference bits for the data area and to verify whether the first and second resistance states of the multiple programmable memory cells in the data area have been accurately written. Preferably, each row of multiple programmable memory cells in the storage array is configured with two reference bits with different resistance states to reduce read interference between multiple programmable memory cells 10 in different rows and improve read reliability.

[0058] The structure of the multiple programmable memory cells in the memory array can be referenced. Figure 1 As shown, the multiple programmable memory cell 10 generates an asymmetric stray field based on the reference layer 41 and the fixed layer 61. During the writing process, by introducing the asymmetric stray field, the magnetic moment of the free layer 21 tends to flip to the direction of the asymmetric stray field, which can reduce the writing voltage of the multiple programmable memory cell 10 and thus reduce its writing power consumption. During the erasure process, the combined effect of the erasure current, the asymmetric stray field, and the external magnetic field effectively reduces the erasure power consumption. Its specific structure and the writing and erasure processes have been described in detail above and will not be repeated here.

[0059] Based on the unidirectional write characteristic of the multiple programmable memory cell 10, after data is written, due to the presence of the asymmetric stray field, applying write current again will not change its resistance state, and the data storage is stable, so it can be used as a reference bit in the data area. Among the multiple programmable memory cells 10 used as reference bits, at least one multiple programmable memory cell 10 is in a first resistance state (such as the initial state), and at least one multiple programmable memory cell 10 is written to a second resistance state.

[0060] In some possible implementations, see [reference] Figure 4 The memory array shown has data area 30 and reference area 40 both formed by multiple programmable memory cells 10. For some of the multiple programmable memory cells 10 in reference area 40, since their resistive state is fixed at the initial state, no additional writing component is required. Therefore, this part of the multiple programmable memory cells 10 can save a write transistor, which can further reduce the write power consumption and area waste of the memory array.

[0061] The reference area 40 and the data area 30 are both formed by multiple programmable memory cells 10. The multiple programmable memory cells 10 arranged in the array can share signal lines. For example, each row of multiple programmable memory cells 10 shares the same read word line RWL and write word line WWL, and each column of multiple programmable memory cells 10 shares a source line SL and bit line BL to save layout area.

[0062] In some possible implementations, the data area 30 may also include an array of magnetic storage cells consisting of multiple magnetic storage cells that do not have asymmetric stray fields.

[0063] Magnetic memory cells without asymmetric stray fields have stray fields that are close to equilibrium and do not bias the magnetic moment of the free layer 21 or the bias effect is so small that it can be ignored. The device type can be Toggle-MRAM (Toggle Magnetoresistive Random Access Memory), or it can be a spin-orbit moment magnetic memory cell or a spin-transfer moment magnetic memory cell, etc., without any restrictions.

[0064] More preferably, the magnetic storage unit is a structural improvement based on the multiple programmable storage unit 10 in the embodiments of this application. The two have the same film layer stacking method. By making the stray field of the multiple programmable storage unit 10 close to equilibrium through structural differentiation design, a magnetic storage unit is formed. Furthermore, the two storage units can be integrated synchronously in the same storage array without additional manufacturing steps, thereby improving manufacturing efficiency and saving manufacturing costs.

[0065] In this embodiment, the reference layer 41 and the fixed layer 61 in the magnetic storage cell can be designed to have the same thickness or cross-sectional area, so that the stray fields generated by the reference layer 41 and the fixed layer 61 have different directions but the same intensity. The stray fields of the two cancel each other out, so that the magnetic storage cell has no stray field. However, the reference layer 41 and the fixed layer 61 in the multiple programmable storage cell 10 have different thicknesses or cross-sectional areas, so that the stray fields generated by the reference layer 41 and the fixed layer 61 have different directions and intensities, thereby generating the required asymmetric stray field. Alternatively, since the smaller the size of the storage cell, the stronger the stray field sensed at the center of the free layer 21, the size of the magnetic storage cell (such as aspect ratio, cross-sectional area, etc.) can be designed to be larger than the size of the multiple programmable storage cell 10 in this application embodiment, so as to ensure that the stray field in the magnetic storage cell is close to equilibrium while the multiple programmable storage cell 10 still has an asymmetric stray field.

[0066] Figure 5 In one embodiment of this application, a storage array includes a data area 30 containing both a multiple programmable memory cell 10 and a magnetic memory cell 20 without an asymmetric stray field. Both cells have the same film layer stacking method. To ensure that the stray field in the magnetic memory cell 20 is nearly balanced while the multiple programmable memory cell 10 still has an asymmetric stray field, the size of the magnetic memory cell 20 is larger than the size of the multiple programmable memory cell 10. Similarly, the multiple programmable memory cell 10 in the reference area 40 also needs to have the same size design as the multiple programmable memory cell 10 in the data area 30 to ensure that their barrier layers 31 are the same size and have the same first and second resistance states. This allows the reference area 40 to confirm whether the first and second resistance states of the multiple programmable memory cell 10 in the data area have been accurately written.

[0067] The memory cell stack structure in the data area 30 and the reference area 40 is the same, and their writing and reading methods are also the same. The multiple programmable memory cells 10 and magnetic memory cells 20 arranged in the array can share signal lines. For example, each row of multiple programmable memory cells 10 and magnetic memory cells 20 can share the same read word line RWL and write word line WWL, and each column of multiple programmable memory cells 10 and magnetic memory cells 20 can share a source line SL and a bit line BL to save layout area.

[0068] For some of the multiple programmable memory cells 10 in the reference region 40, since their resistive state is fixed at the first resistive state, no resistive state writing component is required. Therefore, this portion of the multiple programmable memory cells 10 can save one write transistor, thereby further reducing the write power consumption and area waste of the memory array.

[0069] In the storage array of this embodiment, since the multiple programmable memory cell 10 and the magnetic memory cell 20 have different sizes, their barrier layer 31 sizes are also different, and the resistance values ​​of the first and second resistive states are also different. To avoid data writing errors, the reference bits cannot be mixed. Therefore, the reference area 40 also includes reference bits formed by the magnetic memory cell 20, which are used to confirm whether the first and second resistive states of the magnetic memory cell 20 in the data area 30 have been accurately written.

[0070] To further reduce the power consumption and save layout area of ​​the memory array, this application also proposes a memory array including a data area and a reference area. The data area includes multiple programmable memory cells arranged in the above embodiments and multiple magnetic memory cells without asymmetric spurious fields. The reference area includes multiple programmable memory cells arranged in the above embodiments, at least one multiple programmable memory cell in the reference area is in a first resistive state, and at least one multiple programmable memory cell is written to a second resistive state. The multiple programmable memory cells in the reference area have the same first and second resistive states as the magnetic memory cells, and are used as reference bits for the magnetic memory cell array.

[0071] In the memory array of this embodiment, the multiple programmable memory cells in the reference area can be used as reference bits for multiple programmable memory cells in the data area, and also as reference bits for magnetic memory cells in the data area. On the one hand, the multiple programmable memory cells have lower write and erase power consumption, which can reduce the power consumption of the memory array. On the other hand, it can save the reference bit configuration of magnetic memory cells, reduce the layout area occupied by the reference area and the number of transistors, further reduce the power consumption of the memory array and improve the layout utilization.

[0072] To ensure that the multiple programmable memory cells in the reference region have the same first and second resistive states as the magnetic memory cells, the multiple programmable memory cells need to have the same film stack structure and barrier layer size as the magnetic memory cells. In addition, the multiple programmable memory cells need to retain the asymmetric stray field.

[0073] To meet the above requirements, refer to Figure 6 The multiple programmable memory cell 10 shown in this embodiment has been miniaturized in terms of the film layers above the fixed layer 61 in the reference region. By reducing the cross-sectional area of ​​the fixed layer 61, it has a stronger stray field, which forms an asymmetric stray field with the stray field generated by the reference layer 41, thereby realizing data writing and erasure. At the same time, the barrier layer 31 of the multiple programmable memory cell 10 and the magnetic memory cell 20 have the same size and the same first and second resistance states. The multiple programmable memory cell 10 can be used as a reference bit of the magnetic memory cell 20.

[0074] The storage array reference in this embodiment Figure 7 As shown, similarly, the multiple programmable memory cell 10 in the data area 30 also needs to be designed in the same way as the multiple programmable memory cell 10 in the reference area 40 to ensure that the multiple programmable memory cells 10 in the data area 30 and the reference area 40 have the same first resistance state and second resistance state.

[0075] Ultimately, the multiple programmable memory cell 10 in the reference area 40 of the memory array in this embodiment can be used as a reference bit for both the multiple programmable memory cell 10 in the data area and the magnetic memory cell 20.

[0076] Since the data area 30 and the reference area 40 have the same storage cell structure, their writing and reading methods are also the same. The multiple programmable storage cells 10 and magnetic storage cells 20 arranged in the array can share signal lines. For example, each row of multiple programmable storage cells 10 and magnetic storage cells 20 can share the same read word line RWL and write word line WWL, and each column of multiple programmable storage cells 10 and magnetic storage cells 20 can share a source line SL and a bit line BL, so as to further save the layout area.

[0077] For some of the multiple programmable memory cells 10 in the reference region 40, since their resistive state is fixed at the first resistive state, no resistive state writing component is required. Therefore, this portion of the multiple programmable memory cells 10 can save one write transistor, thereby further reducing the write power consumption and area waste of the memory array.

[0078] Furthermore, since the multiple programmable memory cell 10 in the memory array of this embodiment can be used as a reference bit for the magnetic memory cell 20 in the data area 30, this application embodiment also proposes a memory array, referencing... Figure 8 As shown, with Figure 7 The difference in the illustrated memory array is that the data area 30 is entirely composed of multiple magnetic memory cells 20 without asymmetric spurious fields, while the reference area 40 is formed by multiple programmable memory cells 10 to create the reference bits for the data area 30. In this memory array, based on the unidirectional write characteristics of the multiple programmable memory cells 10, low-power, write-stable reference bits can be obtained, thereby reducing the power consumption of the memory array and improving its reliability.

[0079] In this embodiment of the storage array, both the data area 30 and the reference area 40 include the multiple programmable memory cells 10 arranged in the array as described in the previous embodiment. These multiple programmable memory cells 10 generate an asymmetric stray field based on the reference layer 41 and the fixed layer 61. By introducing the asymmetric stray field, the magnetic moment of the free layer 21 tends towards the direction of the asymmetric stray field. During the writing process, the synergistic effect of the asymmetric stray field and the write current reduces the write voltage of the multiple programmable memory cell 10, thereby reducing its write power consumption. After data writing, due to the presence of the asymmetric stray field, applying the write current again will not change its resistance state, ensuring stable data storage and thus achieving a low-power, high-reliability unidirectional write storage array. During the erasure process, the synergistic effect of the erase current, the asymmetric stray field, and the external magnetic field effectively reduces the erase voltage, thereby reducing the power consumption of the multiple programmable memory cell 10. The erase power consumption is 0; and, based on the unidirectional write characteristic of the multiple programmable memory cell 10, it can be used as a reference bit to form the data area 30 in the memory array; and, the data area 30 and the reference area 40 in the memory array of this application only need structural differences to complete synchronous integration, which effectively improves manufacturing efficiency; in addition, by designing the multiple programmable memory cell 10 in the reference area 40 and the magnetic memory cell 20 in the data area 30 to have the same first resistance state and second resistance state, the multiple programmable memory cell 10 can be used as a substitute reference bit for the magnetic memory cell 20, thereby increasing the flexibility of memory array design and storage density.

[0080] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-time programmable memory cell, comprising: The first antiferromagnetic layer, the free layer, the barrier layer, the reference layer, the coupling layer, the fixed layer and the second antiferromagnetic layer are stacked from bottom to top; The asymmetric stray field is generated based on the stray fields generated by the reference layer and the fixed layer respectively, and the asymmetric stray field is generated based on the different directions and different strengths of the stray fields generated by the reference layer and the fixed layer respectively; The initial state is set as the first resistance state, a write current is applied to the first antiferromagnetic layer, and the multiple programmable memory cells are written to the second resistance state under the action of the asymmetric stray field; An erase current is applied to the first antiferromagnetic layer, and an external magnetic field opposite to the direction of the asymmetric stray field is applied to the multiple programmable memory cells to clear the data stored in the multiple programmable memory cells, and the strength of the external magnetic field is greater than the strength of the asymmetric stray field.

2. The multi-time programmable memory cell of claim 1, wherein, The asymmetric stray field makes the magnetic moment of the free layer tend to flip to a certain specific direction, and the certain specific direction represents the second resistance state; The write current is continuously increased, the magnetic moment of the free layer is stabilized in the certain specific direction, and the multiple programmable memory cells are stabilized in the second resistance state.

3. The multi-time programmable memory cell of claim 1, wherein, The reference layer and the fixed layer have different thicknesses or different cross-sectional areas.

4. The multi-time programmable memory cell of any one of claims 1 to 3, wherein, A target write voltage is applied to the first antiferromagnetic layer to short the barrier layer or open the first antiferromagnetic layer, thereby forming a one-time programmable memory cell.

5. A memory array comprising: The data area and the reference area each include an array of the multiple programmable memory cells according to any one of claims 1 to 3; At least one of the multiple programmable memory cells in the reference area is in the first resistance state, and at least one of the multiple programmable memory cells is written to the second resistance state.

6. The storage array of claim 5, wherein, The data area further includes a magnetic storage unit array composed of a plurality of magnetic storage units without the asymmetric stray field.

7. The storage array of claim 6, wherein, The multiple programmable memory cells and the magnetic storage units have the same film stack structure and different sizes.

8. The storage array of claim 6, wherein, The multiple programmable memory cells in the reference area have the same first resistance state and second resistance state as the magnetic storage units, and are used as reference bits of the magnetic storage unit array.

9. A memory array comprising: The data area and the reference area each include an array of the multiple programmable memory cells according to any one of claims 1 to 3; The reference area includes at least two multiple programmable memory cells according to any one of claims 1 to 3, wherein the multiple programmable memory cells and the magnetic storage units have the same first resistance state and second resistance state, at least one of the multiple programmable memory cells is in the first resistance state, and at least one of the multiple programmable memory cells is written to the second resistance state.

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