A method for manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which is applied to the technical field of semiconductor technology.The application comprises the following steps: providing a substrate with first conductive type doping ions, forming a deep trench in the substrate, forming a doping region with second conductive type doping ions in the part of the substrate below the deep trench, and forming a metal silicide layer at the bottom of the deep trench; thus, by combining the formation of the metal silicide layer at the bottom of the deep trench and the formation of the doping region in the part of the substrate below the deep trench, the characteristics of forming ohmic contact by the close work function of the metal silicide layer and the conductive layer can be achieved, the conduction between the conductive layer and the metal silicide layer can be realized, the carrier concentration in the substrate can be improved by the doping region, the characteristics of forming ohmic contact between the substrate with the improved carrier concentration and the metal silicide layer can be achieved, the conduction between the metal silicide layer and the substrate can be realized, and the same type or also type conduction between the conductive layer and the substrate can be realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] As IC integration density increases, market demands for BCD (Browser-Chip-Device) process products become more stringent. This leads to a corresponding increase in effective area as voltage withstand capabilities rise. To address this issue, Deep Trench Isolation (DTI) structures are employed, achieving higher voltage withstand capabilities within a smaller lateral dimension.

[0003] Currently, the mainstream DTI structures are roughly divided into two types: one is filled with silicon dioxide (SiO2) to play an isolation role, so as to improve the device's withstand voltage; the other is filled with P-type doped polysilicon to a depth of 40um, so as to achieve the same type of conduction with the P-type doped substrate, so as to act as a conductor while also taking out the leakage current and noise at the substrate end.

[0004] However, in DTI where the contact resistance between P-type doped polysilicon and P-type doped substrate, which acts as a conductor, is required to be on the order of several hundred ohms, P-type doped polysilicon with high ion doping concentration is prone to diffusion and thus causes ion contamination under high temperature and stress. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a semiconductor device, which enables polysilicon (conductive layer) to achieve homogeneous or heterogeneous conduction with a substrate or isolation buried layer, thereby reducing manufacturing costs, improving the voltage withstand capability of the semiconductor device, and reducing the chip area occupied by the semiconductor device.

[0006] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor device, comprising: providing a substrate having doped ions of a first conductivity type.

[0007] Deep trenches are formed within the substrate.

[0008] The medium layer is formed on the inner wall of the deep trench.

[0009] A doped region with doped ions of a second conductivity type is formed within a portion of the substrate below the deep trench, wherein the conductivity type of the doped ions of the second conductivity type is the same as that of the doped ions of the first conductivity type.

[0010] A metal silicide layer is formed at the bottom of the deep trench, the metal silicide layer is located in the doped region, and its bottom is in direct contact with the doped region.

[0011] A conductive layer with third conductivity type doping ions is formed on the dielectric layer and the metal silicide layer and fills the deep trench.

[0012] In one optional example, the first conductivity type doping ions and the third conductivity type doping ions can have different conductivity types.

[0013] In one optional example, the material of the conductive layer can include polysilicon.

[0014] In one optional example, before forming the deep trench, the fabrication method can further include:

[0015] An isolation buried layer with fourth conductivity type doping ions is formed in the substrate, the isolation buried layer is located below the deep trench, and a portion of the top of the isolation buried layer directly contacts the bottom of the metal silicide layer, so that the doped region is located in the isolation buried layer.

[0016] In one optional example, the fourth conductivity type doping ions and the first conductivity type doping ions have different conductivity types.

[0017] In one optional example, the fourth conductivity type doping ions and the second conductivity type doping ions can have the same conductivity type.

[0018] In one optional example, the deep trench can have a depth in the substrate in the vertical direction greater than or equal to 40 um.

[0019] In one optional example, the step of forming the metal silicide layer can include:

[0020] A first metal layer is formed on the bottom of the deep trench and the surface of the dielectric layer.

[0021] A second metal layer is formed on the first metal layer.

[0022] The substrate is annealed to cause the first metal layer and the second metal layer on the bottom of the deep trench to react with the substrate thereunder to form the metal silicide layer.

[0023] In one optional example, the material of the first metal layer can include metal titanium or metal cobalt, and the material of the second metal layer can include titanium nitride.

[0024] In one optional example, the semiconductor device can be an LDMOS transistor.

[0025] Compared with the prior art, the technical solution provided by the present application has at least one of the following beneficial effects:

[0026] The present application provides a method for fabricating a semiconductor device, comprising: providing a substrate with first conductive type doping ions, forming a deep trench in the substrate, forming a dielectric layer on the inner sidewall of the deep trench, forming a doping region with second conductive type doping ions in the part of the substrate under the deep trench, the second conductive type doping ions have the same conductive type as the first conductive type doping ions, forming a metal silicide layer on the bottom of the deep trench, the metal silicide layer is located on the doping region and its bottom directly contacts the doping region, forming a conductive layer with third conductive type doping ions on the dielectric layer and the metal silicide layer, and filling the deep trench.

[0027] As described above, in one aspect of the present application, the metal silicide layer formed on the bottom of the deep trench and the doping region with the same conductive type as the substrate formed in the part of the substrate under the deep trench are combined, and the unexpected effect is that the Ohmic contact can be formed by the work function of the metal silicide layer and the conductive layer, the conductive layer and the metal silicide layer are connected, the carrier concentration in the substrate is increased by the doping region, the Ohmic contact can be formed by the carrier concentration in the substrate and the metal silicide layer, the metal silicide layer and the substrate are connected, and the same type or also type of the conductive layer and the substrate is connected.

[0028] In another aspect of the present application, the isolation buried layer (for example, NBL buried layer) is formed in the part of the substrate under the deep trench, the metal silicide layer is formed on the bottom of the deep trench, and the doping region is formed in the isolation buried layer opposite to the deep trench, and the unexpected effect is that the Ohmic contact can be formed by the work function of the metal silicide layer and the conductive layer, the conductive layer and the metal silicide layer are connected, the carrier concentration in the isolation buried layer is increased by the doping region in the isolation buried layer, the Ohmic contact can be formed by the carrier concentration in the isolation buried layer and the metal silicide layer, the metal silicide layer and the isolation buried layer are connected, and the same type or also type of the conductive layer and the isolation buried layer is connected.

[0029] And, since the semiconductor device, such as the LDMOS transistor, in the present application needs a longer drift region extending in the horizontal direction to obtain a higher breakdown voltage, the isolation buried layer conducting with the conductive layer in the deep trench can be used as a partial drift region of the semiconductor device, such as the LDMOS transistor, and thus the width of the semiconductor device, such as the LDMOS transistor, in the horizontal direction can be reduced, and thus the length design requirement of the drift region of the semiconductor device, such as the LDMOS transistor, can be met, the withstand voltage can be improved, and the chip area of the semiconductor device, such as the LDMOS transistor, can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is made of the description to explain the present application together with the following detailed description, and do not constitute a limitation to the present application. In the drawings:

[0031] Figure 1 It is a flow chart of the manufacturing method of the semiconductor device in the embodiment of the present application.

[0032] Figures 2-8 It is a structure schematic diagram of the manufacturing method of the semiconductor device in the first embodiment of the present application in the preparation process.

[0033] Figures 9-16 It is a structure schematic diagram of the manufacturing method of the semiconductor device in the second embodiment of the present application in the preparation process.

[0034] In the drawings, the same components are marked with the same reference numerals, and the drawings are not drawn according to the actual scale.

[0035] 100 - substrate, 101 - deep trench, 110 - epitaxial layer, 101 - deep trench, 120 - pad oxide layer, 130 - dielectric layer, 140 - doped region, 150 - metal layer, 151 - first metal layer, 152 - second metal layer, 160 - metal silicide layer, 170 - conductive layer, 180 - isolation buried layer.

[0036] In the drawings, the same components are marked with the same reference numerals, and the drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0037] In order to make the technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the present application will be further described in detail below in combination with the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to make the present application more thoroughly understood and to fully convey the scope of the present application to those skilled in the art.

[0038] The application will be described in more detail in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present application will become apparent from the following description of the application and the claims. It is to be understood that the drawings are designed solely for purposes of illustration and are not intended to limit the scope of the application, as the application can admit to other equally effective implementations. It is to be understood that "on", "over", and "above" as used herein are to be interpreted in their broadest context to mean not only "on" something without intervening characteristic or layer therebetween (i.e., directly on something), but also to include "on" something with intervening characteristic or layer therebetween.

[0039] In the embodiments of the present application, the terms "first", "second" and the like are used to distinguish similar objects, and are not necessarily used to describe a particular sequential or chronological order. It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0040] For the convenience of understanding, the direction parallel to the substrate 100 and the direction perpendicular to the surface of the substrate 100 are defined in the following, and for the purpose of simplifying the description, the direction parallel to the surface of the substrate 100 is simply referred to as the horizontal direction, and the direction perpendicular to the surface of the substrate 100 is simply referred to as the vertical direction.

[0041] Please refer to Figure 1 , Figure 1 The flowchart of the method for manufacturing a semiconductor device provided in the embodiment is shown in FIG. 1. As shown in FIG. 1, the method for manufacturing a semiconductor device provided in the embodiment includes the following steps: Figure 1

[0042] Step S101, providing a substrate with first conductive type doping ions.

[0043] Step S102, forming a deep trench in the substrate.

[0044] Step S103, forming a dielectric layer on the inner sidewall of the deep trench.

[0045] Step S104, forming a doping region with second conductive type doping ions in the part of the substrate below the deep trench, the second conductive type doping ions have the same conductive type as the first conductive type doping ions.

[0046] Step S105, forming a metal silicide layer at the bottom of the deep trench, the metal silicide layer is located at the doping region, and the bottom of the metal silicide layer directly contacts the doping region.

[0047] Step S106, forming a conductive layer with third conductive type doping ions on the dielectric layer and the metal silicide layer, and filling the deep trench.​

[0048] In order to enable those skilled in the art to which the present application pertains to easily understand the manufacturing method of the semiconductor device in the embodiments of the present application, the manufacturing method of the semiconductor device proposed by the present application will be further described below in combination with the structural schematic diagrams of each structure in the manufacturing process. Among them, Figures 2-8 The structural schematic diagram of the manufacturing method of the semiconductor device provided in the first embodiment of the present application in the manufacturing process is shown in FIG. 1. The following will be described in combination with Figures 2-8 The manufacturing method of the semiconductor device provided in the first embodiment of the present application will be described in detail.

[0049] Please refer to Figure 2 , the structure schematic diagram of forming a deep trench in the substrate in the first embodiment of the present application is shown. As shown in FIG. 1, the substrate 1 is formed by a semiconductor material, and a deep trench 2 is formed in the substrate 1. Figure 2As shown, step S101 is performed to provide a substrate 100, which serves as a platform for forming a semiconductor device, such as an LDMOS transistor (which can be an N-channel LDMOS transistor, for example), including components and / or parts such as a deep trench, a metal silicide layer, a doped region, etc. In one embodiment, the substrate 100 can be any suitable substrate material known in the art, such as a substrate including a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an epitaxial silicon substrate, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, or other suitable material, but is not limited thereto. Those skilled in the art would readily understand that various active components and / or passive components, such as an epitaxial layer and / or a well region (not shown), can be further formed on or in the substrate 100 according to actual device requirements, but are not limited thereto. Preferably, after the substrate 100 is provided, an epitaxial process can be further utilized to form an epitaxial layer 110 having a thickness of about 8 um on a surface of the substrate 100, and then a deposition process can be utilized to form a pad oxide layer 120 having a thickness of about 2000 Å on a surface of the epitaxial layer 110, so that the pad oxide layer 120 can protect the epitaxial layer 110 during a subsequent etching process for forming the deep trench, but is not limited thereto. In addition, the substrate 100 can be a doped substrate material, i.e., the substrate 100 having a first conductivity type dopant, and the epitaxial layer 110 can also be a doped epitaxial material, such as a silicon material having the same conductivity type as the dopant of the substrate 100. Preferably, the conductivity type of the first conductivity type dopant is P-type, and the material of the substrate 100 can be silicon; in this case, the substrate 100 is preferably a P-type silicon substrate. The material of the pad oxide layer 120 can be silicon dioxide, but is not limited thereto.

[0050] Please continue to refer to Figure 2, execute step S102: first form a photoresist layer (not shown) on the pad oxide layer 120, the photoresist layer has an opening pattern therein, the opening pattern is used to form the deep trench; under this setting, further take the photoresist layer as a mask, utilize at least one of etching processes such as dry etching process or wet etching process to etch the pad oxide layer 120, the epitaxial layer 110 and part of the depth of the substrate 100 in sequence along the vertical direction downward, to form at least one deep trench 101 in the pad oxide layer 120, the epitaxial layer 110 and the substrate 100. In an embodiment, the depth of the deep trench 101 in the substrate 100 along the vertical direction can be greater than or equal to 40um, for subsequent construction of the trench isolation structure for wire function, but not limited thereto. It should be understood that the drawing in the first embodiment of the present application only exemplarily forms one deep trench 101 in the substrate 100, and in other embodiments, a plurality of deep trenches 101 can also be provided according to the different settings of the devices in the BCD integrated device. Exemplarily, the shape of the deep trench 101 can be a long strip extending along the vertical direction, and the sidewall of the deep trench 101 has a certain inclination along the vertical direction, but not limited thereto.

[0051] Please refer to Figure 3 , the drawing shows the structure of forming a dielectric layer in the deep trench in the first embodiment of the present application. As shown in Figure 3 , execute step S103: utilize at least one of deposition processes such as physical vapor deposition process, chemical vapor deposition process and atomic layer deposition process to co-form a dielectric layer 130 on the inner surface of the deep trench 101, and on the surface of the pad oxide layer 120 exposed on both sides of the deep trench 101. In an embodiment, the material of the dielectric layer 130 is a single layer or multi-layer dielectric material used to form the trench isolation structure, wherein the applicable dielectric material can exemplarily include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, nitrogen-doped silicon carbide, low dielectric constant dielectric material such as fluorosilicate glass, carbon silicon oxide, spin-on silicon glass, porous low dielectric constant dielectric material, organic polymer dielectric material, or a combination of the above materials, but not limited thereto; exemplarily, the material of the dielectric layer 130 in the first embodiment of the present application is silicon dioxide, i.e. the same as the material of the pad oxide layer 120, thereby increasing the total thickness of the silicon dioxide covering the epitaxial layer 110 along the vertical direction. Exemplarily, the thickness of the dielectric layer 130 on the inner surface of the deep trench 101 and on the surface of the pad oxide layer 120 is about 3000Å~4000Å; under this setting, the thickness of the silicon dioxide on the epitaxial layer 110 is about 5000Å~6000Å, but not limited thereto.

[0052] Please refer to Figure 4, the illustrated is the structural schematic diagram of removing part of the medium layer formed in the deep trench to expose the substrate below the deep trench in the first embodiment of the present application. As shown in Figure 4 , the receiving step S103: the medium layer 130 at the bottom of the deep trench 101 can be removed to expose the substrate 100 below the deep trench 101 by using an etching process, such as dry etching process. In an embodiment, since the medium layer 130 on both sides of the deep trench 101 is not shielded during the process of removing the medium layer 130 at the bottom of the deep trench 101 by using the etching process of the present step, the medium layer 130 on both sides of the deep trench 101 will also be removed by a certain thickness, for example, 1000 Å, in the etching process of the present step, so that the total thickness of the silicon dioxide remaining on both sides of the deep trench 101 is about 5000 Å, but not limited thereto.

[0053] Please refer to Figure 5 , the illustrated is the structural schematic diagram of forming the doped region in part of the substrate below the deep trench in the first embodiment of the present application. As shown in Figure 5 , the execution step S104: the ion implantation process can be used to perform ion implantation to the exposed substrate 100 at the bottom of the deep trench 101 to form the doped region 140 with the second conductive type doped ions in part of the substrate 100 below the deep trench 101. In an embodiment, the conductive type of the second conductive type doped ions is the same as the type of the doped ions of the substrate 100 to achieve the purpose of increasing the carrier concentration of the substrate 100. In other words, the conductive type of the second conductive type doped ions is the same as the conductive type of the first conductive type doped ions; preferably, the second conductive type doped ions are P-type ions, such as boron ions (B), and the doped region 140 is a high-concentration P-type region, for example, the doped concentration of the boron ions is 10 15 cm -3 , but not limited thereto.

[0054] Please refer to Figure 6 , the illustrated is the structural schematic diagram of forming the metal layer in the deep trench in the first embodiment of the present application. As shown in Figure 6As shown, step S105 is performed: a deposition process, such as a chemical vapor deposition process, is further utilized to conformally form a metal layer 150 on the inner surface of the deep trench 101 and on the remaining dielectric layer 130 on both sides of the deep trench 101. In one embodiment, the metal layer 150 can be a single layer structure, such as a metal titanium or a metal cobalt, or a composite layer structure, such as a stack structure of a metal titanium and a titanium nitride. In the first embodiment of the present application, the metal layer 150 is a composite layer structure, i.e., the metal layer 150 includes a first metal layer 151 (a metal titanium or a metal cobalt) and a second metal layer 152 (a titanium nitride) stacked in sequence from bottom to top. Specifically, the first metal layer 151 can have a thickness of about 300 A, and the second metal layer 152 can have a thickness of about 100 A.

[0055] Please refer to Figure 7 , which is a schematic diagram of forming a metal silicide layer at the bottom of a deep trench in the first embodiment of the present application. As shown, Figure 7 , step S105 is continued: then, at least one annealing process is performed on the substrate 100 having the metal layer 150 formed thereon, so as to cause the metal layer 150 at the bottom of the deep trench 101 to react with the portion of the substrate 100 (i.e., the portion of the doped region 140) thereunder to form a metal silicide layer 160. In one embodiment, the substrate 100 having the metal layer 150 formed thereon can be subjected to multiple annealing processes, such as a rapid thermal annealing process (RTA) at a temperature of about 500 °C first, and then a rapid thermal annealing process (RTA) at a temperature of about 800 °C, so as to cause the first metal layer 151 at the bottom of the deep trench 101 to react sufficiently and form a metal silicide layer 160 in a low resistance state, such as a titanium disilicide (TiSi2) or a cobalt disilicide (CoSi2), but not limited thereto. It should be understood that after the metal silicide layer 160 is formed, an etching process, such as a dry etching process, is utilized to remove the metal layer 150 that is not subjected to the metal silicide reaction from the surface of the dielectric layer 130 in the deep trench 101 and from the surface of the dielectric layer 130 on both sides of the deep trench 101.

[0056] Please refer to Figure 8 , which is a schematic diagram of forming a conductive layer (polysilicon) in the remaining space of a deep trench in the first embodiment of the present application. As shown, Figure 8As shown, step S106 is performed: filling and filling up the conductive layer 170 in the remaining space of the deep trench 101 having the metal silicide layer 160 at the bottom and the dielectric layer 130 at the two side walls by using a deposition process, such as a chemical vapor deposition process. In an embodiment, the material of the conductive layer 170 is doped polysilicon, and the doping ions are third-conductivity-type doping ions; the bottom of the conductive layer 170 is on the metal silicide layer 160, and directly contacts the top of the metal silicide layer 160.

[0057] Further, the conductivity type of the third-conductivity-type doping ions in the conductive layer 170 can be the same as or different from the conductivity type of the first-conductivity-type doping ions (in the substrate 100) / the second-conductivity-type doping ions (in the doped region 140). Specifically, when the conductivity type of the third-conductivity-type doping ions in the conductive layer 170 is the same as the conductivity type of the first-conductivity-type doping ions / the second-conductivity-type doping ions, for example, the third-conductivity-type doping ions are P-type ions, such as boron ions (B), because the work function of the metal silicide layer 160 and the conductive layer 170 (P-type doped polysilicon) is close to form an ohmic contact, the conductive layer 170 and the metal silicide layer 160 can be conductive, and because the doped region 140 is a P-type heavily doped region with the same doping ion type as the substrate 100, the doped region 140 increases the carrier concentration in the substrate 100, and the substrate 100 with the increased carrier concentration and the metal silicide layer 160 can form an ohmic contact through single-side tunneling, thereby realizing the conduction of the metal silicide layer 160 and the substrate 100, i.e., finally realizing the same-type conduction of the conductive layer 170 (P-type doped polysilicon) and the substrate 100 (P-type doped silicon). Similarly, when the conductivity type of the third-conductivity-type doping ions in the conductive layer 170 is different from the conductivity type of the first-conductivity-type doping ions / the second-conductivity-type doping ions, for example, the third-conductivity-type doping ions are N-type ions, such as phosphorus ions (P), because the work function of the metal silicide layer 160 and the conductive layer 170 (N-type doped polysilicon) is close to form an ohmic contact, the conductive layer 170 and the metal silicide layer 160 can be conductive, and because the doped region 140 is a P-type heavily doped region with the same doping ion type as the substrate 100, the doped region 140 increases the carrier concentration in the substrate 100, and the substrate 100 with the increased carrier concentration and the metal silicide layer 160 can form an ohmic contact through single-side tunneling, thereby realizing the conduction of the metal silicide layer 160 and the substrate 100, i.e., finally realizing the different-type conduction of the conductive layer 170 (N-type doped polysilicon) and the substrate 100 (P-type doped silicon).

[0058] It should be particularly pointed out that when the conductive layer 170 located in the deep trench 101 and the substrate 100 in the first embodiment of the present application realize homotype conduction, the first metal layer 151 is preferably metal titanium, and the metal silicide layer 160 is preferably titanium disilicide (TiSi2); and when the conductive layer 170 located in the deep trench 101 and the substrate 100 in the first embodiment of the present application realize heterotype conduction, the first metal layer 151 is preferably metal cobalt, and the metal silicide layer 160 is preferably cobalt disilicide (CoSi2), but the present application is not limited thereto.

[0059] Then, a gate structure (not shown) of a semiconductor device such as an LDMOS transistor and a source (not shown) and a drain (not shown) located on both sides of the gate structure can be further formed in the substrate 100 on the side of the deep trench 101 with the conductive layer 170 by using deposition, etching, ion implantation and other processes; in the embodiment of the present application, the LDMOS transistor is preferably an N-channel LDMOS transistor, but the present application is not limited thereto.

[0060] It should be understood that "homotype" in the embodiment of the present application refers to the similarity and relevance between two or more shapes, and the continuous structure shape is constructed.

[0061] Please refer to Figures 9-16 , which is a structural schematic diagram of the semiconductor device provided in the second embodiment of the present application. Figures 9-16

[0062] ​The manufacturing method of the semiconductor device of the present embodiment is substantially the same as the manufacturing method of the semiconductor device of the first embodiment as described above, for example, the epitaxial layer 110 and the pad oxide layer 120 are sequentially formed on the substrate 100 from bottom to top, at least one deep trench 101 is formed in the pad oxide layer 120, the epitaxial layer 110 and the substrate 100, the dielectric layer 130 is formed on the inner sidewall of the deep trench 101, the heavily doped doped region 140 is formed in the region below the deep trench 101, and the metal silicide layer 160 is formed at the bottom of the deep trench 101 and directly contacts the doped region 140, etc., and the same is not described here. The main difference between the manufacturing method of the semiconductor device of the present embodiment and the manufacturing method of the first embodiment is that after the substrate 100 is formed, the epitaxial layer 110 is not directly formed by epitaxial process, but first, the etching stop layer (not shown) and the patterned photoresist layer (not shown) on the etching stop layer are formed on the surface of the substrate 100 by deposition process, then the substrate 100 is etched to remove part of the depth of the substrate 100 in part of the region by using the opening pattern in the patterned photoresist layer, thereby exposing the remaining substrate 100 in the part of the region, and then the isolation buried layer 180 with the fourth conductive type doping ions is formed in the exposed remaining substrate 100 in the part of the region by ion implantation process, and then the patterned photoresist layer and the etching stop layer are removed by etching process such as wet etching process, followed by filling the substrate 100 and forming the epitaxial layer 110 and the pad oxide layer 120 on the surface of the filled substrate 100, as shown in Figure 9 In an embodiment, the isolation buried layer 180 has the fourth conductive type doping ions of a different conductive type from the first conductive type doping ions of the substrate 100; preferably, the first conductive type doping ions of the substrate 100 are P-type ions, and the fourth conductive type doping ions of the isolation buried layer 180 are N-type ions; under this arrangement, the isolation buried layer 180 formed is an NBL buried layer.

[0063] Further, when the deep trench 101 is formed by etching process, the bottom of the deep trench 101 in the second embodiment of the present application needs to partially overlap with the isolation buried layer 180; in other words, the deep trench 101 needs to be formed in the substrate 100 above the isolation buried layer 180, so that the bottom of the deep trench 101 formed directly contacts part of the top of the isolation buried layer 180, as shown in Figure 10 Under this arrangement, when the doped region 140 is formed by step S104 as described above, since the deep trench 101 in the second embodiment of the present application is below the isolation buried layer 180, the doped region 140 formed is in the isolation buried layer 180, as shown in Figure 13As shown, and the doping region 140 has the second conductive type doping ions, the type in the second embodiment of the present application needs to be the same as the fourth conductive type doping ions of the isolation buried layer 180, for example, N-type ions.

[0064] It needs to be particularly pointed out that, since the second embodiment of the present application forms the isolation buried layer 180 (for example, NBL buried layer), the components of the same type conduction or different type conduction in the second embodiment of the present application are the conductive layer 170 (N-type doped polysilicon or P-type doped polysilicon) in the deep trench 101, the metal silicide layer 160 and the isolation buried layer 180, and the isolation buried layer 180 in conduction with the conductive layer 170 in the deep trench 101 can be used as a partial drift region of the semiconductor device, for example, LDMOS transistor, thereby reducing the width of the formed semiconductor device, for example, LDMOS transistor, in the horizontal direction, and achieving the length design requirement of the drift region of the semiconductor device, for example, LDMOS transistor, while improving the withstand voltage and reducing the chip area of the semiconductor device, for example, LDMOS transistor.

[0065] In summary, the present application provides a manufacturing method of a semiconductor device, comprising: providing a substrate with first conductive type doping ions, forming a deep trench in the substrate, forming a dielectric layer on the inner sidewall of the deep trench, forming a doping region with second conductive type doping ions in the part of the substrate below the deep trench, the second conductive type doping ions have the same conductive type as the first conductive type doping ions, forming a metal silicide layer at the bottom of the deep trench, the metal silicide layer is located at the doping region, and its bottom directly contacts the doping region, forming a conductive layer with third conductive type doping ions on the dielectric layer and the metal silicide layer, and filling the deep trench.

[0066] As described above, one aspect of the present application combines the formation of the metal silicide layer at the bottom of the deep trench and the formation of the doping region with the same conductive type doping ions of the substrate in the part of the substrate below the deep trench, and achieves the unexpected effect that: the metal silicide layer (at the bottom of the deep trench) and the conductive layer (material such as polysilicon, located on the metal silicide layer) can form ohmic contact due to their similar work functions, realize the conduction of the conductive layer and the metal silicide layer, and the doping region can improve the carrier concentration in the substrate, and the substrate with improved carrier concentration and the metal silicide layer can form ohmic contact, realize the conduction of the metal silicide layer and the substrate, and also realize the same type or different type conduction of the conductive layer and the substrate.

[0067] In another aspect of the present application, an isolation buried layer (for example, an NBL buried layer) is formed in the part of the substrate under the deep trench, a metal silicide layer is formed at the bottom of the deep trench, and a doped region is formed in the isolation buried layer in alignment with the deep trench, resulting in an unexpected effect that the metal silicide layer and the conductive layer can form an ohmic contact due to their close work functions, the conductive layer and the metal silicide layer are in conduction, the carrier concentration in the isolation buried layer is increased by the doped region in the isolation buried layer, the metal silicide layer and the isolation buried layer are in conduction due to the ohmic contact between the metal silicide layer and the isolation buried layer, and the conductive layer and the isolation buried layer are in the same type or also type conduction.

[0068] In addition, since the semiconductor device, for example, an LDMOS transistor, in the present application needs a longer drift region extending in the horizontal direction to obtain a higher breakdown voltage, the isolation buried layer in conduction with the conductive layer in the deep trench can be used as part of the drift region of the semiconductor device, for example, an LDMOS transistor, thereby reducing the width of the semiconductor device, for example, an LDMOS transistor, in the horizontal direction, and achieving the length design requirement of the drift region of the semiconductor device, for example, an LDMOS transistor, while improving the withstand voltage and reducing the chip area of the semiconductor device, for example, an LDMOS transistor.

[0069] The above description is merely preferred embodiments of the present application but not for limiting the protective scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall fall within the protective scope of the present application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a substrate with doped ions of a first conductivity type; Deep trenches are formed within the substrate; The dielectric layer is formed on the inner wall of the deep trench; A doped region with doped ions of a second conductivity type is formed within a portion of the substrate below the deep trench; A metal silicide layer is formed at the bottom of the deep trench, and the metal silicide layer is located in the doped region, with its bottom in direct contact with the doped region; A conductive layer with doped ions of a third conductivity type is formed on the dielectric layer and the metal silicide layer, and fills the deep trench; Before forming the deep trench, the method further includes: An isolation buried layer with fourth conductivity type doped ions is formed within the substrate, the isolation buried layer is located below the deep trench, and a portion of its top is in direct contact with the bottom of the metal silicide layer, so that the doped region is located in the isolation buried layer; wherein the conductivity type of the fourth conductivity type doped ions is the same as the conductivity type of the second conductivity type doped ions.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The conductivity type of the second conductivity type doped ion is the same as that of the first conductivity type doped ion, and the conductivity type of the first conductivity type doped ion is different from that of the third conductivity type doped ion.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The conductive layer is made of polycrystalline silicon.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The conductivity type of the fourth conductivity type doped ion is different from that of the first conductivity type doped ion.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The depth of the deep trench in the substrate along the vertical direction is greater than or equal to 40 μm.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the metal silicide layer includes: A first metal layer is formed at the bottom of the deep trench and on the surface of the dielectric layer; A second metal layer is formed on top of the first metal layer; The substrate is annealed to cause the first and second metal layers located at the bottom of the deep trench to undergo a metal silicide reaction with the substrate below them, forming the metal silicide layer.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The material of the first metal layer includes titanium or cobalt, and the material of the second metal layer includes titanium nitride.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor device is an LDMOS transistor.

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