High aspect ratio hetero-electronic carrier sheet stack and method of making same

Abstract

The application discloses a high-aspect-ratio hetero-electronic carrier sheet stack and a manufacturing method thereof, and relates to the technical field of substrate manufacturing. The application comprises: an upper plate, which is provided with metal conductive columns in the lowermost layer; a lower plate, which is internally provided with a first through hole; a dielectric layer, which is provided with a pre-drilled hole; wherein the line width, line distance, line thickness and pad thickness of the upper plate are smaller than those of the lower plate; the number of layers of the upper plate is greater than that of the lower plate; the diameter of the metal conductive column is smaller than that of the first through hole, and the diameter of the first through hole is smaller than that of the pre-drilled hole; a hole is opened on the dielectric layer of the lower layer of the lower plate, and the hole exposes the end face of the metal conductive column to form a blind hole; through the size cooperation of the metal conductive column, the through hole and the pre-drilled hole and the blind hole structure design, the application realizes the synergistic optimization of high-density interconnection and structural stability, and has the advantages of improving the aspect ratio, enhancing the structural stability, optimizing the heat management efficiency and reducing the interface defects.

Description

Technical Field

[0001] This invention relates to the field of substrate manufacturing technology, and in particular to a heterogeneous electron carrier stack with a high aspect ratio. Background Technology

[0002] In recent years, with the accelerated evolution of artificial intelligence chips, large-size high-performance computing, and 5G / 6G communication technologies toward 3D heterogeneous integration, traditional organic substrates (such as ABF) and silicon interposers face fundamental challenges in meeting the demands for high bandwidth, low latency, and multi-physics field coordination.

[0003] 1. Existing via technology is limited by aspect ratio, which is generally less than 10:1, making it difficult to meet the interconnection requirements in 3D stacking;

[0004] 2. Symmetrical substrate structures cannot effectively channel local hot spots, such as a heat flux density greater than 500W / cm² in the GPU area, which leads to increased thermal resistance.

[0005] 3. The void ratio of the through-hole filling is greater than the industry average, and the risk of interface delamination increases significantly after high-temperature cycling. Summary of the Invention

[0006] This invention provides a heterogeneous electron carrier stack with a high aspect ratio, which improves the aspect ratio, enhances structural stability, optimizes thermal management efficiency, and reduces interface defects.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] A high aspect ratio heterogeneous electron carrier stack, comprising:

[0009] The top plate has metal conductive pillars at its bottom layer;

[0010] The lower plate has a through hole inside;

[0011] A dielectric layer is disposed on the upper layer of the upper plate, between the upper plate and the lower plate, and on the lower layer of the lower plate. The dielectric layer between the upper plate and the lower plate is provided with pre-drilled holes.

[0012] The upper board has a smaller line width, line spacing, line thickness, and solder pad thickness than the lower board; the upper board has more layers than the lower board; the metal conductive post has a smaller diameter than the first through hole, and the first through hole has a smaller diameter than the pre-drilled hole; the end of the metal conductive post passes through the pre-drilled hole and is stuck inside the first through hole.

[0013] An opening is made in the dielectric layer of the lower plate, which exposes the end face of the metal conductive pillar and forms a blind hole.

[0014] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0015] The length of the metal conductive pillar is less than the thickness of the lower plate.

[0016] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0017] The length of the metal conductive pillar is greater than or equal to the thickness of the lower plate.

[0018] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0019] The central axis of the pre-drilled hole is collinear with the central axis of the first through hole.

[0020] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0021] The metal conductive pillar is made of copper alloy, and the lower plate is made of high-rigidity organic or inorganic substrate. When the lower plate is made of organic substrate, its elastic modulus is ≥50GPa.

[0022] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0023] The upper plate has a coreless structure.

[0024] As a preferred embodiment of the high aspect ratio heterogeneous electron carrier stack structure described in this invention, wherein:

[0025] The upper plate has a core-containing structure, which includes a symmetrical or asymmetrical stacked double core layer.

[0026] A method for manufacturing a high aspect ratio heterogeneous electron carrier stack, applied to the aforementioned high aspect ratio heterogeneous electron carrier stack, includes the following steps:

[0027] Step S100: Select a coreless or core-containing upper plate and set a metal conductive pillar at the bottom layer of the upper plate;

[0028] Step S200: Select a lower plate made of a high-rigidity organic or inorganic substrate, and open a first through hole inside the lower plate.

[0029] Step S300: A dielectric layer is provided on the upper layer of the upper plate, between the upper plate and the lower plate, and on the lower layer of the lower plate, and a pre-drilled hole is provided on the dielectric layer between the upper plate and the lower plate.

[0030] Step S400: The upper plate, dielectric layer and lower plate are stacked and pressed together, wherein the pre-drilled hole is aligned with the central axis of the first through hole and pressed together.

[0031] Step S500: A blind hole is formed on the laminated structure: a hole is made in the dielectric layer of the lower plate, and the hole exposes the end face of the metal conductive pillar to form a blind hole.

[0032] In a preferred embodiment of the manufacturing method of the high aspect ratio heterogeneous electron carrier stack according to the present invention, in step S400, the pressing between the upper plate, the dielectric layer and the lower plate causes the dielectric layer to cover the sidewall of the metal conductive pillar.

[0033] In a preferred embodiment of the manufacturing method of the high aspect ratio heterogeneous electron carrier stack according to the present invention, wherein: in step S400, the pressing between the upper plate, the dielectric layer and the lower plate specifically includes:

[0034] The upper plate, dielectric layer and lower plate are laminated together by means of solder ball connection, blind hole electroplating connection, copper pillar connection or multi-core conductive connection.

[0035] The beneficial effects of this invention are:

[0036] This application provides a heterogeneous electron carrier stack with a high aspect ratio. Through the dimensional matching of metal conductive pillars with through holes and pre-drilled holes, as well as the design of blind hole structure, it achieves synergistic optimization of high-density interconnection and structural stability. It has the advantages of improving aspect ratio (high aspect ratio), enhancing structural stability, optimizing thermal management efficiency, and reducing interface defects. Attached Figure Description

[0037] Figure 1 A schematic diagram of a coreless structure of a high aspect ratio heterogeneous electron carrier stack provided in the first embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a coreless structure of a high aspect ratio heterogeneous electron carrier stack provided in the second embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a core-containing structure of a heterogeneous electron carrier stack with a high aspect ratio provided in the first embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of a core-containing structure of a heterogeneous electron carrier stack with a high aspect ratio, provided for the second embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1. Top board; 2. Bottom board; 3. Dielectric layer; 4. Blind via;

[0043] 11. Metal conductive pillar;

[0044] 21. First through hole. Detailed Implementation

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0046] In existing technologies, the field of 3D heterogeneous integration faces the dual challenges of insufficient through-hole interconnect density and thermal management failure. Traditional stacked structures employ a single-aperture through-hole design, which is prone to interface delamination during high-temperature lamination, and the symmetrical structure cannot adapt to local thermal expansion differences. As chip power density continues to increase, thermal stress concentration inside the substrate leads to microcracks in the substrate's internal hole structure, affecting signal transmission integrity.

[0047] Therefore, refer to Figure 1 and Figure 3 Example 1 is an embodiment of the present invention, providing a high aspect ratio heterogeneous electron carrier stack structure, comprising an upper plate 1, a lower plate 2, and a dielectric layer 3. The upper plate 1 has a metal conductive post 11 at its bottom, the lower plate 2 is a glass substrate, and a through-hole 21 is formed inside the lower plate 2. The dielectric layer 3 is distributed above the upper plate 1, between the upper plate 1 and the lower plate 2, and below the lower plate 2, with pre-drilled holes in the dielectric layer 3 between the upper plate 1 and the lower plate 2. The linewidth, line spacing, line thickness, and solder pad thickness of the upper plate 1 are smaller than those of the lower plate 2; the upper plate 1 has more layers than the lower plate 2; and the diameter of the metal conductive post 11 is smaller than the diameter of the first through-hole 21, the diameter of the first through-hole 21 is smaller than the diameter of the pre-drilled hole, and the end of the metal conductive post 11 passes through the pre-drilled hole and is inserted into the first through-hole 21. A hole is provided in the dielectric layer 3 of the lower plate 2, which forms a blind hole 4 after exposing the end face of the metal conductive pillar 11.

[0048] Among them, the metal conductive pillar 11 refers to the conductive structure that vertically penetrates the upper plate 1, and can be implemented by electroplating copper pillars. The first through hole 21 refers to the through channel inside the lower plate 2, which can be formed by laser drilling, and the hole diameter is larger than the diameter of the metal conductive pillar 11 to accommodate its insertion. The pre-drilled hole refers to the positioning hole on the dielectric layer 3 between the upper plate 1 and the lower plate 2, which can be prepared by mechanical drilling, and its hole diameter is larger than the first through hole 21 to form a positioning allowance. The blind hole 4 is the vertical channel formed by the end face of the metal conductive pillar 11 and the remaining hole after the hole in the lower dielectric layer 3 of the lower plate 2 is exposed after the metal conductive pillar 11 is inserted. The hole can be formed by laser ablation process and is used for subsequent copper plating to establish circuit connection.

[0049] Specifically, during the lamination process, the pre-drilled holes in the dielectric layer 3 between the upper plate 1 and the lower plate 2 form a coaxial positioning relationship with the first through hole 21 of the lower plate 2. The ends of the metal conductive pillars 11 are accurately inserted into the first through hole 21 under the guidance of the pre-drilled holes. Because the diameter of the pre-drilled holes is larger than that of the first through hole 21, structural alignment is maintained even during lamination offset. The holes in the lower dielectric layer 3 of the lower plate 2 directly connect to the end faces of the metal conductive pillars 11, forming blind holes that become short-path conductive channels.

[0050] This application uses metal conductive pillars 11 instead of the traditional TGV electroplating conduction method. The metal conductive pillars 11 achieve a vertical interconnect aspect ratio (e.g., >20:1), solving the problem that traditional electroplating methods cannot fill deep blind vias. This increases the interconnect density by ≥5–8 times, significantly improving issues such as incomplete filling and void formation. Simultaneously, the metal conductive pillar array 11 can integrate asymmetric thermal management channels, such as locally embedded microchannels, to directionally reduce hotspot temperatures by more than 40°C. Furthermore, the stacked configuration provided in this application can form a fan-out arrangement. Combined with the high volumetric ratio metal conductive pillars 11 located on the lower plate 2, signal paths can be optimized to reduce high-frequency crosstalk.

[0051] This further enhances the reliability of the stacked structure in this application. The metal conductive pillars 11 are coated between the dielectric materials to form a large contact area with a high specific surface area, resulting in stronger adhesion to copper and reducing the risk of delamination caused by environmental factors such as high temperature and high humidity on the electron carrier sheet.

[0052] Compared with existing technologies, this solution utilizes the guiding effect of pre-drilled holes to form cantilever supports at the ends of conductive posts, significantly reducing cross-sectional shear forces. Furthermore, while traditional blind holes require penetration through multiple layers, resulting in limited aspect ratios, this solution achieves high aspect ratio blind hole fabrication through layered independent drilling.

[0053] Through the above technical solutions, this application achieves stress buffering between heterogeneous materials via a stepped aperture design, avoiding microcracks during thermal cycling. Short-path conductive channels reduce signal transmission loss and provide a structural basis for high-density interconnects. Furthermore, the asymmetric stacked design enhances local heat dissipation, preventing structural deformation caused by excessive heat flux density. Simultaneously, this application has a low risk of board warping; the glass substrate of its lower plate 2 has low CTE and high rigidity, effectively improving board warping. The stacking of the upper and lower core layers also contributes to improving board warping.

[0054] This application further proposes that the length of the metal conductive post 11 is less than the thickness of the lower plate 2.

[0055] The thickness of the lower plate 2 refers to the total height of the lower plate 2 made of glass substrate in the vertical direction, which can be controlled by adjusting the number of substrate laminations or by selecting core plates of different thicknesses.

[0056] Specifically, the length of the metal conductive post 11 is controlled to be less than the thickness of the lower plate 2. During the lamination process, after the end of the metal conductive post 11 passes through the pre-drilled hole in the dielectric layer 3, it only partially enters the first through hole 21 of the lower plate 2, thus forming a gap between the end of the conductive post and the inner wall of the first through hole 21. This length control, by limiting the vertical extension of the conductive post, avoids bending deformation during high-temperature lamination due to excessive length.

[0057] Through the above technical solution, this application can reduce the phenomenon of interface thermal stress concentration and reduce the risk of interface delamination caused by mismatch of thermal expansion coefficients.

[0058] Through the above technical solution, the combined length of the blind via 4 and the metal conductive post 11 in this application can set the aspect ratio of the vertical interconnect to be greater than 20:1. This ratio setting enables this application to achieve three-dimensional extension within a limited planar space, providing a vertical channel for multi-layer interconnection.

[0059] Compared to existing technologies, conventional via aspect ratios are generally controlled below 10:1, limited by drilling process precision and material thermal stability. This solution overcomes this limitation by optimizing the energy transfer path to achieve a higher aspect ratio in a composite structure of organic / inorganic substrate and dielectric layer 3, allowing more vertical interconnect channels to be accommodated per unit area.

[0060] Through the above technical solution, this application effectively solves the technical problem of insufficient interconnect channels in high-density 3D stacking. The high aspect ratio of vertical interconnects forms dense vertical interconnects within a limited wiring layer, improving the integration of signal transmission paths while reducing planar space occupation and reserving more design space for the layout of heat dissipation channels.

[0061] This application further proposes that the central axis of the pre-drilled hole is collinear with the central axis of the first through hole 21.

[0062] The pre-drilled hole refers to a positioning hole set in the dielectric layer 3 to guide the metal conductive post 11 through which it passes. It can be achieved using laser ablation or mechanical drilling processes, and its diameter is larger than the diameter of the metal conductive post 11 to provide tolerance space. The first through hole 21 refers to a hole structure penetrating the lower plate 2, which can be formed by chemical etching or mechanical drilling. Its diameter must meet the guiding and fixing requirements for the end of the metal conductive post 11 to be inserted. Collinearity of the central axes means that the spatial axes of the pre-drilled hole and the first through hole 21 are completely coincident.

[0063] Specifically, during the lamination process of the stacked structure, the collinear design of the pre-drilled hole and the first through hole 21 allows the metal conductive pillar 11 to pass through the dielectric layer 3 along a single axial path, with its end precisely embedded inside the first through hole 21. At the same time, the blind hole 4 formed at the bottom layer can further extend the conductive distance.

[0064] This application further proposes that the material of the metal conductive pillar 11 is a copper alloy, and the material of the lower plate 2 is a high-rigidity organic substrate or inorganic substrate. When the material of the lower plate 2 is an organic substrate, its elastic modulus is ≥50GPa.

[0065] Among them, copper alloy refers to a metal alloy material with copper as the main component, specifically copper-nickel alloy or copper-titanium alloy, which has high conductivity and creep resistance, and can enhance the structural stability of the conductive pillar. Organic substrate refers to a composite material with a polymer matrix, specifically epoxy resin or polyimide, which has low dielectric constant characteristics, which can reduce signal transmission loss. Inorganic substrate refers to a support layer composed of ceramic or glass composite materials, specifically prepared by alumina ceramic or low-temperature co-fired ceramic process, whose rigidity helps to suppress deformation of the stack, such as aluminum nitride ceramic, prepared by tape casting process. Dielectric layer 3 is composed of any organic material, such as Prepreg or ABF. The heterogeneity is formed by the different materials of the lower plate 2 and dielectric layer 3. Direct pressing of glass substrate (low CTE) and organic dielectric layer (high CTE) can easily lead to delamination. In this case, the pre-drilled dielectric layer precisely covers the metal pillar to form a high bonding interface, which significantly reduces the risk of high-temperature delamination.

[0066] Specifically, the organic substrate lower plate 2 utilizes a multi-layer resin and reinforcing fiber composite structure to achieve a gradient distribution of dielectric properties while maintaining mechanical strength, thus meeting the requirements of high-frequency signal transmission. The conductive pillars and the lower plate 2 are composed of heterogeneous materials, utilizing the high thermal conductivity of copper alloy to directionally dissipate local heat, combined with the low thermal expansion coefficient of the organic substrate to control overall deformation.

[0067] Through the above technical solution, this application effectively reduces the contact resistance at the interface between the conductive pillar and the through hole, suppresses the propagation of microcracks caused by the difference in thermal expansion of materials under high temperature environment, reduces the dielectric loss of high frequency signals during transmission, and improves the long-term reliability of heterostructure in high power density scenarios.

[0068] This application further proposes a method for manufacturing a high aspect ratio heterogeneous electron carrier stack, comprising the following steps: selecting an upper plate 1 with a coreless or core-containing structure, and setting a metal conductive pillar 11 on the bottom layer of the upper plate 1; selecting a lower plate 2 made of an inorganic substrate, and opening a first through hole 21 inside the lower plate 2; setting a dielectric layer 3 on the upper layer of the upper plate 1, the middle of the upper plate 1 and the lower plate 2, and the lower layer of the lower plate 2, and setting a pre-drilled hole on the dielectric layer 3; stacking and pressing the upper plate 1, the dielectric layer 3 and the lower plate 2, wherein the pre-drilled hole is aligned with the central axis of the first through hole 21 and pressed together; opening a hole in the dielectric layer 3 on the lower layer of the lower plate 2, which exposes the end face of the metal conductive pillar 11 to form a blind hole 4.

[0069] The upper board 1, whether coreless or core-containing, refers to a substrate structure with single or multiple metal wiring layers. This can be achieved using a coreless lamination process or a double-sided copper-clad laminate process. This structure can adapt to matching requirements with different coefficients of thermal expansion. Pre-drilled holes refer to pre-formed positioning holes in the dielectric layer 3 between the upper board 1 and the lower board 2. These can be processed using laser drilling or mechanical drilling, and the hole diameter must meet the nesting tolerance requirements between the metal conductive post 11 and the first through-hole 21.

[0070] Specifically, during the lamination process, the dielectric layer 3 softens upon heating and fills the gap between the metal conductive post 11 and the first through hole 21, forming a covering interface structure. The pre-drilled hole and the first through hole 21 are designed to be collinear, ensuring that the end of the metal conductive post 11 is precisely embedded inside the first through hole 21 after lamination, avoiding poor contact caused by misalignment. The metal conductive post 11 continues to be inserted into the hole of the lower dielectric layer of the lower plate 2, exposing the end face of the metal conductive post 11. At this time, the remaining holes without the metal conductive post 11 and the end face of the metal conductive post 11 form blind holes 4, the aspect ratio of which is controlled by adjusting the drilling energy and feed rate.

[0071] In some specific embodiments, the upper plate 1 containing the core structure can be a symmetrically stacked dual-core layer, such as a composite core layer of FR-4 and polyimide; the pre-drilling process can be carried out using a carbon dioxide laser, for example, by controlling the hole diameter accuracy in a pulse mode; the holes in the lower dielectric layer of the lower plate 2 can be opened using a stepped drilling process, for example, by first opening windows with a low-power laser and then penetrating the dielectric layer 3 with a high-power laser.

[0072] Through the above technical solutions, this application solves the problem of interlayer alignment accuracy in large-size electronic carrier stacks and reduces the thermal stress concentration phenomenon during high-temperature pressing. When the substrate of the lower plate 2 is selected as glass or other inorganic substrates, the dimensional stability and thermal cycling reliability of the stack are significantly improved through the heterogeneous integration of the inorganic substrate and the organic dielectric layer 3.

[0073] This application further proposes that in step S400, the pressing between the upper plate 1, the dielectric layer 3, and the lower plate 2 causes the dielectric layer 3 to cover the sidewall of the metal conductive pillar 11; in step S400, the pressing between the upper plate 1, the dielectric layer 3, and the lower plate 2 specifically includes: the pressing between the upper plate 1, the dielectric layer 3, and the lower plate 2 is performed by means of solder ball connection, blind hole electroplating connection, copper pillar connection, or multi-core conductive connection; in step S500, the holes in the lower dielectric layer of the lower plate 2 are opened by mechanical drilling or laser drilling.

[0074] The process of laminating the dielectric layer 3 onto the sidewalls of the metal conductive pillar 11 involves using a lamination process to completely cover the outer surface of the conductive pillar with dielectric material. This can be achieved using a vacuum hot-pressing process, where a temperature gradient is controlled to allow the material to flow plastically above its transition temperature, ensuring a bond between the dielectric material and the conductive pillar. Holes are drilled in the lower dielectric layer 3 of the lower plate 2. These holes can be machine-drilled or laser-drilled, with the processing method chosen based on the material properties of the dielectric layer 3. Specifically, a carbon dioxide laser can be used to process the organic dielectric layer 3, or a tungsten carbide drill bit can be used to process the inorganic composite dielectric layer 3. Energy density control optimizes the perpendicularity of the hole walls.

[0075] In this case, the upper plate 1 and the lower plate 2 are manufactured separately, and the upper plate 1 and the lower plate 2 with high yield are selected to form heterogeneous electronic carrier sheets, which can effectively improve the overall yield.

[0076] Specifically, during the lamination process of the stacked structure, the dielectric layer 3 undergoes viscoelastic flow under heat and pressure. Its pre-drilled structure forms a radial wrap after the metal conductive pillar 11 is inserted, eliminating the gap between the conductive pillar and the through hole. In the processing stage of the holes in the lower dielectric layer of the lower plate 2, mechanical drilling or pulsed laser ablation processes are selected according to the dielectric constant and thermal decomposition temperature of different dielectric materials. Deep hole penetration is achieved while maintaining the hole wall roughness of less than 3 micrometers, ensuring that the upper end face of the conductive pillar is completely exposed without carbonization residue.

[0077] Through the above technical solutions, this application effectively solves the interface delamination problem of high aspect ratio stacked structures under thermal stress, improves the mechanical bonding strength between the conductive pillar and the dielectric layer 3, and at the same time, by optimizing the drilling process combination, ensures a balance between processing accuracy and processing efficiency, and meets the stringent requirements of micro-hole consistency for large-size electronic carrier chips.

[0078] Example 2, refer to Figure 2 and 4 This is another embodiment of the present invention. Unlike the first embodiment, this embodiment provides a heterogeneous electron carrier stack with a high aspect ratio. To verify and illustrate the technical effects of the method, this embodiment uses a conventional technical solution and the method of the present invention for comparative testing. The test results are compared using scientific demonstration methods to verify the real effect of the method.

[0079] This application further proposes that the length of the metal conductive post 11 is greater than or equal to the thickness of the lower plate 2.

[0080] The metal conductive post 11 refers to the conductive structure embedded in the bottom of the upper plate 1. Specifically, it can be formed by electroplating copper alloy material, and its axial extension length needs to cover the space in the thickness direction of the lower plate 2. The thickness of the lower plate 2 refers to the actual measured value of the substrate in the vertical stacking direction, which can be controlled to a specific value range through machining. This parameter directly affects the fit between the conductive post and the through hole.

[0081] Specifically, when the axial length of the metal conductive post 11 is set to be equal to or greater than the thickness of the lower plate 2, the end of the metal conductive post 11 can completely penetrate the pre-drilled hole and extend into the interior of the first through hole 21 during the stacking process. This geometric relationship allows the metal conductive post 11 to form an interference fit with the through hole of the lower plate 2, and the gap is filled by the flow of the dielectric layer 3 during the pressing stage, eliminating the risk of interface separation caused by insufficient length in traditional short post structures. The axial overlap area between the metal conductive post 11 and the first through hole 21 forms a continuous conductive channel, avoiding shear stress concentration caused by the difference in thermal expansion coefficients during high-temperature cycling.

[0082] Through the above technical solution, this application effectively solves the interface delamination problem of high-density electron carrier sheets under temperature cycling conditions and enhances the interlocking strength between heterogeneous materials. The full-length contact between the metal conductive post 11 and the first through hole 21 significantly improves the current conduction efficiency, while providing additional heat conduction paths for local hot spots, avoiding material failure caused by excessive heat flux density.

[0083] Example 3, referring to Figure 1 and 2 This is another embodiment of the present invention. Unlike the first embodiment, this embodiment provides a heterogeneous electron carrier stack with a high aspect ratio. To verify and illustrate the technical effects of the method, this embodiment uses a conventional technical solution and the method of the present invention for comparative testing. The test results are compared using scientific demonstration methods to verify the real effect of the method.

[0084] This application further proposes that the upper plate 1 is a coreless structure.

[0085] The coreless structure refers to the absence of a core reinforcing layer in the upper plate 1, as is found in traditional substrates. This can be achieved by continuously stacking single or multiple layers of homogeneous materials, reducing the difference in thermal expansion coefficients by removing the metal or ceramic core layer. Furthermore, during manufacturing, the coreless structure reduces interlayer stress by adjusting the glass transition temperature of the dielectric material to match the thermal expansion coefficient of the metal conductive pillars 11.

[0086] Specifically, the coreless upper plate 1 eliminates the interface bonding problem between the metal core layer and the dielectric layer 3 in traditional cored substrates, achieving isotropic shrinkage during high-temperature pressing. When the dielectric layer 3 and the metal conductive pillar 11 are heated simultaneously, the dielectric material can expand freely in three dimensions due to the absence of rigid constraints from the metal core layer in the coreless structure, avoiding the formation of shear stress concentration zones around the metal conductive pillar 11. In the subsequent drilling process on the lower dielectric layer of the lower plate, the homogeneous characteristics of the coreless structure improve the drilling positioning accuracy, especially when the aspect ratio of the blind hole 4 exceeds 20:1, the perpendicularity deviation of the hole wall can be controlled within the micrometer range.

[0087] Through the above technical solution, this application effectively solves the problem of thermal stress concentration caused by the interface of heterogeneous materials in core-containing substrates, improves the positioning accuracy during the processing of high aspect ratio blind holes 4, and avoids the risk of delamination between the core layer and the dielectric layer 3 under high-temperature cycling. This coreless structure is particularly suitable for 3D heterogeneous integration scenarios that require directional heat flow, such as improving the heat flux density carrying capacity in the GPU chip area.

[0088] Example 4, refer to Figure 3 and Figure 4 This is another embodiment of the present invention. Unlike the first embodiment, this embodiment provides a heterogeneous electron carrier stack with a high aspect ratio. To verify and illustrate the technical effects of the method, this embodiment uses a conventional technical solution and the method of the present invention for comparative testing. The test results are compared using scientific demonstration methods to verify the real effect of the method.

[0089] This application further proposes a heterogeneous electron carrier stack with a high aspect ratio, wherein the upper plate 1 is a core-containing structure, which includes a symmetrical or asymmetrical stacked double core layer.

[0090] Among them, the core-containing structure refers to a composite board structure with at least two core layers, which can be achieved by laminating glass fiber reinforced epoxy resin or ceramic matrix composite materials. Multiple layers of support are formed by the alternating stacking of the core board and dielectric layer 3. The dual-core layer refers to two independently distributed core layers, which can be achieved by combining materials with different coefficients of thermal expansion. In symmetrical stacking, the two core layers have equal thickness, while in asymmetrical stacking, the thickness difference can be controlled within the range of 20%-50%, used to directionally adjust the thermal stress distribution of the stack.

[0091] Specifically, in the upper plate 1 containing the core structure, the dual-core layers are separated by dielectric materials to form independent functional layers. Symmetrical stacked dual-core layers use the same material and thickness, creating a uniform stress field along the Z-axis of the stack and reducing the deformation gradient during high-temperature pressing. Asymmetric stacked dual-core layers, through differentiated core plate thickness or material, create a thermal expansion compensation mechanism in specific areas. During pressing, the interfacial bonding force between the dual-core layers and the dielectric layer 3 is enhanced through surface roughening treatment, providing lateral support for the metal conductive pillars 11 when penetrating pre-drilled holes and suppressing through-hole displacement.

[0092] Compared to existing technologies, traditional single-core substrates are prone to delamination due to localized stress concentration caused by the uniform thermal expansion coefficient of the core board during lamination. This solution utilizes a symmetrical or asymmetrical design of dual-core layers to create differentiated thermal expansion compensation zones in the XY plane. This allows the thermal stress generated during high-temperature processing in the stacked structure to be absorbed and offset by the dual-core layers, thereby reducing overall warpage. Simultaneously, the additional support surface provided by the dual-core layers enhances the bonding strength between the dielectric layer 3 and the core board, preventing tearing of the dielectric layer 3 during the insertion of the metal conductive pillars 11.

[0093] Through the above technical solution, this application effectively solves the problem of deformation control of large-size electronic carrier sheets during high-temperature pressing. By using the stress compensation mechanism of the dual-core layer, the overall warpage of the stack is reduced to a processable range. At the same time, the interlayer bonding strength is enhanced to withstand the mechanical load of the high-density interconnect structure, providing a stable carrier support foundation for 3D heterogeneous integration.

[0094] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. These computer program instructions can also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means implemented in a flow... Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0095] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A heterogeneous electron carrier stack with a high aspect ratio, characterized in that, include: The upper plate (1) has a metal conductive column (11) at its bottom. The lower plate (2) has a through hole (21) inside. A dielectric layer (3) is disposed on the upper layer of the upper plate (1), between the upper plate (1) and the lower plate (2), and on the lower layer of the lower plate (2). The dielectric layer (3) between the upper plate (1) and the lower plate (2) is provided with pre-drilled holes. Among them, the line width, line spacing, line thickness and solder pad thickness of the upper plate (1) are smaller than those of the lower plate (2); the number of layers of the upper plate (1) is greater than that of the lower plate (2); the diameter of the metal conductive post (11) is smaller than the diameter of the first through hole (21), and the diameter of the first through hole (21) is smaller than the diameter of the pre-drilled hole; the end of the metal conductive post (11) passes through the pre-drilled hole and is stuck inside the first through hole (21); A hole is made in the lower dielectric layer (3) of the lower plate (2), which exposes the end face of the metal conductive pillar (11) and forms a blind hole (4).

2. The heterogeneous electron carrier stack with high aspect ratio as described in claim 1, characterized in that: The length of the metal conductive post (11) is less than the thickness of the lower plate (2).

3. The heterogeneous electron carrier stack with high aspect ratio as described in claim 1, characterized in that: The length of the metal conductive post (11) is greater than or equal to the thickness of the lower plate (2).

4. The heterogeneous electron carrier stack with high aspect ratio as described in any one of claims 1 to 3, characterized in that: The central axis of the pre-drilled hole is collinear with the central axis of the first through hole (21).

5. The heterogeneous electron carrier stack with high aspect ratio as described in claim 1, characterized in that: The metal conductive pillar (11) is made of copper alloy, and the lower plate (2) is made of high-rigidity organic or inorganic substrate. When the material of the lower plate (2) is organic substrate, its elastic modulus is ≥50GPa.

6. The heterogeneous electron carrier stack with high aspect ratio as described in claim 1, characterized in that: The upper plate (1) has a coreless structure.

7. The heterogeneous electron carrier stack with high aspect ratio as described in claim 1, characterized in that: The upper plate (1) is a core-containing structure, which includes a symmetrical or asymmetrical stacked double core layer.

8. A method for manufacturing a high aspect ratio heterogeneous electron carrier stack, applied to the high aspect ratio heterogeneous electron carrier stack described in claim 1; characterized in that, Includes the following steps: Step S100: Select an upper plate (1) with a coreless structure or a core-containing structure, and set a metal conductive pillar (11) at the bottom of the upper plate (1). Step S200: Select a lower plate (2) made of a high-rigidity organic substrate or inorganic substrate, and open a first through hole (21) inside the lower plate (2). Step S300: A dielectric layer (3) is provided on the upper layer of the upper plate (1), between the upper plate (1) and the lower plate (2), and on the lower layer of the lower plate (2), and pre-drilled holes are provided on the dielectric layer (3) between the upper plate (1) and the lower plate (2); Step S400: The upper plate (1), dielectric layer (3) and lower plate (2) are stacked and pressed together, wherein the pre-drilled hole is aligned with the central axis of the first through hole (21) and pressed together. Step S500: A blind hole (4) is formed on the laminated body: a hole is made on the dielectric layer (3) of the lower plate (2), and the hole exposes the end face of the metal conductive pillar (11) to form a blind hole (4).

9. The method for manufacturing a high aspect ratio heterogeneous electron carrier stack as described in claim 8, characterized in that: In step S400, the pressing between the upper plate (1), the dielectric layer (3) and the lower plate (2) causes the dielectric layer (3) to cover the sidewall of the metal conductive pillar (11).

10. The method for manufacturing a high aspect ratio heterogeneous electron carrier stack as described in claim 8, characterized in that, In step S400, the pressing between the upper plate (1), the dielectric layer (3), and the lower plate (2) specifically includes: The upper plate (1), dielectric layer (3) and lower plate (2) are pressed together by means of solder ball connection, blind hole electroplating connection, copper pillar connection or multi-core conductive connection.

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