Buck-boost circuit

Abstract

The invention discloses a buck-boost circuit, and relates to the field of power. The buck-boost circuit comprises a main control chip, a buck-boost module, a first detection module and a second detection module, the first detection module and the second detection module are connected to the two sides of the buck-boost module respectively, circuit input data are collected through the first detection module arranged in front of the buck-boost module, and the buck-boost module adopts two electronic power converter circuits connected in parallel; collecting circuit output data through a second detection module arranged behind the buck-boost module; and receiving the collected circuit output data and circuit input data through the main control chip, and determining the maximum output power of the buck-boost circuit according to the circuit input data and the circuit output data. The technical problem of inaccurate estimation of the maximum output power of the buck-boost circuit caused by lack of an input and output monitoring mechanism for the buck-boost circuit in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electric power, in particular to a Buck-Boost circuit. BACKGROUND

[0002] In the modern field of electric power, Buck-Boost circuits have a wide range of applications in renewable energy power generation systems, mobile electronic devices, and electric vehicle battery management, etc.

[0003] However, these fields are facing the challenges of large input power supply voltage fluctuations and complex and variable load characteristics. Due to the lack of precise input and output monitoring and efficient control mechanism, the traditional Buck-Boost circuit is difficult to achieve stable and efficient power conversion when dealing with these complex working conditions, resulting in low energy conversion efficiency, serious energy waste, and possible impact on the normal operation of the load device due to unstable output voltage, reducing the reliability and performance of the system.

[0004] In view of the above problems, no effective solution has been proposed so far. SUMMARY

[0005] The embodiments of the present application provide a Buck-Boost circuit to at least solve the technical problem of inaccurate maximum output power estimation of the Buck-Boost circuit due to the lack of input and output monitoring mechanism in the prior art.

[0006] According to an aspect of the embodiments of the present application, a Buck-Boost circuit is provided, comprising a main control chip, a Buck-Boost module, and a first detection module and a second detection module connected to the two sides of the Buck-Boost module, respectively, wherein: the first detection module arranged before the Buck-Boost module is used to collect circuit input data, wherein the Buck-Boost module adopts two parallel electronic power converter circuits; the second detection module arranged after the Buck-Boost module is used to collect circuit output data; the main control chip receives the collected circuit output data and circuit input data, and determines the maximum output power of the Buck-Boost circuit according to the circuit input data and the circuit output data.

[0007] Optionally, the first detection module comprises: a battery for providing an input power to be monitored, wherein the negative electrode of the battery is grounded; a first detection submodule for collecting circuit input data of the first side of the Buck-Boost module; a second detection submodule for collecting circuit input data of the second side of the Buck-Boost module, wherein the first side and the second side are opposite sides.

[0008] Optionally, the first detection sub-module comprises: a first resistor, wherein a first end of the first resistor is connected to a positive electrode of the battery, and a second end of the first resistor is connected to a first end of a second resistor, for generating a voltage drop to reflect the size of the input current when the input current changes; the second resistor, wherein a first end of the second resistor is connected to the second end of the first resistor, and a second end of the second resistor is connected to an inverting input terminal of the first operational amplifier, for transmitting the voltage drop on the first resistor to the first operational amplifier; a third resistor, wherein a first end of the third resistor is connected to a non-inverting input terminal of the first operational amplifier, and a second end of the third resistor is connected to the second end of the first resistor, for providing a reference voltage; a fourth resistor, wherein a first end of the fourth resistor is connected to an output terminal of the first operational amplifier, and a second end of the fourth resistor is connected to the inverting input terminal of the first operational amplifier, for forming a voltage feedback to stabilize the output of the first operational amplifier; a fifth resistor, wherein a first end of the fifth resistor is connected to the non-inverting input terminal of the first operational amplifier, and a second end of the fifth resistor is grounded, for eliminating the DC offset of the input voltage and ensuring that the reference point of the first operational amplifier is the ground potential; a sixth resistor, wherein a first end of the sixth resistor is grounded, and a second end of the sixth resistor is connected to a first end of a seventh resistor, for providing a lower part of a voltage dividing network; the seventh resistor, wherein a first end of the seventh resistor is connected to the second end of the sixth resistor, and a second end of the seventh resistor is connected to the second end of the first resistor and connected to an input port of the master control chip, for dividing the input voltage signal to a preset processing range corresponding to the master control chip.

[0009] Optionally, the second detection submodule comprises: an eighth resistor, wherein a first end of the eighth resistor is connected to a positive electrode of the battery, for forming a current detection path together with the battery and a ninth resistor; the ninth resistor, wherein a first end of the ninth resistor is connected to a second end of the eighth resistor, and a second end of the ninth resistor is connected to an inverting input end of the second operational amplifier, for transmitting a voltage drop on the eighth resistor to the second operational amplifier; a tenth resistor, wherein a first end of the tenth resistor is connected to a non-inverting input end of the second operational amplifier, and a second end of the tenth resistor is connected to the second end of the eighth resistor, for providing a reference voltage; an eleventh resistor, wherein a first end of the eleventh resistor is connected to the inverting input end of the second operational amplifier, and a second end of the eleventh resistor is connected to an output end of the second operational amplifier, for forming a voltage feedback and stabilizing the output of the second operational amplifier; a twelfth resistor, wherein a first end of the twelfth resistor is connected to the non-inverting input end of the second operational amplifier, and a second end of the twelfth resistor is grounded, for eliminating a direct current offset of an input voltage and ensuring that a reference point of the second operational amplifier is a ground potential; a thirteenth resistor, wherein a first end of the thirteenth resistor is connected to a feedback signal of the output end of the second operational amplifier, and a second end of the thirteenth resistor is connected to a first end of a fourteenth resistor, for dividing the feedback signal to a preset processing range corresponding to the master control chip; and the fourteenth resistor, wherein a first end of the fourteenth resistor is connected to the second end of the thirteenth resistor, and a second end of the fourteenth resistor is grounded, for transmitting a divided signal of the thirteenth resistor to the ground.

[0010] Optionally, the voltage-lifting and voltage-lowering module comprises: a first field effect transistor, wherein a drain of the first field effect transistor is connected to an output end of the first detection module, a source of the first field effect transistor is connected to the ground through a first inductor, and a gate of the first field effect transistor receives a control signal from the master control chip; the first inductor, wherein a first end of the first inductor is grounded, and a second end of the first inductor is connected to the source of the first field effect transistor, for storing and releasing energy in a switching period of the first field effect transistor; a first diode, wherein a cathode of the first diode is connected to the source of the first field effect transistor, and an anode of the first diode is connected to an input end of the second detection module, for ensuring that energy stored by the first inductor can be transmitted to a load when the first field effect transistor is turned off.

[0011] Optionally, the voltage boosting and bucking module further comprises: a second field effect transistor, wherein the drain of the second field effect transistor is connected to the output end of the first detection module, the source of the second field effect transistor is connected to the ground through a second inductor, and the gate of the second field effect transistor receives a control signal from the master chip; the second inductor, wherein the first end of the second inductor is connected to the source of the second field effect transistor, and the second end of the second inductor is grounded; and a second diode, wherein the cathode of the second diode is connected to the source of the second field effect transistor, and the anode of the second diode is connected to the input end of the second detection module, and the second diode works in parallel with the first diode to ensure that the energy stored in the second inductor can be transmitted to the load when the second field effect transistor is turned off.

[0012] Optionally, the first field effect transistor and the second field effect transistor are controlled by a pulse width modulation signal output by the master chip, and the input voltage is converted by alternating switching, and the required output voltage is stabilized in the target voltage range through the first inductor, the second inductor, the first diode and the second diode.

[0013] Optionally, the second detection module comprises: a fifteenth resistor, wherein the first end of the fifteenth resistor is connected to the anode of the first diode, and the second end of the fifteenth resistor is connected to the first end of a sixteenth resistor, for detecting the output current and converting it into a voltage signal; the sixteenth resistor, wherein the first end of the sixteenth resistor is connected to the inverting input end of a third operational amplifier, and the second end of the sixteenth resistor is connected to the second end of the fifteenth resistor, and the fifteenth resistor and the sixteenth resistor work together to detect the output current; a seventeenth resistor, wherein the first end of the seventeenth resistor is connected to the non-inverting input end of the third operational amplifier, and the second end of the seventeenth resistor is grounded, for eliminating DC offset and providing a reference voltage; an eighteenth resistor, wherein the first end of the eighteenth resistor is connected to the output end of the third operational amplifier, and the second end of the eighteenth resistor is connected to the inverting input end of the operational amplifier, for forming a voltage feedback network to stabilize the output voltage of the amplifier; a nineteenth resistor, wherein the first end of the nineteenth resistor is connected to the non-inverting input end of the third operational amplifier, and the second end of the nineteenth resistor is connected to the first end of a twentieth resistor; the twentieth resistor, wherein the first end of the twentieth resistor is connected to the second end of the nineteenth resistor, and the second end of the twentieth resistor is grounded, and the nineteenth resistor and the twentieth resistor work together to form a voltage dividing network; and a twenty-first resistor, wherein the first end of the twenty-first resistor is connected to the second end of the twentieth resistor, and the second end of the twenty-first resistor is connected to the non-inverting input end of the third operational amplifier, and the twentieth resistor and the twenty-first resistor together form a voltage dividing network to send the divided output voltage signal to the third operational amplifier.

[0014] Optionally, the second detection module further comprises: a twenty-second resistor, wherein a first end of the twenty-second resistor is connected to the anode of the second diode, and a second end of the twenty-second resistor is connected to a first end of a twenty-third resistor, for detecting the second output current and converting it into a voltage signal; the twenty-third resistor, wherein a first end of the twenty-third resistor is connected to the inverting input terminal of the fourth operational amplifier, and a second end of the twenty-third resistor is connected to the second end of the twenty-second resistor, for detecting the second output current together with the twenty-second resistor; a twenty-fourth resistor, wherein a first end of the twenty-fourth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-fourth resistor is grounded, for eliminating DC offset; a twenty-fifth resistor, wherein a first end of the twenty-fifth resistor is connected to the output terminal of the fourth operational amplifier, and a second end of the twenty-fifth resistor is connected to the inverting input terminal of the operational amplifier, for constituting a voltage feedback network and stabilizing the output voltage of the amplifier; a twenty-sixth resistor, wherein a first end of the twenty-sixth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-sixth resistor is grounded, for constituting a lower resistor of a second voltage dividing network; a twenty-seventh resistor and a twenty-eighth resistor, which are combined to constitute an upper resistor of the second voltage dividing network, wherein the twenty-seventh resistor is connected to the anode of the second diode, and the twenty-eighth resistor is connected to the ground; and a twenty-ninth resistor, wherein a first end of the twenty-ninth resistor is connected to a first end of the target capacitor, and a second end of the twenty-ninth resistor is grounded, for transmitting the voltage signal across the target capacitor to the main control chip for processing.

[0015] Optionally, the second detection module further comprises: a target capacitor, wherein a first end of the target capacitor is connected to the second end of the fifteenth resistor and the twenty-second resistor, and a second end of the target capacitor is grounded, for filtering high-frequency noise in the output voltage.

[0016] From the above, it can be seen that the present application collects circuit input data through the first detection module arranged before the boost-buck module, wherein the boost-buck module adopts two parallel electronic power converter circuits; collects circuit output data through the second detection module arranged after the boost-buck module; receives the collected circuit output data and circuit input data through the main control chip, and determines the maximum output power of the boost-buck circuit according to the circuit input data and the circuit output data.

[0017] In the embodiments of the present application, the input and output data of the boost-buck module are monitored in all directions, the first detection module and the second detection module are arranged before and after the boost-buck module respectively, the subtle changes of the input voltage, current and the output voltage, current are captured in real time, and the data are rapidly transmitted to the main control chip, so that the accurate judgment of the circuit running state and the tracking of the maximum power point are realized, and the technical problem of inaccurate estimation of the maximum output power of the boost-buck circuit caused by the lack of input and output monitoring mechanism in the prior art is solved. BRIEF DESCRIPTION OF DRAWINGS

[0018] The drawings described herein are used to provide further understanding of the present application, constitute a part of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitation on the present application. In the drawings:

[0019] Figure 1 is a working flow chart of a boost-buck circuit according to an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of an optional conventional Buck-Boost (direct current-direct current) circuit according to an embodiment of the present application;

[0021] Figure 3 is an architectural diagram of an optional maximum power point intelligent tracking model based on an interleaved parallel Buck-Boost boost-buck circuit according to an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of an optional first detection module circuit according to an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of an optional boost-buck module circuit according to an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of an optional second detection module circuit according to an embodiment of the present application.

[0025] Q, field effect transistor; d, drain; s, source; g, gate; Vin, input power supply; Lf, inductor; D, diode; Cf, capacitor; R, load; 1, main control chip; 2, first detection module; 3, boost-buck module; 4, second detection module; E, battery; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; R13, thirteenth resistor; R14, fourteenth resistor; R15, fifteenth resistor; R16, sixteenth resistor; R17, seventeenth resistor; R18, eighteenth resistor; R19, nineteenth resistor; R20, twentieth resistor; R21, twenty-first resistor; R22, twenty-second resistor; R23, twenty-third resistor; R24, twenty-fourth resistor; R25, twenty-fifth resistor; R26, twenty-sixth resistor; R27, twenty-seventh resistor; R28, twenty-eighth resistor; R29, twenty-ninth resistor; U1, first operational amplifier; U2, second operational amplifier; U3, third operational amplifier; U4, fourth operational amplifier; P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, 10 input terminals of the main control chip; Q1, first field effect transistor; Q2, second field effect transistor; A1, A2, two input terminals of the first detection module; B1, B2, two input terminals of the second detection module; L1, first inductor; L2, second inductor; D1, first diode; D2, second diode; C, target capacitor. DETAILED DESCRIPTION

[0026] In order to enable persons skilled in the art to better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular chronological or sequential order. It should be understood that the data thus used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a list of steps or units as processes, methods, systems, products, or apparatuses are not necessarily limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products, or apparatuses.

[0028] It should also be noted that the information collected by the present application (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) are authorized by the user or authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of related data comply with relevant laws, regulations and standards in relevant regions, necessary security measures are taken, public order and good customs are not violated, and appropriate operation portals are provided for users to choose authorization or refusal. For example, interfaces are provided between the system and related users or agencies, and before obtaining relevant information, the interface needs to send a request to the aforementioned user or agency, and after receiving the consent information feedback from the aforementioned user or agency, the relevant information is obtained.

[0029] According to an embodiment of the present application, an embodiment of a boost-buck circuit is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in a different order than that shown herein.

[0030] Figure 1 is a working flowchart of a boost-buck circuit according to an embodiment of the present application, as shown in Figure 1 The circuit includes the following steps:

[0031] Step S101, collecting circuit input data through a first detection module arranged before the boost-buck module.

[0032] In step S101, the boost-buck module uses two parallel electronic power converter circuits.

[0033] Optionally, the first detection module is located before the buck-boost module and is used to collect input data of the circuit, the input data including input voltage and current, and the first detection module can provide real-time state information of the input end for the master control chip through accurate monitoring. The first detection module can capture subtle changes in the input voltage and current in real time and transmit them to the master control chip.

[0034] Optionally, the buck-boost module is composed of two parallel Buck-Boost circuits, and such a parallel structure can provide greater output power while reducing the demand for filtering elements, reducing cost and electromagnetic interference, and improving electromagnetic compatibility. The parallel Buck-Boost circuits can also dynamically allocate power according to changes in the load, thereby improving the stability and efficiency of the circuit system. When the load is light, one of the circuits can provide the main power, while the other circuit is in a low-power standby state; when the load suddenly increases, the two circuits can quickly work together to provide sufficient power.

[0035] Step S102, collecting circuit output data through the second detection module arranged after the buck-boost module.

[0036] Optionally, the second detection module is located after the buck-boost module and is used to collect output data of the circuit, the output data including output voltage and current, and the second detection module can provide real-time state information of the output end for the master control chip through accurate monitoring. The second detection module can capture subtle changes in the output voltage and current in real time and transmit them to the master control chip quickly.

[0037] Step S103, receiving the collected circuit output data and circuit input data through the master control chip, and determining the maximum output power of the buck-boost circuit according to the circuit input data and the circuit output data.

[0038] Optionally, the master control chip serves as the control core of the buck-boost circuit, is responsible for receiving the collected data from the first detection module and the second detection module, and controls the working state of the buck-boost module according to the data, thereby determining the maximum output power of the buck-boost circuit. The master control chip can use a common single-chip microcomputer and receive sampling data of voltage and current through a built-in or externally connected analog-to-digital converter. The master control chip can use the perturb and observe method to obtain the maximum power point, thereby realizing intelligent control of the buck-boost circuit.

[0039] Optionally, Figure 2 is a schematic diagram of an optional conventional Buck-Boost circuit according to an embodiment of the present application, as Figure 2As shown, the traditional Buck-Boost circuit is a single-tube non-isolated DC-DC conversion circuit, which can realize the function that the output voltage can be higher or lower than the input voltage. The specific circuit composition is as follows: the field effect tube Q (as a switching tube), the drain d is connected to the positive pole of the input power Vin, and receives the input voltage; the source s is connected to one end of the inductor, and controls the charging path of the inductor Lf; the gate g receives the PWM (Pulse Width Modulation) signal, controls the conduction and turn-off of the field effect tube Q, thereby realizing the conversion and control of electric energy. The inductor Lf plays a role of energy storage and filtering in the circuit, when the field effect tube Q is turned on, the inductor Lf stores energy; when the field effect tube Q is turned off, the inductor Lf releases energy, maintains the continuity of the current. The diode D provides a freewheeling path for the inductor Lf during the turn-off of the field effect tube Q, ensures that the current in the inductor Lf can continue to flow, and prevents the current from suddenly changing to produce a high reverse voltage. The capacitor Cf is used for filtering, smoothing the output voltage, reducing the ripple of the output voltage, and improving the stability of the output voltage. The input power Vin provides the input voltage for the circuit, and the voltage value and stability directly affect the output performance of the circuit. The load R represents the load connected to the output end of the circuit, and the resistance value determines the output current and power of the circuit.

[0040] Optionally, Figure 3 is an optional architecture diagram of a maximum power point intelligent tracking model based on an interleaved parallel Buck-Boost boost-buck circuit according to an embodiment of the present application, as Figure 3 As shown, the first detection module 2 and the second detection module 4 respectively collect the input and output data of the boost-buck module 3, and transmit them to the main control chip 1. The main control chip 1 determines the maximum power point through the perturbation and observation method according to the input and output data, and controls the working state of the boost-buck module 3 to realize the maximum power output. This MPPT (Maximum Power Point Tracking) model can effectively improve the reliability and stability of the boost-buck module 3, ensure that the entire circuit system can stably operate under various complex working conditions, and avoid damage to the load device caused by abnormal voltage or current fluctuations.

[0041] From the above, the present application adopts the way of accurately monitoring the input and output data of the boost-buck module in all directions, by respectively setting the first detection module and the second detection module before and after the boost-buck module, the purpose of capturing the subtle changes of the input voltage, current and output voltage, current in real time and rapidly transmitting the data to the main control chip is achieved, thereby realizing the accurate judgment of the circuit operating state and the tracking of the maximum power point, and further solving the technical problem that the maximum output power of the boost-buck circuit is not accurately estimated due to the lack of input and output monitoring mechanism in the prior art.

[0042] In an optional embodiment, the first detection module comprises: a battery for providing an input power to be monitored, wherein the negative electrode of the battery is grounded; a first detection submodule for collecting circuit input data on the first side of the boost-buck module; and a second detection submodule for collecting circuit input data on the second side of the boost-buck module, wherein the first side and the second side are opposite sides.

[0043] Optionally, the battery serves as an input power to provide power support for the entire circuit. The negative electrode of the battery is grounded to provide a stable reference potential, thereby ensuring the normal operation of the boost-buck circuit.

[0044] Optionally, by arranging the detection submodules on both sides of the boost-buck module, the input state of the circuit can be more comprehensively monitored to ensure the accuracy and integrity of the input data. Based on the input data, the master control chip can more accurately determine the working state of the circuit, discover potential problems in time and make adjustments, and at the same time provide data support for the tracking of the maximum power point. This comprehensive monitoring mechanism can ensure that the boost-buck circuit can operate stably under various complex working conditions, effectively avoid damage to the load equipment caused by abnormal voltage or current fluctuations, and thereby improve the reliability and stability of the boost-buck module.

[0045] In an optional embodiment, the first detection sub-module comprises: a first resistor, wherein a first end of the first resistor is connected to a positive electrode of the battery, and a second end of the first resistor is connected to a first end of a second resistor, for generating a voltage drop when the input current changes, to reflect the size of the input current; the second resistor, wherein a first end of the second resistor is connected to the second end of the first resistor, and a second end of the second resistor is connected to an inverting input terminal of the first operational amplifier, for transmitting the voltage drop on the first resistor to the first operational amplifier; a third resistor, wherein a first end of the third resistor is connected to a non-inverting input terminal of the first operational amplifier, and a second end of the third resistor is connected to the second end of the first resistor, for providing a reference voltage; a fourth resistor, wherein a first end of the fourth resistor is connected to an output terminal of the first operational amplifier, and a second end of the fourth resistor is connected to the inverting input terminal of the first operational amplifier, for forming a voltage feedback to stabilize the output of the first operational amplifier; a fifth resistor, wherein a first end of the fifth resistor is connected to the non-inverting input terminal of the first operational amplifier, and a second end of the fifth resistor is connected to ground, for eliminating the DC offset of the input voltage and ensuring that the reference point of the first operational amplifier is the ground potential; a sixth resistor, wherein a first end of the sixth resistor is connected to ground, and a second end of the sixth resistor is connected to a first end of a seventh resistor, for providing a lower part of a voltage dividing network; the seventh resistor, wherein a first end of the seventh resistor is connected to the second end of the sixth resistor, and a second end of the seventh resistor is connected to the second end of the first resistor and connected to an input port of the master control chip, for dividing the input voltage signal to a preset processing range corresponding to the master control chip.

[0046] Optionally, when the input current passes through the first resistor, a voltage drop is generated across the first resistor, and the voltage drop is proportional to the input current, which is transmitted to the inverting input terminal of the first operational amplifier through the second resistor.

[0047] Optionally, the input voltage is divided to a range that can be processed by the master control chip through the voltage dividing network composed of the sixth resistor and the seventh resistor, and the divided voltage signal is transmitted to the input port of the master control chip.

[0048] Optionally, the first operational amplifier provides a reference voltage through the third resistor and the fifth resistor, and forms a voltage feedback through the fourth resistor, thereby ensuring the stability and accuracy of the output voltage.

[0049] In an optional embodiment, the second detection sub-module comprises: an eighth resistor, wherein the first end of the eighth resistor is connected to the positive pole of the battery, for forming a current detection path together with the battery and a ninth resistor; the ninth resistor, wherein the first end of the ninth resistor is connected to the second end of the eighth resistor, and the second end of the ninth resistor is connected to the inverting input terminal of the second operational amplifier, for transmitting the voltage drop on the eighth resistor to the second operational amplifier; a tenth resistor, wherein the first end of the tenth resistor is connected to the non-inverting input terminal of the second operational amplifier, and the second end of the tenth resistor is connected to the second end of the eighth resistor, for providing a reference voltage; an eleventh resistor, wherein the first end of the eleventh resistor is connected to the inverting input terminal of the second operational amplifier, and the second end of the eleventh resistor is connected to the output terminal of the second operational amplifier, for forming a voltage feedback and stabilizing the output of the second operational amplifier; a twelfth resistor, wherein the first end of the twelfth resistor is connected to the non-inverting input terminal of the second operational amplifier, and the second end of the twelfth resistor is grounded, for eliminating the DC offset of the input voltage and ensuring that the reference point of the second operational amplifier is the ground potential; a thirteenth resistor, wherein the first end of the thirteenth resistor is connected to the feedback signal of the output terminal of the second operational amplifier, and the second end of the thirteenth resistor is connected to the first end of a fourteenth resistor, for dividing the feedback signal to a preset processing range corresponding to the master control chip; and the fourteenth resistor, wherein the first end of the fourteenth resistor is connected to the second end of the thirteenth resistor, and the second end of the fourteenth resistor is grounded, for transmitting the voltage signal divided by the thirteenth resistor to the ground.

[0050] Optionally, when the input current passes through the eighth resistor, a voltage drop is generated across the eighth resistor. The voltage drop is proportional to the input current, and is transmitted to the inverting input terminal of the second operational amplifier through the ninth resistor.

[0051] Optionally, the input voltage is divided to a range that can be processed by the master control chip through the voltage dividing network formed by the thirteenth resistor and the fourteenth resistor, and the divided voltage signal is transmitted to the input port of the master control chip.

[0052] Optionally, the second operational amplifier provides a reference voltage through the tenth resistor and the twelfth resistor, forms a voltage feedback through the eleventh resistor, and ensures the stability and accuracy of the output voltage.

[0053] Optionally, Figure 4 is a schematic diagram of an optional first detection module circuit according to an embodiment of the present application, as Figure 4As shown, the first detection module circuit takes the battery E as the input power supply, and the positive electrode is connected to the first end of the first resistor R1 and the eighth resistor R8, respectively, to provide power support for the circuit. The first resistor R1 and the eighth resistor R8 act as sampling resistors, respectively cooperating with the second resistor R2, the third resistor R3 and the ninth resistor R9, the tenth resistor R10 to form a voltage follower circuit, which detects and amplifies the input current through the first operational amplifier U1 and the second operational amplifier U2, ensuring that the host chip 1 can accurately obtain current information. At the same time, the sixth resistor R6, the seventh resistor R7 and the thirteenth resistor R13, the fourteenth resistor R14 form a voltage dividing network to divide the input voltage, transmit the voltage signal after voltage division to the input port of the host chip 1, and realize the detection of the input voltage. In addition, the fourth resistor R4 and the eleventh resistor R11 provide voltage feedback for the first operational amplifier U1 and the second operational amplifier U2 to stabilize the output signal, while the fifth resistor R5 and the twelfth resistor R12 provide a reference ground potential for the non-inverting input terminal of the operational amplifier to eliminate DC offset. In addition, P1 and P2 are the output ports of the host chip 1, and A1 and A2 are the input terminals of the first detection module. The entire circuit cooperates with these components to provide the host chip 1 with accurate input state information, thereby realizing accurate control of the boost-buck module, ensuring stable operation of the circuit under various complex working conditions, and improving the reliability and stability of the system.

[0054] Optionally, the first detection module circuit can realize accurate detection of the input side voltage and current of the boost-buck module through the cooperation of the above-mentioned components, provide the host chip with accurate input state information, and thereby realize accurate control of the boost-buck module.

[0055] In an alternative embodiment, the boost-buck module comprises: a first field effect transistor, wherein the drain of the first field effect transistor is connected to the output terminal of the first detection module, the source of the first field effect transistor is connected to the ground through a first inductor, and the gate of the first field effect transistor receives a control signal from the host chip; a first inductor, wherein the first end of the first inductor is grounded, and the second end of the first inductor is connected to the source of the first field effect transistor, for storing and releasing energy during the switching period of the first field effect transistor; a first diode, wherein the cathode of the first diode is connected to the source of the first field effect transistor, and the anode of the first diode is connected to the input terminal of the second detection module, for ensuring that the energy stored in the first inductor can be transmitted to the load when the first field effect transistor is off.

[0056] Optionally, the first field effect transistor, as a switching element, controls the conversion and transmission of electric energy, the drain is connected to the output of the first detection module, and can receive the input signal from the first detection module. The source of the first field effect transistor is connected to the ground through the first inductor, which can ensure that the electric energy can be stored and released in the switching cycle; the gate can receive the control signal from the master control chip, so as to control the conduction and turn-off according to the PWM signal of the master control chip.

[0057] Optionally, the first inductor plays a role of energy storage and filtering in the boost-buck circuit. When the first field effect transistor is turned on, the inductor stores energy; when the first field effect transistor is turned off, the inductor releases energy, maintaining the continuity of the current.

[0058] Optionally, the first diode can ensure that the energy stored in the first inductor can be transmitted to the load when the first field effect transistor is turned off, thereby preventing the reverse flow of current and protecting the circuit.

[0059] In an optional embodiment, the boost-buck module further comprises: a second field effect transistor, wherein the drain of the second field effect transistor is connected to the output of the first detection module, the source of the second field effect transistor is connected to the ground through a second inductor, and the gate of the second field effect transistor receives a control signal from the master control chip; the second field effect transistor is staggered and connected in parallel with the first field effect transistor, and together realizes the boost-buck function; a second inductor, wherein the first end of the second inductor is connected to the source of the second field effect transistor, and the second end of the second inductor is grounded; a second diode, wherein the cathode of the second diode is connected to the source of the second field effect transistor, and the anode of the second diode is connected to the input of the second detection module, and the second diode works in parallel with the first diode to ensure that the energy stored in the second inductor can be transmitted to the load when the second field effect transistor is turned off.

[0060] Optionally, the second field effect transistor, as another switching element, is staggered and connected in parallel with the first field effect transistor, and together realizes the boost-buck function. This staggered and parallel connection design can improve the power handling capability of the circuit, reduce the demand for filtering elements, reduce costs and electromagnetic interference.

[0061] Optionally, the master control chip controls the conduction and turn-off of the first field effect transistor and the second field effect transistor through the PWM signal, so that the first inductor and the second inductor can store and release energy in different time periods, thereby effectively reducing the ripple current, improving the stability of the output voltage, and at the same time improving the power handling capability of the circuit.

[0062] Optionally, through the above design, the buck-boost module can realize efficient conversion of input voltage and current, ensuring stable operation under different working conditions. The cooperative work of the first field effect transistor, the first inductor and the first diode, and the second field effect transistor, the second inductor and the second diode ensures efficient storage and transmission of electrical energy, improving the reliability and stability of the entire circuit.

[0063] Optionally, Figure 5 is a schematic diagram of an optional buck-boost module circuit according to an embodiment of the present application, as Figure 5 shown, the buck-boost module circuit adopts an interleaved parallel Buck-Boost architecture, including two parallel buck-boost circuits to realize high-efficiency energy conversion and stable output. The first field effect transistor Q1 and the second field effect transistor Q2 serve as switching elements, with their drains connected to the output of the first detection module 1, their sources connected to the ground through the first inductor L1 and the second inductor L2, and their gates receiving PWM control signals from the main control chip 1 through the input terminals P9 and P10 of the main control chip 1. The first ends of the first inductor L1 and the second inductor L2 are connected to the ground, and the second ends are connected to the sources of the first field effect transistor Q1 and the second field effect transistor Q2, respectively, responsible for storing and releasing energy during the switching period. The cathodes of the first diode D1 and the second diode D2 are connected to the sources of the first field effect transistor Q1 and the second field effect transistor Q2, respectively, and the anodes are connected to the input terminals B1 and B2 of the second detection module 4, ensuring that when the first field effect transistor Q1 and the second field effect transistor Q2 are off, electrical energy can be transmitted to the load. The main control chip 1 controls the conduction and turn-off of the first field effect transistor Q1 and the second field effect transistor Q2 through the PWM signal, realizing the buck-boost conversion of the input voltage. Through the cooperative action of these components, the entire buck-boost module circuit not only improves the power handling capability, but also reduces the ripple current, enhances the stability of the output voltage, reduces the cost and electromagnetic interference, and improves the reliability and efficiency of the entire system.

[0064] In an optional embodiment, the first field effect transistor and the second field effect transistor are controlled by the pulse width modulation signal output by the main control chip, realizing buck-boost conversion of the input voltage through alternating switching, and stabilizing the required voltage within the target voltage range through the first inductor, the second inductor, the first diode and the second diode.

[0065] Optionally, the first field effect transistor and the second field effect transistor are controlled by the pulse width modulation signal output by the main control chip, which enables the two field effect transistors to alternately switch, thereby realizing buck-boost conversion of the input voltage. Specifically, when the main control chip sends a PWM signal, it will control the gates of the two MOS transistors respectively, so that the two transistors are turned on and off according to the preset timing. In this way, the input voltage is effectively converted into the required output voltage.

[0066] Meanwhile, the first inductor, the second inductor, the first diode and the second diode in the circuit work together to ensure the voltage required for stable output in the target voltage range. When the first field effect transistor is turned on, the input power charges the first inductor through the first detection module and the first field effect transistor, at this time the inductor stores energy, and the first diode is in reverse bias state and does not conduct. When the first field effect transistor is turned off, the current in the first inductor cannot be interrupted instantaneously, so the inductor releases energy to the load through the first diode, maintains the continuity of the current, and ensures the stability of the output voltage.

[0067] Similarly, when the second field effect transistor is turned on, the input power charges the second inductor through the first detection module and the second field effect transistor, and the second diode is in reverse bias state and does not conduct. When the second field effect transistor is turned off, the current in the second inductor releases energy to the load through the second diode, preventing the current from flowing in the opposite direction and protecting the circuit.

[0068] In an alternative embodiment, the second detection module comprises: a fifteenth resistor, wherein the first end of the fifteenth resistor is connected to the anode of the first diode, and the second end of the fifteenth resistor is connected to the first end of a sixteenth resistor, for detecting the output current and converting it into a voltage signal; a sixteenth resistor, wherein the first end of the sixteenth resistor is connected to the inverting input terminal of the third operational amplifier, and the second end of the sixteenth resistor is connected to the second end of the fifteenth resistor, which works together with the fifteenth resistor to detect the output current; a seventeenth resistor, wherein the first end of the seventeenth resistor is connected to the non-inverting input terminal of the third operational amplifier, and the second end of the seventeenth resistor is grounded, for eliminating the DC offset and providing a reference voltage; an eighteenth resistor, wherein the first end of the eighteenth resistor is connected to the output terminal of the third operational amplifier, and the second end of the eighteenth resistor is connected to the inverting input terminal of the operational amplifier, for constituting a voltage feedback network to stabilize the output voltage of the amplifier; a nineteenth resistor, wherein the first end of the nineteenth resistor is connected to the non-inverting input terminal of the third operational amplifier, and the second end of the nineteenth resistor is connected to the first end of a twentieth resistor; a twentieth resistor, wherein the first end of the twentieth resistor is connected to the second end of the nineteenth resistor, and the second end of the twentieth resistor is grounded, which works together with the nineteenth resistor to constitute a voltage dividing network; a twenty-first resistor, wherein the first end of the twenty-first resistor is connected to the second end of the twentieth resistor, and the second end of the twenty-first resistor is connected to the non-inverting input terminal of the third operational amplifier, which works together with the twentieth resistor to constitute a voltage dividing network and sends the divided output voltage signal to the third operational amplifier.

[0069] Optionally, when the current passes through the fifteenth resistor, a voltage drop is generated across the two ends of the resistor, which is proportional to the current passing through, thereby achieving detection of the output current. The third operational amplifier amplifies the voltage signal detected by the resistors, ensuring that the host chip can accurately detect changes in the output current.

[0070] Optionally, the nineteenth resistor, the twentieth resistor and the twenty-first resistor together constitute a voltage dividing network, which divides the output voltage signal to a suitable level. The seventeenth resistor is connected to the non-inverting input terminal of the third operational amplifier and grounded, providing a stable reference voltage to ensure the accuracy and stability of the amplifier.

[0071] In an alternative embodiment, the second detection module further comprises: a twenty-second resistor, wherein the first end of the twenty-second resistor is connected to the anode of the second diode, and the second end of the twenty-second resistor is connected to the first end of a twenty-third resistor, for detecting the second output current and converting it into a voltage signal; the twenty-third resistor, wherein the first end of the twenty-third resistor is connected to the inverting input terminal of the fourth operational amplifier, and the second end of the twenty-third resistor is connected to the second end of the twenty-second resistor, which acts together with the twenty-second resistor to detect the second output current; a twenty-fourth resistor, wherein the first end of the twenty-fourth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and the second end is grounded, for eliminating DC offset; a twenty-fifth resistor, wherein the first end of the twenty-fifth resistor is connected to the output terminal of the fourth operational amplifier, and the second end of the twenty-fifth resistor is connected to the inverting input terminal of the operational amplifier, for constituting a voltage feedback network to stabilize the output voltage of the amplifier; a twenty-sixth resistor, wherein the first end of the twenty-sixth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and the second end of the twenty-sixth resistor is grounded, for constituting the lower resistor of the second voltage dividing network; a twenty-seventh resistor and a twenty-eighth resistor, which combine to constitute the upper resistor of the second voltage dividing network, wherein the twenty-seventh resistor is connected to the anode of the second diode, and the twenty-eighth resistor is connected to ground; a twenty-ninth resistor, wherein the first end of the twenty-ninth resistor is connected to the first end of the target capacitor, and the second end is grounded, for transmitting the voltage signal across the target capacitor to the host chip for processing.

[0072] Optionally, when the current passes through the twenty-second resistor, a voltage drop is generated across the two ends of the resistor, which is proportional to the current passing through, thereby achieving detection of the second output current. The fourth operational amplifier amplifies the voltage signal detected by the resistors, ensuring that the host chip can accurately detect changes in the second output current.

[0073] Optionally, the voltage dividing network composed of the twenty-seventh resistor and the twenty-eighth resistor divides the output voltage signal of the second diode to a suitable level. The twenty-sixth resistor and the twenty-fourth resistor are connected to the non-inverting input terminal of the fourth operational amplifier, respectively, to provide a stable reference voltage, ensuring the accuracy and stability of the amplifier. The second end is connected to the ground to eliminate the DC offset, ensuring that the reference point of the amplifier is the ground potential.

[0074] In an optional embodiment, the second detection module further comprises a target capacitor, wherein the first end of the target capacitor is connected to the second end of the fifteenth resistor and the twenty-second resistor, and the second end of the target capacitor is connected to the ground, for filtering high-frequency noise in the output voltage.

[0075] Optionally, by connecting the first end of the target capacitor to the second end of the fifteenth resistor and the twenty-second resistor, the target capacitor can directly act on the voltage signal path after the preliminary current detection, effectively filtering the high-frequency interference that may be generated during the conversion of current to voltage signal. The second end of the target capacitor is connected to the ground to provide a stable reference point for the capacitor, which can effectively bypass the high-frequency noise signal to the ground, preventing these noise signals from entering the subsequent amplification and processing circuit.

[0076] Optionally, by introducing the target capacitor, the second detection module can not only accurately monitor the output current and voltage of the boost-buck module, but also effectively filter the high-frequency noise in the output voltage, ensuring the stability and purity of the output voltage. This design further improves the performance of the circuit, making it better adapt to various complex application scenarios and enhancing the reliability and stability of the system.

[0077] Optionally, Figure 6 is a schematic diagram of an optional second detection module circuit according to an embodiment of the present application, as Figure 6As shown, the fifteenth resistor R15 and the twenty-second resistor R22 are connected to the anodes of the first diode D1 and the second diode D2 through the input terminals B1 and B2 of the second detection module 4, respectively, for detecting the output current and converting it into a voltage signal. One end of the fifteenth resistor R15 and the twenty-second resistor R22 is also connected to the sixteenth resistor R16 and the twenty-third resistor R23, respectively, and then to the inverting input terminals of the third operational amplifier U3 and the fourth operational amplifier U4, to realize the amplification processing of the current signal. In order to eliminate the DC offset and provide a stable reference voltage, the seventeenth resistor R17 and the twenty-fourth resistor R24 are connected to the non-inverting input terminals of the third operational amplifier U3 and the fourth operational amplifier U4 and grounded, respectively. At the same time, the eighteenth resistor R18 and the twenty-fifth resistor R25 constitute a voltage feedback network to stabilize the output voltage of the amplifier and ensure the stability and accuracy of the signal. In addition, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-sixth resistor R26, and the twenty-seventh resistor R27 and the twenty-eighth resistor R28 together constitute a voltage dividing network to send the divided output voltage signal to B1 and B2. The target capacitor C is connected to the second end of the fifteenth resistor R15 and the twenty-second resistor R22 and grounded, for filtering out the high-frequency noise in the output voltage and ensuring the stability and purity of the output voltage. In addition, the twenty-ninth resistor R29 is connected in parallel with the target capacitor C, with one end grounded, and P5, P6, P7, and P8 are the input terminals of the main control chip 1. The entire second detection module circuit provides accurate feedback information for the main control chip 1 through the synergistic effect of these components, thereby realizing accurate control and management of the boost-buck module and enhancing the reliability and stability of the system.

[0078] Optionally, the second detection module circuit realizes accurate monitoring and stable output of the output current and voltage of the boost-buck module through the synergistic effect of the above-mentioned components, providing accurate feedback information for the main control chip, thereby realizing accurate control and management of the boost-buck module.

[0079] The above-mentioned embodiments or examples of the present application are not exhaustive, and only illustrate some of the embodiments or examples, and are not intended to be a specific limitation on the scope of protection of the present application. In the case of no contradiction, each step in a certain embodiment or example in the present application can be implemented as an independent example, and the steps can be combined arbitrarily, for example, the scheme after removing some steps in a certain embodiment or example can also be implemented as an independent example, and the order of the steps in a certain embodiment or example can be exchanged arbitrarily, in addition, the optional mode or optional example in a certain embodiment or example can be combined arbitrarily; in addition, the embodiments or examples can be combined arbitrarily, for example, the steps of different embodiments or examples can be combined arbitrarily, a certain embodiment or example can be combined with the optional mode or optional example of other embodiments or examples.

[0080] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0081] In the above-mentioned embodiments of the present application, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0082] In the several embodiments provided by the present application, it should be understood that the disclosed technology can be implemented in other ways. Of course, the unit embodiment described above is only illustrative, and for example, the division of units can be a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, unit or module, which can be electrical or other forms.

[0083] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed to multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment scheme.

[0084] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0085] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0086] The above is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A voltage boosting circuit, characterized by comprising: The step-up and step-down circuit comprises a master control chip, a step-up and step-down module, and a first detection module and a second detection module connected to two sides of the step-up and step-down module respectively, wherein: The first detection module arranged before the step-up and step-down module is used to collect circuit input data, and the step-up and step-down module adopts two parallel electronic power converter circuits; The second detection module arranged after the step-up and step-down module is used to collect circuit output data; The master control chip receives the collected circuit input data and circuit output data, and determines the maximum output power of the step-up and step-down circuit according to the circuit input data and the circuit output data.

2. The boost-buck circuit according to claim 1, wherein The first detection module comprises: a storage battery for providing an input power to be monitored, wherein the negative electrode of the storage battery is grounded; a first detection sub-module for collecting circuit input data of a first side of the step-up and step-down module; a second detection sub-module for collecting circuit input data of a second side of the step-up and step-down module, wherein the first side and the second side are opposite sides.

3. The boost-buck circuit of claim 2, wherein The first detection sub-module comprises: a first resistor, wherein the first end of the first resistor is connected to the positive electrode of the storage battery, and the second end of the first resistor is connected to the first end of a second resistor, for generating a voltage drop when the input current changes to reflect the size of the input current; a second resistor, wherein the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the inverting input terminal of a first operational amplifier, for transmitting the voltage drop on the first resistor to the first operational amplifier; a third resistor, wherein the first end of the third resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second end of the third resistor is connected to the second end of the first resistor, for providing a reference voltage; a fourth resistor, wherein the first end of the fourth resistor is connected to the output terminal of the first operational amplifier, and the second end of the fourth resistor is connected to the inverting input terminal of the first operational amplifier, for forming a voltage feedback to stabilize the output of the first operational amplifier; a fifth resistor, wherein the first end of the fifth resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second end is grounded, for eliminating the DC offset of the input voltage and ensuring that the reference point of the first operational amplifier is the ground potential; a sixth resistor, wherein the first end of the sixth resistor is grounded, and the second end of the sixth resistor is connected to the first end of a seventh resistor, for providing a lower part of a voltage dividing network; the seventh resistor, wherein the first end of the seventh resistor is connected to the second end of the sixth resistor, the second end of the seventh resistor is connected to the second end of the first resistor, and the second end of the seventh resistor is connected to the input port of the master control chip, for dividing the input voltage signal to a preset processing range corresponding to the master control chip.

4. The boost-buck circuit of claim 2, wherein The second detection sub-module comprises: an eighth resistor, wherein the first end of the eighth resistor is connected to the positive electrode of the storage battery, for constituting a current detection path together with the storage battery and a ninth resistor; a ninth resistor, wherein a first end of the ninth resistor is connected to a second end of the eighth resistor, and a second end of the ninth resistor is connected to an inverting input terminal of the second operational amplifier, for transmitting the voltage drop on the eighth resistor to the second operational amplifier; a tenth resistor, wherein a first end of the tenth resistor is connected to a non-inverting input terminal of the second operational amplifier, and a second end of the tenth resistor is connected to the second end of the eighth resistor, for providing a reference voltage; an eleventh resistor, wherein a first end of the eleventh resistor is connected to the inverting input terminal of the second operational amplifier, and a second end of the eleventh resistor is connected to an output terminal of the second operational amplifier, for forming a voltage feedback to stabilize the output of the second operational amplifier; a twelfth resistor, wherein a first end of the twelfth resistor is connected to the non-inverting input terminal of the second operational amplifier, and a second end of the twelfth resistor is connected to ground, for eliminating the DC offset of the input voltage and ensuring that the reference point of the second operational amplifier is the ground potential; a thirteenth resistor, wherein a first end of the thirteenth resistor is connected to the feedback signal of the output terminal of the second operational amplifier, and a second end of the thirteenth resistor is connected to a first end of a fourteenth resistor, for dividing the feedback signal to a preset processing range corresponding to the master chip; a fourteenth resistor, wherein a first end of the fourteenth resistor is connected to the second end of the thirteenth resistor, and a second end of the fourteenth resistor is connected to ground, for transmitting the divided voltage signal of the thirteenth resistor to the ground.

5. The boost-buck circuit of claim 1, wherein The buck-boost module comprises: a first field effect transistor, wherein a drain of the first field effect transistor is connected to an output terminal of the first detection module, a source of the first field effect transistor is connected to ground through a first inductor, and a gate of the first field effect transistor receives a control signal from the master chip; a first inductor, wherein a first end of the first inductor is connected to ground, and a second end of the first inductor is connected to the source of the first field effect transistor, for storing and releasing energy in the switching period of the first field effect transistor; a first diode, wherein a cathode of the first diode is connected to the source of the first field effect transistor, and an anode of the first diode is connected to an input terminal of the second detection module, for ensuring that the energy stored in the first inductor can be transmitted to the load when the first field effect transistor is off.

6. The boost-buck circuit of claim 5, wherein, The buck-boost module further comprises: a second field effect transistor, wherein a drain of the second field effect transistor is connected to the output terminal of the first detection module, a source of the second field effect transistor is connected to ground through a second inductor, and a gate of the second field effect transistor receives a control signal from the master chip, and the second field effect transistor is staggered and connected in parallel with the first field effect transistor to realize the buck-boost function together; a second inductor, wherein a first end of the second inductor is connected to the source of the second field effect transistor, and a second end of the second inductor is connected to ground. A second diode, wherein the cathode of the second diode is connected to the source of the second field effect transistor, and the anode of the second diode is connected to the input of the second detection module, and the second diode works in parallel with the first diode to ensure that the energy stored in the second inductor can be transmitted to the load when the second field effect transistor is turned off.

7. The boost-buck circuit of claim 6, wherein, The first field effect transistor and the second field effect transistor are controlled by the pulse width modulation signal output by the master chip, and the input voltage is converted by alternating switching, and the required voltage is stably output within the target voltage range through the first inductor, the second inductor, the first diode, and the second diode.

8. The boost-buck circuit of claim 1, wherein, The second detection module comprises: A fifteenth resistor, wherein the first end of the fifteenth resistor is connected to the anode of the first diode, and the second end of the fifteenth resistor is connected to the first end of a sixteenth resistor, for detecting the output current and converting it into a voltage signal; A sixteenth resistor, wherein the first end of the sixteenth resistor is connected to the inverting input of a third operational amplifier, and the second end of the sixteenth resistor is connected to the second end of the fifteenth resistor, and the fifteenth resistor and the sixteenth resistor work together to detect the output current; A seventeenth resistor, wherein the first end of the seventeenth resistor is connected to the non-inverting input of the third operational amplifier, and the second end of the seventeenth resistor is grounded, for eliminating DC offset and providing a reference voltage; An eighteenth resistor, wherein the first end of the eighteenth resistor is connected to the output of the third operational amplifier, and the second end of the eighteenth resistor is connected to the inverting input of the operational amplifier, for forming a voltage feedback network to stabilize the output voltage of the amplifier; A nineteenth resistor, wherein the first end of the nineteenth resistor is connected to the non-inverting input of the third operational amplifier, and the second end of the nineteenth resistor is connected to the first end of a twentieth resistor; A twentieth resistor, wherein the first end of the twentieth resistor is connected to the second end of the nineteenth resistor, and the second end of the twentieth resistor is grounded, and the nineteenth resistor and the twentieth resistor work together to form a voltage dividing network; A twenty-first resistor, wherein the first end of the twenty-first resistor is connected to the second end of the twentieth resistor, and the second end of the twenty-first resistor is connected to the non-inverting input of the third operational amplifier, and the twentieth resistor and the twenty-first resistor together form a voltage dividing network to send the divided output voltage signal to the third operational amplifier.

9. The boost-buck circuit of claim 8, wherein, The second detection module further comprises: A twenty-second resistor, wherein the first end of the twenty-second resistor is connected to the anode of the second diode, and the second end of the twenty-second resistor is connected to the first end of a twenty-third resistor, for detecting the second output current and converting it into a voltage signal; A twenty-third resistor, wherein the first end of the twenty-third resistor is connected to the inverting input of a fourth operational amplifier, and the second end of the twenty-third resistor is connected to the second end of the twenty-second resistor, and the twenty-second resistor and the twenty-third resistor work together to detect the second output current; A twenty-fourth resistor, wherein a first end of the twenty-fourth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-fourth resistor is grounded, for eliminating DC offset; A twenty-fifth resistor, wherein a first end of the twenty-fifth resistor is connected to the output terminal of the fourth operational amplifier, and a second end of the twenty-fifth resistor is connected to the inverting input terminal of the operational amplifier, for constituting a voltage feedback network and stabilizing the output voltage of the amplifier; A twenty-sixth resistor, wherein a first end of the twenty-sixth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-sixth resistor is grounded, for constituting a lower resistor of a second voltage dividing network; A twenty-seventh resistor and a twenty-eighth resistor, which are combined to constitute an upper resistor of the second voltage dividing network, wherein the twenty-seventh resistor is connected to the anode of the second diode, and the twenty-eighth resistor is connected to the ground; A twenty-ninth resistor, wherein a first end of the twenty-ninth resistor is connected to a first end of the target capacitor, and a second end of the twenty-ninth resistor is grounded, for transmitting the voltage signal across the target capacitor to the host chip for processing.

10. The boost-buck circuit of claim 9, wherein, The second detection module further comprises: A target capacitor, wherein a first end of the target capacitor is connected to the second ends of the fifteenth resistor and the twenty-second resistor, and a second end of the target capacitor is grounded, for filtering high-frequency noise in the output voltage. A twenty-fourth resistor, wherein a first end of the twenty-fourth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-fourth resistor is grounded, for eliminating DC offset; A twenty-fifth resistor, wherein a first end of the twenty-fifth resistor is connected to the output terminal of the fourth operational amplifier, and a second end of the twenty-fifth resistor is connected to the inverting input terminal of the operational amplifier, for constituting a voltage feedback network and stabilizing the output voltage of the amplifier; A twenty-sixth resistor, wherein a first end of the twenty-sixth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, and a second end of the twenty-sixth resistor is grounded, for constituting a lower resistor of a second voltage dividing network; A twenty-seventh resistor and a twenty-eighth resistor, which are combined to constitute an upper resistor of the second voltage dividing network, wherein the twenty-seventh resistor is connected to the anode of the second diode, and the twenty-eighth resistor is connected to the ground; A twenty-ninth resistor, wherein a first end of the twenty-ninth resistor is connected to a first end of the target capacitor, and a second end of the twenty-ninth resistor is grounded, for transmitting the voltage signal across the target capacitor to the host chip for processing. The second detection module further comprises: A target capacitor, wherein a first end of the target capacitor is connected to the second ends of the fifteenth resistor and the twenty-second resistor, and a second end of the target capacitor is grounded, for filtering high-frequency noise in the output voltage.

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