Dual-path charge pump frequency source circuit and radar system

Abstract

The invention relates to the technical field of mixed signal integrated circuit design, in particular to a double-path charge pump frequency source circuit and a radar system, and the circuit comprises a phase frequency detector, an integral path charge pump, a proportional path charge pump, a loop filter and a voltage-controlled oscillator module. The phase frequency detector detects the phase difference and the frequency difference of an input reference signal and a feedback signal, and respectively drives the integral path charge pump and the proportional path charge pump which are connected in parallel; the integral path charge pump generates an integral control signal, the proportional path charge pump generates a proportional control signal, and the two paths of signals are combined and then input into the loop filter; the loop filter carries out filtering processing on the mixed signal and outputs stable direct current control voltage to the voltage-controlled oscillator module; the voltage-controlled oscillator generates an oscillation voltage signal of a target frequency according to the control voltage. Through the double-path charge pump structure, the phase noise performance and the loop stability of the frequency source are improved, and the high-precision frequency synthesis circuit is suitable for a high-precision frequency synthesis scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mixed signal integrated circuit design, and particularly relates to a dual-path charge pump frequency source circuit and a radar system. BACKGROUND

[0002] With the development of wireless communication, detection and sensing technology, the performance, integration and cost requirements of radar systems are increasing. The frequency source circuit (the core is a phase-locked loop) provides a stable clock, which plays a key role in the performance of the radar system. The radar system has very high requirements for the quality of the clock signal. The problems of stable clock signal, low jitter and anti-interference need to be solved to ensure signal quality, transmission distance and system reliability.

[0003] In the clock signal generation link of the radar system, the high-quality low-frequency clock signal output by the crystal oscillator is multiplied based on the phase-locked loop (PLL) technology to obtain a stable, low-jitter high-frequency clock signal. Among them, the charge pump phase-locked loop (CPPLL) becomes the preferred solution due to its unique advantages. Compared with the all-digital phase-locked loop (ADPLL), CPPLL can effectively avoid quantization noise interference and high power noise sensitivity problems. It not only can realize high frequency resolution and high precision signal output, but also has excellent robust performance due to the simple system architecture. In the parameter design aspect, by setting the auxiliary charge pump current Icp _ p which is much smaller than the main charge pump current Icp _ i (about 30 mu A), the integral capacitance value is successfully reduced while maintaining the loop dynamic characteristics unchanged. Then, by adjusting the control voltage with the loop filter, the output frequency of the voltage-controlled oscillator (VCO) is precisely adjusted, and finally the frequency synchronization and phase locking targets are achieved.

[0004] Although the above scheme shows good performance in clock signal generation, the parasitic capacitance effect of the integral capacitor has not been effectively solved. This parasitic capacitance will have a significant impact on the system phase noise performance, and become a key factor restricting the further improvement of the phase-locked loop performance. SUMMARY

[0005] The technical problem to be solved by the present application is to solve the technical problem that the radar system in the prior art is difficult to balance high frequency, low jitter output and small phase error for the frequency source circuit.

[0006] The purpose of the present application is achieved by the following technical solutions: In a first aspect, the present application provides a dual-path charge pump frequency source circuit, comprising a frequency discriminator, an integral path charge pump, a proportional path charge pump, a loop filter module and a voltage-controlled oscillator module; The frequency discriminator is connected with the integral path charge pump and the proportional path charge pump respectively, and is used for detecting the phase difference and the frequency difference between the input reference signal and the feedback signal; The integral path charge pump and the proportional path charge pump are connected to the loop filter module in parallel; the integral path charge pump is used for generating an integral control signal according to the phase difference and the frequency difference; and the proportional path charge pump is used for generating a proportional control signal according to the phase difference and the frequency difference; The loop filter module is connected with the voltage-controlled oscillator module, and outputs a control voltage of the voltage-controlled oscillator module after receiving the integral control signal of the integral path charge pump and the proportional control signal of the proportional path charge pump; The voltage-controlled oscillator module is used for generating an oscillation voltage according to the control voltage output by the loop filter module.

[0007] As a further improvement of the present application, the frequency discriminator comprises a front-stage logic module, a rear-stage logic module, a control logic module and an output signal module; The front-stage logic module is connected with the input end of the control logic module through a first node; the front-stage logic module comprises four NOR gates; the first input end of the first NOR gate is used for receiving the input reference signal, the first input ends of the last three NOR gates are sequentially connected with the output ends of the previous NOR gates, and the first input ends of the second and third NOR gates are directly connected; the second input ends of all the NOR gates are sequentially connected with the output ends of the next NOR gates, and the last NOR gate is connected with the input end of the rear-stage logic module; The rear-stage logic module is connected with the input end of the control logic module through the first node; the rear-stage logic module comprises four NOR gates; the first input end of the first NOR gate is connected with the second input end of the last NOR gate in the front-stage logic module; the first input ends of all the NOR gates are connected with the output ends of the previous NOR gates; and the second input end of the last NOR gate is used for inputting the feedback signal; The control logic module comprises a ninth NOR gate and two control components; the two input ends of the ninth NOR gate are connected with the control components respectively, and the output end is connected with the front-stage logic module and the rear-stage logic module through the first node respectively; the other input end of one control component is connected with the front-stage logic module, and outputs an upper control signal and a corresponding inverse logic signal according to the phase difference and the frequency difference of the front-stage logic module; the other input end of the other control component is connected with the rear-stage logic module, and outputs a lower control signal and a corresponding inverse logic signal according to the phase difference and the frequency difference of the rear-stage logic module; The output signal module comprises several inverter assemblies connected in series for outputting the control signal outputted by the control logic module and the corresponding inverse logic signal.

[0008] As a further improvement of the present application, the control assembly comprises two inverters connected in series and a transmission gate. One end of the transmission gate is connected to the input end of the ninth NOR gate and is connected to the line between the two inverters connected in series, and the other end is connected to the output signal module. The input end of the first inverter of the two inverters connected in series is used to connect the previous logic module or the subsequent logic module; the output end of the last inverter is connected to the control assembly.

[0009] As a further improvement of the present application, the integral path charge pump and the proportional charge pump are connected in parallel through a current source module, and the current source module comprises a current source and three MOS tubes. The gates of the three MOS tubes are connected to complete current source replication, and the sources of the three MOS tubes are connected to the power supply VDD; the drain of the first MOS tube is connected to the negative electrode of the current source, the drain of the second MOS tube is connected to the integral path charge pump, and the drain of the third MOS tube is connected to the proportional path charge pump.

[0010] As a further improvement of the present application, the integral path charge pump and the proportional path charge pump have the same structure and each comprises a bias circuit, a first switch unit, a second switch unit and a current source control module. The output end of the bias circuit of the integral path charge pump is connected in parallel with the output end of the bias circuit of the proportional path charge pump, and then connected to the current source control module of the integral path switch; the integral path switch refers to the first switch unit and the second switch unit corresponding to the integral path charge pump. The input of the first switch unit is used to access the upper bias end of the current source module; the input end of the second switch unit accesses the lower bias end of the current source; the output end of the first switch unit is connected to the output end of the second switch unit, and outputs the integral control signal and the proportional control signal.

[0011] As a further improvement of the present application, the loop filter module comprises an integral path filter and a proportional path filter. The integral path filter comprises a first resistor, a first capacitor and a second capacitor; the first resistor is connected in series with the second capacitor, and then connected in parallel with the first capacitor and grounded; one end of the first capacitor is also connected to the output end of the integral path charge pump; the port connected with the first resistor of the second capacitor is also connected to the input end of the voltage-controlled oscillator module. The proportional path filter comprises five MOS tubes; the gate and the drain of the first MOS tube are connected with the gate of the second MOS tube and the positive pole of the current source; the source of the first MOS tube and the source of the second MOS tube are grounded; the drain of the second MOS tube is connected with the gate and the drain of the third MOS tube, and the gate of the fifth MOS tube and the output end of the proportional path charge pump are also connected; the source of the third MOS tube, the drain and the source of the fourth MOS capacitor and the source of the fifth MOS tube are connected in parallel and then connected to the power supply VDD; the drain of the fifth MOS tube is used as the output end and is connected to the input end of the voltage-controlled oscillator module.

[0012] As a further improvement of the application, the voltage-controlled oscillator module comprises a four-stage differential ring oscillator; the four-stage differential ring oscillator comprises four ring oscillator delay units and corresponding four buffer modules; The four ring oscillator delay units are a pseudo-differential pair unit composed of a plurality of inverters, the non-inverting output ends of all the ring oscillator delay units are connected with the inverting input ends of the corresponding buffer modules, the inverting input ends of the ring oscillator delay units are connected with the inverting input ends of the corresponding buffer modules of the previous ring oscillator delay units, the inverting input end of the first ring oscillator delay unit is connected with the inverting input end of the fourth buffer module, forming a cascaded closed loop structure; the four buffer modules respectively output one way of differential signals.

[0013] As a further improvement of the application, the buffer module is used for outputting the input reference signal as a digital signal with full swing from the power supply to the ground and a duty cycle of 50%, and the input reference signal is a clock signal.

[0014] As a further improvement of the application, a programmable frequency divider is further included, the input end of the programmable frequency divider is connected with the output end of the voltage-controlled oscillator module, and the output end is connected with the input end of the frequency discriminator, for adjusting the output signal of the voltage-controlled oscillator module.

[0015] In the second aspect, the application provides a radar system, comprising a reference signal interface, a control circuit, a frequency divider module and a clock frequency source; the output end of the clock frequency source is connected with the frequency divider module, the input end is connected with the control circuit and the reference signal interface, for receiving the frequency source control signal output by the control circuit; the output end of the frequency divider is used for outputting a frequency signal; the control circuit interacts with the outside through a control line and controls the clock frequency source at the same time; and the clock frequency source applies the above-mentioned double-path charge pump frequency source circuit.

[0016] The beneficial effects of the present application are as follows: the frequency source circuit of the double-path charge pump provided by the present application detects the phase difference and frequency difference between the input reference signal and the feedback signal through the frequency discriminator and phase discriminator, and then generates a control signal. The integral path charge pump and the proportional path charge pump operate in parallel, and generate integral control signals and proportional control signals according to the outputs of the frequency discriminator and phase discriminator, respectively, wherein the integral path charge pump focuses on long-term frequency stability, and the proportional path charge pump quickly responds to phase deviation, and the signals of the two are combined in the loop filter module. The loop filter module receives and processes the control signals from the two paths, filters out high-frequency noise, smooths the output voltage, and finally forms a stable control voltage for adjusting the operating point of the voltage-controlled oscillator module. The voltage-controlled oscillator module automatically adjusts its oscillation frequency according to the control voltage output by the loop filter module, so as to realize precise control of the frequency and phase locking. The double-path design method, through the complementary action of the integral and proportional paths, not only improves the capture range and locking speed of the circuit, but also effectively suppresses frequency jitter and phase noise, providing a high-quality clock signal source for high-precision application scenarios such as radar systems.

[0017] Among them, the proportional path generates a voltage signal proportional to the instantaneous phase difference by quickly responding to the high-frequency phase error (such as data jitter or burst interference) output by the frequency discriminator and phase discriminator, directly adjusts the frequency tuning sensitivity (Kvco) of the voltage-controlled oscillator module, and realizes fast locking and dynamic tracking; the high-bandwidth characteristic of the proportional path can quickly compensate for the phase deviation caused by high-frequency noise, avoiding the loss of phase-locked loop due to instantaneous disturbance. The double-path realizes a wideband, low-jitter, high-stability phase-locked loop system through dynamic current matching and complementary filtering characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a basic application framework schematic diagram of the frequency source circuit in the embodiment of the present application; Figure 2 is a basic circuit of the frequency source circuit in the embodiment of the present application; Figure 3 is a circuit diagram of the frequency discriminator and phase discriminator in the embodiment of the present application; Figure 4 is a charge pump model diagram in the embodiment of the present application; Figure 5 is a charge pump schematic diagram in the embodiment of the present application; Figure 6 is a circuit schematic diagram of an integral path filter circuit in an embodiment of the present application; Figure 7 is a circuit schematic diagram of a proportional path filter circuit in an embodiment of the present application; Figure 8 is a VCO model diagram in an embodiment of the present application; Figure 9 is a circuit schematic diagram of a ring oscillator delay unit circuit in an embodiment of the present application; Figure 10 is a circuit schematic diagram of a VCO buffer module circuit in an embodiment of the present application; Figure 11 is a circuit schematic diagram of a programmable frequency divider circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the objects and technical solutions of the present application clearer and more convenient to understand, the present application will be further described in detail below in combination with the drawings and embodiments. The specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0021] The technical solutions of the present application will be described clearly and completely below in combination with the drawings and specific embodiments, wherein the described embodiments are only a part of the embodiments of the present application, but not all the embodiments.

[0022] Embodiment 1 The present embodiment provides a dual-path charge pump frequency source circuit, which realizes a wide-band, low-jitter and high-stable phase-locked loop system through dynamic current matching and complementary filtering characteristics of the dual-path.

[0023] The circuit comprises a frequency discriminator, an integral path charge pump, a proportional path charge pump, a loop filter module and a voltage-controlled oscillator module.

[0024] The frequency discriminator is connected with the integral path charge pump and the proportional path charge pump respectively, and is used to detect the phase difference and the frequency difference between the input reference signal and the feedback signal. The integral path charge pump and the proportional path charge pump are connected to the loop filter module in parallel. The integral path charge pump is used to generate an integral control signal according to the phase difference and the frequency difference. The proportional path charge pump is used to generate a proportional control signal according to the phase difference and the frequency difference. The loop filter module is connected with the voltage-controlled oscillator module, and outputs a control voltage of the voltage-controlled oscillator module after receiving the integral control signal of the integral path charge pump and the proportional control signal of the proportional path charge pump. The voltage-controlled oscillator module is used to generate an oscillation voltage according to the control voltage output by the loop filter module, and adjust the frequency according to the oscillation voltage.

[0025] The technical scheme of the embodiment provides an integral path and proportional path charge pump frequency source circuit capable of effectively improving frequency stability and reducing phase noise.

[0026] As a further embodiment in the embodiment, the frequency discriminator and phase discriminator comprises a front-stage logic module, a rear-stage logic module, a control logic module and an output signal module. The front-stage logic module is used to generate upper control signals and corresponding inverse logic signals. The rear-stage logic module is used to generate lower control signals and corresponding inverse logic signals.

[0027] The front-stage logic module is connected with the input end of the control logic module through the first node; the front-stage logic module comprises four NOR gates; the first input end of the first NOR gate is used to receive the input reference signal, the first input ends of the last three NOR gates are sequentially connected with the output ends of the previous NOR gates, and the first input ends of the second and third NOR gates are directly connected; the second input ends of all the NOR gates are connected with the output ends of the next NOR gates, and the last NOR gate is connected with the input end of the rear-stage logic module.

[0028] The rear-stage logic module is connected with the input end of the control logic module through the first node; the rear-stage logic module comprises four NOR gates; the first input end of the first NOR gate is connected with the second input end of the last NOR gate in the front-stage logic module; the first input ends of all the NOR gates are connected with the output ends of the previous NOR gates; and the second input end of the last NOR gate is used to input the feedback signal.

[0029] The control logic module comprises a ninth NOR gate and two control components; two inputs of the ninth NOR gate are connected with the control components respectively, and an output thereof is connected with a previous-stage logic module and a next-stage logic module through a first node respectively; another input of one control component is connected with the previous-stage logic module, and an upper control signal and a corresponding inverse logic signal are output according to a phase difference and a frequency difference of the previous-stage logic module; another input of another control component is connected with the next-stage logic module, and a lower control signal and a corresponding inverse logic signal are output according to a phase difference and a frequency difference of the next-stage logic module.

[0030] The output signal module comprises a plurality of serially connected inverter components, and is used for outputting the control signals and the corresponding inverse logic signals output by the control logic module.

[0031] The control component comprises two serially connected inverters and a transmission gate. One end of the transmission gate is connected with an input end of the ninth NOR gate and is connected to a line between the two serially connected inverters, and the other end is connected to the output signal module; an input end of a first inverter of the two serially connected inverters is used for connecting the previous-stage logic module or the next-stage logic module; and an output end of a last inverter is connected with the control component.

[0032] The integral path charge pump and the proportional path charge pump are connected in parallel through a current source module. The current source module comprises a current source and three MOS tubes. The gates of the three MOS tubes are connected, and current source replication is completed. The sources of the three MOS tubes are connected to a power supply VDD; the drain of a first MOS tube is connected to a negative electrode of the current source, the drain of a second MOS tube is connected to the integral path charge pump, and the drain of a third MOS tube is connected to the proportional path charge pump.

[0033] Further, the integral path charge pump and the proportional path charge pump have the same structure, and each comprises a bias circuit, a first switch unit, a second switch unit and a current source control module.

[0034] The output end of the bias circuit of the integral path charge pump and the output end of the bias circuit of the proportional path charge pump are connected in parallel and then connected to the current source control module of the integral path switch. The integral path switch refers to the first switch unit and the second switch unit corresponding to the integral path charge pump. The input of the first switch unit is used for accessing the upper bias end of the current source module; the input end of the second switch unit accesses the lower bias end of the current source; the output end of the first switch unit is connected with the output end of the second switch unit, and an integral control signal and a proportional control signal are output.

[0035] The loop filter module comprises an integral path filter and a proportional path filter. Wherein: The integral path filter comprises a first resistor, a first capacitor and a second capacitor; the first resistor and the second capacitor are connected in series, and then the series connection is connected in parallel with the first capacitor and grounded; one end of the first capacitor is also connected with an output end of an integral path charge pump; a port connected with the first resistor of the second capacitor is also connected to an input end of a voltage-controlled oscillator module.

[0036] The proportional path filter comprises five MOS transistors; a gate and a drain of a first MOS transistor and a gate of a second MOS transistor are connected with a positive electrode of a current source; sources of the first MOS transistor and the second MOS transistor are grounded; a drain of the second MOS transistor and a gate and a drain of a third MOS transistor are connected, and the gate and the drain of the third MOS transistor are also connected with a gate of a fifth MOS transistor and an output end of a proportional path charge pump; a source of the third MOS transistor, a drain and a source of a fourth MOS capacitor and a source of the fifth MOS transistor are connected in parallel and then connected to a power supply VDD; a drain of the fifth MOS transistor is used as an output end and is connected to an input end of the voltage-controlled oscillator module.

[0037] The voltage-controlled oscillator module comprises a four-stage differential ring oscillator. The four-stage differential ring oscillator comprises four ring oscillator delay units and corresponding four buffer modules; noninverted output ends of all the ring oscillator delay units are connected with inverted input ends of corresponding buffer modules, inverted input ends of the ring oscillator delay units are connected with inverted input ends of buffer modules of a previous ring oscillator delay unit, the inverted input end of the first ring oscillator delay unit is connected with an inverted input end of the fourth buffer module, forming a cascaded closed loop structure; the four buffer modules respectively output one differential signal.

[0038] The buffer module is used for outputting an input reference signal as a full-swing power supply to ground digital signal with a duty cycle of 50%, and the input reference signal is a clock signal.

[0039] In addition, the embodiment also comprises a programmable frequency divider, an input end of the programmable frequency divider is connected with an output end of the voltage-controlled oscillator module, and an output end of the programmable frequency divider is connected with an input end of the frequency discriminator, and the programmable frequency divider is used for adjusting an output signal of the voltage-controlled oscillator module.

[0040] Embodiment 2 As a further preferred embodiment of embodiment 1, the embodiment provides a specific embodiment of a dual-path charge pump frequency source circuit.

[0041] The dual-path charge pump frequency source circuit in the embodiment is applied to a radar system and is used as a clock frequency source. As shown in FIG. 1, the dual-path charge pump frequency source circuit comprises an integral path filter, a proportional path filter, a voltage-controlled oscillator module and a frequency discriminator. Figure 1As shown, an external reference signal (ref) is input to the clock frequency source, and the signal generated by the clock frequency source is output to the frequency divider. On the other hand, the frequency source control signal output by the control circuit is received to adjust itself. The frequency divider outputs multiple signals, which are respectively supplied to the ADC (analog-to-digital converter), high-speed I / O (input / output interface), and frequency synthesizer. The output of the frequency synthesizer is connected to the radar transmitter and the antenna phased array unit. The control circuit interacts with the outside world through control lines and controls the clock frequency source and other modules.

[0042] Among them, such as Figure 2 The diagram shows the dual-path charge pump frequency source circuit, i.e., the clock frequency source, of this embodiment. The circuit includes a frequency and phase detector, an integrating path charge pump, a proportional path charge pump, a loop filter module, and a voltage-controlled oscillator (VCO) module. The frequency and phase detector detects the phase and frequency differences between the input reference signal and the feedback signal output by the programmable frequency divider, generating pull-up and pull-down control signals, and transmitting these control signals to the integrating and proportional path charge pumps. The integrating and proportional path charge pumps are connected in parallel and then connected to the loop filter module. The integrating path charge pump receives the pull-up and pull-down control signals output by the frequency and phase detector, generating a first charging current and a first discharging current as the integrating control signal. The proportional path charge pump receives the pull-up and pull-down control signals output by the frequency and phase detector, generating a second charging current and a second discharging current as the proportional control signal. The loop filter receives the output signals from the integrating and proportional path charge pumps and outputs the control voltage for the VCO. The loop filter includes a first loop filter and a second loop filter. When the integral path charge pump outputs a first charging current, the first loop filter increases the control voltage; when the integral path charge pump outputs a discharging current, the first loop filter branch decreases the control voltage. When the proportional path charge pump outputs a second charging current, the second loop filter branch increases the control voltage; when the proportional path charge pump outputs a discharging current, the second loop filter branch decreases the control voltage.

[0043] The voltage-controlled oscillator module includes a ring oscillator delay unit and an output buffer stage. It generates an oscillation voltage based on the control voltage output by the loop filter. When the oscillation voltage increases, the oscillation frequency of the output signal increases, and when the oscillation voltage decreases, the oscillation frequency of the output signal decreases.

[0044] A programmable frequency divider is used to divide the output signal of a voltage-controlled oscillator according to a program, and generate a feedback signal that is output to a frequency and phase detector for comparison with a reference clock signal.

[0045] like Figure 3 As shown, the frequency and phase detector includes: first to ninth NOR gates, first to twelfth inverters, and first to second transmission gates. The specific connections are as follows: The first input end of the first NOR gate NOR1 is connected with a reference signal; the second input end of the first NOR gate NOR1, the output end of the second NOR gate NOR2 and the input end of the first inverter are connected; the output end of the first NOR gate NOR1, the first output end of the second NOR gate NOR2 and the first output end of the third NOR gate NOR3 are connected; the second input end of the second NOR gate, the output end of the third NOR gate and the first input end of the fourth NOR gate are connected; the second input end of the third NOR gate and the output end of the fourth NOR gate are connected; the second input end of the eighth NOR gate is connected with a feedback signal; the first input end of the eighth NOR gate, the output end of the seventh NOR gate and the input end of the seventh inverter are connected; the output end of the eighth NOR gate, the second input end of the seventh NOR gate and the second input end of the sixth NOR gate are connected; the first input end of the seventh NOR gate, the output end of the sixth NOR gate and the second input end of the fifth NOR gate are connected; the first input end of the sixth NOR gate and the output end of the fifth NOR gate are connected; the second input end of the fourth NOR gate, the first input end of the fifth NOR gate and the output end of the ninth NOR gate are connected; the output of the first inverter, the input of the second inverter, the input of the first transmission gate and the first input end of the ninth NOR gate are connected; the output end of the seventh inverter, the input end of the eighth inverter, the input end of the second transmission gate and the second input end of the ninth NOR gate are connected; the output of the second to fourth inverters outputs an up control signal UP; the first transmission gate and the fifth to sixth inverters output an inverse logic of the up control signal UPB; the eighth to tenth inverters output a down control signal DN; the second transmission gate and the eleventh to twelfth inverters output an inverse logic of the down control signal DNB. The phase frequency detector is used for detecting the frequency difference and phase difference of the input signal and the feedback signal, and generating the pull-down control signal and the pull-up control signal.

[0046] The working principle of the phase frequency detector is as follows: the core of the circuit is to use the NOR gate (NOR, NOT-OR gate), the inverter (INV, Inverter) and the transmission gate (T-GATE, Transmission Gate) to cooperate to change the reference signal and the feedback signal into the required control signal. The NOR gate itself can perform the logic operation of the first or the second NOR. The NOR gates of the front stage (NOR1-NOR4) and the rear stage (NOR5-NOR8) in the embodiment are connected in cross to form a small feedback loop (for example, NOR3 and NOR4 are connected together), so as to stabilize the signal. The role of the inverter is very direct, that is, to reverse the high and low levels of the signal. The multiple-stage inverters are connected in series (for example, INV2-INV4), so as to avoid signal distortion. The transmission gate is like a controllable switch, which determines whether the signal can pass through. Cooperating with the inverter, the transmission gate can generate a signal UPB which is completely opposite to the main signal (for example, UP), so that the one positive and one negative signals can meet the cooperative control requirements of the subsequent circuit. The ninth NOR gate NOR9 receives the intermediate signals of the front stage and the rear stage, and then feeds back the processing results, so as to ensure that the signal processing of the whole circuit is more coordinated.

[0047] As Figure 4 , Figure 5 shown, the structure of the integral path charge pump and the proportional path charge pump is similar, including: bias circuit, current source, first switch unit, second switch unit; wherein the current source is connected through the gate of PMOS tube M0, PMOS tube M1, PMOS tube M2 to copy; the source of PMOS tube M0, PMOS tube M1, PMOS tube M2 is connected with power supply VDD, the drain of PMOS tube M0 is connected with the negative pole of current source; the drain of PMOS tube M1 is connected with the integral path charge pump bias module; the drain of PMOS tube M2 is connected with the input of proportional path charge pump bias module; the output of integral path charge pump bias circuit is connected with the current source control module of integral path switch; the output of proportional path charge pump bias circuit is connected with the current source control module of integral path switch; the first switch unit contains PMOS tube M3, PMOS tube M7 and NMOS tube M4, NMOS tube M8, wherein the gate of PMOS tube M3, the gate of NMOS tube M8 is connected with the output UPB of frequency discriminator, the gate of NMOS tube M4, the gate of PMOS tube M7 is connected with the output UP of frequency discriminator, the input of first switch unit is connected with the upper bias current source; the second switch unit contains PMOS tube M5, PMOS tube M9 and NMOS tube M6, wherein the gate of PMOS tube M5, NMOS tube M10 is connected with the output DNB of frequency discriminator, the gate of NMOS tube M6, the gate of PMOS tube M9 is connected with the output DN of frequency discriminator, the input of second switch unit is connected with the lower bias current source; the output end of first switch unit is connected with the output end of second switch unit as output signal Vctrl_i, Vctrl_p.

[0048] The core logic of the integral path charge pump and the proportional path charge pump charge pump is to convert the UP / UPB, DN / DNB signals of the frequency discriminator into stable control voltages Vctrl_i, Vctrl_p through current source replication and accurate control of switches. First, PMOS tubes M0, M1 and M2 are connected together through the gate, and PMOS tube M0 first forms a loop with the original current source to determine the reference current; M1 and M2 will copy the same current as the reference current because they are connected to the gate of M0, and will supply power to the biasing modules of the integral path and the proportional path, so as to ensure the stability of the current of the two paths and avoid subsequent signal fluctuations. Then, the biasing circuit will convert the copied current into a control signal suitable for the operation of the switch, and transmit it to the current source control module of the switch to ensure that the switch can be stably turned on or turned off. And two switch units act according to the UP / UPB, DN / DNB control signals output by the frequency discriminator: for example, when the UP signal is valid, MOS tube M4 and MOS tube M7 are turned on, and the upper biasing current can pass through the first switch unit; when the DN signal is valid, MOS tube M6 and MOS tube M9 are turned on, and the lower biasing current can pass through the second switch unit. Finally, the outputs of the two switches are combined to form Vctrl_i and Vctrl_p voltages that can control the subsequent circuit.

[0049] As shown in Figure 6 , the integral path filter includes a first resistor R, a first capacitor C1 and a second capacitor C2; wherein the capacitor uses a MOS capacitor, one end of the first capacitor C1 and one end of the resistor R are connected with the input signal Vctrl_i; the other end of the first resistor R and one end of the second capacitor C2 are connected with the output Vctrl; the other ends of the first capacitor C1 and the second capacitor C2 are grounded.

[0050] As shown in Figure 7 , the proportional path filter includes a current source circuit, a current mirror biasing circuit: NMOS tube M1, NMOS tube M2, diode-connected PMOS tube M3, PMOS capacitor M4 and PMOS tube M5; wherein the anode of the current source is connected with the gate and drain of NMOS tube M1 and the gate of NMOS tube M2; the sources of NMOS tube M1 and NMOS tube M2 are grounded; the drain of NMOS tube M2, the gate and drain of PMOS tube M3, the gate of PMOS capacitor tube M4, the gate of PMOS tube M5 and the input signal Vctrl_p are connected; the source of PMOS tube M3, the drain and source of PMOS capacitor tube M4 and the source of PMOS tube M5 are connected to VDD; the drain of PMOS tube M5 is connected to the output Vctrl.

[0051] As shown in Figure 8As shown, the core module of the voltage-controlled oscillator is a four-stage differential ring oscillator, including: first to fourth ring delay units and first to fourth differential buffer circuits. The outputs of the first and second loop filters are connected to Vbias of the first to fourth ring delay units of the voltage-controlled oscillator, the non-inverting input of the first delay module, the non-inverting input of the second ring delay unit and the non-inverting input of the first buffer circuit are connected; the non-inverting input of the third ring delay unit, the non-inverting input of the second buffer circuit are connected; the non-inverting input of the fourth ring delay unit, the non-inverting input of the third buffer circuit are connected; the non-inverting input of the first ring delay unit, the non-inverting input of the fourth buffer circuit are connected; the outputs of the first to fourth differential buffer circuits output differential signals respectively.

[0052] Among them, the first to fourth buffer modules output the clock signal as a full-swing power-to-ground digital square wave signal with a duty cycle of 50%.

[0053] The output currents of the integral path and the proportional path charge pump are superimposed at the control end of the oscillator, and the overall circuit is as shown in Figure 8 The four-stage differential ring oscillator in the design can generate eight single-ended clock signals with a phase difference of 45°, or four differential clock signals with a phase difference of 90°. After being amplified by the internal buffer, the clock signal is output as a full-swing digital signal with power to ground. The ring delay unit circuit is as shown in Figure 9 The latch is composed of a pseudo-differential pair composed of two inverters and another two inverters. In order to ensure that the circuit does not oscillate in common mode, the common-mode gain must be much smaller than the differential-mode gain, and in this embodiment, the latch circuit size is the same as the pseudo-differential pair size. The output buffer circuit is as shown in Figure 10 As shown, the input signal differential clock signal uses capacitive coupling, and the DC bias voltage is provided by the inverter with resistance feedback, and then the driving capability is improved through the inverter chain, and the crossed inverters are used to correct the duty cycle of the clock signal.

[0054] As shown in Figure 11As shown, the programmable frequency divider module comprises: a first fourth 2 / 3 frequency divider, a first third AND gate, a first third NAND gate, a first third OR gate, a first third inverter, a D flip-flop, a two-way data selector; wherein the fin of the first 2 / 3 frequency divider is connected to the output of the VCO, and the second input of the two-way data selector; the fout of the first 2 / 3 frequency divider is connected to the fin of the second 2 / 3 frequency divider; the fout of the second 2 / 3 frequency divider is connected to the fin of the third 2 / 3 frequency divider; the fout of the third 2 / 3 frequency divider is connected to the fin of the fourth 2 / 3 frequency divider; the modin of the fourth 2 / 3 frequency divider is connected to the power supply VDD; the modout of the fourth 2 / 3 frequency divider is connected to the input of the third NAND gate; the output of the third NAND gate is connected to the modin of the third 2 / 3 frequency divider; the modout of the third 2 / 3 frequency divider is connected to the output of the third OR gate; the output of the third OR gate is connected to the two inputs of the second NAND gate; the output of the second NAND gate is connected to the modin of the second 2 / 3 frequency divider; the modout of the second 2 / 3 frequency divider is connected to the output of the second OR gate; the output of the second OR gate is connected to the two inputs of the first NAND gate; the output of the first NAND gate is connected to the modin of the first 2 / 3 frequency divider; the modout of the first 2 / 3 frequency divider is connected to the first input of the two-way data selector; the control signals P<0>~P<3> are connected to the P terminals of the first fourth 2 / 3 frequency divider respectively; the control signals P<1>~P<3> are connected to the second inputs of the first third OR gate respectively; the control signal P<4> is connected to the second input of the third NAND gate and the first input of the third OR gate; the output of the first OR gate is connected to the input of the first inverter and the first selection terminal of the two-way data selector; the output of the first inverter is connected to the second selection terminal of the two-way data selector; the output of the two-way data selector is connected to the clk of the D flip-flop; the Q' terminal of the D flip-flop is connected to the D terminal of the D flip-flop; the Q of the D flip-flop is connected to the buffer stage composed of the second third inverter; the output of the third inverter is connected to OUT.

[0055] Preferably, the frequency division coefficient of the programmable frequency divider is determined by the input of five control codes P<0>~P<4>. The frequency divider designed in this paper can realize 1-31 integer programmable frequency division, and realize linear adjustment of the output frequency.

[0056] In summary, compared with traditional single-path phase-locked loops, this invention features independent integral path charge pumps and filters, as well as proportional path charge pumps and filters. By employing dual-path charge pumps and leveraging dynamic current matching and complementary filtering characteristics, it achieves wide bandwidth, low jitter, and high stability for the frequency source circuit. In a dual-path PLL system, current noise contributes less to the output phase noise. Furthermore, by increasing the charge pump current in the proportional path and reducing the integral path current using a smaller capacitor, loop noise is reduced without sacrificing area. A voltage buffer circuit is designed after the integral path charge pump output to ensure equal output voltages for the left and right switching currents, matching the channel length modulation effect. To achieve a full swing of the output voltage from power supply to ground, a parallel PMOS and NMOS differential pair structure is used to realize the common-mode range of the rail-to-rail input signal.

[0057] In a dual-path frequency source system, compared to passive filters, active filters using integral and proportional paths can reduce the layout area and achieve higher integration. Through high-frequency noise filtering, current matching, and dynamic response optimization, the transient performance and anti-interference capability of the phase-locked loop are improved, and jitter is reduced.

[0058] In the buffer module of the voltage-controlled oscillator: the input signal differential clock signal is capacitively coupled, the DC bias voltage is provided by the inverter with resistor feedback, and then the drive capability is improved through the inverter chain. The output signal is a square wave signal of 0~VDD. The cross inverter is used to correct the duty cycle of the clock signal to 50%.

[0059] Programmable frequency divider module such as Figure 11 As shown, the division factor of the frequency divider is determined by the five input control codes. The frequency divider designed in this paper can achieve programmable division by integers from 1 to 31, enabling linear adjustment of the output frequency.

[0060] In summary, the frequency source circuit provided by this invention can achieve low jitter, low power consumption, adjustable frequency, and fast locking. In radar systems, it can serve as the clock frequency source for other modules such as chip ADC, high-speed I / O, radar transmitter, and antenna phased array unit, thereby improving the integration and signal processing capabilities of the radar system.

Claims

1. A dual-path charge pump frequency source circuit, characterized by, The phase frequency detector, the integral path charge pump, the proportional path charge pump, the loop filter module and the voltage controlled oscillator module are connected in series. The phase frequency detector is connected with the integral path charge pump and the proportional path charge pump, and is used for detecting the phase difference and the frequency difference between the input reference signal and the feedback signal. The integral path charge pump and the proportional path charge pump are connected in parallel and then connected to the loop filter module; the integral path charge pump is used for generating the integral control signal according to the phase difference and the frequency difference; and the proportional path charge pump is used for generating the proportional control signal according to the phase difference and the frequency difference. The loop filter module is connected with the voltage controlled oscillator module, and outputs the control voltage of the voltage controlled oscillator module after receiving the integral control signal of the integral path charge pump and the proportional control signal of the proportional path charge pump. The voltage controlled oscillator module is used for generating the oscillation voltage according to the control voltage output by the loop filter module.

2. The dual-path charge pump frequency source circuit of claim 1, wherein, The phase frequency detector comprises a front-stage logic module, a rear-stage logic module, a control logic module and an output signal module. The front-stage logic module is connected with the input end of the control logic module through a first node; the front-stage logic module comprises four NOR gates; the first input end of the first NOR gate is used for receiving the input reference signal, the first input ends of the last three NOR gates are sequentially connected with the output ends of the previous NOR gates, and the first input ends of the second and third NOR gates are directly connected; the second input ends of all the NOR gates are sequentially connected with the output ends of the next NOR gates, and the last NOR gate is connected with the input end of the rear-stage logic module. The rear-stage logic module is connected with the input end of the control logic module through the first node; the rear-stage logic module comprises four NOR gates; the first input end of the first NOR gate is connected with the second input end of the last NOR gate in the front-stage logic module; the first input ends of all the NOR gates are connected with the output ends of the previous NOR gates; and the second input end of the last NOR gate is used for receiving the feedback signal. The control logic module comprises a ninth NOR gate and two control components; the two input ends of the ninth NOR gate are connected with the control components respectively, and the output end is connected with the front-stage logic module and the rear-stage logic module through the first node respectively; the other input end of one control component is connected with the front-stage logic module, and the one control component outputs the upper control signal and the corresponding inverse logic signal according to the phase difference and the frequency difference of the front-stage logic module; the other input end of the other control component is connected with the rear-stage logic module, and the other control component outputs the lower control signal and the corresponding inverse logic signal according to the phase difference and the frequency difference of the rear-stage logic module. The output signal module comprises a plurality of serially connected inverter components, and is used for outputting the control signal and the corresponding inverse logic signal output by the control logic module.

3. The dual-path charge pump frequency source circuit of claim 2, wherein, The control component comprises two serially connected inverters and a transmission gate. One end of the transmission gate is connected with the input end of the ninth NOR gate and is connected to the line between the two serially connected inverters, and the other end is connected to the output signal module. The input end of the first inverter of the two serially connected inverters is used for connecting the front-stage logic module or the rear-stage logic module; and the output end of the last inverter is connected with the control component.

4. The dual-path charge pump frequency source circuit of claim 1, wherein, The integral path charge pump and the proportional path charge pump are connected in parallel through a current source module, and the current source module comprises a current source and three MOS tubes; The gates of the three MOS tubes are connected, and current source replication is completed; the sources of the three MOS tubes are connected to a power supply VDD; the drain of the first MOS tube is connected to the negative electrode of the current source; the drain of the second MOS tube is connected to the integral path charge pump; and the drain of the third MOS tube is connected to the proportional path charge pump.

5. The dual-path charge pump frequency source circuit of claim 4, wherein, The integral path charge pump and the proportional path charge pump have the same structure and comprise a bias circuit, a first switch unit, a second switch unit and a current source control module; The output end of the bias circuit of the integral path charge pump is connected to the output end of the bias circuit of the proportional path charge pump, and then connected to the current source control module of the integral path switch; the integral path switch refers to the first switch unit and the second switch unit corresponding to the integral path charge pump; The input of the first switch unit is used for accessing the upper bias end of the current source module; the input of the second switch unit accesses the lower bias end of the current source; the output end of the first switch unit is connected to the output end of the second switch unit, and outputs the integral control signal and the proportional control signal.

6. The dual-path charge pump frequency source circuit of claim 1, wherein, The loop filter module comprises an integral path filter and a proportional path filter; The integral path filter comprises a first resistor, a first capacitor and a second capacitor; the first resistor and the second capacitor are connected in series, and then connected in parallel with the first capacitor and grounded; one end of the first capacitor is also connected to the output end of the integral path charge pump; the port connected to the first resistor of the second capacitor is also connected to the input end of a voltage-controlled oscillator module; The proportional path filter comprises five MOS tubes; the gate and the drain of the first MOS tube are connected to the gate of the second MOS tube and the positive electrode of the current source; the sources of the first MOS tube and the second MOS tube are grounded; the drain of the second MOS tube and the gate and the drain of the third MOS tube are connected, and the gate of the fifth MOS tube and the output end of the proportional path charge pump are also connected; the source of the third MOS tube, the drain and the source of the fourth MOS capacitor and the source of the fifth MOS tube are connected in parallel and then connected to the power supply VDD; the drain of the fifth MOS tube serves as an output end and is connected to the input end of the voltage-controlled oscillator module.

7. The dual-path charge pump frequency source circuit of claim 1, wherein, The voltage-controlled oscillator module comprises a four-stage differential ring oscillator; the four-stage differential ring oscillator comprises four ring delay units and corresponding four buffer modules; The ring delay unit is a pseudo-differential pair unit composed of a plurality of inverters; the non-inverted output end of all the ring delay units is connected to the inverted input end of the corresponding buffer module; the inverted input end of the ring delay unit is connected to the inverted input end of the buffer module corresponding to the previous ring delay unit; the inverted input end of the first ring delay unit is connected to the inverted input end of the fourth buffer module, forming a cascaded closed loop structure; the four buffer modules respectively output one differential signal.

8. The dual-path charge pump frequency source circuit of claim 7, wherein, The buffer module is used for outputting the input reference signal as a digital signal with full swing from the power supply to the ground and a duty cycle of 50%; the input reference signal is a clock signal.

9. The dual-path charge pump frequency source circuit of claim 1, wherein, The programmable frequency divider has an input connected to an output of the voltage-controlled oscillator module and an output connected to an input of the frequency discriminator, for adjusting the output signal of the voltage-controlled oscillator module.

10. A radar system comprising a reference signal interface, a control circuit, a frequency divider module, a clock frequency source; the clock frequency source output end is connected with the frequency divider module, the input end is connected with the control circuit and the reference signal interface, and is used for receiving a frequency source control signal output by the control circuit; the frequency divider output end is used for outputting a frequency signal; the control circuit interacts with the outside through a control line and controls the clock frequency source at the same time; characterized in that, The clock frequency source uses a dual-path charge pump frequency source circuit according to any one of claims 1 to 9.

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