PCB manufacturing methods and PCB

Abstract

This application relates to the field of printed circuit board manufacturing technology, and discloses a PCB manufacturing method and a PCB. The PCB manufacturing method includes: providing a sub-board, including a first metal layer and a first dielectric layer; processing a plurality of first blind vias on the sub-board; filling the first blind vias with a first conductive material; disposing a first add-on board on the side of the first metal layer away from the first dielectric layer, the first add-on board including a first circuit layer and a first interconnect layer; processing a plurality of second blind vias on the first add-on board; filling the second blind vias with a second conductive material; and processing a crimping blind via on the side of the first circuit layer away from the first interconnect layer to remove a portion of the first add-on board, a portion of the second conductive material, a portion of the sub-board, and a portion of the first conductive material, with the remaining second conductive material and the remaining first conductive material electrically connected. The PCB manufacturing method and PCB provided in this application are used to solve the problem of difficulty in manufacturing crimping blind vias with a large thickness-to-diameter ratio in related technologies.

Description

Technical Field

[0001] This application relates to the field of printed circuit board manufacturing technology, and in particular to a method for manufacturing a PCB and the PCB itself. Background Technology

[0002] Holes on a PCB (Printed Circuit Board) are crucial structures for achieving electrical connections, mechanical fixation, and heat dissipation. Common through-holes penetrate all layers of the PCB, with metal-plated walls forming conductive channels to facilitate signal or power transmission between different layers. Blind vias, on the other hand, do not penetrate the PCB and are used only to connect specific layers, avoiding the "penetration" of through-holes into other unrelated layers. This saves internal PCB space and reduces the space occupied by blind vias in wiring, making them suitable for high-density designs. For some multi-layer, high-density PCBs, press-fit blind vias are designed as press-fit holes to achieve electrical connections and mechanical fixation between components and the PCB through mechanical pressing.

[0003] In the process of processing crimped blind holes, the drilling depth is first controlled according to the layers to be connected to make blind holes. Then, the sidewalls and bottom of the blind holes are plated with metal using an electroplating process to meet the electrical connection requirements. However, this process is limited by the ability to plate the blind holes deeply. When the thickness-to-diameter ratio of the blind hole is large (such as exceeding 1:1), problems such as inconsistent plating thickness inside the hole, hole bottom depression or voids, and thin plating thickness are likely to occur. Therefore, it is difficult to make crimped blind holes with a large thickness-to-diameter ratio. Summary of the Invention

[0004] This application provides a PCB manufacturing method and a PCB, which solves the problem of difficulty in manufacturing press-fit blind vias with large thickness-to-diameter ratios in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a PCB, comprising:

[0006] A sub-board is provided, the sub-board comprising a first metal layer and a first dielectric layer stacked together;

[0007] Multiple first blind holes are processed on the sub-board from the side of the first metal layer away from the first dielectric layer. The multiple first blind holes are distributed at intervals along a ring path and penetrate the first metal layer.

[0008] The first blind hole is filled with a first conductive material, which is connected to and electrically conductive with the first metal layer.

[0009] A first add-in plate is provided on the side of the first metal layer away from the first dielectric layer. The first add-in plate includes a first circuit layer and a first connection layer stacked together. The first connection layer is located between the first metal layer and the first circuit layer.

[0010] Multiple second blind vias are processed on the first layer on the side of the first line layer away from the first connection layer. The multiple second blind vias are distributed at intervals along the annular path. The multiple second blind vias correspond one-to-one with the multiple first blind vias. The first conductive material defines at least a portion of the bottom wall of the second blind via.

[0011] The second blind hole is filled with a second conductive material, which is connected to and electrically conductive to the first circuit layer.

[0012] A crimped blind hole is machined on the side of the first circuit layer away from the first connection layer to remove part of the first add-on board, part of the second conductive material, part of the sub-board and part of the first conductive material. The edge of the cross-section of the crimped blind hole coincides with the annular path. The remaining second conductive material and the remaining first conductive material are connected and electrically conductive.

[0013] In some embodiments, the axis of the first blind hole is located on the annular path, and the axis of the second blind hole is located on the annular path.

[0014] In some embodiments, the first blind hole and the second blind hole are coaxially arranged and have the same diameter.

[0015] In some embodiments, filling the first blind hole with a first conductive material includes: filling the first blind hole with an electroplated layer by chemical electroplating, wherein the electroplated layer is the first conductive material; or, filling the first blind hole with a conductive paste and sintering and solidifying the conductive paste to form the first conductive material.

[0016] And / or, filling the second blind hole with a second conductive material includes: filling the second blind hole with an electroplated layer, wherein the electroplated layer is the second conductive material, by means of chemical electroplating; or, filling the second blind hole with a conductive paste and sintering and solidifying the conductive paste to form the second conductive material.

[0017] In some embodiments, the sub-board further includes a second metal layer located on the side of the first dielectric layer opposite to the first metal layer, the first blind via penetrating the second metal layer or the second metal layer defining the bottom wall of the first blind via; the first conductive material is connected to and electrically conductive with the second metal layer.

[0018] In some embodiments, after filling the second blind via with a second conductive material and before forming the press-fit blind via away from the first interconnect layer from the first wiring layer, the PCB fabrication method further includes:

[0019] A second layer plate is provided on the side of the first line layer away from the first connection layer. The second layer plate includes a second line layer and a second connection layer stacked together. The second connection layer is located between the first line layer and the second line layer.

[0020] Multiple third blind vias are processed on the second layer on the side of the second circuit layer away from the second connection layer. The multiple third blind vias are distributed at intervals along the annular path. The multiple third blind vias correspond one-to-one with the multiple second blind vias. The second conductive material defines at least a portion of the bottom wall of the third blind via.

[0021] The third blind via is filled with a third conductive material, which is connected to and electrically conductive with the second circuit layer.

[0022] The process of machining a crimped blind via on the side of the first circuit layer opposite to the first connection layer includes:

[0023] The crimped blind hole is machined from the side of the second circuit layer away from the second connection layer to remove part of the second add-on board, part of the third conductive material, part of the first add-on board, part of the second conductive material, part of the sub-board and part of the first conductive material. The edge of the cross-section of the crimped blind hole coincides with the annular path. The remaining third conductive material, the remaining second conductive material and the remaining first conductive material are connected and electrically conductive.

[0024] In some embodiments, two first metal layers are provided, and the two first metal layers are located on opposite sides of the first dielectric layer.

[0025] Secondly, embodiments of this application provide a PCB, the PCB including a sub-board, the sub-board including a first metal layer and a first dielectric layer stacked together, a first add-on board disposed on the side of the first metal layer away from the first dielectric layer, the first add-on board including a first circuit layer and a first connection layer stacked together, the first connection layer being located between the first metal layer and the first circuit layer;

[0026] The sub-board is provided with a plurality of first blind holes, which are distributed at intervals along a ring path and penetrate the first metal layer; the first blind holes are filled with a first conductive material, which is connected to and electrically conductive to the first metal layer.

[0027] The first add-in plate is provided with a plurality of second blind holes, which are distributed at intervals along the annular path. The plurality of second blind holes are provided in a one-to-one correspondence with the plurality of first blind holes. The first conductive material defines at least a portion of the bottom wall of the second blind hole. The second blind hole is filled with a second conductive material, which is connected to and electrically conductive to the first circuit layer. The second conductive material is also connected to and electrically conductive to the first conductive material.

[0028] The PCB is provided with a crimped blind hole, which penetrates the first add-on board, the second conductive material, the sub-board and the first conductive material. The edge of the cross-section of the crimped blind hole coincides with the annular path. The first conductive material and the second conductive material define part of the inner wall of the crimped blind hole.

[0029] In some embodiments, the axis of the first blind hole is located on the annular path, and the axis of the second blind hole is located on the annular path.

[0030] In some embodiments, the first blind hole and the second blind hole are coaxially arranged and have the same diameter.

[0031] In some embodiments, the sub-board further includes a second metal layer located on the side of the first dielectric layer opposite to the first metal layer, the first blind via penetrating the second metal layer or the second metal layer defining the bottom wall of the first blind via; the first conductive material is connected to and electrically conductive with the second metal layer.

[0032] In some embodiments, the PCB further includes a second add-on board, the second add-on board including a second circuit layer and a second connection layer stacked together, the second connection layer being located between the first circuit layer and the second circuit layer; the second add-on board is provided with a plurality of third blind vias, the plurality of third blind vias being distributed at intervals along the annular path, the plurality of third blind vias being provided one-to-one with the plurality of second blind vias, the second conductive material defining at least a portion of the bottom wall of the third blind via; the third blind vias are filled with a third conductive material, the third conductive material being connected to and electrically conductive with the second circuit layer, the third conductive material being connected to and electrically conductive with the second conductive material; the crimping blind vias penetrate the second add-on board, the third conductive material defining a portion of the inner sidewall of the crimping blind vias.

[0033] In some embodiments, two first metal layers are provided, and the two first metal layers are located on opposite sides of the first dielectric layer.

[0034] Thirdly, embodiments of this application provide a PCB, the PCB including a first metal layer, a first interconnect layer and a first circuit layer, the first interconnect layer being located between the first metal layer and the first circuit layer; the PCB is provided with a crimp-through hole, the crimp-through hole penetrating the first circuit layer, the first interconnect layer and the first metal layer, the PCB is provided with a plurality of conductive portions, the plurality of conductive portions being spaced apart along the edge of the crimp-through hole, the conductive portions defining a portion of the inner sidewall of the crimp-through hole, the first circuit layer and the first metal layer being connected to the conductive portions and electrically conductive.

[0035] In some embodiments, the PCB is provided with a plurality of process blind vias, the plurality of process blind vias being spaced apart around the crimp blind vias, and the conductive portion being disposed one-to-one inside the process blind vias.

[0036] Fourthly, embodiments of this application provide a PCB, which is manufactured by the PCB manufacturing method described in the first aspect.

[0037] The PCB manufacturing method provided in this application has the following advantages: First, multiple first blind vias are processed on the sub-board from the side of the first metal layer away from the first dielectric layer. The multiple first blind vias are distributed at intervals along a circular path and penetrate the first metal layer. Then, a first conductive material is filled into the first blind vias. The first conductive material is connected to and electrically conductive to the first metal layer. A first add-on board is provided on the side of the first metal layer away from the first dielectric layer. The first add-on board includes a first circuit layer and a first connection layer stacked together. The first connection layer is located between the first metal layer and the first circuit layer. Then, multiple second blind vias are processed on the first add-on board from the side of the first circuit layer away from the first connection layer. Multiple second blind holes are spaced apart along an annular path, and each second blind hole corresponds to a first blind hole. A first conductive material defines at least part of the bottom wall of the second blind hole and fills the second blind hole with the second conductive material. The second conductive material is connected to and electrically conductive with the second metal layer. Therefore, a crimped blind hole can be processed from the side of the first circuit layer away from the first connection layer to remove part of the first add-on board, part of the second conductive material, part of the sub-board and part of the first conductive material. The edge of the cross-section of the crimped blind hole coincides with the annular path. The remaining second conductive material is connected to and electrically conductive with the remaining first conductive material. Therefore, it is relatively convenient to manufacture crimped blind holes with a large thickness-to-diameter ratio.

[0038] The advantages of the PCB manufacturing method provided in this application compared to the prior art can be found in the description of the advantages of the PCB provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart of a PCB manufacturing method in one embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the structure of a sub-plate having multiple first blind holes in one embodiment of this application;

[0042] Figure 3 yes Figure 2 The top view corresponding to the sub-board shown;

[0043] Figure 4 Is Figure 2 A schematic diagram showing the first blind hole of the sub-board filled with the first conductive material;

[0044] Figure 5 Is Figure 4 The diagram shows a first enhancement layer plate disposed on the side of the first metal layer of the sub-board away from the first dielectric layer, and a plurality of second blind holes are processed on the first enhancement layer plate;

[0045] Figure 6 Is Figure 5 A schematic diagram showing the second blind hole of the first add-on plate filled with a second conductive material.

[0046] Figure 7 It is by Figure 6 A crimped blind via is fabricated on the side of the first circuit layer of the first add-on board that is away from the first connection layer, in order to remove part of the first add-on board, part of the second conductive material, part of the sub-board and part of the first conductive material, to obtain a schematic diagram of the PCB structure;

[0047] Figure 8 yes Figure 7 The top view corresponding to the PCB shown;

[0048] Figure 9 This is a schematic diagram of filling the first blind hole of the sub-board with a first conductive material in another embodiment of this application;

[0049] Figure 10 Through Figure 9 A schematic diagram of the PCB structure with press-fit blind vias fabricated from the corresponding sub-board;

[0050] Figure 11 This is a schematic diagram of the PCB structure in another embodiment of this application.

[0051] The markings in the diagram mean:

[0052] 00. Circular path;

[0053] 10. Sub-board;

[0054] 11. First metal layer; 12. First dielectric layer; 13. Second metal layer; 14. Second dielectric layer;

[0055] 20. First blind hole;

[0056] 30. First conductive material;

[0057] 40. First addition layer;

[0058] 41. First Line Layer; 42. First Connection Layer;

[0059] 50. Second blind hole;

[0060] 60. Second conductive material;

[0061] 70. Crimped blind hole;

[0062] 80. Second addition layer;

[0063] 81. Second line layer; 82. Second connection layer;

[0064] 90. Third conductive material. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0066] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0068] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0069] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0070] Holes on a PCB (Printed Circuit Board) are crucial structures for achieving electrical connections, mechanical fixation, and heat dissipation. Common through-holes penetrate all layers of the PCB, with metal-plated walls forming conductive channels to facilitate signal or power transmission between different layers. Blind vias, on the other hand, do not penetrate the PCB and are used only to connect specific layers, avoiding the "penetration" of through-holes into other unrelated layers. This saves internal PCB space and reduces the space occupied by blind vias in wiring, making them suitable for high-density designs. For some multi-layer, high-density PCBs, press-fit blind vias are designed as press-fit holes to achieve electrical connections and mechanical fixation between components and the PCB through mechanical pressing.

[0071] In the process of processing crimped blind holes, the drilling depth is first controlled according to the layers to be connected to make blind holes. Then, the sidewalls and bottom of the blind holes are plated with metal using an electroplating process to meet the electrical connection requirements. However, this process is limited by the ability to plate the blind holes deeply. When the thickness-to-diameter ratio of the blind hole is large (such as exceeding 1:1), problems such as inconsistent plating thickness inside the hole, hole bottom depression or voids, and thin plating thickness are likely to occur. Therefore, it is difficult to make crimped blind holes with a large thickness-to-diameter ratio.

[0072] In view of this, this application provides a method for manufacturing a PCB and the PCB itself. The method involves first fabricating a plurality of first blind vias on a sub-board from the side of the first metal layer away from the first dielectric layer. These first blind vias are spaced apart along a circular path and penetrate the first metal layer. Then, a first conductive material is filled into each of the first blind vias. The first conductive material is connected to and electrically conductive with the first metal layer. A first add-on board is then disposed on the side of the first metal layer away from the first dielectric layer. The first add-on board includes a first circuit layer and a first connection layer stacked together, with the first connection layer located between the first metal layer and the first circuit layer. Finally, a plurality of second blind vias are fabricated on the first add-on board from the side of the first circuit layer away from the first connection layer. Multiple second blind holes are spaced apart along an annular path, and each second blind hole corresponds to a first blind hole. A first conductive material defines at least part of the bottom wall of the second blind hole and fills the second blind hole with the second conductive material. The second conductive material is connected to and electrically conductive with the second metal layer. Therefore, a crimped blind hole can be processed from the side of the first circuit layer away from the first connection layer to remove part of the first add-on board, part of the second conductive material, part of the sub-board and part of the first conductive material. The edge of the cross-section of the crimped blind hole coincides with the annular path. The remaining second conductive material is connected to and electrically conductive with the remaining first conductive material. Therefore, it is relatively convenient to manufacture crimped blind holes with a large thickness-to-diameter ratio.

[0073] Please refer to Figure 1 , Figure 2 and Figure 3 This application provides a method for manufacturing a PCB, including:

[0074] S100: A sub-board 10 is provided, the sub-board 10 including a first metal layer 11 and a first dielectric layer 12 stacked together.

[0075] The first metal layer 11 can be a copper layer, a silver layer, or an aluminum layer, etc. One or more first metal layers 11 may be provided. The first dielectric layer 12 can be formed by pressing and curing a prepreg, and may include resin and fiberglass cloth.

[0076] S200: Multiple first blind holes 20 are processed on the sub-board 10 from the side of the first metal layer 11 away from the first dielectric layer 12. The multiple first blind holes 20 are distributed at intervals along the annular path 00 and the first blind holes 20 penetrate the first metal layer 11.

[0077] The first blind hole 20 can be machined using mechanical drilling or laser drilling. Figure 2 In the embodiment shown, the first blind hole 20 penetrates the first metal layer 11.

[0078] It should be noted that the multiple first blind holes 20 are distributed at intervals along the annular path 00, which means that the projections of the multiple first blind holes 20 on the surface of the sub-plate 10 all intersect with the annular path 00.

[0079] S300: Please refer to this as well. Figure 4 The first blind hole 20 is filled with a first conductive material 30, which is connected to and electrically conductive with the first metal layer 11.

[0080] The first conductive material 30 can be made of copper, silver, or aluminum, and the material of the first conductive material 30 can be the same as that of the first metal layer 11, such as both being copper.

[0081] A first conductive material 30 can be used to fill the first blind hole 20 with an electroplated layer by means of chemical electroplating.

[0082] For example, VCP (Vertical Continuous Plating) electroplating can be used to fill the first blind hole 20 with an electroplated layer.

[0083] Alternatively, conductive paste is filled into the first blind hole 20 and sintered and solidified to form the first conductive material 30.

[0084] S400: Please refer to this as well. Figure 5 A first enhancement plate 40 is provided on the side of the first metal layer 11 away from the first dielectric layer 12. The first enhancement plate 40 includes a first circuit layer 41 and a first connection layer 42 stacked together. The first connection layer 42 is located between the first metal layer 11 and the first circuit layer 41.

[0085] The first circuit layer 41 can be a copper layer, a silver layer, or an aluminum layer, etc. One or more first circuit layers 41 can be provided. The first connecting layer 42 can be formed by pressing and curing a prepreg, and it may include resin and fiberglass cloth.

[0086] The first extension plate 40 and the sub-plate 10 can be pressed together. During the pressing process, the first connecting layer 42 (prepreg) bonds the sub-plate 10 and the first circuit layer 41 into one piece.

[0087] It should be noted that the first circuit layer 41 can be copper foil. Depending on the different stack-up structure design of the PCB product, in other embodiments, the first add-on board 40 can also be a prepreg and other substrates, such as a single-sided copper-clad substrate, a double-sided copper-clad substrate, or a multilayer substrate.

[0088] S500: A plurality of second blind holes 50 are processed on the first layer plate 40 from the side of the first line layer 41 away from the first connection layer 42. The plurality of second blind holes 50 are distributed at intervals along the annular path 00. The plurality of second blind holes 50 are provided in a one-to-one correspondence with the plurality of first blind holes 20. The first conductive material 30 defines at least part of the bottom wall of the second blind hole 50.

[0089] The second blind hole 50 can be manufactured by mechanical drilling or laser drilling. The projections of the first blind hole 20 and the second blind hole 50 in the direction perpendicular to the thickness of the sub-plate 10 at least partially intersect.

[0090] S600: Please refer to this as well. Figure 6 The second blind hole 50 is filled with a second conductive material 60, which is connected to and electrically conductive with the first circuit layer 41.

[0091] The second conductive material 60 can be made of copper, silver, or aluminum, and the material of the second conductive material 60 can be the same as that of the first circuit layer 41, such as both being copper.

[0092] A chemical electroplating method can be used to fill the second blind hole 50 with an electroplated layer, which is a second conductive material 60.

[0093] For example, VCP electroplating can be used to fill the second blind hole 50 with an electroplated layer.

[0094] Alternatively, conductive paste is filled into the second blind hole 50 and sintered and cured to form the second conductive material 60.

[0095] S700: Please refer to this as well. Figure 7 and Figure 8 A crimping blind hole 70 is formed on the side of the first circuit layer 41 away from the first connection layer 42 to remove part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30. The edge of the cross-section of the crimping blind hole 70 coincides with the annular path 00. The remaining second conductive material 60 and the remaining first conductive material 30 are connected and electrically conductive.

[0096] Among them, the crimped blind hole 70 can be processed by mechanical drilling or laser drilling or a combination of both.

[0097] A crimped blind via 70 is fabricated on the side of the first circuit layer 41 away from the first connection layer 42. After removing part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10, and part of the first conductive material 30, the remaining first conductive material 30 and the remaining second conductive material 60 are exposed on the inner wall of the crimped blind via 70, which serve as the conductive layer of the crimped blind via 70. The first circuit layer 41 and the first metal layer 11 are electrically connected through the remaining second conductive material 60 and the remaining first conductive material 30, thereby achieving electrical connection with the inner / outer layer circuits of the PCB. There is no need to perform a hole metallization process on the crimped blind via 70 again. When the component pin is crimped into the crimped blind via 70, electrical connection can be achieved by directly contacting the second conductive material 60 and the first conductive material 30 on the inner wall of the crimped blind via 70. Therefore, crimped blind vias with a large thickness-to-diameter ratio can be fabricated.

[0098] It is understandable that the remaining second conductive material 60 and the remaining first conductive material 30 are spaced apart and discontinuous.

[0099] As an implementable method, the PCB provided in this application embodiment includes a sub-board 10, the sub-board 10 includes a first metal layer 11 and a first dielectric layer 12 stacked together, a first enhancement board 40 is provided on the side of the first metal layer 11 away from the first dielectric layer 12, the first enhancement board 40 includes a first circuit layer 41 and a first connection layer 42 stacked together, the first connection layer 42 is located between the first metal layer 11 and the first circuit layer 41.

[0100] The sub-board 10 is provided with a plurality of first blind holes 20, which are distributed at intervals along the annular path 00. The first blind holes 20 penetrate the first metal layer 11. The first blind holes 20 are filled with a first conductive material 30, which is connected to and electrically conductive to the first metal layer 11.

[0101] The first add-on plate 40 is provided with a plurality of second blind holes 50, which are distributed at intervals along the annular path 00. The plurality of second blind holes 50 are provided in a one-to-one correspondence with the plurality of first blind holes 20. The first conductive material 30 defines at least a portion of the bottom wall of the second blind hole 50. The second blind hole 50 is filled with a second conductive material 60, which is connected to and electrically conductive to the first circuit layer 41. The second conductive material 60 is connected to and electrically conductive to the first conductive material 30.

[0102] The PCB is provided with a crimping blind hole 70, which penetrates the first add-on board 40, the second conductive material 60, the sub-board 10 and the first conductive material 30. The edge of the cross-section of the crimping blind hole 70 coincides with the annular path 00. The first conductive material 30 and the second conductive material 60 define part of the inner wall of the crimping blind hole 70.

[0103] The PCB and its manufacturing method provided in this application embodiment firstly fabricate multiple first blind vias 20 on a sub-board 10 from the side of the first metal layer 11 away from the first dielectric layer 12. These first blind vias 20 are spaced apart along a ring path 00 and penetrate the first metal layer 11. Then, a first conductive material 30 is filled into each of the first blind vias 20, and the first conductive material 30 is connected to and electrically conductive with the first metal layer 11. A first add-on board 40 is then disposed on the side of the first metal layer 11 away from the first dielectric layer 12. The first add-on board 40 includes a first circuit layer 41 and a first connection layer 42 stacked together, with the first connection layer 42 located between the first metal layer 11 and the first circuit layer 41. Finally, multiple second blind vias 5 are fabricated on the first add-on board 40 from the side of the first circuit layer 41 away from the first connection layer 42. Multiple second blind holes 50 are distributed at intervals along the annular path 00. The multiple second blind holes 50 are arranged one-to-one with the multiple first blind holes 20. The first conductive material 30 defines at least part of the bottom wall of the second blind hole 50 and fills the second blind hole 50 with the second conductive material 60. The second conductive material 60 is connected to the second metal layer 13 and is electrically conductive. Therefore, the crimping blind hole 70 can be processed from the side of the first circuit layer 41 away from the first connecting layer 42 to remove part of the first add-on plate 40, part of the second conductive material 60, part of the sub-plate 10 and part of the first conductive material 30. The edge of the cross-section of the crimping blind hole 70 coincides with the annular path 00. The remaining second conductive material 60 and the remaining first conductive material 30 are connected and electrically conductive. Therefore, it is relatively convenient to manufacture the crimping blind hole 70 with a large thickness-diameter ratio.

[0104] Please refer to Figure 7 and Figure 8 As an implementable method, the PCB provided in this application embodiment includes a first metal layer 11, a first connection layer 42, and a first circuit layer 41. The first connection layer 42 is located between the first metal layer 11 and the first circuit layer 41. The PCB is provided with a crimping blind hole 70, which penetrates the first circuit layer 41, the first connection layer 42, and the first metal layer 11. The PCB is provided with a plurality of conductive parts, which are spaced apart along the edge of the crimping blind hole 70. The conductive parts define a portion of the inner sidewall of the crimping blind hole 70. The first circuit layer 41 and the first metal layer 11 are both connected to the conductive parts and are electrically conductive.

[0105] This setup makes it relatively easy to manufacture crimped blind holes 70 with a large thickness-to-diameter ratio.

[0106] It is understood that the conductive part may include a portion of the second conductive material 60 and a portion of the first conductive material 30.

[0107] Optionally, the PCB is provided with multiple process blind vias, which are spaced apart around the crimping blind vias 70, and the conductive parts are arranged one-to-one inside the process blind vias.

[0108] This setup makes it relatively easy to manufacture crimped blind holes 70 with a large thickness-to-diameter ratio.

[0109] It is understood that the process blind via may include a portion of the first blind via 20 and a portion of the second blind via 50.

[0110] Please refer to Figures 2 to 8 In some embodiments, the axis of the first blind hole 20 is located on the annular path 00, and the axis of the second blind hole 50 is located on the annular path 00.

[0111] By adopting the above scheme, a crimping blind hole 70 can be processed on the side of the first circuit layer 41 away from the first connection layer 42. After removing part of the first add-on board 40, part of the second conductive material 60, part of the daughter board 10 and part of the first conductive material 30, the area of ​​the first conductive material 30 exposed on the side after the first blind hole 20 is cut is maximized, and the area of ​​the second conductive material 60 exposed on the side after the second blind hole 50 is cut is maximized. Thus, after the component pins and the crimping blind hole 70 are crimped, the conductivity between the remaining second conductive material 60 and the remaining first conductive material 30 and the component pins can be improved.

[0112] Optionally, the first blind hole 20 and the second blind hole 50 are coaxially arranged and have the same diameter.

[0113] With this configuration, a crimping blind hole 70 can be processed on the side of the first circuit layer 41 away from the first connection layer 42. After removing part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30, the remaining second conductive material 60 and the remaining first conductive material 30 have a larger connection area and better conductivity.

[0114] Optionally, the diameter of the first blind hole 20 is 4mil-7mil, such as 4mil, 5mil, 6mil or 7mil, and the spacing between two adjacent first blind holes 20 is 6mil-12mil, such as 6mil, 8mil, 9mil or 12mil.

[0115] This configuration ensures that when the first blind hole 20 is filled with the first conductive material 30, the first blind hole 20 can be fully filled by the first conductive material 30, improving the filling quality. At the same time, a crimping blind hole 70 can be processed on the side of the first circuit layer 41 away from the first connection layer 42 to remove part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30, ensuring the conductivity between the remaining first conductive material 30 and the component pins.

[0116] It is understandable that the diameter of the second blind hole 50 is 4mil-7mil, such as 4mil, 5mil, 6mil or 7mil, and the distance between two adjacent second blind holes 50 is 6mil-12mil, such as 6mil, 8mil, 9mil or 12mil.

[0117] This configuration ensures that when the second blind hole 50 is filled with the second conductive material 60, the second blind hole 50 can be fully filled by the second conductive material 60, improving the filling quality. At the same time, a crimping blind hole 70 can be processed on the side of the first circuit layer 41 away from the first connection layer 42 to remove part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30, ensuring the conductivity between the remaining second conductive material 60 and the component pins.

[0118] Please refer to Figures 2 to 4 In some embodiments, the first blind hole 20 is filled with a first conductive material 30, including:

[0119] The first blind hole 20 is filled with an electroplated layer by chemical electroplating, and the first electroplated layer is a first conductive material 30.

[0120] Alternatively, conductive paste is filled into the first blind hole 20 and sintered and solidified to form the first conductive material 30.

[0121] By adopting the above scheme, the first conductive material 30 can be filled into the first blind hole 20 relatively easily.

[0122] Please refer to Figure 5 and Figure 6 In some embodiments, the second blind hole 50 is filled with a second conductive material 60, including:

[0123] The second blind hole 50 is filled with an electroplating layer using chemical electroplating, and the electroplating layer is a second conductive material 60.

[0124] Alternatively, conductive paste is filled into the second blind hole 50 and sintered and cured to form the second conductive material 60.

[0125] By adopting the above scheme, the second conductive material 60 can be filled into the second blind hole 50 relatively easily.

[0126] Please refer to Figures 2 to 4 In some embodiments, the sub-board 10 further includes a second metal layer 13 located on the side of the first dielectric layer 12 away from the first metal layer 11, and a first blind via 20 penetrating the second metal layer 13 or the second metal layer 13 defining the bottom wall of the first blind via 20; the first conductive material 30 is connected to the second metal layer 13 and is electrically conductive.

[0127] By adopting the above scheme, a crimping blind hole 70 can be processed on the side of the first circuit layer 41 away from the first connection layer 42. After removing part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30, the first circuit layer 41, the first metal layer 11 and the second metal layer 13 are electrically connected through the remaining second conductive material 60 and the remaining first conductive material 30.

[0128] It should be noted that the second metal layer 13 can be a copper layer, a silver layer, or an aluminum layer, etc. The material of the second metal layer 13 can be the same as that of the first metal layer 11, such as both being copper. Multiple second metal layers 13 can be provided, and a second dielectric layer 14 is provided between two adjacent metal layers. The second dielectric layer 14 can be formed by pressing and curing a prepreg, and it can include resin and fiberglass cloth.

[0129] For example, the sub-board 10 can be formed by laminating a stack of copper foil, prepreg, copper-clad laminate, and prepreg copper foil arranged in sequence. Alternatively, the sub-board 10 can be formed directly by laminating two or more double-sided copper-clad laminates and a prepreg sandwiched between them, without specific limitations. It is understood that the copper layers located in the inner layers of the sub-board 10 have already been fabricated before lamination.

[0130] It should also be noted that in other embodiments, the first blind via 20 may only penetrate the first metal layer 11 but not the first dielectric layer 12, that is, the first conductive material 30 is not connected to the second metal layer 13. Whether the first conductive material 30 is connected to the second metal layer 13 depends on the specific number of circuit layers that the press-fit blind via 70 needs to be connected, which is related to the specific PCB design and is not intended to limit the embodiments of this application.

[0131] Please refer to Figure 9 In another embodiment, two first metal layers 11 are provided, and the two first metal layers 11 are located on opposite sides of the first dielectric layer 12.

[0132] By adopting the above scheme, first extension plates 40 can be provided on both sides of the two first metal layers 11 and crimping blind holes 70 can be processed.

[0133] For example, the sub-board 10 may be a double-sided copper-clad substrate, wherein the substrate in the middle is a first dielectric layer 12, and the copper layers covering both sides of the substrate are first metal layers 11.

[0134] It should be noted that in other embodiments, the sub-board 10 may also be a multilayer substrate formed by at least one lamination, that is, having three or more copper layers (first metal layer 11), and the first blind via 20 penetrates at least one copper layer and part or all of the substrate layer of the sub-board 10.

[0135] Please refer to Figure 10 and Figure 11 In yet another embodiment, after the second conductive material 60 is filled into the second blind via 50, and before the press-fit blind via 70 is formed on the side of the first circuit layer 41 away from the first interconnect layer 42, the PCB fabrication method further includes:

[0136] First, a second layer 80 is provided on the side of the first line layer 41 away from the first connection layer 42. The second layer 80 includes a second line layer 81 and a second connection layer 82 stacked together, with the second connection layer 82 located between the first line layer 41 and the second line layer 81.

[0137] The second circuit layer 81 can be a copper layer, a silver layer, or an aluminum layer, etc. One or more second circuit layers 81 can be provided. The second connecting layer 82 can be formed by pressing and curing a prepreg, and it may include resin and fiberglass cloth.

[0138] It should be noted that the second circuit layer 81 can be copper foil. Depending on the different stack-up structure design of the PCB product, in other embodiments, the second add-on board 80 can also be a prepreg or other substrates, such as a single-sided copper-clad substrate, a double-sided copper-clad substrate, or a multilayer substrate.

[0139] Secondly, a plurality of third blind holes are processed on the second layer plate 80 from the side of the second circuit layer 81 away from the second connection layer 82. The plurality of third blind holes are distributed at intervals along the annular path 00. The plurality of third blind holes are arranged in a one-to-one correspondence with the plurality of second blind holes 50. The second conductive material 60 defines at least part of the bottom wall of the third blind holes.

[0140] The third blind hole can be produced by mechanical drilling or laser drilling.

[0141] It should be noted that the axis of the third blind hole can be located on the annular path 00, and the first blind hole 20 and the third blind hole are coaxially arranged and have the same diameter. Other blind holes can also be designed on the sub-plate 10, the first extension plate 40, and the second extension plate 80. The first blind hole 20, the second blind hole 50, and the third blind hole can be fabricated at the same time as drilling other blind holes. That is, the first blind hole 20, the second blind hole 50, and the third blind hole are drilled and metallized together with the other designed blind holes without additional processing steps, thereby improving production efficiency and saving costs. Of course, in another embodiment, they can also be fabricated separately.

[0142] Next, a third conductive material 90 is filled into the third blind hole, and the third conductive material 90 is connected to and electrically conductive with the second circuit layer 81.

[0143] The material of the third conductive material 90 can be copper, silver or aluminum, etc., and the material of the third conductive material 90 can be the same as that of the first circuit layer 41, such as copper.

[0144] A third conductive material 90 can be used to fill the third blind hole with an electroplating layer by means of chemical electroplating.

[0145] For example, VCP electroplating can be used to fill the third blind hole with an electroplated layer.

[0146] Alternatively, a conductive paste is filled into the third blind hole, and the conductive paste is sintered and solidified to form a third conductive material 90.

[0147] As one possible implementation, a crimped blind via 70 is formed on the side of the first circuit layer 41 opposite to the first connection layer 42, including:

[0148] A crimping blind hole 70 is machined on the side of the second circuit layer 81 away from the second connection layer 82 to remove part of the second add-on board 80, part of the third conductive material 90, part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30. The edge of the cross-section of the crimping blind hole 70 coincides with the annular path 00. The remaining third conductive material 90, the remaining second conductive material 60 and the remaining first conductive material 30 are connected and electrically conductive.

[0149] As an implementable embodiment, the PCB provided in this application also includes a second add-on board 80. The second add-on board 80 includes a second circuit layer 81 and a second connection layer 82 stacked together. The second connection layer 82 is located between the first circuit layer 41 and the second circuit layer 81. The second add-on board 80 is provided with a plurality of third blind vias, which are distributed at intervals along an annular path 00. The plurality of third blind vias correspond one-to-one with a plurality of second blind vias 50. A second conductive material 60 defines at least a portion of the bottom wall of the third blind via. The third blind via is filled with a third conductive material 90, which is connected to and electrically conductive with the second circuit layer 81 and with the second conductive material 60. A crimped blind via 70 penetrates the second add-on board 80, and the third conductive material 90 defines a portion of the inner sidewall of the crimped blind via 70.

[0150] By adopting the above solution, it is possible to manufacture crimped blind vias 70 with a larger aspect ratio, and at the same time, to produce PCBs with more layers.

[0151] It is understandable that different depths of crimped blind holes 70 can be manufactured by adjusting the number of stacked add-on plates, and different depths of crimped blind holes 70 can also be manufactured by adjusting the depth of the blind holes processed on a single add-on plate. However, when using electroplating to fill the blind holes processed on the add-on plate with conductive material, the thickness-to-diameter ratio of the blind holes processed on the add-on plate should not exceed the conventional processing capacity. If it exceeds 1:1, it will easily affect the filling quality of the corresponding blind holes.

[0152] It should be noted that a first add-on board 40 and a second add-on board 80 can be provided on both sides of the two first metal layers 11, and crimping blind holes 70 can be machined. The crimping blind holes 70 are machined on the side of the second circuit layer 81 away from the second connection layer 82. After removing part of the second add-on board 80, part of the third conductive material 90, part of the first add-on board 40, part of the second conductive material 60, part of the sub-board 10 and part of the first conductive material 30, other processing steps such as outer layer circuits, solder mask, surface treatment and molding can be completed to complete other processes of PCB manufacturing.

[0153] This application also provides a PCB, which is manufactured by the PCB manufacturing method described above.

[0154] The PCB provided in this application embodiment is manufactured by first fabricating multiple first blind vias 20 on the sub-board 10 from the side of the first metal layer 11 away from the first dielectric layer 12. These first blind vias 20 are spaced apart along a ring path 00 and penetrate the first metal layer 11. Then, a first conductive material 30 is filled into each of the first blind vias 20, and the first conductive material 30 is connected to and electrically conductive with the first metal layer 11. A first add-on board 40 is disposed on the side of the first metal layer 11 away from the first dielectric layer 12. The first add-on board 40 includes a first circuit layer 41 and a first connection layer 42 stacked together, with the first connection layer 42 located between the first metal layer 11 and the first circuit layer 41. Finally, multiple second blind vias 50 are fabricated on the first add-on board 40 from the side of the first circuit layer 41 away from the first connection layer 42. Multiple second blind holes 50 are distributed at intervals along the annular path 00. Each of the multiple second blind holes 50 corresponds to a multiple of the first blind holes 20. The first conductive material 30 defines at least part of the bottom wall of the second blind hole 50 and fills the second blind hole 50 with the second conductive material 60. The second conductive material 60 is connected to and electrically conductive with the second metal layer 13. Therefore, the crimping blind hole 70 can be processed from the side of the first circuit layer 41 away from the first connecting layer 42 to remove part of the first add-on plate 40, part of the second conductive material 60, part of the sub-plate 10 and part of the first conductive material 30. The edge of the cross-section of the crimping blind hole 70 coincides with the annular path 00. The remaining second conductive material 60 and the remaining first conductive material 30 are connected and electrically conductive. Therefore, it is relatively convenient to manufacture the crimping blind hole 70 with a large thickness-to-diameter ratio.

[0155] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of manufacturing a PCB, characterized by, The application relates to a PCB manufacturing method, which comprises the following steps: providing a subboard, wherein the subboard comprises a first metal layer and a first dielectric layer which are arranged in a stack mode; processing a plurality of first blind holes on the subboard from one side of the first metal layer away from the first dielectric layer, wherein the first blind holes are distributed along a ring path at intervals, and the first blind holes penetrate the first metal layer; filling a first conductive material in the first blind holes, wherein the first conductive material is connected with the first metal layer and electrically conductive; arranging a first build-up plate on the side of the first metal layer away from the first dielectric layer, wherein the first build-up plate comprises a first circuit layer and a first connecting layer which are arranged in a stack mode, and the first connecting layer is arranged between the first metal layer and the first circuit layer; processing a plurality of second blind holes on the first build-up plate from one side of the first circuit layer away from the first connecting layer, wherein the second blind holes are distributed along the ring path at intervals, the second blind holes are arranged one by one corresponding to the first blind holes, and the first conductive material defines at least part of the bottom wall of the second blind holes; filling a second conductive material in the second blind holes, wherein the second conductive material is connected with the first circuit layer and electrically conductive; processing a press-fit blind hole from one side of the first circuit layer away from the first connecting layer, so as to remove part of the first build-up plate, part of the second conductive material, part of the subboard and part of the first conductive material, the edge of the cross section of the press-fit blind hole coincides with the ring path, and the remaining second conductive material and the remaining first conductive material are connected and electrically conductive.

2. The method of claim 1, wherein The axis of the first blind hole is located on the ring path, and the axis of the second blind hole is located on the ring path.

3. The method of claim 2, wherein the step of applying the solder paste to the PCB comprises applying the solder paste to the PCB using a stencil printer. The first blind hole and the second blind hole are coaxially arranged and have equal diameters.

4. The method of claim 1, wherein The step of filling the first conductive material in the first blind hole comprises the following steps: filling an electroplated layer in the first blind hole by using chemical electroplating, the electroplated layer is the first conductive material; or filling conductive paste in the first blind hole, and sintering and solidifying the conductive paste to form the first conductive material. The step of filling the second conductive material in the second blind hole comprises the following steps: filling an electroplated layer in the second blind hole by using chemical electroplating, the electroplated layer is the second conductive material; or filling conductive paste in the second blind hole, and sintering and solidifying the conductive paste to form the second conductive material.

5. The method of claim 1, wherein The subboard further comprises a second metal layer which is located on the side of the first dielectric layer away from the first metal layer, and the first blind hole penetrates the second metal layer or the second metal layer defines the bottom wall of the first blind hole. The first conductive material is connected with the second metal layer and electrically conductive.

6. The method of manufacturing a PCB according to any one of claims 1 to 5, wherein After the step of filling the second conductive material in the second blind hole and before the step of processing the press-fit blind hole from one side of the first circuit layer away from the first connecting layer, the PCB manufacturing method further comprises the following steps: A second build-up plate is arranged on a side of the first circuit layer away from the first connection layer, the second build-up plate comprising a second circuit layer and a second connection layer arranged in a stack, the second connection layer being located between the first circuit layer and the second circuit layer; A plurality of third blind holes are processed on the second build-up plate from a side of the second circuit layer away from the second connection layer, the plurality of third blind holes being distributed along the annular path, the plurality of third blind holes being arranged in one-to-one correspondence with the plurality of second blind holes, the second conductive material defining at least part of a bottom wall of the third blind hole; A third conductive material is filled in the third blind hole, the third conductive material being connected to and electrically connected to the second circuit layer; The crimping blind hole is processed from the side of the first circuit layer away from the first connection layer, comprising: The crimping blind hole is processed from the side of the second circuit layer away from the second connection layer, so as to remove part of the second build-up plate, part of the third conductive material, part of the first build-up plate, part of the second conductive material, part of the sub-plate and part of the first conductive material, an edge of a cross section of the crimping blind hole coincides with the annular path, and the remaining third conductive material, the remaining second conductive material and the remaining first conductive material are connected and electrically connected.

7. The method of manufacturing a PCB according to any one of claims 1 to 5, wherein The first metal layer is provided in two, and the two first metal layers are respectively located on opposite sides of the first dielectric layer.

8. A PCB, characterized by The PCB comprises a sub-plate, the sub-plate comprising a first metal layer and a first dielectric layer arranged in a stack, a first build-up plate being arranged on a side of the first metal layer away from the first dielectric layer, the first build-up plate comprising a first circuit layer and a first connection layer arranged in a stack, the first connection layer being located between the first metal layer and the first circuit layer; The sub-plate is provided with a plurality of first blind holes, the plurality of first blind holes being distributed along an annular path, the first blind holes penetrating the first metal layer; the first blind holes are filled with a first conductive material, the first conductive material being connected to and electrically connected to the first metal layer; The first build-up plate is provided with a plurality of second blind holes, the plurality of second blind holes being distributed along the annular path, the plurality of second blind holes being arranged in one-to-one correspondence with the plurality of first blind holes, the first conductive material defining at least part of a bottom wall of the second blind hole; the second blind hole is filled with a second conductive material, the second conductive material being connected to and electrically connected to the first circuit layer, the second conductive material and the first conductive material being connected and electrically connected; The PCB is provided with a crimping blind hole, the crimping blind hole penetrating the first build-up plate, the second conductive material, the sub-plate and the first conductive material, an edge of a cross section of the crimping blind hole coincides with the annular path, the first conductive material and the second conductive material defining part of an inner wall of the crimping blind hole.

9. The PCB of claim 8, wherein, The axis of the first blind hole is located on the annular path, and the axis of the second blind hole is located on the annular path.

10. The PCB of claim 9, wherein, The first blind hole and the second blind hole are coaxially arranged and have equal diameters.

11. The PCB of claim 8, wherein, The sub-board further comprises a second metal layer located on a side of the first dielectric layer away from the first metal layer, the first blind hole penetrating through the second metal layer or the second metal layer defining a bottom wall of the first blind hole; The first conductive material is connected with and in electrical conduction with the second metal layer.

12. The PCB of any one of claims 8 to 11, wherein, The PCB further comprises a second build-up board comprising a second circuit layer and a second connection layer stacked, the second connection layer being located between the first circuit layer and the second circuit layer; the second build-up board is provided with a plurality of third blind holes, the plurality of third blind holes being spaced apart along the annular path, the plurality of third blind holes being provided in one-to-one correspondence with the plurality of second blind holes, the second conductive material defining at least part of a bottom wall of the third blind hole; the third blind hole is filled with a third conductive material, the third conductive material being connected with and in electrical conduction with the second circuit layer, the third conductive material being connected with and in electrical conduction with the second conductive material; the crimp blind hole penetrates through the second build-up board, the third conductive material defining part of an inner wall of the crimp blind hole.

13. The PCB of any one of claims 8-11, wherein, The first metal layer is provided in two, and the two first metal layers are respectively located on two opposite sides of the first dielectric layer.

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