Method for improving morphology of semiconductor device

Abstract

The invention provides a method for improving the morphology of a semiconductor device, and solves the technical problem that the morphology of a mandrel is not good due to an etching load effect when an NAND flash memory is manufactured by adopting a self-aligned double pattern technology in the prior art. The method provided by the invention comprises the step of forming a graphical mandrel on a laminated structure comprising a core layer and a mandrel layer by adopting a photoetching process. The key point is that a photomask in a transparent mode is adopted in the photoetching process. And then, forming a side wall spacer on the side wall of the patterned core shaft, removing the core shaft, and etching the core layer by taking the side wall spacer as a mask. By adopting the transparent mode photomask, the etching load effect between the storage array region and the peripheral circuit region is effectively relieved, so that the mandrel with sharp outline and no top damage is obtained, and the uniformity and integrity of the side wall spacer and the final core layer pattern are further ensured. The size precision, the product yield and the reliability of the device structure can be remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the morphology of semiconductor devices. Background Technology

[0002] As semiconductor process nodes continue to evolve, device feature sizes are shrinking to below the resolution limits of photolithography. To manufacture higher-density memory devices, such as NAND flash memory, self-aligned dual patterning (SADP), also known as sidewall image transfer, has become a key process solution.

[0003] A typical SADP process flow includes the following steps: First, a target layer (e.g., an amorphous silicon layer for forming conductive structures) and a mandrel layer (e.g., silicon oxide) are sequentially deposited on the substrate to be processed. Next, the mandrel layer is patterned using photolithography and etching processes to form a series of temporary structures called mandrels. Then, a spacer material is conformally deposited on the surface of the patterned mandrel (including the top and sidewalls). Subsequently, the horizontal portion of the spacer material is removed by anisotropic etching (e.g., dry etch-back), leaving only structures called sidewall spacers on the sidewalls of the mandrel. Afterward, the mandrel is removed by selective etching, and the remaining sidewall spacers form a mask pattern with a spacing half that of the original photolithographic pattern. Finally, based on this sidewall spacer mask, the underlying target layer is etched to form the final device structure (e.g., word lines of NAND flash memory) with smaller feature sizes and higher density.

[0004] In this complex process chain, topography control at each step is crucial. In particular, the profile quality of the initially formed mandrel directly determines the shape and uniformity of the subsequent sidewall spacers, and ultimately affects the dimensional accuracy and electrical performance of the finally etched device structure.

[0005] However, in NAND flash memory chips, there is a significant difference in pattern density between the high-density memory array and the low-density peripheral circuitry. In traditional processes, the photolithography step for patterning the core layer typically uses a dark mode or dark tone mask. In this mode, most of the mask is made of opaque material (such as chromium), with light-transmitting areas only designed where the core pattern needs to be formed. When using this type of mask and positive photoresist, the resulting photoresist pattern after photolithography and development is a sparse, linear structure. During subsequent etching of the core layer, most of the core layer material is exposed and etched away. This large-area etching requirement can cause severe etching load effects between different regions with vastly different pattern densities (memory array and peripheral circuitry). This loading effect makes it difficult to control the morphology of the mandrel in high-density memory arrays. For example, its top is prone to damage due to uneven ion bombardment, and the taper of the sidewalls also deteriorates. This suboptimal mandrel morphology leads to uneven thickness and poor shape of the sidewall spacers formed on its sidewalls, which in turn causes dimensional deviations, or even open circuits or short circuits, in the word line structure etched using this as a mask, severely damaging the chip's yield and reliability.

[0006] Therefore, overcoming the load effect caused by pattern density differences in SADP process, improving the initial morphology of the mandrel from the source, and thus ensuring the accuracy of the final device structure is an important challenge facing the field of advanced semiconductor manufacturing. Summary of the Invention

[0007] The technical problem to be solved by this invention is to provide a method for improving the morphology of semiconductor devices. This method addresses the issue that in the prior art, when using self-aligned double patterning (SADP) technology to manufacture NAND flash memory, the use of a conventional dark-field mode photomask to pattern the core layer results in a significant etching load effect between the high-density memory array area and the low-density peripheral circuit area. This leads to poor core morphology, top damage, poor sidewall steepness, and ultimately affects the dimensional accuracy, electrical performance, and manufacturing yield of the final device structure (such as word lines).

[0008] To achieve the above and other related objectives, the present invention provides a method for improving the morphology of a semiconductor device, applied to the fabrication of NAND flash memory on a semiconductor substrate including a memory array region and a peripheral circuit region, characterized in that it includes at least:

[0009] Step 1: Provide a stacked structure to be patterned on the semiconductor substrate, wherein the stacked structure to be patterned includes a core layer and a core layer from bottom to top;

[0010] Step 2: Form a photoresist layer on the mandrel layer;

[0011] Step 3: Expose and develop the photoresist layer using photolithography to form a patterned photoresist mask, wherein the photolithography process uses a transparent photomask.

[0012] Step 4: Using the patterned photoresist mask as a mask, etch the core layer to form a patterned core;

[0013] Step 5: Form sidewall spacers on the sidewalls of the patterned mandrel;

[0014] Step 6: Remove the graphical mandrel;

[0015] Step 7: Using the sidewall spacers as a mask, etch the core layer.

[0016] Preferably, the layout of the light-transmitting areas of the photomask corresponds to the space between the patterned mandrels, while the layout of the opaque areas of the photomask corresponds to a predetermined pattern of the patterned mandrels.

[0017] Preferably, by using the transparent mode photomask in step three, the total area of ​​the opaque region of the photomask during photolithography is increased, thereby reducing the etching load effect caused by the difference in pattern density between the memory array region and the peripheral circuit region when etching the core layer in step four.

[0018] Preferably, the reduction of the etching load effect improves the morphology of the patterned mandrel, enabling the sidewall spacers to be formed more uniformly on the sidewalls of the patterned mandrel in step five.

[0019] Preferably, in step one, the core layer is an amorphous silicon layer.

[0020] Preferably, in step one, the core layer is an amorphous silicon layer.

[0021] Preferably, in step one, the core layer is a silicon oxide layer.

[0022] Preferably, the core layer is a silicon oxide layer deposited using tetraethoxysilane as a precursor.

[0023] Preferably, in step five, the material of the sidewall spacer is silicon nitride or silicon carbide.

[0024] Preferably, in step six, the step of removing the patterned mandrel includes selective wet etching of the patterned mandrel.

[0025] As described above, the method for improving the morphology of semiconductor devices according to the present invention has the following beneficial effects:

[0026] This invention replaces the traditional dark-mode photomask used for mandrel patterning with a transparent-mode photomask. This method ensures that the exposed area of ​​the etched material tends to be consistent across different pattern density regions (memory array region and peripheral circuit region) during the mandrel layer etching step, thereby significantly balancing the etching load. This fundamentally avoids differences in ion bombardment caused by uneven load effects, resulting in mandrel patterns with sharp top contours, minimal top damage, and steep sidewalls. Attached Figure Description

[0027] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0028] Figure 2 The diagram shows a mandrel pattern formed after etching the mandrel layer using existing technology (e.g., using a dark field mode photomask);

[0029] Figure 3 The image shown is a schematic diagram of a mandrel graphic electron microscope image, representing the prior art.

[0030] Figure 4 The diagram shows a mandrel pattern formed after etching the mandrel layer according to the present invention.

[0031] Figure 5 The image shown is a schematic diagram of a pattern electron microscope image of the mandrel of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] This invention provides a method for improving the morphology of semiconductor devices, applied to the fabrication of NAND flash memory on a semiconductor substrate 101 containing a memory array region and a peripheral circuit region. It is particularly suitable for the fabrication process of two-dimensional planar NAND flash memory using advanced process nodes, which employs self-aligned dual patterning (SADP) technology to form high-density device structures. This method improves the morphology of the mandrel from the source by optimizing the photolithography patterning step in the SADP process, thereby ensuring that the final core layer 108 pattern has excellent dimensional uniformity and contour integrity, thus improving the overall device performance and manufacturing yield.

[0034] The method specifically includes the following steps:

[0035] Step 1: Provide a stacked structure to be patterned on a semiconductor substrate 101. The stacked structure to be patterned includes a core layer 108 and a spindle layer 110 from bottom to top.

[0036] In some embodiments, in step one, the core layer 108 is an amorphous silicon (a-Si) layer, and the mandrel layer 110 is a silicon oxide layer. This material selection utilizes the high etch selectivity between amorphous silicon and silicon oxide, laying the foundation for subsequent precise removal of the mandrel layer 110 without damaging the core layer 108 and the sidewall spacers.

[0037] In some embodiments, the core layer 110 is a silicon oxide layer deposited using tetraethoxysilane (TEOS) as a precursor. By using TEOS as a precursor through methods such as chemical vapor deposition (CVD), a dense, uniform silicon oxide layer with good step coverage can be obtained.

[0038] In a more specific embodiment, a complete gate stack has been pre-formed on a semiconductor substrate 101 (e.g., a silicon substrate) before the patterned stack structure is provided. This gate stack, from bottom to top, may include: a low-voltage oxide layer 102 (LV OX), a floating gate layer 103 (FG), an inter-electrode dielectric layer 104, a control gate layer 105 (CG), a silicon nitride (SiN) layer 106 serving as a dielectric layer, and a silicon oxide (TEOS) layer 107. The self-aligned dual patterning process of this invention is performed on this complete gate stack, and the resulting pattern will be used to etch the underlying gate stack.

[0039] Step 2: Form a photoresist layer on the core layer 110.

[0040] The photoresist layer can be a positive photoresist or a negative photoresist. In this embodiment, a positive photoresist is preferred, as it becomes easily soluble in the developer after exposure.

[0041] Step 3: The photoresist layer is exposed and developed using photolithography to form a patterned photoresist mask. The photolithography process uses a clear mode mask.

[0042] In some embodiments, in step three, the transparent mode photomask is characterized in that the layout of the light-transmitting areas of the photomask corresponds to the space between the patterned mandrels, while the layout of the opaque areas of the photomask corresponds to a predetermined pattern of the patterned mandrels. In other words, a transparent mode (or bright field mode, Clear Tone) photomask is used in conjunction with positive photoresist, and the light-blocking chromium layer pattern on the photomask corresponds to the desired mandrel structure. Light passes through the transparent area (most area) of the photomask to expose the underlying photoresist. After development, the exposed photoresist is removed, and the remaining unexposed photoresist pattern is the mask for the mandrel.

[0043] In some embodiments, by employing a transparent photomask in step three, the total area of ​​the opaque region of the photomask during photolithography is increased, thereby reducing the etching load effect caused by the pattern density difference between the memory array region and the peripheral circuit region when etching the core layer 110 in step four. Compared with the conventional dark field mode, in the transparent mode, the area of ​​the core layer 110 material to be etched away (i.e., the area not covered by the photoresist mask) is relatively small and more uniform, whether in the high-density memory array region or the low-density peripheral circuit region. This greatly balances the etching load in different regions, making the plasma distribution more uniform across the entire wafer, thus providing a key guarantee for obtaining a high-quality core morphology.

[0044] Step 4: Using a patterned photoresist mask as a mask, etch the core layer 110 to form a patterned core.

[0045] This etching step typically employs dry etching techniques such as reactive ion etching to achieve highly anisotropic etching, ensuring that the sidewalls of the mandrel are as vertical as possible, thereby obtaining a mandrel structure with good morphology and no top damage.

[0046] To more clearly illustrate the beneficial effects of this invention, please refer to the accompanying drawings. Figure 2 and attached Figure 3 For understanding. The same or similar reference numerals in the figures represent the same or similar components, wherein the substrate is 101, and the gate structure layers stacked upwards in sequence include a low-voltage oxide layer 102, a floating gate layer 103, a control gate layer 104, a silicon nitride layer 105 and a silicon oxide layer 106, and a core layer 107 (e.g., amorphous silicon) and a core layer 108 (e.g., TEOS) are further disposed thereon.

[0047] Appendix Figure 2 The diagram schematically illustrates the mandrel pattern 109 formed by etching the mandrel layer 108 using existing techniques (e.g., using a dark-field mode photomask). An electron microscope image of the mandrel pattern 109 is shown below. Figure 3As shown, due to the significant etching load effect in areas with large differences in pattern density, the top of the mandrel pattern 109 is prone to top damage, resulting in an overall less sharp profile and poor sidewall steepness. This undesirable morphology will severely affect the formation quality of subsequent sidewall spacers.

[0048] In comparison, attached Figure 4 The diagram schematically illustrates the mandrel pattern 110 formed after etching the mandrel layer 108 using the method of the present invention (i.e., using a transparent mode photomask in step three). An electron microscope image of the mandrel pattern 110 is shown below. Figure 5 As shown. Because the method of the present invention effectively alleviates the etching load effect, the etching of the core layer is more uniform and precise. The resulting core pattern 110 has a clear top profile, sharp edges, almost no top damage, and its sidewalls exhibit excellent steepness, presenting an ideal tapered profile overall. This high-quality core pattern 110 provides better pre-layer conditions for forming uniform sidewall spacers in the subsequent step five, fundamentally ensuring the accuracy and integrity of the final pattern (i.e., the etched pattern of the core layer 107) formed by the sidewall image transfer technology, thereby significantly improving the performance and manufacturing yield of the final semiconductor device.

[0049] Step 5: Form sidewall spacers on the sidewalls of the graphic mandrel.

[0050] In some embodiments, the reduction of the etching load effect in step four improves the morphology of the patterned mandrel, enabling the sidewall spacers to be formed more uniformly on the sidewalls of the patterned mandrel in step five. Because top damage to the mandrel is effectively suppressed, and the sidewall profile is steeper and closer to the ideal tapered profile, the final sidewall spacers exhibit significantly improved width and height consistency across the entire wafer, particularly within the memory array region, during conformal deposition and etch-back of the sidewall spacer material. This avoids sidewall spacer breakage or dimensional instability caused by poor mandrel morphology.

[0051] In some embodiments, in step five, the sidewall spacer material is silicon nitride or silicon carbide. Silicon nitride (SiN) or silicon carbide (SiC) are chosen because they exhibit excellent etching selectivity relative to the silicon oxide (TEOS) of the mandrel layer 110 and the amorphous silicon of the core layer 108. This ensures that the sidewall spacer mask maintains its structural integrity during subsequent removal of the mandrel and etching of the core layer 108.

[0052] Step 6: Remove the graphical mandrel.

[0053] In some embodiments, step six, the step of removing the patterned mandrel, includes selective wet etching of the patterned mandrel, wherein the wet etching may employ a dilute hydrofluoric acid (DHF) solution. Since the mandrel layer 110 is silicon oxide, the sidewall spacers are silicon nitride (or silicon carbide), and the core layer 108 is amorphous silicon, the use of a dilute hydrofluoric acid solution can efficiently and selectively remove the mandrel completely without damaging the sidewall spacers and the underlying core layer 108, leaving only the independent sidewall spacer pattern as a mask for the next step.

[0054] Step 7: Using the sidewall spacers as a mask, etch the core layer 108.

[0055] Through a series of optimizations in this invention, the core layer 108 (e.g., an amorphous silicon structure that will become part of the word line) ultimately etched not only achieves frequency multiplication in size, but its sidewall profile is also precisely controlled, exhibiting an ideal tapered shape. This controlled tapered profile is crucial for ensuring the quality of subsequent filling, metallization, and other processes, as well as the electrical performance and reliability of the final device, thereby comprehensively improving the performance and yield of NAND flash memory products.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of improving a semiconductor device topography, applied to fabricating a NAND flash memory on a semiconductor substrate including a memory array region and a peripheral circuit region, characterized by, At least including: Step 1: Provide a stacked structure to be patterned on the semiconductor substrate, wherein the stacked structure to be patterned includes a core layer and a core layer from bottom to top; Step 2: Form a photoresist layer on the mandrel layer; Step 3: Expose and develop the photoresist layer using photolithography to form a patterned photoresist mask, wherein the photolithography process uses a transparent photomask. Step 4: Using the patterned photoresist mask as a mask, etch the core layer to form a patterned core; Step 5: Form sidewall spacers on the sidewalls of the patterned mandrel; Step 6: Remove the graphical mandrel; Step 7: Using the sidewall spacers as a mask, etch the core layer.

2. The method of claim 1, wherein: The layout of the light-transmitting areas of the photomask corresponds to the space between the patterned mandrels, while the layout of the opaque areas of the photomask corresponds to a predetermined pattern of the patterned mandrels.

3. The method of claim 1, wherein: By using the transparent mode photomask in step three, the total area of ​​the opaque region of the photomask during photolithography is increased, thereby reducing the etching load effect caused by the difference in pattern density between the memory array region and the peripheral circuit region when etching the core layer in step four.

4. The method of claim 3, wherein: The reduction of the etching load effect improves the morphology of the patterned mandrel, enabling the sidewall spacers to be formed more uniformly on the sidewalls of the patterned mandrel in step five.

5. The method of claim 1, wherein: In step one, the core layer is an amorphous silicon layer.

6. The method of claim 1, wherein: In step one, the core layer is an amorphous silicon layer.

7. The method for improving the morphology of a semiconductor device according to claim 1, characterized in that: In step one, the core layer is a silicon oxide layer.

8. The method for improving the morphology of a semiconductor device according to claim 7, characterized in that: The core layer is a silicon oxide layer deposited using tetraethoxysilane as a precursor.

9. The method for improving the morphology of a semiconductor device according to claim 1, characterized in that: In step five, the material of the sidewall spacer is silicon nitride or silicon carbide.

10. The method for improving the morphology of a semiconductor device according to claim 1, characterized in that: In step six, the step of removing the patterned mandrel includes selective wet etching of the patterned mandrel.

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