MOSFET manufacturing process, field effect transistor and power equipment
By reducing the number of photolithography steps in the MOSFET manufacturing process, self-alignment of primary and secondary ion implantation is achieved, solving the overlay error problem caused by multiple photolithography steps and improving the alignment accuracy and electrical performance of the source and drain regions.
Patent Information
- Application Number
- CN202510965627.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-12-05
AI Technical Summary
In existing MOSFET manufacturing processes, multiple photolithography steps lead to overlay errors, which limit the miniaturization of cell size and affect electrical performance.
A first ion implantation is achieved by forming a first mask layer on the substrate surface and performing photolithography and etching to form a first implantation window. Subsequently, a trench is formed on the polysilicon layer surface and the gate and sidewalls are formed by dry etching, achieving self-alignment of the second ion implantation and reducing the number of photolithography steps.
Simplify the photolithography process, reduce overlay errors, improve the alignment accuracy of the source and drain regions, and optimize electrical performance, such as reducing parasitic resistance and capacitance, and improving switching speed and power density.
Smart Images
Figure CN121078747A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a MOSFET manufacturing process, a field-effect transistor, and a power device. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor widely used in power conversion circuits. MOSFETs are classified into two types based on the polarity of their "channels" (working charge carriers): "N-type" and "P-type," commonly referred to as NMOSFETs and PMOSFETs, respectively. Other abbreviations include NMOS and PMOS.
[0003] In related technologies, at least one photolithography process is required before primary ion implantation, secondary ion implantation, and gate formation to facilitate self-alignment of each ion implantation or dry etching process. During this process, multiple photolithography processes can limit the miniaturization of cell size due to overlay errors, affecting the electrical performance of field-effect transistors in terms of on-resistance, power density, etc. Summary of the Invention
[0004] The main objective of this application is to provide a MOSFET manufacturing process that aims to achieve self-aligned processes for primary and secondary ion implantation while reducing the number of photolithography steps.
[0005] To achieve the above objectives, the MOSFET manufacturing process proposed in this application includes: A first mask layer is generated on the surface of the substrate. The first mask layer is photolithographically and etched to form two first implantation windows. Ion implantation is performed once in each of the two first implantation windows so that two first active regions are formed on the substrate. Remove the first mask layer, and sequentially form an isolation layer and a polysilicon layer on the surface of the substrate; Two trenches are formed by photolithography and etching at the position of the first implantation window on the polycrystalline silicon layer corresponding to the substrate; A second mask layer and a third mask layer are sequentially formed on the surface of the polysilicon layer. The second mask layer and the third mask layer are dry etched to form a gate in the polysilicon layer, and a sidewall is formed on both sides of each trench. Each trench exposes the bottom of the trench corresponding to the two sidewalls to form a second implantation window. Secondary ion implantation is performed in both second implantation windows to form two second active regions at the location where the first active region is located on the substrate. The two first active regions and the corresponding second active regions form the source region and the drain region, respectively.
[0006] In another embodiment, the material of the second mask layer is silicon dioxide.
[0007] In another embodiment, the third mask layer is made of silicon nitride.
[0008] In another embodiment, the area of the first injection window is larger than the area of the first injection window. In another embodiment, the minimum thickness of each of the sidewalls is 50-200 nm.
[0009] In another embodiment, the thickness of the third mask layer is greater than the thickness of the second mask layer.
[0010] In another embodiment, the step of sequentially forming a second mask layer and a third mask layer on the surface of the polysilicon layer, performing dry etching on the second mask layer and the third mask layer to form a gate in the polysilicon layer, and forming a sidewall on both sides of each trench includes: A second mask layer is formed on the surface of the polycrystalline silicon layer by thermal oxidation, and a third mask layer is formed on the upper surface of the second mask layer by vapor deposition. Dry etching is performed on the area of the third mask layer that covers the second mask layer and the area of the bottom of the trench. Dry etching is used to etch the area of the second mask layer covering the polysilicon layer and the bottom area of the trench to form the gate and a sidewall on both sides of each trench.
[0011] This application also proposes a field-effect transistor, which is obtained by the above-described MOSFET manufacturing process, and the field-effect transistor includes: A substrate having a source region and a drain region, the source region and the drain region being disposed near the top surface of the substrate. An isolation layer covers the top surface of the substrate and has openings at the corresponding source and drain regions; A polysilicon layer is provided, which covers the isolation layer. The polysilicon layer has two trenches, each trench corresponding to and connected to the opening. The portion of the polysilicon layer between the two trenches constitutes a gate. Sidewalls are provided on the sidewalls of each of the trenches, extending along the sidewalls of the trenches from the bottom of the trench to the opening of the trench. In another embodiment, the field-effect transistor further includes a protective layer and a source / drain metal layer, the protective layer covering the polysilicon layer and the sidewalls and being disposed away from the opening, and the source / drain metal layer being disposed at the opening.
[0012] This application also proposes a power device comprising the aforementioned field-effect transistor.
[0013] In this application, a first ion implantation is performed to form a first active region by generating a first mask layer on the substrate surface and then performing photolithography and etching to form a first implantation window. Subsequently, a trench is formed by photolithography and etching at the position of the polysilicon layer corresponding to the substrate. By sequentially forming a second and a third mask layer, and simultaneously forming the gate using dry etching, sidewalls are formed on both sides of the trench. The sidewalls achieve self-alignment of the second implantation window, eliminating the need for separate photolithography during secondary ion implantation, thus reducing the number of photolithography steps. This process not only simplifies the photolithography steps and reduces overlay errors caused by multiple photolithography steps, but also improves the alignment accuracy of the source and drain regions, optimizes the electrical performance of the device, such as reducing parasitic resistance and capacitance, and improving switching speed and power density. Attached Figure Description
[0014] Figure 1 This is a schematic flowchart of an embodiment of step S10 of the MOSFET manufacturing process provided in this application. Figure 2 A schematic flowchart of an embodiment of step S20 of the MOSFET manufacturing process provided in this application; Figure 3 A schematic flowchart of an embodiment of step S30 of the MOSFET manufacturing process provided in this application; Figure 4 A schematic flowchart of an embodiment of step S40 of the MOSFET manufacturing process provided in this application; Figure 5 A schematic diagram of a structural embodiment of step S50 of the MOSFET manufacturing process provided in this application; Figure 6 A flowchart of a first embodiment of the MOSFET manufacturing process provided in this application; Figure 7 A flowchart of a second embodiment of the MOSFET manufacturing process provided in this application.
[0015] Explanation of icon numbers: 10. Substrate; 101. First mask layer; 101a. First implantation window; 11. First active region; 12. Second active region; 10a. Source region; 10b. Drain region; 20. Isolation layer; 30. Polysilicon layer; 30a. Trench; 301. Gate; 302. Sidewall; 40. Second mask layer; 50. Third mask layer.
[0016] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0017] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0018] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0019] The main objective of this application is to provide a MOSFET manufacturing process that aims to achieve self-aligned processes for primary and secondary ion implantation while reducing the number of photolithography steps.
[0020] To achieve the above objectives, please refer to Figure 6 The MOSFET manufacturing process proposed in this application includes: Step S10: A first mask layer 101 is generated on the surface of the substrate 10. The first mask layer 101 is photolithographically and etched to form two first implantation windows 101a. Ion implantation is performed once in each of the two first implantation windows 101a so that the substrate 10 forms two first active regions 11. Step S20: Remove the first mask layer 101, and sequentially form an isolation layer 20 and a polysilicon layer 30 on the surface of the substrate 10; Step S30: Photolithography and etching are performed on the polysilicon layer 30 to form two trenches 30a, and each trench 30a is aligned with a first implantation window 101a; Step S40: A second mask layer 40 and a third mask layer 50 are sequentially formed on the surface of the polysilicon layer 30. The second mask layer 40 and the third mask layer 50 are dry etched to form a gate 301 on the polysilicon layer 30, and a sidewall 302 is formed on both sides of each trench 30a. Step S50: Each trench 30a is exposed at the bottom of the corresponding two sidewalls 302 to form a second implantation window. Secondary ion implantation is performed in both second implantation windows to form two second active regions 12 at the location where the first active region 11 is on the substrate 10. The two first active regions 11 and the corresponding second active regions 12 respectively form source region 10a and drain region 10b.
[0021] In this application, a first ion implantation is performed to form a first active region by generating a first mask layer on the substrate surface and then performing photolithography and etching to form a first implantation window. Subsequently, a trench is formed by photolithography and etching at the position of the polysilicon layer corresponding to the substrate. By sequentially forming a second and a third mask layer, and simultaneously forming the gate using dry etching, sidewalls are formed on both sides of the trench. The sidewalls achieve self-alignment of the second implantation window, eliminating the need for separate photolithography during secondary ion implantation, thus reducing the number of photolithography steps. This process not only simplifies the photolithography steps and reduces overlay errors caused by multiple photolithography steps, but also improves the alignment accuracy of the source and drain regions, optimizes the electrical performance of the device, such as reducing parasitic resistance and capacitance, and improving switching speed and power density.
[0022] In step S10, please refer to Figure 1First, a layer of photoresist is uniformly spin-coated on the surface of substrate 10. Then, the pre-designed pattern is precisely transferred onto the photoresist layer through a mask and exposure equipment (usually a stepper repetitive projection lithography machine), allowing the photoresist to undergo a chemical reaction under the irradiation of a specific light source (such as ultraviolet light). Next, the photoresist is developed using a developer to remove the exposed portion (positive photoresist) or the unexposed portion (negative photoresist), thereby forming patterns corresponding to the two first implantation windows 101a on the first mask layer 101. Based on the pattern on the photoresist, dry etching (such as reactive ion etching) or wet etching techniques are used to remove the material in the corresponding implantation window region on the first mask layer 101, exposing the surface of the substrate 10 and forming the two first implantation windows 101a. Appropriate ion types (such as phosphorus ions for N-type doping and aluminum ions for P-type doping) and precise control of implantation energy and dose are selected to ensure that ions can penetrate the mask layer and form a shallow first active region 11 in the substrate 10. It is understood that the first ion implantation can be performed simultaneously in both first implantation windows 101a using an ion implantation device, or the first ion implantation can be performed sequentially in both first implantation windows 101a. This is not limited here. These first active regions 11 will serve as the lightly doped portions of the source and drain regions 10b, facilitating the subsequent formation of the lightly doped drain (LDD) structure, thereby optimizing the device's switching characteristics and breakdown voltage performance. This step precisely defines the implantation region using photolithography and etching techniques, ensuring the accuracy and consistency of ion implantation. The formed first active regions 11 lay the foundation for the subsequent construction of the source and drain regions 10b, and their size and location directly affect the device's electrical performance and structural characteristics.
[0023] Understandably, after implantation, high-temperature annealing is performed according to the requirements of the field-effect transistor to meet the design requirements. Since high-temperature annealing is a relatively mature process in this field, no further explanation is needed.
[0024] Then proceed to step S20, please refer to [link / reference] Figure 2The process typically employs a wet etching technique, in which the substrate 10 is immersed in a hydrofluoric acid (HF) solution. The HF reacts chemically with the first mask layer 101 (usually a silicon dioxide layer) to generate water-soluble fluorosilicates, thereby removing the first mask layer 101 from the surface of the substrate 10. Subsequently, the substrate 10 is rinsed with deionized water to remove residues and then dried. An isolation layer 20 is first formed on the dried substrate 10. The isolation layer 20 is typically made of silicon dioxide and can be prepared using processes such as thermal oxidation or chemical vapor deposition (CVD). In this process, the substrate 10 is placed in a high-temperature oxidation furnace. By controlling parameters such as temperature, pressure, and oxygen flow rate within the furnace, an oxidation reaction occurs on the surface of the substrate 10, generating a uniform silicon dioxide film, i.e., the isolation layer 20. The main function of the isolation layer 20 is to protect the source region 10a and the drain region 10b, preventing subsequent polysilicon deposition and etching processes from causing unnecessary impact on these regions, ensuring that the doping characteristics of the source and drain regions 10b are fully preserved. Subsequently, a polysilicon layer 30 is formed on top of the isolation layer 20 using chemical vapor deposition (CVD) or other suitable deposition methods. Polysilicon, due to its excellent conductivity and thermal stability, is widely used in the manufacture of the gate 301 material. During deposition, the thickness and quality of the polysilicon layer 30 can be adjusted by precisely controlling deposition parameters such as temperature, pressure, and gas flow rate to meet specific device design requirements. In this step, the isolation layer 20 primarily protects the substrate 10, preventing subsequent processes from affecting the formed source and drain regions 10b, and provides a good substrate for the uniform growth of the polysilicon layer 30. The polysilicon layer 30 is a key material for the subsequent formation of the gate 301, and its quality and thickness have a significant impact on the performance of the gate 301.
[0025] Then proceed to step S30, see [link / reference] Figure 3 Specifically, a layer of photoresist is uniformly coated on the surface of the polysilicon layer 30. A pre-designed pattern is precisely transferred onto the photoresist layer using a mask and exposure equipment. The photoresist undergoes a chemical reaction under the illumination of a specific light source. Then, the photoresist is developed using a developer to remove the exposed portion (positive photoresist) or the unexposed portion (negative photoresist), exposing the area on the polysilicon layer 30 corresponding to the trench 30a. Then, according to the pattern on the photoresist, the unwanted portion of the polysilicon layer 30 is precisely removed using dry etching (such as reactive ion etching) or wet etching techniques to form two trenches 30a. During this process, it is ensured that the images formed by the two photolithography steps overlap so that each trench 30a is aligned with the first injection window 101a. Trench 30a is formed in polysilicon layer 30 by photolithography and etching techniques, providing the necessary structural basis for subsequent gate 301 formation and sidewall 302 construction. It also helps to achieve isolation between source and drain regions 10b and gate 301, ensuring normal operation of the device.
[0026] In step S40, please refer to Figure 4 A second mask layer 40 is formed on the surface of the polysilicon layer 30 by thermal oxidation. A third mask layer 50 is formed on the upper surface of the second mask layer 40 by vapor deposition. Using dry etching technology, the area covered by the third mask layer 50 covering the second mask layer 40 and the bottom area of the trench 30a are first etched away. Then, the area covered by the second mask layer 40 covering the polysilicon layer 30 and the bottom area of the trench 30a are etched away, thereby forming a gate 301 on the polysilicon layer 30 and forming a sidewall 302 on both sides of each trench 30a. This step precisely patterns the polysilicon layer 30 into the gate 301 using dry etching technology, while simultaneously forming sidewalls 302 on both sides of the trench 30a.
[0027] Finally, in step S50, please refer to Figure 5 At the bottom of trench 30a, the sidewalls of sidewalls 302 extend from the bottom of trench 30a to the opening of trench 30a. The area between the two sidewalls 302 of each trench 30a is the second implantation window. Subsequently, a suitable ion species (same as or different from the first ion implantation, depending on the specific device design) is selected, and the implantation energy and dose are precisely controlled. The implantation energy is usually in the range of 200-500 keV, and the dose is approximately 1-10E17cm. -3 This ensures that ions can penetrate the sidewall 302 and the polysilicon layer 30 to form a second active region 12 in the substrate 10. The depth of the second active region 12 is greater than that of the first active region 11, typically between 0.5 and 2 μm. By precisely controlling the implantation energy and dose, and utilizing the blocking effect of the sidewall 302, the source region 10a and drain region 10b are precisely formed. In this next step, the purpose of the secondary ion implantation is to further form complete source and drain regions 10b based on the first active region 11. The self-alignment of the sidewall 302 ensures the precise formation of the source and drain regions 10b, avoiding device performance degradation due to alignment errors. Simultaneously, this self-aligned process helps optimize the device's electrical properties such as on-resistance, switching speed, and breakdown voltage.
[0028] In another embodiment, the second mask layer 40 is made of silicon dioxide. Silicon dioxide itself has the characteristic of easy control of growth thickness. By precisely adjusting the oxidation process parameters, the thickness that meets specific requirements can be easily obtained, providing strong support for the precise design of devices. Meanwhile, silicon dioxide exhibits excellent etchability and leaves no residue during etching, enabling precise pattern formation in subsequent photolithography and etching processes. This avoids device defects caused by incomplete etching or residual substances, significantly improving device yield. Regarding etching selectivity, the combination of silicon dioxide and silicon nitride demonstrates superior performance. Their different etching rates in dry etching allow for precise control of etching depth and shape, thereby achieving accurate construction of the gate 301 and sidewall 302 structures. This plays a crucial role in improving device performance and reliability. In terms of interface characteristics, the high-quality interface between silicon dioxide and polysilicon effectively passivates polysilicon surface defects, reduces interface state density, and significantly enhances the electrical stability of the interface. This is essential for ensuring the electrical characteristics of the gate 301. Furthermore, the high-temperature stability of silicon dioxide and polysilicon ensures that the structure and performance of the silicon dioxide layer and polysilicon layer 30 are fully maintained in subsequent high-temperature processes, preventing device performance degradation caused by thermal stress or chemical reactions. During the doping process, the barrier effect of silicon dioxide can precisely control the doping region and prevent doped ions from diffusing into non-target regions. At the same time, it does not introduce impurities or interfere with the doping effect, thus ensuring the high quality and consistency of the doping process.
[0029] In another embodiment, the third mask layer 50 is made of silicon nitride. Silicon nitride possesses excellent insulation and chemical stability, providing good sidewall protection during etching to prevent damage to the polysilicon layer 30. Its high hardness also enhances the mechanical strength of the mask layer, ensuring structural integrity during complex processes. Silicon nitride and silicon dioxide have significantly different etching rates; in dry etching, the etching rate of silicon nitride is much higher than that of silicon dioxide. This allows for precise control of etching depth and shape during etching, enabling accurate construction of the gate 301 and sidewall 302 structures. Furthermore, the interface characteristics between silicon nitride and polysilicon are excellent, effectively passivating polysilicon surface defects, reducing interface state density, and enhancing the electrical stability of the interface. This is crucial for ensuring the electrical characteristics of the gate 301. The combination of silicon nitride and silicon dioxide also exhibits excellent thermal stability, ensuring the integrity of the structure and performance of the silicon nitride layer and polysilicon layer 30 under high-temperature process conditions, preventing device performance degradation caused by thermal stress or chemical reactions. Silicon nitride exhibits excellent etching selectivity during etching, enabling precise control over etching depth and shape. This allows for accurate fabrication of the gate 301 and sidewall 302 structures, playing a crucial role in improving device performance and reliability. Simultaneously, the silicon nitride sidewall 302, utilizing its inherent properties and location, effectively isolates the gate 301 from the source region 10a and drain region 10b, achieving electrical isolation. It can be retained in subsequent processes without affecting product performance and does not require removal. In another embodiment, the area of the first injection window 101a is larger than that of the second injection window 101a. This larger first injection window 101a reduces the precision requirements of photolithography and etching processes, making pattern transfer easier. Simultaneously, the shallow doped region formed facilitates the subsequent formation of a lightly doped drain (LDD) structure, optimizing the device's switching characteristics and breakdown voltage performance. The smaller second injection window further reduces self-alignment requirements, ensuring the accuracy of the injection region even with overlay errors, preventing device performance degradation, and allowing for more precise control of the doped region range, reducing lateral diffusion, and ensuring the device structure's accuracy and consistency. Furthermore, this area difference enables a layered doping structure, with the source and drain regions 10b exhibiting different characteristics in the depth direction, optimizing electrical performance and providing greater process adjustment space to better adapt to different device design requirements. At the same time, a larger first injection window 101a facilitates uniform impurity diffusion during subsequent high-temperature processes, reducing localized excessively high or low concentrations and improving electrical performance; a smaller second injection window allows for more precise control of impurity concentration distribution, avoiding unnecessary deep doping and optimizing device conductivity and breakdown voltage.
[0030] In another embodiment, the thickness of the third mask layer 50 is greater than the thickness of the second mask layer 40. This design fully considers the characteristics of the two mask layer materials: the second mask layer 40 is silicon dioxide, which has advantages such as easy control of growth thickness, easy etching, and no residue; while the third mask layer 50 is silicon nitride, which has high hardness, excellent insulation properties, and chemical stability. The thicker silicon nitride layer can better protect the polysilicon layer 30 during etching, reducing the damage to the polysilicon layer 30 caused by etching, while enhancing the mechanical strength of the mask layer and ensuring structural integrity is maintained in complex process flows. In addition, the significant difference in etching rate between silicon nitride and silicon dioxide allows for more precise control of etching depth and shape in dry etching, thereby achieving accurate construction of the gate 301 and sidewall 302 structures. This design not only improves the device yield but also ensures that the structure and performance of the silicon nitride layer and polysilicon layer 30 are fully maintained in subsequent high-temperature processes, thereby optimizing the overall electrical performance of the device.
[0031] In another implementation, please refer to Figure 7 Step S40 includes: Step S41: A second mask layer 40 is formed on the surface of the polysilicon layer 30 by thermal oxidation, and a third mask layer 50 is formed on the upper surface of the second mask layer 40 by vapor deposition. Step S42: Dry etching the area of the third mask layer 50 covering the second mask layer 40 and the bottom area of the trench 30a; Step S43: Dry etching of the area of the second mask layer 40 covering the polysilicon layer 30 and the bottom area of the trench 30a to form the gate 301 and a sidewall 302 on both sides of each trench 30a.
[0032] In step S41, the silicon wafer is placed in a high-temperature oxidation furnace. Under controlled process parameters such as temperature, pressure, and oxygen flow rate, an oxidation reaction occurs on the surface of the polysilicon layer 30, generating a silicon dioxide thin film, namely the second mask layer 40. During the oxidation reaction, silicon atoms combine with oxygen atoms to form a dense silicon dioxide thin film. This film has good insulation properties and chemical stability, and can also serve as a barrier layer for subsequent etching, protecting the polysilicon layer 30 from over-etching. Subsequently, a silicon nitride thin film is deposited on the upper surface of the second mask layer 40 using chemical vapor deposition (CVD) technology, serving as the third mask layer 50. During the CVD process, the reactive gases undergo a chemical reaction under high temperature and low pressure conditions, depositing a uniform silicon nitride thin film on the silicon wafer surface. Silicon nitride has excellent insulation properties, chemical stability, and high etching selectivity, and can serve as a hard mask layer, playing a crucial role in subsequent dry etching. It precisely controls the etching depth and shape, effectively protecting the polysilicon layer 30 and the second mask layer 40 from accidental etching. In this step, a second and a third mask layer 50 are sequentially formed on the surface of the polysilicon layer 30 to prepare for the subsequent dry etching process. The second mask layer 40 (silicon dioxide) acts as a buffer and protector, while the third mask layer 50 (silicon nitride) utilizes its high hardness and good etching selectivity to ensure the precise formation of the gate 301 structure and sidewall 302 structure during dry etching, while avoiding unnecessary damage to the polysilicon layer 30 and other areas, thus improving device yield and performance.
[0033] In step S42, plasma dry etching technology is used to etch the third mask layer 50 by selecting appropriate process parameters such as etching gas, power, and pressure. During the etching process, active particles in the plasma react chemically with the third mask layer 50, etching away the material of the third mask layer 50. The target area for etching is the portion covering the second mask layer 40 and the portion of the third mask layer 50 covering the bottom of the trench 30a. The purpose of this step is to remove the unwanted portions of the third mask layer 50, namely the portion of the third mask layer 50 covering the second mask layer 40 and the bottom of the trench 30a. This is done to expose the second mask layer 40 in subsequent etching processes, allowing for further etching of the second mask layer 40, while also ensuring that the bottom region of the trench 30a can be etched, thereby creating conditions for the formation of the gate 301 and sidewall 302 structures.
[0034] In step S3, after partially removing the third mask layer 50, dry etching continues. This time, the target of etching is the second mask layer 40, also using plasma dry etching technology. Based on the material (silicon dioxide) characteristics of the second mask layer 40, appropriate etching gas and process parameters are selected. The etched area is the portion of the second mask layer 40 covering the polysilicon layer 30 and the bottom of the trench 30a. During etching, the active plasma chemically reacts with the silicon dioxide, etching away the silicon dioxide material. By precisely controlling the etching depth and shape, a gate 301 structure is finally formed on the polysilicon layer 30. On both sides of the trench 30a, because a portion of the second mask layer 40 is etched away, a sidewall 302 structure is naturally formed. The sidewall 302 is formed because, during the etching process, due to the difference in mask layer thickness and etching rate, a portion of the mask layer on the sidewalls of the trench 30a is retained, thus forming sidewalls 302 of a certain thickness on both sides of the trench 30a. This step is to ultimately form the key structures of the device—the gate 301 and sidewalls 302. By removing a specific portion of the second mask layer 40, the gate 301 structure is formed above the polysilicon layer 30. The gate 301 is the core component of the MOSFET device, used to control the current between the source and drain. Simultaneously, the sidewall 302 structures formed on both sides of the trench 30a play a crucial role. The sidewalls 302 provide a self-aligned window for subsequent secondary ion implantation, ensuring the accuracy of ion implantation and avoiding device performance degradation due to alignment errors. Furthermore, the sidewalls 302 can also isolate the source and drain regions 10b to a certain extent, reducing leakage current and improving the switching performance and reliability of the device.
[0035] This application also proposes a field-effect transistor, which is obtained by the above-described MOSFET manufacturing process, and the field-effect transistor includes: Substrate 10, the substrate 10 having a source region 10a and a drain region 10b, the source region 10a and the drain region 10b being disposed near the top surface of the substrate 10. An isolation layer 20 covers the top surface of the substrate 10 and has an opening at each of the source region 10a and the drain region 10b. A polysilicon layer 30 is provided, which covers the isolation layer 20. The polysilicon layer 30 has two trenches 30a, each trench 30a is provided to correspond to and connect to the opening. The portion of the polysilicon layer 30 located between the two trenches 30a constitutes a gate 301. Sidewall 302, the sidewall 302 is provided on the sidewall of each of the trenches 30a, the sidewall 302 extends along the sidewall of the trench 30a from the bottom of the trench 30a to the opening of the trench 30a. Specifically, the drain, source, and gate 301 of the field-effect transistor are formed on the same side of the substrate 10. The substrate 10 is typically made of silicon (Si) and is the basic structure of the transistor. Source region 10a and drain region 10b are formed on it, and these regions are located near the top surface of the substrate 10. The source and drain are typically made of doped semiconductor materials, with appropriate impurities introduced through ion implantation. For example, for N-type MOSFETs, source and drain regions 10b are typically implanted with N-type impurities such as phosphorus ions; for P-type MOSFETs, P-type impurities such as boron ions are implanted. Different doping types result in different types of MOSFETs, namely NMOS and PMOS. These two types of MOSFETs have different applications in circuit design and can be used individually or in combination to construct various logic circuits and power devices.
[0036] The isolation layer 20 is typically made of silicon dioxide and covers the top surface of the substrate 10. It has uniformly distributed openings at the locations corresponding to the source region 10a and the drain region 10b to facilitate electrical connection between the subsequent polysilicon layer 30 and the source and drain regions 10b. The main function of the isolation layer 20 is to protect the substrate 10, preventing the polysilicon deposition and etching process from affecting the source and drain regions 10b, while ensuring that the doping characteristics of the source and drain regions 10b are fully preserved.
[0037] The polysilicon layer 30, typically composed of polysilicon (Poly-Si) material, covers the isolation layer 20 and has two trenches 30a. Each trench 30a corresponds to and connects to an opening on the isolation layer 20 to achieve electrical connection with the source region 10a and the drain region 10b. Polysilicon is widely used in the manufacture of the gate 301 material due to its excellent conductivity and thermal stability. The portion of the polysilicon layer 30 located between the two trenches 30a serves as the gate 301, controlling the current between the source and drain. Its quality and thickness have a significant impact on the performance of the gate 301.
[0038] The sidewall 302, constructed from insulating materials such as silicon dioxide and silicon nitride, is located on the sidewall of each trench 30a and extends from the bottom to the opening of the trench. The sidewall 302 provides self-alignment during secondary ion implantation, ensuring precise formation of the source and drain regions 10b, while reducing leakage current and improving the switching performance and reliability of the device. Through the blocking effect of the sidewall 302, precise alignment of the source and drain regions 10b is achieved, optimizing the device's on-resistance, switching speed, and withstand voltage.
[0039] In another embodiment, the minimum thickness of each sidewall 302 is 50-200 nm. Within this range, it provides sufficient barrier effect for subsequent secondary ion implantation, ensuring that implanted ions are accurately contained within the predetermined area, avoiding ion diffusion caused by excessively thin sidewalls 302, and improving the accuracy of the device structure; while avoiding additional manufacturing costs or impacting device performance due to excessive thickness. Simultaneously, a moderate sidewall 302 thickness helps achieve better etching selectivity and control during etching, reducing etching non-uniformity and ensuring the uniformity and integrity of the sidewall 302 structure. Furthermore, during device operation, the appropriate thickness of the sidewall 302 effectively isolates the source and drain regions 10b, reducing leakage current and improving the switching performance and reliability of the device.
[0040] In another embodiment, the field-effect transistor further includes a protective layer and a source / drain metal layer. The protective layer covers the polysilicon layer 30 and the sidewall 302, and is disposed away from the opening. The source / drain metal layer is disposed at the opening. Specifically, the protective layer covers the surfaces of the polysilicon layer 30 and the sidewall 302, providing protection and preventing damage to the polysilicon layer 30 and the sidewall 302 during subsequent processes or use. The protective layer is typically made of silicon dioxide, silicon nitride, or other suitable insulating materials, and is formed by processes such as chemical vapor deposition (CVD). The protective layer can improve the stability and reliability of the device, while reducing the impact of the external environment on the device performance. The source / drain metal layer is disposed at the opening, forming a good electrical connection with the source region 10a and the drain region 10b. The source / drain metal layer is typically made of metal materials with good conductivity, such as aluminum (Al) or copper (Cu), and is formed by processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The purpose of setting source and drain metal layers is to reduce the contact resistance of the source and drain regions 10b, improve current transmission efficiency, and thus optimize the electrical performance of the field-effect transistor.
[0041] This application also proposes a power device, which includes the field-effect transistor described above. The specific structure of the field-effect transistor is as described in the above embodiments. Since this power device adopts all the technical solutions of all the above embodiments of the field-effect transistor, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.
[0042] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.
Claims
1. A MOSFET fabrication process, characterized by, The MOSFET manufacturing process comprises: forming a first mask layer (101) on the surface of a substrate (10), performing photoetching and etching on the first mask layer (101) to form two first implantation windows (101a), and performing first ion implantation on the two first implantation windows (101a) to form two first active regions (11) on the substrate (10); removing the first mask layer (101) and sequentially forming an isolation layer (20) and a polysilicon layer (30) on the surface of the substrate (10); performing photoetching and etching on the polysilicon layer (30) to form two trenches (30a), and aligning one first implantation window (101a) with each trench (30a); sequentially forming a second mask layer (40) and a third mask layer (50) on the surface of the polysilicon layer (30), performing dry etching on the second mask layer (40) and the third mask layer (50) to form a gate (301) on the polysilicon layer (30), and forming a side wall (302) on both sides of each trench (30a); exposing the bottom of each trench (30a) to form a second implantation window, performing second ion implantation on the two second implantation windows to form two second active regions (12) on the substrate (10) at the positions of the first active regions (11), and forming a source region (10a) and a drain region (10b) respectively by the two first active regions (11) and the corresponding second active regions (12).
2. The MOSFET fabrication process of claim 1, wherein, The material of the second mask layer (40) is silicon dioxide.
3. The MOSFET fabrication process of claim 1, wherein, The material of the third mask layer (50) is silicon nitride.
4. The MOSFET fabrication process of claim 1, wherein, The area of the first implantation window (101a) is greater than that of the first implantation window (101a).
5. The MOSFET fabrication process of claim 1, wherein, The thickness of the third mask layer (50) is greater than that of the second mask layer (40).
6. The MOSFET fabrication process of claim 6, wherein, The step of sequentially forming a second mask layer (40) and a third mask layer (50) on the surface of the polysilicon layer (30), performing dry etching on the second mask layer (40) and the third mask layer (50) to form a gate (301) on the polysilicon layer (30), and forming a side wall (302) on both sides of each trench (30a) comprises: forming a second mask layer (40) on the surface of the polysilicon layer (30) by thermal oxidation, and forming a third mask layer (50) on the upper surface of the second mask layer (40) by vapor deposition; dry etching the third mask layer (50) to cover the area of the second mask layer (40) and the bottom of the trench (30a); dry etching the second mask layer (40) to cover the polysilicon layer (30) and the bottom of the trench (30a) to form the gate (301) and the side wall (302) on both sides of each trench (30a).
7. A field effect transistor, which is obtained by the MOSFET manufacturing process according to any one of claims 1 to 6, characterized in that, The field effect transistor comprises: A substrate (10) having a source region (10a) and a drain region (10b) disposed near a top surface of the substrate (10) An isolation layer (20) covering the top surface of the substrate (10) and having an opening at each of the source region (10a) and the drain region (10b) A polysilicon layer (30) disposed on the isolation layer (20), the polysilicon layer (30) having two trenches (30a), each of the trenches (30a) corresponding to and communicating with the openings, and the polysilicon layer (30) having a gate (301) between the two trenches (30a) A sidewall (302) disposed on a sidewall of each of the trenches (30a), the sidewall (302) extending along the sidewall of the trench (30a) from a bottom of the trench (30a) to an opening of the trench (30a).
8. The field-effect transistor as claimed in claim 1, characterized in that, The minimum thickness of each of the sidewalls (302) is 50-200nm.
9. The field-effect transistor as claimed in claim 8, characterized in that, The field effect transistor further comprises a protective layer covering the polysilicon layer (30) and the sidewalls (302) and disposed away from the openings, and a source-drain metal layer disposed in the openings.
10. A power device, characterized by The power device comprises the field effect transistor of any one of claims 8 or 9.