Silicon carbide transistor, method of fabrication, and electronic device

Abstract

The application relates to the field of semiconductor technology and discloses a silicon carbide transistor, a manufacturing method and an electronic device. The silicon carbide transistor comprises a substrate and a silicon carbide layer arranged above the substrate. The silicon carbide layer comprises a buffer layer, a drift layer and a source contact layer which are sequentially arranged above the substrate. A gate trench is arranged on the side surface of the silicon carbide layer away from the substrate. The bottom of the gate trench is located in the drift layer. The bottom of the gate trench is filled with first doped silicon carbide. The surface of the first doped silicon carbide is sequentially stacked with a gate and an auxiliary electrode. The auxiliary electrode is connected with the gate. The gate and the auxiliary electrode comprise different materials. In this way, the resistance of the gate of the silicon carbide transistor is reduced, and the switching speed of the silicon carbide transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and provides a silicon carbide transistor, a manufacturing method and an electronic device. BACKGROUND

[0002] As a semiconductor material with wide band gap, high breakdown field strength, high thermal conductivity, and similar mobility to silicon, silicon carbide has broad prospects in power electronic applications and is widely used in new energy vehicles, charging piles, photovoltaic, etc.

[0003] Since the size of the gate of the silicon carbide transistor in the current manufacturing process is relatively narrow, the resistance of the gate is relatively large, thereby causing the switching speed of the silicon carbide transistor to be relatively slow. Therefore, how to improve the switching speed of the silicon carbide transistor becomes a technical problem to be solved in the field. SUMMARY

[0004] The embodiments of the present application provide a silicon carbide transistor, a manufacturing method and an electronic device to improve the switching speed of the silicon carbide transistor.

[0005] The specific technical solutions provided by the present application are as follows:

[0006] In a first aspect, the embodiments of the present application provide a silicon carbide transistor, comprising: a substrate, and a silicon carbide layer arranged on the substrate; the silicon carbide layer comprises: a buffer layer, a drift layer, and a source contact layer arranged on the substrate in sequence.

[0007] The silicon carbide layer is provided with a gate trench on a side surface away from the substrate, the bottom of the gate trench is located in the drift layer, the bottom of the gate trench is filled with first doped silicon carbide, the surface of the first doped silicon carbide is sequentially stacked with a gate and an auxiliary electrode, the auxiliary electrode is connected with the gate, and the gate and the auxiliary electrode comprise different materials.

[0008] In a second aspect, the embodiments of the present application further provide a manufacturing method of the silicon carbide transistor as described in the first aspect, comprising:

[0009] forming a silicon carbide layer on the substrate;

[0010] etching a gate trench on a side surface of the silicon carbide layer away from the substrate;

[0011] forming first doped silicon carbide by epitaxy on the bottom of the gate trench;

[0012] forming the gate and the auxiliary electrode on the surface of the first doped silicon carbide in sequence.

[0013] In a third aspect, the embodiments of the present application provide an electronic device, comprising: the silicon carbide transistor as described in the first aspect.

[0014] The application has the following beneficial effects:

[0015] The silicon carbide transistor, the manufacturing method and the electronic device provided in the application have the following beneficial effects: The silicon carbide transistor includes a substrate and a silicon carbide layer arranged above the substrate. The silicon carbide layer includes a buffer layer, a drift layer and a source contact layer arranged above the substrate in sequence. A gate trench is arranged on a side surface of the silicon carbide layer away from the substrate. The bottom of the gate trench is located in the drift layer. The bottom of the gate trench is filled with first doped silicon carbide. The surface of the first doped silicon carbide is stacked with a gate and an auxiliary electrode in sequence. The auxiliary electrode is connected with the gate. The gate and the auxiliary electrode include different materials. In this way, the resistance of the gate of the silicon carbide transistor is reduced, and the switching speed of the silicon carbide transistor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A cross-sectional view of a first silicon carbide transistor provided in the application is provided.

[0017] Figure 2 A cross-sectional view of a second silicon carbide transistor provided in the application is provided.

[0018] Figure 3 A cross-sectional view of a third silicon carbide transistor provided in the application is provided.

[0019] Figure 4 A cross-sectional view of a fourth silicon carbide transistor provided in the application is provided.

[0020] Figure 5 A cross-sectional view of a fifth silicon carbide transistor provided in the application is provided.

[0021] Figure 6 A cross-sectional view of a sixth silicon carbide transistor provided in the application is provided.

[0022] Figure 7 A cross-sectional view of a seventh silicon carbide transistor provided in the application is provided.

[0023] Figure 8 A cross-sectional view of the first silicon carbide transistor provided in the application along a third direction is provided.

[0024] Figure 9 A cross-sectional view of the second silicon carbide transistor provided in the application along a third direction is provided.

[0025] Figure 10 A flowchart of a manufacturing method of a silicon carbide transistor provided in the application is provided.

[0026] Figure 11 A cross-sectional view of an eighth silicon carbide transistor provided in the application is provided.

[0027] Figure 12 A ninth cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0028] Figure 13 A tenth cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0029] Figure 14 An eleventh cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0030] Figure 15 A twelfth cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0031] Figure 16 A thirteenth cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0032] Figure 17 A fourteenth cross-sectional view of a silicon carbide transistor according to an embodiment of the present application is provided.

[0033] Figure 18 A cross-sectional view of the cross-sectional view in Figure 2 in the direction of AA' is provided according to an embodiment of the present application.

[0034] Figure 19 A cross-sectional view of the cross-sectional view in Figure 5 in the direction of BB' is provided according to an embodiment of the present application.

[0035] Figure 20 A cross-sectional view of the cross-sectional view in Figure 9 in the direction of CC' is provided according to an embodiment of the present application.

[0036] Figure 21 A structural schematic diagram of an electronic device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0037] The specific embodiments of a silicon carbide transistor, a manufacturing method thereof and an electronic device provided by the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0038] First, the structural composition of the silicon carbide transistor will be introduced with reference to the drawings.

[0039] The embodiments of the present application provide a silicon carbide transistor, which refers to Figure 1As shown, the silicon carbide transistor comprises a substrate 100 and a silicon carbide layer arranged on the substrate 100.

[0040] The substrate 100 and the silicon carbide layer can be made of P-type silicon carbide or N-type silicon carbide, and the silicon carbide transistor can be of P-type or N-type, which is not limited herein.

[0041] Referring to Figure 1 As shown, the silicon carbide layer comprises a buffer layer 200, a drift layer 300 and a source contact layer 400 arranged on the substrate 100 in sequence.

[0042] The buffer layer 200, the drift layer 300 and the source contact layer 400 are formed on the substrate 100 by multiple epitaxy, and the source contact layer 400 can also be formed by ion implantation.

[0043] The silicon carbide layer is provided with a gate trench 301 on the side surface away from the substrate 100, and the bottom of the gate trench 301 is located in the drift layer 300. The bottom of the gate trench 301 is filled with a first doped silicon carbide 302.

[0044] Referring to Figure 1 As shown, the gate trench 301 is arranged on the side surface of the silicon carbide layer away from the substrate 100, and the gate trench 301 penetrates the source contact layer 400 and extends into the drift layer 300. The bottom of the gate trench 301 does not penetrate the drift layer 300. The extension direction of the gate trench 301 in the radial direction (i.e. the direction indicated by L2 in FIG. 1) is the [11-20] crystal direction, and in some embodiments, the angle between the extension direction and the [11-20] crystal direction is within 0.2 degrees. Figure 1 The angle between the sidewall of the gate trench 301 and the second direction (i.e. the direction indicated by L2 in FIG. 1) is usually greater than 85 degrees, and the second direction is the stacking direction of the buffer layer 200, the drift layer 300 and the source contact layer 400 on the substrate 100. Figure 1 The angle between the sidewall of the gate trench 301 and the second direction (i.e. the direction indicated by L2 in FIG. 1) is usually greater than 85 degrees, and the second direction is the stacking direction of the buffer layer 200, the drift layer 300 and the source contact layer 400 on the substrate 100.

[0045] Further, the first doped silicon carbide 302 is formed by epitaxial backfilling in the gate trench 301. The size d1 of the first doped silicon carbide 302 in the second direction is about 1 um, and the thickness of the first doped silicon carbide 302 formed by epitaxial backfilling is more uniform, so that the threshold voltage of the silicon carbide transistor is also more stable.

[0046] The surface of the first doped silicon carbide 302 is sequentially stacked with a gate 303 and an auxiliary electrode 304, and the auxiliary electrode 304 is connected to the gate 303. The gate 303 and the auxiliary electrode 304 comprise different materials.

[0047] Referring toFigure 1 and Figure 2 As shown, the gate 303 is disposed on the surface of the first doped silicon carbide 302 away from the substrate 100. The projection of the gate 303 onto the bottom of the gate trench 301 is less than or equal to the area of ​​the bottom of the gate trench 301. Based on this, an auxiliary electrode 304 is formed again through epitaxial backfilling. The auxiliary electrode 304 is disposed on the gate 303 along a second direction, i.e., the auxiliary electrode 304 is stacked on top of the formed gate 303. The gate 303 is disposed between the first doped silicon carbide 302 and the auxiliary electrode 304. Furthermore, the auxiliary electrode 304 and the gate 303 are electrically connected in parallel. This results in a lower gate resistance after the auxiliary electrode 304 and the gate 303 are connected, thereby improving the switching speed of the silicon carbide transistor.

[0048] It should be noted that the gate 303 and the auxiliary electrode 304 are made of different materials. Thus, the different material properties of the auxiliary electrode 304 and the gate 303 can solve problems such as process compatibility and power consumption control during fabrication. For example, the gate 303 is made of nickel silicide, and the auxiliary electrode 304 is made of polycrystalline silicon.

[0049] In the first embodiment, see Figure 1 and Figure 3 As shown, the silicon carbide transistor also includes a second doped silicon carbide 305 and a third doped silicon carbide 306. The second doped silicon carbide 305 is disposed on the side of the source contact layer 400 away from the substrate 100, and the third doped silicon carbide 306 is located in the gate trench 301 and connected between the first doped silicon carbide 302 and the second doped silicon carbide 305. The first doped silicon carbide 302 and the third doped silicon carbide 306 form a U-shaped cavity.

[0050] See Figure 1 As shown, in addition to the first doped silicon carbide 302, the silicon carbide transistor also includes a second doped silicon carbide 305 and a third doped silicon carbide 306. That is, during the epitaxial backfilling process of forming the first doped silicon carbide 302, the second doped silicon carbide 305 is formed on the side of the source contact layer 400 away from the substrate, and the third doped silicon carbide 306 is formed on the sidewall of the gate trench 301. In this way, the first doped silicon carbide 302 and the second doped silicon carbide 305 are integrally formed through the third doped silicon carbide 306.

[0051] The second doped silicon carbide 305 is disposed on the side of the source contact layer 400 facing away from the substrate 100, i.e. on the surface of the mesa between two adjacent gate trenches. The mesa is the surface of the silicon carbide layer other than the position of the gate trench, and for example, a mesa is formed between two adjacent gate trenches on the surface of the silicon carbide layer. In addition, the gate trench 301 also includes two side walls, and the third doped silicon carbide 306 is disposed on the surface of the side walls.

[0052] In addition, the third doped silicon carbide 306 disposed on the two opposite side walls in the gate trench 301 and the first doped silicon carbide 302 disposed at the bottom of the gate trench 301 form a U-shaped cavity.

[0053] It should be noted that the thickness d2 of the second doped silicon carbide 305 in the second direction is about 0.1-0.2 um, and the thickness d3 of the third doped silicon carbide 306 in the vertical direction of the side wall is about 0.02-0.04 um. In this way, the side wall of the U-shaped cavity formed is thin, on the one hand, the size of the silicon carbide transistor formed by the epitaxial backfilling process is smaller and more uniform, and on the other hand, the threshold voltage of the silicon carbide transistor is more stable.

[0054] Referring to Figure 1 As shown, the silicon carbide transistor further includes an insulating structure 307 filled in the U-shaped cavity, the gate 303 covers part of the surface of the first doped silicon carbide 302, and the insulating structure 307 covers the remaining surface of the first doped silicon carbide 302.

[0055] Further, the gate trench 301 is filled, i.e. the insulating structure 307 is filled in the U-shaped cavity formed by the first doped silicon carbide 302 and the third doped silicon carbide 306, and the insulating structure 307 is disposed on the surface of the third doped silicon carbide 306 on both sides of the gate trench 301, as shown in Figure 3 In addition, the insulating structure 307 on both sides in the gate trench 301 has a hollow part, which can expose part of the surface of the first doped silicon carbide 302 at the bottom of the gate trench 301, so that the gate 303 and the auxiliary electrode 304 are disposed in the hollow part, so that the gate 303 and the auxiliary electrode 304 are sequentially stacked on the surface of the first doped silicon carbide 302.

[0056] In another embodiment, the silicon carbide transistor further comprises a second doped silicon carbide 305 and a third doped silicon carbide 306, the second doped silicon carbide 305 is disposed on a side of the source contact layer 400 facing away from the substrate, and the second doped silicon carbide 305 exposes at least part of the surface of the source contact layer 400, the third doped silicon carbide 306 is disposed in the gate trench and connected between the first doped silicon carbide 302 and the second doped silicon carbide 305, and the source 308 is disposed on the at least part of the surface of the source contact layer 400 exposed by the second doped silicon carbide 305.

[0057] As shown in Figure 3 Unlike the prior art, in which the source 308 is disposed in the size of the entire mesa, in the present application, the source 308 is disposed in the size of only part of the mesa. In the manufacturing process, a through hole is first formed in the second doped silicon carbide 305. The through hole is opened on the surface of the second doped silicon carbide 305 and penetrates through the second doped silicon carbide 305 until it is flush with the source contact layer 400, i.e., the second doped silicon carbide 305 exposes at least part of the surface of the source contact layer 400, and the source 308 is connected to the source contact layer 400. Then, the source 308 is disposed in the through hole. In this way, the size of the source 308 is relatively small, further avoiding the risk of short circuit between the source 308 and the gate 303 through the second doped silicon carbide 305, thereby facilitating improvement of the performance of the silicon carbide transistor.

[0058] It should be noted that, as shown in Figure 3 The first length h1 of the source 308 in the reference plane in the first direction is greater than the second length h2 of the source 308 in the reference plane in the first direction, where the reference plane is a plane formed by the intersection of the second direction and the first direction, the first length h1 is the length of the side of the source 308 in the reference plane facing away from the source contact layer 400, and the second length h2 is the length of the side of the source 308 in the reference plane facing toward the source contact layer 400.

[0059] As shown in Figure 3 Considering that the shape of the through hole is generally trapezoidal in a second plane formed by the intersection of the first direction and the second direction, the shape of the source 308 in the reference plane needs to be adapted to the shape of the through hole. In the above reference plane, the length of the side of the source 308 in the reference plane facing away from the source contact layer 400 is denoted as the first length h1, and the length of the side of the source 308 in the reference plane facing toward the source contact layer 400 is denoted as the second length h2, as shown in Figure 3 The first length h1 is greater than the second length h2, and the entire source 308 forms a trapezoidal shape, the first direction is consistent with the L1 axis direction, and the second direction is consistent with the L2 axis direction.

[0060] As shown in Figure 4As shown, the silicon carbide transistor comprises an insulation structure in the U-shaped cavity, i.e. the third doped silicon carbide 306 is located in the gate trench 301 and connected between the first doped silicon carbide 302 and the second doped silicon carbide 305, so that the U-shaped cavity is formed between the first doped silicon carbide 302 and the third doped silicon carbide 306, and the insulation structure 307 is arranged on the surface of the third doped silicon carbide 306 on both sides of the gate trench 301, i.e. the insulation structure 307 covers the surface of the third doped silicon carbide 306 on the sidewall in addition to covering the surface of the first doped silicon carbide 302 on the bottom.

[0061] Further, the gate 303 is arranged on the side surface of the first doped silicon carbide 302 in the gate trench 301 away from the substrate 100, and then the auxiliary electrode 304 is stacked on the gate 303, i.e. the gate 303 is arranged between the first doped silicon carbide 302 and the auxiliary electrode 304, thereby further reducing the resistance of the gate and improving the switching speed of the silicon carbide transistor.

[0062] During the preparation process, a through hole is usually formed in the second doped silicon carbide 305 to expose part of the surface of the source contact layer 400, and the source 308 is arranged in the through hole, thereby avoiding the risk of short circuit between the source 308 and the gate 303 through the second doped silicon carbide 305, and improving the performance of the silicon carbide transistor.

[0063] In another preparation process of the silicon carbide transistor, considering that the first doped silicon carbide 302 is usually P-type silicon carbide, when the device is subjected to avalanche breakdown, the P-type silicon carbide generates hole current diffusing in the second direction. Based on this, referring to Figure 5 As shown, the N-type doped region 800 is arranged in the third direction on the side of the first doped silicon carbide away from the bottom of the gate trench, and the N-type doped region 800 extends in the third direction. It should be noted that the N-type doped region 800 comprises at least one N-type doped part, i.e. in one case, as shown in Figure 6 As shown, the number of N-type doped parts 801 is one, and the one N-type doped part 801 is integrally arranged in the third direction; in another case, as shown in Figure 7 As shown, the N-type doped part 801 comprises a plurality of N-type doped parts 801, and the N-type doped parts 801 are arranged in the third direction, i.e. the P-type silicon carbide and the N-type doped part 801 are arranged in the third direction in sequence and are spaced apart, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate, as shown in Figure 7 As shown, the third direction is consistent with the L3 axis direction, and the second direction is the direction of the substrate pointing to the source contact layer, as shown in Figure 7 As shown, the second direction is consistent with the L2 axis direction.

[0064] In one embodiment, the N-type doped region 800 is an N+ doped region. When the device undergoes avalanche breakdown, hole leakage will inevitably occur. The N+ doped region can enhance the recombination of holes in the hole leakage with excess electrons in the N+ doped region, thereby accelerating the extraction effect of hole current diffused along the second direction in the region where the P-type silicon carbide is located to the gate contact electrode side.

[0065] In another embodiment, see [reference] Figure 8 As shown, the aforementioned N-type doped region 800 includes N+ type doped regions and N- type doped regions stacked along the second direction. In this way, the aforementioned N+ type doped regions and N- type doped regions can form a built-in electric field, and the direction of the built-in electric field is the aforementioned second direction. When the device experiences avalanche breakdown, the built-in electric field formed by the aforementioned N+ type doped regions and N- type doped regions can further enhance the recombination of holes in the hole leakage current with excess electrons in the N+ doped region, thereby accelerating the extraction effect of the hole current diffused along the second direction in the region where the P-type silicon carbide is located to the gate contact electrode side.

[0066] It should be noted that, in one case, refer to Figure 8 As shown, the length of the N+ doped region 800 (or, the N+ and N- doped regions) along the third direction does not exceed the length of the first doped silicon carbide 302 along the third direction. The length d6 of the N+ doped region 800 (or, the N+ and N- doped regions) along the first direction is equal to the length of the gate 303 along the first direction, that is, the orthogonal projection of the N+ doped region 800 (or, the N+ and N- doped regions) onto the substrate coincides with the orthogonal projection of the gate 303 onto the substrate, as shown. Figure 8 As shown, the first direction is consistent with the L1 axis direction.

[0067] In another case, see Figure 9 As shown, the length of the N+ doped region 800 (or, the N+ and N- doped regions) along the third direction does not exceed the length of the first doped silicon carbide 302 along the third direction. The length d7 of the N+ doped region 800 (or, the N+ and N- doped regions) along the first direction is equal to the circumferential length of the gate trench 301 along the first direction. That is, the orthogonal projection of the N+ doped region 800 (or, the N+ and N- doped regions) onto the substrate covers the orthogonal projection of the gate trench 301 onto the substrate. This can accelerate the extraction effect of hole current diffused along the second direction in the region where the P-type silicon carbide is located to the gate contact electrode side.

[0068] The other structures are the same as the above description, and will not be repeated here. In the silicon carbide transistor formed in this embodiment, not only the gate 303 and the auxiliary electrode 304 with smaller sizes are formed, but also the source 308 with a smaller size is formed, so that the switching speed of the silicon carbide transistor is improved, and the performance of the silicon carbide transistor is effectively improved.

[0069] Optionally, the drift layer 300 and the first doped silicon carbide 302 form a super junction 309, and the specific structure of the super junction 309 can be referred to the structure shown in Figure 3 .

[0070] In this way, the super junction 309 formed by the drift layer 300 and the first doped silicon carbide 302 makes the P-type doped columns and the N-type doped columns in the silicon carbide transistor form multiple PN junction structures, so that the volume of the depletion region is increased, the number of electrons or holes drifting through the depletion region in the same time is increased, and the turn-on time of the silicon carbide transistor is reduced. When the turn-on voltage of the silicon carbide transistor is low, the silicon carbide transistor can also have a faster turn-on speed, the turn-on efficiency of the silicon carbide transistor is improved, and the performance of the silicon carbide transistor is further improved. In addition, the super junction 309 is located in the drift layer 300 of the silicon carbide transistor, so that the electric field distribution of the drift layer 300 can be adjusted, the charge balance is achieved, and the performance of the silicon carbide transistor is further improved.

[0071] It should be noted that in the embodiment shown in Figure 1-3 , the drift layer 300 and the first doped silicon carbide 302 can both form a super junction 309, which will not be repeated here.

[0072] Based on the same inventive concept, the embodiment of the present application also provides a first silicon carbide transistor manufacturing method, and the implementation principle of the manufacturing method is similar to the implementation principle of the above-mentioned silicon carbide transistor. The specific implementation manner of the manufacturing method can be referred to the above-mentioned embodiments of the silicon carbide transistor, and the repeated parts will not be repeated here.

[0073] Specifically, the manufacturing method of the silicon carbide transistor provided by the embodiment of the present application includes the following steps, which can be referred to the structure shown in Figure 10 .

[0074] S201: Forming a silicon carbide layer on the substrate 100.

[0075] In the implementation process, the following can be included: using a chemical vapor deposition (CVD) process, using methane or propane as a material growth gas, and using hydrogen as a carrier gas to epitaxially grow a silicon carbide layer. Of course, the silicon carbide layer can also be obtained by other methods known to those skilled in the art, which is not limited here.

[0076] Referring to Figure 11As shown, the buffer layer 200, the drift layer 300 and the source contact layer 400 are sequentially formed on the substrate 100 by multiple epitaxy.

[0077] S202: Etching a gate trench 301 on the side surface of the silicon carbide layer away from the substrate 100.

[0078] The specific process can include: depositing a hard mask layer on the side surface of the silicon carbide layer away from the substrate 100, and the hard mask layer can be one of silicon dioxide, silicon nitride or a metal layer. After the hard mask layer is deposited, the hard mask layer is patterned using a mask, and then a deep trench is etched on the side surface of the silicon carbide layer away from the substrate 100 by dry etching, to form the gate trench 301, as shown in Figure 12 For the gate trench 301: the depth d4 of the gate trench 301 is between 0.5 and 5 um; and the lateral size of the mesa between the current etched gate trench 301 and the adjacent gate trench 301 is also ensured, for example, the above lateral size d5 is between 0.3 and 2 um.

[0079] S203: Epitaxially forming a first doped silicon carbide 302 on the bottom of the gate trench 301.

[0080] The specific process can include: epitaxial backfilling of silicon carbide in the formed gate trench 301, and a standard silicon carbide epitaxy process is used in the backfilling process: silane, propane and hydrogen are used as carrier gas, trimethylaluminum is used as doped source gas, the silicon-carbon ratio in the source gas is 1:1, the growth temperature is 1650°C, the pressure is 60kPa, and the growth time is 3-6h. In order to etch the surface of the gate trench 301 during epitaxial backfilling and prevent the gate trench 301 from closing too early during backfilling, while ensuring that the thickness of the backfilled silicon carbide is small, hydrogen chloride is also added to the above carrier gas. During the backfilling process, the gas flow rates of silane, propane, hydrogen chloride and hydrogen are 36sccm, 12sccm, 1.8slm and 40slm respectively.

[0081] Thus, the silicon carbide layer formed on the bottom of the gate trench 301 is the first doped silicon carbide 302, as shown in Figure 13 .

[0082] In one embodiment, when the first doped silicon carbide 302 is formed, a second doped silicon carbide 305 is epitaxially formed on the side of the source contact layer 400 away from the substrate 100.

[0083] In the epitaxial backfill process, the first doped silicon carbide 302 is formed at the bottom of the gate trench 301, and the silicon carbide layer epitaxially formed on the side of the source contact layer 400 away from the substrate 100, i.e., the silicon carbide layer formed by the mesa, is referred to as the second doped silicon carbide 305. The second doped silicon carbide 305 is formed by the process shown in Figure 14 .

[0084] Correspondingly, when the second doped silicon carbide 305 is formed, the third doped silicon carbide 306 is epitaxially formed on the sidewall of the gate trench 301.

[0085] Optionally, before the gate 303 and the auxiliary electrode 304 are formed, the second doped silicon carbide 305 is etched to form a via hole, the via hole penetrates the second doped silicon carbide 305 and exposes the source contact layer 400, i.e., the corresponding region Z1 of the top of the mesa is exposed through the via hole. Figure 14

[0086] The specific process of forming the via hole includes: depositing a hard mask layer on the surface of the first doped silicon carbide 302, and then performing the steps of spin-coating photoresist, exposure, development, and curing, and then etching the via hole in the hard mask layer. Unlike the solution in the related art that completely opens the entire mesa and removes it by etching, the via hole etched on the mesa is small during the etching process, which reduces the requirements for the steps of photolithography and etching in the semiconductor process, thereby increasing the process compatibility of the solution.

[0087] Further, in order to make the size of the source 308 of the formed silicon carbide transistor smaller, the specific process can include: depositing a hard mask layer on the surface of the first doped silicon carbide 302 and the third doped silicon carbide 306, the hard mask layer can be one of silicon dioxide, silicon nitride, a metal layer, or spin-on glass, and the hard mask layer is patterned, and then the hard mask layer is etched, and only part of the second doped silicon carbide 305 is left in the mesa.

[0088] It should be noted that, in the etching process, the region on the top of the mesa is etched to stop at an angle a between the sidewall of the source contact layer 400 and the vertical direction, as shown in Figure 14 , 0° < a < 90°.

[0089] Optionally, as shown in Figure 15 ​As shown, to form the insulating structure 307 in the U-shaped cavity, the specific process can include: using a silicon dioxide film deposition process to perform oxide deposition on the inside of the gate trench 301 again, for example, the oxide deposition can be performed by using low pressure chemical vapor deposition (LPCVD), so as to realize that the sidewall of each gate trench 301 presents two opposite spacing areas, i.e., the insulating structure 307 in the U-shaped cavity formed by the first doped silicon carbide 302 and the third doped silicon carbide 306.

[0090] S204: sequentially forming the gate 303 and the auxiliary electrode 304 on the surface of the first doped silicon carbide 302.

[0091] Here, the forming process of the source 308 of the silicon carbide transistor is introduced first. An ohmic metal layer, for example, metal nickel, is deposited on the surface of the mesa, and the thickness of the deposited ohmic metal layer is 30-100 nm. Then, a rapid thermal annealing process is used, for example, the temperature is controlled to be 1000°C and the time is controlled to be 2 min during the rapid annealing process of the deposited metal layer.

[0092] Since the metal nickel does not react with the oxide, the silicide formed on the top of the mesa is the source 308. Finally, the wet process is used to remove the excess metal nickel. In the case that the via penetrates the second doped silicon carbide 305 and exposes the source contact layer 400, refer to Figure 16 As shown, if the silicide formed on the top region of the mesa is directly used as the source 308, and the silicide on the bottom of the gate trench 301 is directly used as the gate 303, the source 308 and the gate 303 will be short-circuited through the third doped silicon carbide 306, thereby causing the failure of the source 308 and the gate 303.

[0093] Based on this, the silicide on the top region of the mesa is further subjected to photolithography and etching, so that the excess part of the silicon carbide of the source 308 can be removed, and the source 308 is formed in the via, so that the source 308 is connected with the source contact layer 400. The process of removing the excess part of the silicon carbide of the source 308 includes: spin-coating photoresist on the surface of the silicide on the top region of the mesa, and the remaining photoresist 310 after the exposure and development process is refered to Figure 17 As shown.

[0094] It should be noted that in the process of etching the insulating structure 307 in the U-shaped cavity, a hydrofluoric acid-based solution wet etching or a hydrofluoric acid vapor etching can be used. The hydrofluoric acid reacts with the silicon dioxide in the insulating structure 307 to form soluble hexafluorosilicic acid, but the etching rate of silicon (including polysilicon) is extremely low, so that the insulating structure 307 can be effectively removed, and the U-shaped cavity is not affected by the etching process.

[0095] In order to further eliminate the risk of short circuit between the source 308 and the gate 303 of the silicon carbide transistor, a vertical dry etching is performed to remove the silicon carbide except the part covered by the photoresist, and to retain the silicide covering the via and the silicide at the bottom of the gate trench 301. Then, the remaining photoresist 310 mask on the surface of the device is removed, so that the remaining silicide in the top region of the mesa is removed. Referring to Figure 4 , the risk of direct short circuit between the source 308 and the gate 303 is eliminated.

[0096] Then, a further medium layer 600 is backfilled on the surface of the device, for example, a spin-on glass, to fill the trench area of the device again. A mask is used to pattern the contact window to the source 308 and the gate 303. Then, the window is cleared by etching. It should be noted that the source 308 is connected to the gate 303 outside the mesa and the trench area through interconnection. An opening is made on the medium layer 600, and a thick metal layer 700 is filled on the surface of the device. The thick metal layer 700 on the surface is etched again by a mask to divide the source metal contact area and the drain metal contact area.

[0097] Similarly, in order to form the gate 303 of the silicon carbide transistor, an ohmic metal layer, for example, nickel, is deposited on the surface of the first doped silicon carbide 302, so that a silicide is formed on the surface of the first doped silicon carbide 302, which is the gate 303. Referring to Figure 16 , the gate 303 is formed. Since the nickel does not react with the insulating structure 307 in the U-shaped cavity, the source 308 and the gate 303 are isolated.

[0098] The gate trench 301 in which the gate 303 has been formed is continuously backfilled with at least part of the conductive material, for example, the conductive material is polysilicon. Then, the filled conductive material is etched back, and the distribution of the remaining conductive material is shown in Figure 4 . The remaining conductive material is the auxiliary electrode 304, which is formed on the gate 303 on the surface of the first doped silicon carbide 302. The auxiliary electrode 304 is conductively interconnected with the gate 303, so that the overall gate resistance is smaller, thereby improving the switching speed of the silicon carbide transistor.

[0099] See Figure 4 As shown, after forming the source 308 and gate 303 of the silicon carbide transistor, contact windows are further formed for the source 308 and gate 303. The specific process may include: depositing a dielectric layer 600 on the surface of the device (including the source 308, gate 303, and the insulating structure 307 within the aforementioned U-shaped cavity, etc.), for example, the dielectric layer 600 is spin-coated glass. A mask is then used to pattern the contact windows of the source 308 and gate 303. Then, the dielectric layer 600 is etched using an etching process to form the windows of the source 308 and gate 303, respectively.

[0100] A metal layer 700 is deposited on the surface of the device, and then the metal layer 700 on the surface is etched through a mask to separate the source metal contact area and the drain metal contact area. A back metallization layer 500 is formed on the bottom of the substrate 100 of the device, thus completing the fabrication of the entire silicon carbide transistor.

[0101] It should be added here that, such as Figure 18 As shown, the positions indicated by dashed boxes 1 to 6 are the openings of the source metal contact area. The openings indicated by dashed boxes 1 and 4 are spaced apart, as are the openings indicated by dashed boxes 2 and 5, and the openings indicated by dashed boxes 3 and 6. The openings indicated by dashed boxes 1, 2, and 3 on line AA' are aligned in a direction perpendicular to line AA'. Similarly, the openings indicated by dashed boxes 4, 5, and 6 are aligned in a direction perpendicular to line AA'.

[0102] like Figure 19 As shown, the dashed boxes 7 to 9 indicate the openings of the source metal contact area. The opening indicated by dashed box 7 extends in a direction perpendicular to the BB' line, the opening indicated by dashed box 8 extends in a direction perpendicular to the BB' line, and the opening indicated by dashed box 9 extends in a direction perpendicular to the BB' line. The openings indicated by dashed boxes 7, 8, and 9 on the BB' line are aligned horizontally in a direction perpendicular to the BB' line. Furthermore, Figure 19 The diagram also shows an N-type doped region 800, for example, an N+ doped region, in... Figure 19 The orthographic projection of the N+ doped region 800 on the substrate coincides with the orthographic projection of the gate on the substrate.

[0103] like Figure 20As shown, the dashed positions indicated by the dashed boxes 10-16 are openings of the source metal contact regions, the openings indicated by the dashed box 10 and the openings indicated by the dashed box 13 are arranged in an interval, the openings indicated by the dashed box 11, the openings indicated by the dashed box 14 and the openings indicated by the dashed box 15 are arranged in an interval, the openings indicated by the dashed box 12 and the openings indicated by the dashed box 16 are arranged in an interval, the adjacent openings indicated by the dashed box 10 and the dashed box 11 on the CC' line are staggered in a direction perpendicular to the CC' line, similarly, the adjacent openings indicated by the dashed box 13 and the dashed box 14 on the CC' line are staggered in a direction perpendicular to the CC' line, the adjacent openings indicated by the dashed box 15 and the dashed box 16 on the CC' line are staggered in a direction perpendicular to the CC' line, the interval openings indicated by the dashed box 10 and the dashed box 12 on the CC' line are arranged in a line in a direction perpendicular to the CC' line, similarly, the interval openings indicated by the dashed box 13 and the dashed box 16 on the CC' line are arranged in a line in a direction perpendicular to the CC' line. In addition, Figure 20 The N-type doped region 800, for example, an N+ doped region, is also shown in the figure. Figure 20 In the figure, the length of the N+ doped region in the third direction is not more than the length of the first doped silicon carbide 302 in the third direction.

[0104] In addition, a channel region is also formed between the backfill regions, and in the implementation process, an angled ion implantation is used to realize two high-doped charge regions inside the channel region, for example, with a lateral size of 0.2 μm and a doping concentration of 1e17 / cm3. A very low doping, for example, 1e15 / cm3, is used for the center layer of the channel, so as to reduce the influence of the fluctuation of the carrier concentration of the channel core layer and the lateral size of the mesa width on the threshold voltage of the silicon carbide transistor due to process fluctuation.

[0105] Based on the same inventive concept, refer to Figure 21 As shown, the electronic device provided by the embodiment of the present application comprises the silicon carbide transistor as described above.

[0106] The specific application scenarios of the electronic device described above include, but are not limited to, vehicle-mounted chips, high-voltage inverters, charging piles, high-voltage photovoltaics, etc.

[0107] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. A silicon carbide transistor, characterized by, The application relates to a silicon carbide transistor, which comprises a substrate and a silicon carbide layer arranged on the substrate; the silicon carbide layer comprises a buffer layer, a drift layer and a source contact layer arranged on the substrate in sequence; a gate trench is arranged on a side surface of the silicon carbide layer away from the substrate, the bottom of the gate trench is located in the drift layer, the bottom of the gate trench is filled with first doped silicon carbide, the surface of the first doped silicon carbide is sequentially stacked with a gate and an auxiliary electrode, the auxiliary electrode is connected with the gate, the gate and the auxiliary electrode comprise different materials, the gate comprises nickel silicide, and the auxiliary electrode comprises polysilicon; the silicon carbide transistor further comprises second doped silicon carbide and third doped silicon carbide; the second doped silicon carbide is arranged on a side of the source contact layer away from the substrate, and at least part of the surface of the source contact layer is exposed by the second doped silicon carbide; the third doped silicon carbide is located in the gate trench and is connected between the first doped silicon carbide and the second doped silicon carbide; a source is arranged on the at least part of the surface of the source contact layer exposed by the second doped silicon carbide; the first length of the source in a first direction in a reference surface is greater than the second length of the source in the first direction in the reference surface; an N-type doped region is arranged on a side of the first doped silicon carbide away from the bottom of the gate trench in a third direction; the N-type doped region extends in the third direction; the third direction is perpendicular to the first direction and the second direction; at least one N-type doped part is arranged in the N-type doped region; the N-type doped part is arranged in a plurality of forms; the N-type doped parts are arranged in the third direction in a spaced manner; the first doped silicon carbide is P-type silicon carbide; the drift layer and the first doped silicon carbide form a super junction; the reference surface is a plane formed by the intersection of the first direction and the second direction; the first direction is parallel to the surface of the substrate; the second direction is the direction of the substrate pointing to the source contact layer; the first length is the length of the source on a side of the reference surface away from the source contact layer; and the second length is the length of the source on a side of the reference surface towards the source contact layer. The silicon carbide transistor further comprises second doped silicon carbide and third doped silicon carbide; the second doped silicon carbide is arranged on a side of the source contact layer away from the substrate; and the third doped silicon carbide is located in the gate trench and is connected between the first doped silicon carbide and the second doped silicon carbide; the first doped silicon carbide and the third doped silicon carbide form a U-shaped cavity; the silicon carbide transistor further comprises an insulating structure filled in the U-shaped cavity; the gate covers part of the surface of the first doped silicon carbide; and the insulating structure covers the remaining surface of the first doped silicon carbide. The N-type doped part comprises an N+ type doped region; or the N-type doped part comprises an N+ type doped region and an N- type doped region stacked in the second direction. ​ ​ ​ 2. The silicon carbide transistor of Claim 1 wherein, ​ ​ 3. The silicon carbide transistor of Claim 1 wherein, ​ 4. The silicon carbide transistor of Claim 1 wherein, The length of the N-type doped region along a first direction is equal to the length of the gate along the first direction, the first direction being perpendicular to the third direction and the second direction respectively.

5. The silicon carbide transistor of Claim 1 wherein, The length of the N-type doped region along a first direction is equal to the length of the gate trench along the first direction, the first direction being perpendicular to the third direction and the second direction respectively.

6. A method of fabricating a silicon carbide transistor as claimed in any one of claims 1 to 5, wherein, The method comprises: forming a silicon carbide layer on a substrate; etching the gate trench on a side surface of the silicon carbide layer away from the substrate; forming the first doped silicon carbide epitaxially on the bottom of the gate trench; forming a gate and an auxiliary electrode on the surface of the first doped silicon carbide in sequence.

7. An electronic device, characterized by The method comprises: The silicon carbide transistor according to any one of claims 1-5.

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