Semiconductor structure, method of manufacturing the same, and semiconductor device
By designing a concave work function layer in the semiconductor structure and covering it with a protective layer, the defect problem generated by the metal gate during the grinding process was solved, ensuring the stability of device performance and chip yield.
Patent Information
- Application Number
- CN202511632337.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2045-11-10
AI Technical Summary
During the formation of metal gates, due to the soft hardness and active properties of the gate material, defects such as particle residue, scratches, and corrosion are easily generated during chemical mechanical polishing, which affect the performance of the device.
The semiconductor structure design includes a substrate, dielectric stack, work function stack, and barrier layer. A concave structure is formed by selective etching, and a continuous sealed protective layer is formed on the surface of the work function layer to isolate it from the etching solution during subsequent CMP and wet cleaning processes.
This effectively avoids threshold voltage drift and gate leakage caused by physical damage or chemical corrosion to the work function layer, thus improving chip yield and reliability.
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Figure CN121078782B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a preparation method thereof, and a semiconductor device. BACKGROUND
[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly realized by continuously reducing the size of integrated circuit devices to improve its speed. In advanced chip manufacturing, a high dielectric parameter metal gate (HK-MG) process is widely used to improve chip performance, in which a plurality of work function metals can be selected to adjust the threshold voltage of the metal gate.
[0003] However, in the process of forming the metal gate, due to the soft hardness and active properties of the gate material, defects such as particle residues, scratches, and corrosion are easily generated in chemical mechanical polishing (CMP), which destroys the original morphology of the gate in subsequent processes, thereby affecting the performance of the device. SUMMARY
[0004] Therefore, it is necessary to provide a semiconductor structure, a preparation method thereof, and a semiconductor device to at least maintain the morphology of the gate in subsequent polishing processes to solve the technical problems in the prior art.
[0005] In a first aspect, the present application provides a semiconductor structure, comprising: a substrate, a first surface of the substrate comprising interlayer dielectric layers and metal gates alternately arranged along a first direction parallel to the first surface; the metal gate comprising:
[0006] a dielectric stack, penetrating the interlayer dielectric layer along a direction towards the substrate via a top surface of the metal gate;
[0007] a work function stack, extending into the dielectric stack via the top surface of the metal gate, and a bottom surface thereof being within the bottom surface of the dielectric stack in a projection on the first surface; the work function stack comprising a work function layer and a protection layer arranged in a second direction away from the substrate;
[0008] a barrier layer, penetrating the protection layer along a direction towards the substrate via the top surface of the metal gate and extending into the work function layer, and a bottom surface thereof being within the bottom surface of the work function layer in a projection on the first surface;
[0009] a metal conductive layer, extending into the barrier layer via the top surface of the metal gate.
[0010] In the semiconductor structure in the above embodiment, the protection layer covers the top surface of the work function layer, so that the longitudinal section of the work function layer is in the shape of a concave character, and the whole metal gate is embedded, thereby effectively avoiding direct contact between the etching solution and the work function layer when the etching solution penetrates along the defects or damage on the surface of the cover layer after the subsequent process of grinding, ensuring the integrity of the work function layer morphology and avoiding the influence of the threshold voltage of the metal gate.
[0011] In some embodiments, the dielectric stack includes a first dielectric layer, a second dielectric layer arranged in sequence along a second direction;
[0012] The first dielectric layer is located on the top surface of the substrate;
[0013] The second dielectric layer is located on the top surface of the first dielectric layer;
[0014] The work function stack extends into the second dielectric layer through the top surface of the metal gate.
[0015] In some embodiments, the substrate includes a first active region, a second active region arranged along a first direction;
[0016] The second dielectric layer in the first active region is the same as or different from the second dielectric layer of the second active region.
[0017] In some embodiments, the protection layer is prepared synchronously with the second dielectric layer in the first active region in the same process step.
[0018] In a second aspect, the application provides a semiconductor structure preparation method for preparing the semiconductor structure as described in any one of the above embodiments, including: providing a substrate;
[0019] Providing a substrate, the substrate including interlayer dielectric layers and initial metal gates arranged alternately along a first direction parallel to a first surface;
[0020] Forming a work function stack in the initial metal gate, and the remaining initial metal gate and the work function stack are used to form a metal gate; the metal gate further includes: a dielectric stack, a barrier layer, and a metal conductive layer;
[0021] The dielectric stack penetrates the interlayer dielectric layer along a direction towards the substrate through the top surface of the metal gate;
[0022] The work function stack extends into the dielectric stack through the top surface of the metal gate, and the bottom surface thereof is projected onto the bottom surface of the dielectric stack; the work function stack includes a work function layer and a protection layer arranged in sequence along a second direction away from the substrate;
[0023] The barrier layer penetrates the protection layer and extends into the work function layer along a direction towards the substrate through the top surface of the metal gate, and the bottom surface thereof is projected onto the bottom surface of the work function layer;
[0024] The metal conductive layer extends into the barrier layer via the top surface of the metal gate.
[0025] In the preparation method in the above embodiment, the initial work function layer is partially removed by selective etching to form a concave structure, which ensures that the top surface of the work function layer is lower than the top surface of the metal gate. The protection layer completely wraps the work function layer of the concave structure, avoiding the exposure of the work function layer to the top surface of the metal gate in the related art, thereby blocking the penetration path of the subsequent etching solution, and the work function layer at the bottom of the gate is not affected, so that the threshold voltage is not affected.
[0026] In some embodiments, the initial metal gate comprises: a dielectric stack, a barrier layer, a metal conductive layer, and an initial work function layer.
[0027] The initial work function layer extends into the dielectric stack via the top surface of the initial metal gate, and the bottom surface thereof is located within the bottom surface of the dielectric stack in the orthogonal projection of the first surface.
[0028] The barrier layer extends into the work function layer via the top surface of the initial metal gate in a direction towards the substrate and penetrates the protection layer, and the bottom surface thereof is located within the bottom surface of the work function layer in the orthogonal projection of the first surface.
[0029] In some embodiments, the formation of the protection layer comprises:
[0030] The target gas is used to remove part of the initial work function layer to obtain grooves arranged at intervals along the first direction; the grooves extend into the initial work function layer via the top surface of the initial metal gate, and the bottom surface is not lower than the bottom surface of the barrier layer.
[0031] In some embodiments, the formation of the metal gate comprises:
[0032] A protection material layer is formed on the top surface of the interlayer dielectric layer and in the grooves.
[0033] Part of the protection material layer is removed to obtain a protection layer that fills the grooves, and the remaining initial metal gate and the protection layer are used to constitute the metal gate.
[0034] In some embodiments, the use of the target gas to remove part of the initial work function layer comprises:
[0035] The target gas comprising hydrogen fluoride and ammonia is used to remove part of the initial work function layer, and the remaining initial work function layer is used to constitute the work function layer of the metal gate.
[0036] In a third aspect, the present application also provides a semiconductor device comprising the semiconductor structure as described in any one of the above embodiments; or a semiconductor structure formed by the preparation method as described in any one of the above embodiments.
[0037] In the semiconductor device in the above embodiment, threshold voltage drift, gate leakage and other key failure problems caused by physical damage or chemical corrosion of the work function layer can be effectively avoided, chip manufacturing defects are reduced from the source, and reliable guarantee is provided for the improvement of chip yield.
[0038] The semiconductor structure, the preparation method thereof and the electronic device provided in the application have the following unexpected technical effects:
[0039] In the process, the work function layer in the concave shape is accurately molded by selective etching, and a continuous and sealed protective layer is formed on the surface and sidewall of the work function layer by conformal coating process, so as to isolate the etching solution in subsequent CMP, wet cleaning and other processes, effectively guarantee the integrity of the work function layer, avoid device failure, and thus significantly improve the chip yield. BRIEF DESCRIPTION OF DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.
[0041] Figure 1a It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0042] Figure 1b It is a schematic diagram of a preparation process of a semiconductor structure in the related art; Figure 1a It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0043] Figure 2 It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0044] Figure 3 It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0045] Figure 4 It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0046] Figure 5a It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0047] Figure 5b It is a schematic diagram of a preparation process of a semiconductor structure in the related art; Figure 5a It is a schematic diagram of a preparation process of a semiconductor structure in the related art;
[0048] Figure 6A cross-sectional schematic view of the structure obtained after forming the recess in step S302 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0049] Figure 7 A cross-sectional schematic view of the structure obtained after forming the protection layer in step S304 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0050] Figure 8 A cross-sectional schematic view of the structure obtained after forming the metal gate in step S108 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0051] Figure 9 A comparison schematic view of the semiconductor structure provided in the present application and the semiconductor structure provided in the related art.
[0052] Explanation of reference signs:
[0053] 10, substrate; 11, interlayer dielectric layer; 12, gate trench; 20, dielectric stack; 21, first dielectric layer; 22, second dielectric layer; 201, first dielectric material layer; 202, second dielectric material layer; 203, third dielectric material layer; 204, fourth dielectric material layer; 205, fifth dielectric material layer; 30, work function stack; 31, work function layer; 32, protection layer; 311, initial work function layer; 321, recess; 322, protection material layer; 40, barrier layer; 50, metal conductive layer. DETAILED DESCRIPTION
[0054] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application is more thorough and complete.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein only for the purpose of describing the specific embodiments of the present application, and is not intended to limit the present application.
[0056] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.
[0057] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0058] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, use of the term "and / or" includes any and all combinations of associated items.
[0059] Embodiments of the application will be described with reference to cross-sectional illustrations that are schematic representations of ideal embodiments (and intermediate structures) of the application. Variations to the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.
[0060] As shown in the process flow as Figure 1a In the process of forming the gate structure by grinding, the grinding particles and the grinding liquid residues are easy to adhere and gather on the top surface of the gate, forming particle contaminants. In the dry etching step of the high resistivity (HiR) process, the surface of the cover layer forms local stress concentration or uneven etching due to the particle residues, resulting in defects such as pinholes and cracks in the cover layer, which destroys the continuity of the cover layer, causing the work function layer below to be directly exposed. When entering the subsequent wet etching process, although the gate metal layers are filled normally, the etching solution will penetrate to the work function layer along the channels formed by the defects of the cover layer. Since the etching rate of the etching solution to the work function layer material is significantly higher than that of the metal layer, the solution will continue to corrode along the sidewall of the work function layer, eventually causing the bottom work function layer to be partially missing, forming a void, as shown in the specific structure as Figure 1b which directly leads to the electrical performance failure of the device, such as threshold voltage drift and gate leakage, seriously affecting the chip yield and reliability.
[0061] Based on this, please refer to Figure 2 In the embodiments of the present application, the substrate can include a first surface located on the front surface, and a back surface opposite to the front surface, i.e. a second surface. In the case of ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and a direction away from the substrate includes a second direction perpendicular to the first surface of the substrate. In the embodiments of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.
[0062] The semiconductor structure includes: a substrate 10, a first surface 10a of the substrate 10 includes an interlayer dielectric layer 11 and a metal gate alternately arranged along the OY direction; the metal gate includes:
[0063] A dielectric stack 20 penetrates the interlayer dielectric layer 11 along the ZO direction (the opposite direction of the OZ direction) through the top surface of the metal gate;
[0064] The work function layer 30 extends into the dielectric layer 20 through the top surface of the metal gate, and the bottom surface of the work function layer 30 is located within the bottom surface of the dielectric layer 20 in the orthographic projection of the first surface 10a; the work function layer 30 comprises a work function layer 31 and a protective layer 32 arranged in sequence along the OZ direction.
[0065] The barrier layer 40 extends into the work function layer 31 through the top surface of the metal gate along the ZO direction and penetrates the protective layer 32, and the bottom surface of the barrier layer 40 is located within the bottom surface of the work function layer 31 in the orthographic projection of the first surface 10a.
[0066] The metal conductive layer 50 extends into the barrier layer 40 through the top surface of the metal gate.
[0067] For example, the substrate 10 comprises a first active region A and a second active region B arranged along the OY direction.
[0068] In the embodiment, the first active region A is a P-type active region, and the second active region B is an N-type active region. Of course, other electrical or isolation structures can also be included in the active region, which is a known technology of the metal gate process, and the specific structure is not described in detail.
[0069] Further, in some embodiments, the dielectric layer 20 comprises a first dielectric layer 21 and a second dielectric layer 22; the first dielectric layer 21 is located on the top surface of the substrate 10; the second dielectric layer 22 is located on the top surface of the first dielectric layer 21; and the work function layer 30 extends into the second dielectric layer 22 through the top surface of the metal gate.
[0070] For example, the second dielectric layer 22 in the first active region A is the same as or different from the second dielectric layer 22 in the second active region B.
[0071] The semiconductor structure in the above embodiment can be compared with the semiconductor structure of the related art in Figure 1a When compared with the semiconductor structure of the related art in the present application, the protective layer completely covers the top surface of the work function layer, so that the work function layer is embedded in the metal gate. When the subsequent wet etching process is performed, even if the top surface of the gate covers the layer and the etching solution penetrates to the surface of the protective layer through the defect channel, the etching solution cannot continue to erode downward due to the physical barrier and chemical inertness of the protective layer, thereby ensuring the structural integrity of the work function layer inside the gate. Compared with the structure in which the target work function layer is partially exposed in the prior art, the penetration path of the etching solution is effectively blocked, the risk of missing the target work function layer is effectively reduced, and the reliability of the semiconductor structure is improved.
[0072] In some embodiments, the protective layer 32 and the second dielectric layer 22 located in the first active region A are prepared synchronously in the same process step, please refer to Figures 3-9 On the other hand, the present application provides a preparation method of a semiconductor structure, which is used for preparing the semiconductor structure as Figure 2The semiconductor structure and the work function layer inside it are shown in Figure 3 The method comprises steps S102-S104.
[0073] Step S102: providing a substrate 10; the substrate comprises, along the OY direction, alternating interlayer dielectric layers 11 and initial metal gates;
[0074] Step S104: forming a work function layer 30 in the initial metal gate, and the remaining initial metal gate and the work function layer 30 are used to form a metal gate; the metal gate further comprises: an interlayer dielectric layer 20, a barrier layer 40, and a metal conductive layer 50.
[0075] The interlayer dielectric layer 20 penetrates the interlayer dielectric layer 11 along the ZO direction (the opposite direction of the OZ direction) through the top surface of the metal gate; the work function layer 30 extends into the interlayer dielectric layer 20 through the top surface of the metal gate, and the bottom surface of the work function layer 30 is located within the bottom surface of the interlayer dielectric layer 20 in the orthographic projection of the first surface 10a; the work function layer 30 comprises, along the OZ direction, a work function layer 31 and a protective layer 32 arranged in sequence; the barrier layer 40 penetrates the protective layer 32 along the ZO direction through the top surface of the metal gate and extends into the work function layer 31, and the bottom surface of the barrier layer 40 is located within the bottom surface of the work function layer 31 in the orthographic projection of the first surface 10a; the metal conductive layer 50 extends into the barrier layer 40 through the top surface of the metal gate.
[0076] The semiconductor structure obtained after steps S102-S104 can be seen in Figure 2 In order to facilitate the understanding of the present application, Figures 4 to 9 is a schematic diagram of each step of an exemplary semiconductor structure preparation method provided by the embodiments of the present application, wherein Figure 4 An example of the semiconductor structure prepared by the preparation method of the present application can also have other suitable examples, which are not limited by the present application. The following will be described in detail Figures 4 to 9 The semiconductor structure provided by the embodiments of the present application will be described in detail.
[0077] Please refer to Figures 4-5b Step S102 further comprises:
[0078] Please refer to Figure 4 Step S202: forming an interlayer dielectric layer 11 on the top surface of the substrate 10 by a deposition process, and then performing a photolithography and etching process to form gate trenches 12 spaced apart along the OY direction in the interlayer dielectric layer 11.
[0079] For example, substrate 10 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1). x As, Ga x Al 1-x N、In x Ga 1-x As, etc.) or combinations thereof. The substrate 10 may include other device structures (not shown), such as isolation trench structures. Those skilled in the art can select the substrate specifically according to the transistor type, therefore the type of substrate should not limit the scope of protection of this application.
[0080] For example, the interlayer dielectric layer 11 is typically a dielectric material, including but not limited to silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiO2). x N y )wait.
[0081] In this embodiment, as described above, the substrate 10 is made of silicon (Si) and includes a P-type first active region A and an N-type second active region B arranged along the OY direction.
[0082] Please see Figure 5a and Figure 5b Step S204: A first dielectric material layer 201 located at the bottom of the gate trench 12 is formed sequentially in the gate trench 12 by a deposition process, a second dielectric material layer 202 and a third dielectric material layer 203 are stacked on the top surface of the first dielectric material layer 201, and a fourth dielectric material layer 204 is formed covering the remaining inner wall of the gate trench 12 and the top surface of the third dielectric material layer 203.
[0083] After further forming a fifth dielectric material layer 205 in the gate trench 12 corresponding to the first active region A, an initial work function layer 311, a barrier layer 40, and a metal conductive layer 50 are then formed in the gate trench 12 using a deposition process. After chemical mechanical polishing of the above embodiment, the following is obtained: Figure 5a The initial metal gate is shown. Figure 5a As shown, the initial work function layer 311 extends into the second dielectric layer 22 via the top surface of the initial metal gate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the second dielectric layer 22.
[0084] The barrier layer 40 extends into the initial work function layer 311 via the top surface of the initial metal grid, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the initial work function layer 311.
[0085] For example, the material of the first dielectric material layer 201 includes, but is not limited to, silicon oxide (SiO2) and silicon oxynitride (SiO2). x N y (or hafnium-based oxides such as HfSiO)
[0086] For example, the material of the second dielectric material layer 202 includes, but is not limited to, materials with a high k dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), titanium oxide (TiO2), or silicon oxide (SiO2); the material of the barrier layer 40 includes, but is not limited to, silicon oxide (SiO2), doped oxides (such as silicon phosphosilicate glass (PSG), borosilicate glass (BPSG)), or silicon nitride (SiN), etc., mainly used to improve the capacitance value of the device and reduce power consumption. The specific physical thickness can be determined by the performance requirements of the device.
[0087] For example, the materials of the third dielectric material layer 203, the fourth dielectric material layer 204 and the fifth dielectric material layer 205 include, but are not limited to, metal nitrides, such as titanium nitride (TiN) or tantalum nitride (TaN).
[0088] For example, the material of the initial work function layer 311 includes, but is not limited to, titanium carbide (TiC), tantalum carbide (TaC), tantalum gold (Ta-Au) alloy, titanium aluminum (TiAl), tantalum copper (Ta-Cu), titanium aluminum carbide (TiAlC) or tantalum nitride (TaN) or combinations thereof.
[0089] For example, the barrier layer 40 is made of a composite layer of titanium nitride and titanium (TTN), which is mainly used to improve the capacitance of the transistor and enhance its ability to drive current. It can also be used as a diffusion barrier layer to prevent the material forming the metal conductive layer 50 from diffusing into the underlying dielectric layer.
[0090] For example, the material of the metal conductive layer 50 includes, but is not limited to, at least one of aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), and platinum (Pt). In this embodiment, the material of the metal conductive layer 50 is Al.
[0091] In this embodiment, titanium aluminum compound (TiAl) is selected as the initial work function layer 311, which has a suitable work function value and can effectively regulate the threshold voltage of the device. Of course, the choice of material for the initial work function layer is not limited to this; other materials can also be selected. The key is that when etching with the target gas, the etching rate of the initial work function layer material must be significantly higher than that of the fourth dielectric layer, the fifth dielectric layer, the barrier layer, and the metal conductive layer to form a sufficient etching selectivity. This effectively protects the underlying and lateral barrier layer structures when removing part of the initial work function layer material, avoiding adverse effects on device performance. This matching design of material selection and etching process provides a flexible process window for device manufacturing.
[0092] In addition, in this embodiment, the first dielectric material layer 201, the second dielectric material layer 202, and the third dielectric material layer 203 together constitute the first dielectric layer 21, as shown in the structure. Figure 5a As shown; the fourth dielectric material layer 204 and the fifth dielectric material layer 205 together constitute the second dielectric layer 22 of the first active region A; the fourth dielectric material layer 204 alone constitutes the second dielectric layer 22 of the second active region B.
[0093] TiN is used as the third dielectric material layer 203 and TaN is used as the fourth dielectric material layer 204. Together, they form a double diffusion barrier structure to prevent the work function layer material from diffusing into the device. TiN is used as the fifth dielectric material layer 205 to increase the work function of the first active region A of the P-type, adjust the threshold voltage, and improve the electrical characteristics of the device.
[0094] Please see Figures 6-8 Step S104 further includes:
[0095] Please see Figure 6 Step S302: A portion of the initial work function layer 311 is removed using the target gas to obtain grooves 321 spaced apart along the OY direction. The grooves 321 extend into the initial work function layer from the top surface of the initial metal grid, and their bottom surface is not lower than the bottom surface of the barrier layer 40. The grooves 321 are located between the barrier layer 40 and the dielectric stack 20. The remaining initial work function layer is used to construct the work function layer 31.
[0096] Furthermore, the target gases include hydrogen fluoride (HF) and ammonia (NH3) to remove part of the initial work function layer within the gate trench, resulting in... Figure 7 The work function layer 31 is then annealed onto the substrate 10 to remove reaction byproducts and repair interface defects.
[0097] For example, at radio frequency (RF) power, a mixture of hydrogen fluoride (HF) and ammonia (NH3) dissociates to form NH4F, containing F. -The etching rate of the group on the initial work function layer (such as TiAl) is significantly higher than that on the second dielectric layer 22, the barrier layer 40 (such as TTN) and the metal conductive layer 50 (Al), thus enabling selective removal of the initial work function layer in the gate trench portion.
[0098] Of course, other target gases can be selected. As mentioned above, it is only necessary to ensure that the etching rate of the target gas on the initial work function layer material is significantly higher than the etching rate of other exposed film layers to form a sufficient etching selectivity.
[0099] In the above embodiments, the annealing process for removing byproducts can be completed within the same process chamber, without adding any additional processes and reducing process costs. The bottom surface of the groove is not lower than the barrier layer primarily to ensure that a sufficient work function layer is retained within the metal gate, so as not to affect the performance of the formed semiconductor device.
[0100] Please see Figure 7 Step 304: A protective material layer 322 covering the interlayer dielectric layer 11 and the initial metal gate is formed using atomic layer deposition (ALD) process; the protective material layer 322 fills the groove.
[0101] For example, the material of the protective material layer 322 includes, but is not limited to, metal nitrides. In this embodiment, TiN is used as the protective material layer.
[0102] Please see Figure 8 Step 306: The protective material layer with its top surface above the interlayer dielectric layer 11 is removed by argon (Ar) sputtering to obtain a protective layer 32 that fills the groove. Since the second dielectric layer 22 of the first active region A includes a fifth dielectric material layer 205 of the same material as the protective layer 32, N2O plasma treatment is used to repair the damage to the second dielectric layer 22 caused during the removal of the protective layer 32. The remaining protective layer 32 and the work function layer 31 are used to construct the work function stack 30, which together with the remaining initial metal gate constitutes the metal gate.
[0103] In the above embodiments, the protective layer prepared by atomic layer deposition (ALD) has excellent conformability and can completely enclose the sidewalls of the second dielectric layer and the barrier layer, without any surface being exposed on the gate surface. Therefore, in the subsequent wet etching process, the etching solution cannot come into contact with the work function layer, fundamentally avoiding the risk of the bottom work function layer being corroded.
[0104] In some embodiments, this application also provides a semiconductor device, including the semiconductor structure described in the above embodiments; or including a semiconductor structure prepared by the preparation method mentioned in the above embodiments. Since the semiconductor devices of the above embodiments and the semiconductor structures and preparation methods provided in this application are based on the same inventive concept, the semiconductor devices employing such semiconductor structures and preparation methods have all the advantages of the semiconductor structures and preparation methods provided in this application, which will not be elaborated upon here.
[0105] In the above embodiments, the unexpected technical effect of this application is:
[0106] Figure 9 A comparative schematic diagram of the semiconductor structure provided in this application and the semiconductor structures provided in related technologies, wherein, Figure 9 Figure (a) shows the semiconductor structure provided in this application. Figure 9 Figure (b) shows the semiconductor structure provided by the related technology. By selecting suitable materials such as TiAl as the initial work function layer and dielectric stacking, the etching rate of the initial work function layer material is ensured to be significantly higher than that of other film layers exposed on the top surface of the metal gate, forming a sufficient etching selectivity. When selectively removing part of the initial work function layer, it effectively protects the other film layer structures of the metal gate and avoids performance degradation. The protective layer prepared by atomic layer deposition (ALD) has excellent conformability and good step coverage, which can completely wrap the surface of the work function layer, so that the work function layer is embedded in the metal gate, as shown by the arrow. In the subsequent wet etching process, it blocks the contact path between the etching solution and the work function layer, avoiding the corrosion risk of the bottom work function layer from the root. At the same time, the plasma treatment process is used to repair the etching damage, ensuring the integrity of its structure and electrical performance.
[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, Includes: a substrate, wherein a first surface of the substrate includes an interlayer dielectric layer and a metal gate arranged alternately along a first direction parallel to the first surface; The metal grid includes: A dielectric stack extends through the interlayer dielectric layer via the top surface of the metal gate in a direction toward the substrate; The work function stack extends into the dielectric stack via the top surface of the metal gate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the dielectric stack; the work function stack includes a work function layer and a protective layer arranged sequentially along a second direction away from the substrate; the protective layer includes a metal nitride and is made of the same material as the dielectric stack. A barrier layer extends through the protective layer and into the work function layer via the top surface of the metal gate in a direction toward the substrate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the work function layer. A conductive metal layer extends into the barrier layer via the top surface of the metal gate; The conductive metal layer and the barrier layer are formed before the protective layer.
2. The semiconductor structure according to claim 1, characterized in that, The dielectric stack includes a first dielectric layer and a second dielectric layer arranged sequentially along the second direction; The first dielectric layer is located on the top surface of the substrate; The second dielectric layer is located on the top surface of the first dielectric layer; The work function stack extends into the second dielectric layer via the top surface of the metal gate.
3. The semiconductor structure according to claim 2, characterized in that, The substrate includes a first active region and a second active region arranged along the first direction; The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.
4. The semiconductor structure according to claim 3, characterized in that, The protective layer and the second dielectric layer located in the first active region are prepared simultaneously in the same process steps.
5. A method for fabricating a semiconductor structure, characterized in that, A method for preparing the semiconductor structure as described in any one of claims 1-4, comprising: A substrate is provided, the substrate including interlayer dielectric layers and an initial metal gate arranged alternately along a first direction parallel to the first surface; A work function stack is formed within the initial metal gate, and the remaining initial metal gate and the work function stack are used to form a metal gate; the metal gate further includes: a dielectric stack, a barrier layer and a metal conductive layer; The dielectric stack extends through the interlayer dielectric layer via the top surface of the metal gate in a direction toward the substrate; The work function stack extends into the dielectric stack via the top surface of the metal gate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the dielectric stack; the work function stack includes a work function layer and a protective layer arranged sequentially along a second direction away from the substrate; the protective layer includes a metal nitride, which is the same material as the dielectric stack. The barrier layer extends through the protective layer and into the work function layer via the top surface of the metal gate in a direction toward the substrate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the work function layer. The conductive metal layer extends into the barrier layer via the top surface of the metal gate; the conductive metal layer and the barrier layer are formed prior to the protective layer.
6. The preparation method according to claim 5, characterized in that, The initial metal gate includes: the dielectric stack, the barrier layer, the metal conductive layer, and the initial work function layer; The initial work function layer extends into the dielectric stack via the top surface of the initial metal gate, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the dielectric stack. The barrier layer extends into the initial work function layer via the top surface of the initial metal grid, and the orthographic projection of its bottom surface onto the first surface lies within the bottom surface of the initial work function layer.
7. The preparation method according to claim 6, characterized in that, Forming the protective layer includes: A portion of the initial work function layer is removed using a target gas to obtain grooves spaced apart along the first direction; the grooves extend into the initial work function layer via the top surface of the initial metal grid, and their bottom surface is not lower than the bottom surface of the barrier layer.
8. The preparation method according to claim 7, characterized in that, Removing a portion of the initial work function layer using a target gas includes: A target gas including hydrogen fluoride and ammonia is used to remove part of the initial work function layer, and the remaining initial work function layer is used to form the work function layer.
9. The preparation method according to claim 7, characterized in that, Forming the metal grid includes: A protective material layer is formed on the top surface of the interlayer dielectric layer and within the groove; By removing part of the protective material layer, a protective layer is obtained that fills the groove. The remaining initial metal grid and the protective layer are used to form the metal grid.
10. A semiconductor device, characterized in that, Including the semiconductor structure as described in any one of claims 1-4; or A semiconductor structure prepared by the preparation method according to any one of claims 5-9.
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