Two-step time-to-digital converter and method thereof, phase-locked loop and analog-to-digital converter

Abstract

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

Description

Technical Field

[0001] This invention relates to a time-to-digital converter and its time-to-digital conversion method, and particularly to a high-resolution, low-power two-step time-to-digital converter and its time-to-digital conversion method, as well as an all-digital phase-locked loop and analog-to-digital converter employing the two-step time-to-digital converter. Background Technology

[0002] The Time-to-Digital Converter (TDC), as the core circuit of a high-precision time measurement system, functions to convert continuous time-domain signals into discrete digital signals. Benefiting from the continuous development of semiconductor manufacturing technology, key performance indicators of TDCs (such as time resolution) have been improved to the picosecond level. This technological breakthrough has made it an important building block for all-digital phase-locked loops (ADPLLs) and high-precision analog-to-digital converters (ADCs). For example, the design of an all-digital phase-locked loop (ADPLL) requires the synergistic optimization of performance indicators such as high resolution, excellent linearity, wide dynamic range, and large signal bandwidth through a Time-to-Digital Converter (TDC).

[0003] While improving TDC resolution helps reduce quantization error and improve in-band phase noise, it presents significant design conflicts with dynamic range extension and power consumption control. Traditional delay-chain TDCs, despite offering optimal conversion rates, are limited by process constraints related to propagation delay, nonlinear errors caused by device mismatch, and the exponential dependence of measurement range on the number of delay cells. To address these challenges, researchers have developed groundbreaking architectures: vernier TDCs quantize using the delay difference between delay cells in dual delay lines, overcoming process limitations; two-step TDCs employ a hierarchical strategy combining delay line coarse quantization and vernier fine quantization, maintaining high resolution while extending dynamic range.

[0004] However, traditional two-step TDC uses selectors as time margin extraction circuits, but as the number of coarse quantization bits increases, the number of logic gates in the selector increases significantly, leading to an increase in the area and power consumption of the two-step TDC. Summary of the Invention

[0005] (1) Technical problems to be solved To address the technical problem that the number of logic gates in the selector increases significantly with the increase of coarse quantization bits, leading to an increase in the area and power consumption of existing two-step time-to-digital converters, this invention provides a high-resolution, low-power two-step time-to-digital converter and its time-to-digital conversion method, as well as an all-digital phase-locked loop and analog-to-digital converter using the two-step time-to-digital converter.

[0006] (2) Technical solution This invention provides a two-step time-to-digital conversion method, which includes the following steps: Coarse-level TDC: The reference signal rs is sequentially delayed by a time t3. N Level 1 delay, for each delayed signal S11~S1 N1 The thermometer codes Q[1]Q[2]……Q[ are coarsely quantized relative to the feedback signal fb respectively. N 1]; Time margin extraction: Based on the time margin that was not measured by coarse quantization, the start signal and stop signal are obtained. Fine-level TDC: Fine-scale quantization of Start and Stop to form thermometer codes P[1]P[2]……P[ N 2]; Decoding: Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1; The method for extracting time margin includes the following steps: When Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In this process, the first signal to arrive is selected as Start, and fb is delayed by time t1 as Stop; When Q[1]~Q[ N 1] When the pairs are the same, select the pair rs after a delay of time t2 as Start, and select the pair fb after a delay of time t2 as Stop.

[0007] The present invention also provides a two-step time-to-digital converter, comprising: Coarse-stage TDC circuit: The reference signal rs is sequentially delayed by a time t3. N Level 1 delay, for each delayed signal S11~S1 N1 The thermometer codes Q[1]Q[2]……Q[ are coarsely quantized relative to the feedback signal fb respectively. N 1]; Time margin extraction circuit: Based on the time margin that the coarse quantization failed to measure, the start signal and stop signal are obtained. Fine-scale TDC circuit: Fine-scale Start and Stop are used to form thermometer codes P[1]P[2]……P[ N 2]; Decoding circuit: Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1; The time margin extraction circuit is configured as follows: When Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In this process, the first signal to arrive is selected as Start, and fb is delayed by time t1 as Stop; When Q[1]~Q[ N 1] When the pairs are the same, select the pair rs after a delay of time t2 as Start, and select the pair fb after a delay of time t2 as Stop.

[0008] As a further improvement to the above solution, the time margin extraction circuit includes: The time start signal output circuit includes a condition trigger circuit, a dynamic OR gate circuit, and a first selection circuit; the condition trigger circuit is used to determine Q[1]~Q[ N 1] Whether they are pairwise different or pairwise the same, and in judging Q[1]~Q[ N 1] When two pairs of S1 to S2 are not simultaneously connected, N1 All are delayed by time t1, and there is no output when they are all the same; the dynamic OR gate is used to determine Q[1]~Q[ N 1] When they are different from each other, in the delayed S1 to S2 N1 In the process, the first arriving signal is selected; the first selection circuit is used to determine Q[1]~Q[ N 1] When the pairs are different, the first signal to arrive is taken as Start; when judging Q[1]~Q[ N 1] When the pairs are identical, select the pair after a delay time t2 on rs as the Start; The time-stop signal output circuit is used to delay the feedback signal fb by time t1 and time t2 respectively, and when Q[1]~Q[ N 1] When the pairs are different, the feedback signal fb of the output delay time t1 is used as Stop, when Q[1]~Q[ N 1] When the pairs are the same, select the feedback signal fb with delay time t2 as Stop.

[0009] Furthermore, the condition triggering circuit includes: NOR gates NOR1 to NOR N1 From Q[1] to Q[ N 1] Select in sequence the two adjacent signals: Q[1]Q[2], Q[2]Q[3], ..., Q[ N 1-1]Q[ N 1], and sequentially used as NOR1~NOR gates. N1 A pair of input signals; First delay unit DL11~DL1 N1 Used to respectively target S1 to S N1 Delay time t1; and Transmission gates TG1~TG N1 They are respectively controlled by NOR1 to NOR gates. N1 The output signal is given, and when it is valid, the output signals S1 to S2 after a delay of time t1 are output respectively. N1 .

[0010] Furthermore, the dynamic OR gate circuit includes: NMOS transistors N1~N N1 ,That N One gate is connected to the condition-triggered circuit for outputting the delayed S1 to S2 gates. N1 of N One output terminal; The PMOS transistor P1 has its gate connected to a voltage source, and its source connected to NMOS transistors N1 to N2. N1 The drain electrode; PMOS transistor P2 has its gate connected to NMOS transistors N1 to N2. N1 The drain of the transistor is connected to the drain of PMOS transistor P1, and its source serves as the output of a dynamic OR gate circuit; and NMOS transistor N0, whose gate is connected to NMOS transistors N1 to N2. N1 The drain of the transistor is connected to the source of the NMOS transistor N1 to N2. N1 The source of P2 is connected to the source of P2.

[0011] Furthermore, the first selection circuit includes: The second delay unit DL2 is used to delay the reference signal rs by time t2, and The output of the first selector MUX1 and the output of the dynamic OR gate circuit and the second delay unit DL2 are respectively connected to the two input terminals of the first selector MUX1. The enable terminal of the first selector MUX1 is controlled by Q[1]. When Q[1]=0, the output signal of the dynamic OR gate circuit is selected as Start. When Q[1]=1, the output signal of the second delay unit DL2 is selected.k1 The output signal is used as Start.

[0012] As a further improvement to the above scheme, the time stop signal output circuit includes: The third delay unit DL3 is used to delay the feedback signal fb by time t1; The fourth delay unit DL4 is used to delay the feedback signal fb by time t2; The outputs of the second selector MUX2, the third delay unit DL3, and the fourth delay unit DL4 are respectively connected to the two inputs of the second selector MUX2. The enable terminal of the second selector MUX2 is controlled by Q[1]. When Q[1]=0, the output signal of the third delay unit DL3 is selected as Stop. When Q[1]=1, the output signal of the fourth delay unit DL4 is selected as Stop.

[0013] As a further improvement to the above scheme, the coarse-level TDC circuit includes: Fifth delay unit DL51~DL5 N1 They are cascaded sequentially, with each stage having a delay time of t3. The input of the fifth delay unit DL51 in the first stage is the reference signal rs. D flip-flops D11~D1 N1 Its data input terminals are respectively connected to the fifth delay units DL51 to DL5 N1 The output of the clock input receives the feedback signal fb, and its output terminals output Q1 to Q2 respectively. N1 .

[0014] As a further improvement to the above scheme, the fine-level TDC circuit includes: Sixth delay unit DL61~DL6 N2 They are cascaded sequentially, with each stage having a delay time of t4. The input of the sixth delay unit DL61 in the first stage is the start signal. Seventh Delay Unit DL71~DL7 N2 They are cascaded sequentially, with each stage having a delay time of t5. The input of the seventh delay unit DL71 in the first stage is the time stop signal Stop. D flip-flops D21~D2 N2 Its data input terminals are respectively connected to the sixth delay unit DL61~DL6 N2 The output of the clock is connected to the seventh delay unit DL71 to DL78 respectively. N2 The output of , its output terminals output P1 to P1 respectively. N2 .

[0015] As a further improvement to the above scheme, the delay unit used for each delay includes: PMOS transistor PM1 ~P M3 P M1 The gate receives the first control voltage V 1, P M1 The drain is connected to the voltage source, P M1 P source terminal M2 The drain, P M2 The gate of P is used as the input of the corresponding delay unit. M2 P source terminal M3 gate, P M3 The drain is connected to the voltage source, P M3 The source is used as the output of the corresponding delay unit; NMOS transistor N M1 ~N M3 N M1 gate connection P M2 The gate, N M1 Drain connection P M2 The source, N M1 The source terminal is N M2 The drain, N M2 The gate receives the second control voltage V 2, N M2 The source is grounded, N M3 gate connection P M3 The gate, N M3 Drain connection P M3 The source, N M3 The source is grounded; According to the first control voltage V 1 and second control voltage V The change in 2 alters the delay time of the corresponding delay unit.

[0016] The present invention also provides an all-digital phase-locked loop, which employs the aforementioned arbitrary two-step time-to-digital converter to convert continuous time-domain signals into discrete digital signals.

[0017] The present invention also provides an analog-to-digital converter, which employs the above-mentioned arbitrary two-step time-to-digital converter to convert continuous time-domain signals into discrete digital signals.

[0018] (3) Beneficial effects Compared with the prior art, the present invention: (1) The time margin extraction of the Start signal and Stop signal of the present invention is designed to be in Q[1]~Q[ N[1] The system switches between two states: two different states and two identical states. A corresponding time margin extraction scheme is designed for each state. Therefore, regardless of how many bits the coarse quantization bits increase, it always chooses one of the two states. In each state, a corresponding start signal (Start) and stop signal (Stop) are output. This solves the technical problem that as the number of logic gates in the selector increases with the increase in the number of coarse quantization bits, leading to increased area and power consumption in existing two-step TDCs. Therefore, this invention achieves high resolution and low power consumption while maintaining a wide measurement range and reducing design complexity.

[0019] (2) The time margin extraction circuit used in this invention can accurately transmit the remaining time interval between the coarse and fine quantization stages, and it has two working modes, which can effectively reduce power consumption. Attached Figure Description

[0020] Figure 1 This is a flowchart of a two-step time-to-digital conversion method provided in an embodiment of the present invention.

[0021] Figure 2 It is to achieve Figure 1 A block diagram of a two-step time-to-digital converter using the two-step time-to-digital conversion method.

[0022] Figure 3 for Figure 2 Circuit diagram of the time margin extraction circuit.

[0023] Figure 4 for Figure 2 A schematic diagram of fine-level quantization timing for a medium-fine-level TDC circuit.

[0024] Figure 5 for Figure 2 Circuit diagram of the Chinese decoding circuit.

[0025] Figure 6 for Figure 2 Simulation results of DNL and INL for a two-step time-to-digital converter.

[0026] Figure 7 for Figure 2 Circuit diagram of the intermediate delay unit. Detailed Implementation

[0027] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] Please see Figure 1 , Figure 1 This is a flowchart of a two-step time-to-digital conversion method provided in an embodiment of the present invention. The two-step time-to-digital conversion method includes steps one through four.

[0031] Step 1, Coarse TDC: First quantization.

[0032] The reference signal rs is sequentially delayed by a time t3. N First-stage delay, take the signal S11~S1 after each delay. N1 For S11~S1 N1 The coarse-quantized signals Q1 to Q2 are obtained by coarse quantization relative to the feedback signal fb. N1 This forms the thermometer code Q[1]Q[2]……Q[ N 1).

[0033] Step 2: Extract time margin: Extract the time margin that was not measured by coarse quantization.

[0034] Based on the time margin that the coarse quantization failed to measure, the start signal and the stop signal are obtained.

[0035] In this invention, the method for extracting time margin includes the following steps: When Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In this process, the first signal to arrive is selected as Start, and fb is delayed by time t1 as Stop; When Q[1]~Q[ N1] When the pairs are the same, select the pair rs after a delay of time t2 as Start, and select the pair fb after a delay of time t2 as Stop.

[0036] Step 3, Fine-level TDC: Second quantization.

[0037] The start and stop time signals are refined to obtain refined signals P1 to PQ. N2 This forms the thermometer code P[1]P[2]……P[ N 2).

[0038] Step 4: Decoding: Decode the thermometer code into binary code.

[0039] Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1.

[0040] Step four can be implemented using a thermometer code to binary code decoder, therefore the coarse-stage TDC outputs Q1 to Q... N1 It can be directly input into the corresponding input terminal of the thermometer code to binary code decoder, directly using the thermometer code Q[1]Q[2]……Q[ N Received in the form of 1].

[0041] Therefore, in the two-step time-to-digital converter method of the present invention, the coarse-level TDC measures the reference signal and the feedback signal for a first period of time, and decodes the result into a thermometer code to a binary code to obtain the first quantization result; the time margin extraction selects the first quantization result, extracts the time margin that was not measured in the first period of time, and uses it as the time start signal and stop signal of the subsequent fine-level TDC; the fine-level TDC measures the time start signal and the time stop signal for a second period of time, and decodes the result into a thermometer code to a binary code to obtain the second quantization result. The first quantization result is used as the high bit and the second quantization result is used as the low bit, and the final binary code formed is the output of this two-step time-to-digital converter. Therefore, the time margin extraction of the time start signal Start and the time stop signal Stop of the present invention is designed to be in Q[1]~Q[ N[1] The system switches between two states: two different states and two identical states. A corresponding time margin extraction scheme is designed for each state. Therefore, regardless of how many bits the coarse quantization bits increase, it always chooses one of the two states. In each state, a corresponding start signal (Start) and stop signal (Stop) are output. This solves the technical problem that as the number of logic gates in the selector increases with the increase in the number of coarse quantization bits, leading to increased area and power consumption in existing two-step TDCs. Therefore, this invention achieves high resolution and low power consumption while maintaining a wide measurement range and reducing design complexity.

[0042] Please see Figure 2 , Figure 2 It is to achieve Figure 1 The block diagram of the two-step time-to-digital converter (TDC) is shown in the figure. This TDC meets the key requirements of the time measurement module in an all-digital phase-locked loop (PLL) and analog-to-digital converter (ADC), enabling high-resolution, low-power conversion of continuous time-domain signals into discrete digital signals. The two-step TDC includes a coarse-stage TDC circuit, a time margin extraction circuit, a fine-stage TDC circuit, and a decoding circuit.

[0043] The coarse-stage TDC circuit, also known as a tapped delay chain module, is used to sequentially delay the reference signal rs by a time t3. N First-stage delay, take the signal S11~S1 after each delay. N1 For S11~S1 N1 The coarse-quantized signals Q1 to Q2 are obtained by coarse quantization relative to the feedback signal fb. N1 This forms the thermometer code Q[1]Q[2]……Q[ N 1]. In this embodiment, N 1 = 2 n1 -1, n1 Let's take 3 as an example to illustrate, therefore N 1 is equivalent to 7. The coarse-stage TDC circuit enables the first-stage measurement of the time difference between the reference signal rs and the feedback signal fb.

[0044] The coarse-level TDC circuit may include: the fifth delay unit DL51 to DL5 N1 D flip-flops D11~D1 N1 Fifth delay unit DL51~DL5 N1 The circuits are cascaded sequentially, with each stage having a delay time of t3. The input of the fifth delay unit DL51 in the first stage is the reference signal rs. D flip-flops D11~D1 N1 The data input terminals are respectively connected to the fifth delay unit DL51~DL5 N1 The output of the clock input receives the feedback signal fb, and its output terminals output Q1 to Q2 respectively. N1 .

[0045] therefore, N The fifth delay units DL51 to DL55 are connected sequentially in stage 1. N1 and N Level 1 D flip-flops D11~D1 N1 This enables the first-stage measurement of the time difference between the reference signal rs and the feedback signal fb. Because a D flip-flop is used, the corresponding output is either 0 or 1; therefore, Q1 to Q... N1 and Q[1]Q[2]……Q[ N The content of 1] is the same, therefore, it can be equivalent to the output thermometer code Q[1]Q[2]……Q[ of the coarse-level TDC circuit. N 1).

[0046] The time margin extraction circuit is used to obtain the start signal and stop signal based on the time margin that was not measured by coarse quantization. Please refer to... Figure 3 , Figure 3 for Figure 2 Circuit diagram of the time margin extraction circuit. The time margin extraction circuit is configured as follows: when Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In the process, the first arriving signal is selected as Start, and fb is delayed by time t1 as Stop; when Q[1]~Q[ N 1] When both pairs are the same, the delay time t2 for rs is selected as Start, and the delay time t2 for fb is also selected as Stop. Therefore, the time margin extraction circuit can include: a time start signal output circuit and a time stop signal output circuit.

[0047] The time start signal output circuit may include a condition trigger circuit, a dynamic OR gate circuit, and a first selection circuit. The condition trigger circuit is used to determine Q[1]~Q[ N 1] Whether they are pairwise different or pairwise the same, and in judging Q[1]~Q[ N 1] When two pairs of S1 to S2 are not simultaneously connected, N1 All are delayed by time t1, and there is no output when they are all the same. The dynamic OR gate is used to determine Q[1]~Q[ N 1] When they are different from each other, in the delayed S1 to S2 N1 In the process, the first arriving signal is selected. The first selection circuit is used to determine Q[1]~Q[ N 1] When the pairs are different, the first signal to arrive is taken as Start; when judging Q[1]~Q[ N 1] When the pairs are the same, select the pair after the delay time t2 of rs as Start.

[0048] Conditional triggering circuits may include: NOR1 to NOR gates. N1 First delay unit DL11~DL1 N1 Transmission gates TG1 to TG N1 NOR gates NOR1 to NOR2 N1 From Q[1] to Q[ N 1] Select in sequence the two adjacent signals: Q[1]Q[2], Q[2]Q[3], ..., Q[ N 1-1]Q[ N 1], and sequentially used as NOR1~NOR gates. N1 A pair of input signals. First delay units DL11~DL1 N1 For S1 to S N1 Delay time t1. Transmission gate TG1~TG N1 Controlled by NOR1 to NOR gates respectively N1 The output signal is given, and when it is valid, the output signals S1 to S2 after a delay of time t1 are output respectively. N1 .

[0049] Dynamic OR gate circuits may include: NMOS transistors N1 to N N1 PMOS transistor P1, PMOS transistor P2, NMOS transistor N0. NMOS transistors N1~N N1 of N One gate is connected to the condition-triggered circuit for outputting the delayed S1 to S2 gates. N1 of N One output terminal. The gate of PMOS transistor P1 is connected to a voltage source, and the source of PMOS transistor P1 is connected to NMOS transistors N1 to N2. N1 The drain of PMOS transistor P2 is connected to the gate of NMOS transistors N1 to N2. N1 The drain of PMOS transistor P2 is connected to the drain of PMOS transistor P1, and the source of PMOS transistor P2 serves as the output terminal of the dynamic OR gate circuit. The gate of NMOS transistor N0 is connected to the gate of NMOS transistors N1 to N2. N1 The drain of NMOS transistor N0 is connected to the source of NMOS transistors N1 to N2. N1 The source of the NMOS transistor is connected to the source of the PMOS transistor P2.

[0050] The first selection circuit may include: a second delay unit DL2 and a first selector MUX1. The second delay unit DL2 is used to delay the reference signal rs by time t2. The output of the dynamic OR gate circuit and the output of the second delay unit DL2 are respectively connected to the two inputs of the first selector MUX1. The enable terminal of the first selector MUX1 is controlled by Q[1]. When Q[1]=0, the output signal of the dynamic OR gate circuit is selected as Start. When Q[1]=1, the second delay unit DL2 is selected. k1 The output signal is used as Start. The first selector MUX1 can be a 2-to-1 selector.

[0051] The time-stop signal output circuit is used to delay the feedback signal fb by time t1 and time t2 respectively, and when Q[1]~Q[ N 1] When the pairs are different, the feedback signal fb of the output delay time t1 is used as Stop, when Q[1]~Q[ N 1] When the pairs are the same, select the feedback signal fb with delay time t2 as Stop.

[0052] The time-stop signal output circuit may include: a third delay unit DL3, a fourth delay unit DL4, and a second selector MUX2. The third delay unit DL3 is used to delay the feedback signal fb for time t1. The fourth delay unit DL4 is used to delay the feedback signal fb for time t2. The output terminals of the third delay unit DL3 and the fourth delay unit DL4 are respectively connected to the two input terminals of the second selector MUX2. The enable terminal of the second selector MUX2 is controlled by Q[1]. When Q[1]=0, the output signal of the third delay unit DL3 is selected as Stop. When Q[1]=1, the output signal of the fourth delay unit DL4 is selected as Stop.

[0053] Therefore, in the time-stop signal output circuit, Q1~Q N1 (That is, Q[1]Q[2]……Q[ N 1) The output after pairwise XOR is used as the gating signal of the transmission gate, and the delay signals S1 to S2 are... N1 After passing through the corresponding delay units, they are input to the corresponding transmission gates. When Q1~Q N1 When the pairs are not identical, the transmission gate opens and outputs the delayed S1~S2. N1 When Q1~Q N1 When all pairs of signals are identical, the transmission gate closes, the output is 0, and the reference signal rs is output. The output of each transmission gate is connected to a dynamic OR gate to select the first arriving signal (i.e., S1 to S2). N1 The signal that changes from 0 to 1 first is then connected to one input of the 2-to-1 selector (i.e., the first selector MUX1). After a corresponding delay, the reference signal is connected to the other input of the 2-to-1 selector.

[0054] The time margin extraction circuit has two modes. When the time difference between the reference signal rs and the feedback signal fb is greater than the tap delay chain (i.e., the cascaded DL51~DL5), the time margin extraction circuit can be used in two modes. N1 When the resolution is 0, i.e., Q1 is 0, the corresponding signals S1 to S2 are selected through a transmission gate and a dynamic OR gate. N1 The first one to be reached is selected. When the time difference between the reference signal rs and the feedback signal fb is less than the resolution of the tap delay chain, i.e. when Q1 is 1, the transmission gate and dynamic OR gate are skipped, and the delayed reference signal is directly output through the 2-to-1 selector to reduce power consumption.

[0055] In the time-stop signal output circuit, when the time difference between the reference signal rs and the feedback signal fb is greater than the resolution of the tap delay chain, the feedback signal fb is connected to one input of the 2-to-1 selector (i.e., the second selector MUX2) through the third delay unit DL3. When the time difference between the reference signal rs and the feedback signal fb is less than the resolution of the tap delay chain, the feedback signal fb is connected to the other input of the 2-to-1 selector through the fourth delay unit DL4.

[0056] Please refer to it again. Figure 2 The fine-level TDC circuit, also known as a vernier-type delay chain module, is used to fine-quantize Start and Stop signals to obtain fine-quantized signals P1 to PQ. N2 This forms the thermometer code P[1]P[2]……P[ N 2]. In this embodiment, N 2 = 2 n2 -1, n2, taking 4 as an example for illustration, therefore N 2 is 15.

[0057] The detailed TDC circuit may include: the sixth delay unit DL61 to DL6 N2 The seventh delay unit DL71~DL7 N2 D flip-flops D21~D2 N2 The sixth delay unit DL61~DL6 N2 The stages are cascaded sequentially, with each stage having a delay time of t4. The input to the sixth delay unit DL61 in the first stage is the start signal. The seventh delay units are DL71 to DL72. N2 The circuits are cascaded sequentially, with each stage having a delay time of t5. The input to the seventh delay unit DL71 in the first stage is the time stop signal (Stop). D flip-flops D21~D2... N2 The data input terminals are respectively connected to the sixth delay unit DL61~DL6 N2 The output of the D flip-flops D21~D2 N2The clock input terminals are respectively connected to the seventh delay units DL72 to DL7 N2 The output of the D flip-flops D21~D2 N2 The output terminals output P1 to P1 respectively. N2 .

[0058] Please see Figure 4 , Figure 4 This is a timing diagram for fine-level quantization. Therefore, the fine-level TDC circuit can include two delay chains with different delays: cascaded sixth delay units DL61 to DL6 N2 Cascaded seventh delay units DL71~DL7 N2 The two delay chains are denoted as the fast delay chain and the slow delay chain, respectively; the slow delay chain contains... N The two slow delay units are connected in sequence, and the fast delay chain contains... N Two fast delay units are connected in sequence, and the outputs of each slow delay unit and fast delay unit are connected to the input and clock input of the corresponding D flip-flop, respectively. Since the output of a D flip-flop is either 0 or 1, the outputs P1 to P2 of the fine-stage TDC circuit are... N2 and, P[1]P[2]……P[ N The actual content expressed in 2] is consistent, therefore, it can be equivalent to the output thermometer code P[1]P[2]……P[ of the fine-level TDC circuit. N 2).

[0059] The decoding circuit, also known as the thermometer code to binary code decoding module, is used to: convert Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1. In practical applications of decoding circuits, a thermometer code to binary code decoder can be used. Please refer to [link / reference]. Figure 5 , Figure 5 for Figure 2 The circuit diagram of the Chinese decoding circuit shows that Q[1]Q[2]……Q[7] is decoded into 3 high bits: [A1][A2][A3].

[0060] Therefore, the bit width of the decoding circuit is n3 = n1 + n2, and in this embodiment, n3: 3 + 4 = 7 bits. The outputs of the coarse-level TDC circuit and the fine-level TDC circuit are converted into binary codes with fixed bit width and weighted bits. This binary code serves as the final output of the two-step time-to-digital converter. The decoding circuit may include four 2-to-1 selectors to convert the outputs of the coarse-level TDC circuit Q[1]Q[2]……Q[ NThe outputs P[1]P[2]……P

[15] of the fine-level TDC are converted into a binary code with a fixed bit width (7 bits) and weighted bits (the high 3 bits correspond to the coarse-level TDC circuit and the low 4 bits correspond to the fine-level TDC circuit). This binary code is used as the final output of the two-step time-to-digital converter.

[0061] Please see Figure 6 , Figure 6 for Figure 2 Simulation results of DNL and INL for a two-step time-to-digital converter. The DNL of the high-resolution, low-power two-step time-to-digital converter is 0.5, and the INL is 1.25. In a coarse-stage TDC circuit, its resolution... τ 1. Determined by the delay time t3 of the fifth delay unit: τ 1 = t3 have N Delay chain DL51~DL5 with a fifth delay unit N1 The dynamic range T1 is: T1= N 1×t3 In fine-level TDC circuits, its resolution τ 2 is determined by the time difference between two different sixth and seventh delay units: τ 2 = t5 - t4 have N Delay chains DL61 to DL6 with two sixth delay units N2 The dynamic range T2 is: T2= N 2×t4 have N Delay chains DL71 to DL7 with two seventh delay units N2 The dynamic range of 3 is: T3= N 2×t5 Therefore, the dynamic range T of this two-step time-to-digital converter is: T = T1 + (T3 - T2) Therefore, we can conclude that: t 3、 t 4、 t5 is determined by the resolution required for the two-step time-to-digital converter. 1、 t2 can be an empirical value, or it can be set without being based on experience, as long as t1 and t2 ensure that S1~S after delay processing are satisfied. N1 The arrival times of rs and fb at their respective selectors must all be later than the enable time of their selectors. For example, t1 needs to ensure that S1~S after delay processing N1The arrival times of rs to the first selector MUX1 are both later than the enable time of the first selector MUX1. t2 must ensure that the arrival time of fb after delay processing to the second selector MUX2 is later than the enable time of the second selector MUX2.

[0062] The delay unit used in each delay can change the delay time according to changes in the external control voltage, such as... Figure 7 As shown, the delay unit used for each delay may include: PMOS transistor P M1 ~P M3 NMOS transistor N M1 ~N M3 .

[0063] P M1 The gate receives the first control voltage V 1, P M1 The drain is connected to the voltage source VDD, P M1 P source terminal M2 The drain, P M2 The gate of P is used as the input IN of the corresponding delay unit. M2 P source terminal M3 gate, P M3 The drain is connected to the voltage source VDD, P M3 The source of N serves as the output OUT of the corresponding delay unit. M1 gate connection P M2 The gate, N M1 Drain connection P M2 The source pole forms the first node NET1, N M1 The source terminal is N M2 The drain, N M2 The gate receives the second control voltage V 2, N M2 The source is grounded, N M3 gate connection P M3 The gate forms the second node NET2, N M3 Drain connection P M3 The source, N M3 The source is grounded. Based on the first control voltage... V 1 and second control voltage V The change in 2 alters the delay time of the corresponding delay unit.

[0064] In summary, this invention achieves high resolution and low power consumption while maintaining a wide measurement range and reducing design complexity. The time margin extraction circuit used in this invention can accurately transmit the remaining time interval between the coarse and fine quantization stages, and it also has two operating modes, which can effectively reduce power consumption.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A two-step time-to-digital conversion method, comprising the following steps: Coarse-level TDC: The reference signal rs is sequentially delayed by a time t3. N Level 1 delay, for each delayed signal S11~S1 N1 The thermometer codes Q[1]Q[2]……Q[ are coarsely quantized relative to the feedback signal fb respectively. N 1]; Time margin extraction: Based on the time margin that was not measured by coarse quantization, the start signal and stop signal are obtained. Fine-level TDC: Fine-scale quantization of Start and Stop to form thermometer codes P[1]P[2]……P[ N 2]; Decoding: Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1; The method for extracting time margin is characterized by the following steps: When Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In this process, the first signal to arrive is selected as Start, and fb is delayed by time t1 as Stop; When Q[1]~Q[ N 1] When the pairs are the same, select the pair rs after a delay of time t2 as Start, and select the pair fb after a delay of time t2 as Stop.

2. A two-step time-to-digital converter, comprising: Coarse-stage TDC circuit: The reference signal rs is sequentially delayed by a time t3. N Level 1 delay, for each delayed signal S11~S1 N1 The thermometer codes Q[1]Q[2]……Q[ are coarsely quantized relative to the feedback signal fb respectively. N 1]; Time margin extraction circuit: Based on the time margin that the coarse quantization failed to measure, the start signal and stop signal are obtained. Fine-scale TDC circuit: Fine-scale Start and Stop are used to form thermometer codes P[1]P[2]……P[ N 2]; Decoding circuit: Q[1]Q[2]……Q[ N 1] Decoded as n1 high-order bits, P[1]P[2]……P[ N 2] Decoded into n2 bits of low-order binary code, N 1 = 2 n1 -1, N 2 = 2 n2 -1; Its characteristic is that the time margin extraction circuit is configured as follows: When Q[1]~Q[ N 1] When they are different in pairs, S1 to S2 N1 After a delay of time t1, and within the delayed periods S1 to S2... N1 In this process, the first signal to arrive is selected as Start, and fb is delayed by time t1 as Stop; When Q[1]~Q[ N 1] When the pairs are the same, select the pair rs after a delay of time t2 as Start, and select the pair fb after a delay of time t2 as Stop.

3. The two-step time-to-digital converter according to claim 2, characterized in that, The time margin extraction circuit includes: The time start signal output circuit includes a condition trigger circuit, a dynamic OR gate circuit, and a first selection circuit; the condition trigger circuit is used to determine Q[1]~Q[ N 1] Whether they are pairwise different or pairwise the same, and in judging Q[1]~Q[ N 1] When two pairs of S1 to S2 are not simultaneously connected, N1 All are delayed by time t1, and there is no output when they are all the same; the dynamic OR gate is used to determine Q[1]~Q[ N 1] When they are different from each other, in the delayed S1 to S2 N1 In the process, the first arriving signal is selected; the first selection circuit is used to determine Q[1]~Q[ N 1] When the pairs are different, the first signal to arrive is taken as Start; when judging Q[1]~Q[ N 1] When the pairs are identical, select the pair after a delay time t2 on rs as the Start; The time-stop signal output circuit is used to delay the feedback signal fb by time t1 and time t2 respectively, and when Q[1]~Q[ N 1] When the pairs are different, the feedback signal fb of the output delay time t1 is used as Stop, when Q[1]~Q[ N 1] When the pairs are the same, select the feedback signal fb with delay time t2 as Stop.

4. The two-step time-to-digital converter according to claim 3, characterized in that, The condition trigger circuit includes: NOR gates NOR1 to NOR N1 From Q[1] to Q[ N 1] Select in sequence the two adjacent signals: Q[1]Q[2], Q[2]Q[3], ..., Q[ N 1-1]Q[ N 1], and sequentially used as NOR1~NOR gates. N1 A pair of input signals; First delay unit DL11~DL1 N1 Used to respectively target S1 to S N1 Delay time t1; and Transmission gates TG1~TG N1 They are respectively controlled by NOR1 to NOR gates. N1 The output signal is given, and when it is valid, S1 to S2 are output after a delay of time t1 respectively. N1 ; And / or, dynamic OR gate circuits include: NMOS transistors N1~N N1 ,That N One gate is connected to the condition trigger circuit for outputting the delayed S1~S2. N1 of N One output terminal; The PMOS transistor P1 has its gate connected to a voltage source, and its source connected to NMOS transistors N1 to N2. N1 The drain electrode; PMOS transistor P2 has its gate connected to NMOS transistors N1 to N2. N1 The drain of the transistor is connected to the drain of PMOS transistor P1, and its source serves as the output of a dynamic OR gate circuit; and NMOS transistor N0, whose gate is connected to NMOS transistors N1 to N2. N1 The drain of the transistor is connected to the source of the NMOS transistor N1 to N2. N1 The source of P2 is connected to the source of P2. And / or, the first selection circuit includes: The second delay unit DL2 is used to delay the reference signal rs by time t2, and The output of the first selector MUX1 and the output of the dynamic OR gate circuit and the second delay unit DL2 are respectively connected to the two input terminals of the first selector MUX1. The enable terminal of the first selector MUX1 is controlled by Q[1]. When Q[1]=0, the output signal of the dynamic OR gate circuit is selected as Start. When Q[1]=1, the output signal of the second delay unit DL2 is selected. k1 The output signal is used as Start.

5. The two-step time-to-digital converter according to claim 3, characterized in that, The time-stop signal output circuit includes: The third delay unit DL3 is used to delay the feedback signal fb by time t1; The fourth delay unit DL4 is used to delay the feedback signal fb by time t2; The outputs of the second selector MUX2, the third delay unit DL3, and the fourth delay unit DL4 are respectively connected to the two inputs of the second selector MUX2. The enable terminal of the second selector MUX2 is controlled by Q[1]. When Q[1]=0, the output signal of the third delay unit DL3 is selected as Stop. When Q[1]=1, the output signal of the fourth delay unit DL4 is selected as Stop.

6. The two-step time-to-digital converter according to claim 2, characterized in that, The coarse-level TDC circuit includes: Fifth delay unit DL51~DL5 N1 They are cascaded sequentially, with each stage having a delay time of t3. The input of the fifth delay unit DL51 in the first stage is the reference signal rs. D flip-flops D11~D1 N1 Its data input terminals are respectively connected to the fifth delay units DL51 to DL5 N1 The output of the clock input receives the feedback signal fb, and its output terminals output Q1 to Q2 respectively. N1 .

7. The two-step time-to-digital converter according to claim 2, characterized in that, The fine-level TDC circuit includes: Sixth delay unit DL61~DL6 N2 They are cascaded sequentially, with each stage having a delay time of t4. The input of the sixth delay unit DL61 in the first stage is the start signal. Seventh Delay Unit DL71~DL7 N2 They are cascaded sequentially, with each stage having a delay time of t5. The input of the seventh delay unit DL71 in the first stage is the time stop signal Stop. D flip-flops D21~D2 N2 Its data input terminals are respectively connected to the sixth delay unit DL61~DL6 N2 The output of the clock is connected to the seventh delay unit DL71 to DL78 respectively. N2 The output of , its output terminals output P1 to P1 respectively. N2 .

8. The two-step time-to-digital converter according to claim 2, characterized in that, The delay unit used for each delay includes: PMOS transistor P M1 ~P M3 P M1 The gate receives the first control voltage V 1, P M1 The drain is connected to the voltage source, P M1 P source terminal M2 The drain, P M2 The gate of P is used as the input of the corresponding delay unit. M2 P source terminal M3 The gate, P M3 The drain is connected to the voltage source, P M3 The source is used as the output of the corresponding delay unit; NMOS transistor N M1 ~N M3 N M1 gate connection P M2 The gate, N M1 Drain connection P M2 The source, N M1 The source terminal is N M2 The drain, N M2 The gate receives the second control voltage V 2, N M2 The source is grounded, N M3 gate connection P M3 The gate, N M3 Drain connection P M3 The source, N M3 The source is grounded; According to the first control voltage V 1 and second control voltage V The change in 2 alters the delay time of the corresponding delay unit.

9. A fully digital phase-locked loop, characterized in that, It employs a two-step time-to-digital converter as described in any one of claims 1 to 8 to convert continuous time-domain signals into discrete digital signals.

10. An analog-to-digital converter, characterized in that, It employs a two-step time-to-digital converter as described in any one of claims 1 to 8 to convert continuous time-domain signals into discrete digital signals.

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