An ultra-low power consumption low dropout linear voltage regulator circuit

Abstract

The application discloses a kind of ultra-low power consumption low dropout linear voltage stabilizing circuit, it is related to integrated circuit design field, including band gap reference circuit, operational amplifier circuit, feedback circuit;The band gap reference circuit is used to generate reference voltage VREF, feedback circuit is used to generate different feedback voltage FB, and operational amplifier circuit is used to generate stable output voltage VOUT according to reference voltage VREF and feedback voltage FB;Feedback circuit includes diode connection structure;Diode connection structure includes several diode connection structure PMOS tubes in series, for changing the voltage value of each PMOS tube by changing the number of series PMOS tubes.This application replaces the resistance feedback used by traditional LDO, and uses MOS tube voltage division feedback connected by diode.The structure has the characteristics of ultra-low power consumption and small area, and the size of output voltage VOUT can be adjusted by adjusting the number of feedback MOS tubes.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a kind of ultra-low power consumption low differential linear voltage stabilizing circuit. BACKGROUND

[0002] As power management chip, low dropout linear regulator (LDO) has the characteristics of low noise, small ripple and small area, and is widely used in the market, and lower power consumption and smaller area are one of the trends of LDO development. The traditional LDO uses resistance feedback, and the required low power consumption leads to a large resistance, so it is difficult to balance between power consumption and area.

[0003] The traditional LDO circuit is composed of an input reference voltage, an operational amplifier, a switching power tube and a feedback series voltage dividing resistor. The reference voltage VREF generated by the bandgap reference source is fed back to the reverse input terminal of the LDO operational amplifier, and the output voltage VOUT of the LDO is fed back to the same input terminal of the operational amplifier after being divided by the voltage dividing resistor. The operational amplifier amplifies the difference between VREF and the feedback voltage VF and outputs it to the gate of the power tube to drive the power tube to adjust the output voltage and obtain a stable output voltage.

[0004] The traditional LDO uses voltage dividing resistors at the output end, which generates current on this branch. When we need low power consumption, we need a large resistance on this branch to achieve the output voltage value. For example, a 20nA resistance consumes 50MΩ resistance to output 1V voltage, which occupies a large area and has a relatively high cost.

[0005] The existing patent technology CN114706441A provides a low-power low-dropout linear regulator, which simultaneously considers the influence of the transient response and output ripple of the low-dropout linear regulator, and improves the transient response and output ripple of the output while reducing the power consumption through the current limiting circuit and the buffer circuit coupled with the output. In this technology, the output voltage feedback adopts a resistance feedback form, which consumes a large area. SUMMARY

[0006] The present application aims to overcome the shortcomings of the prior art and provide an ultra-low power consumption low differential linear voltage stabilizing circuit to obtain a low-power stable voltage output.

[0007] The purpose of the present application is achieved by the following technical solutions:

[0008] An ultra-low power consumption low differential linear voltage stabilizing circuit, comprising a bandgap reference circuit, an operational amplifier circuit and a feedback circuit; the bandgap reference circuit is used to generate a reference voltage VREF, the feedback circuit is used to generate different feedback voltages FB, and the operational amplifier circuit is used to generate a stable output voltage VOUT according to the reference voltage VREF and the feedback voltage FB;

[0009] The operational amplifier circuit comprises an operational amplifier, a reference voltage VREF output end of the bandgap reference circuit is connected to a non-inverting input end of the operational amplifier, a feedback voltage FB output end of the feedback circuit is connected to an inverting input end of the operational amplifier, and an output end of the operational amplifier outputs a voltage VOUT;

[0010] The feedback circuit comprises a thirteenth PMOS tube, a fourteenth PMOS tube and a diode connection structure in series; the diode connection structure comprises a plurality of diode-connected PMOS tubes in series, for changing the voltage division voltage value of each PMOS tube by changing the number of the series PMOS tubes, and the gate and the drain of the diode-connected PMOS tube are short-circuited; the source of the thirteenth PMOS tube is connected to the output voltage VOUT end of the operational amplifier circuit, the gate and the drain of the thirteenth PMOS tube are both connected to the feedback voltage FB output end, the source of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, the gate and the drain of the fourteenth PMOS tube are both connected to the first end of the diode connection structure, and the second end of the diode connection structure is grounded.

[0011] Further, the bandgap reference circuit comprises a PNP-type BJT tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube.

[0012] The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected to a power supply VDD, the drain of the first PMOS tube is connected to the emitter of the PNP-type BJT tube, the gate of the first NMOS tube and the gate of the second NMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube, the drain of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the drain of the first NMOS tube are connected, the source of the first NMOS tube is connected to the drain of the second NMOS tube and the source of the fifth NMOS tube, the source of the second NMOS tube is connected to the drain and the gate of the third NMOS tube, the base and the collector of the PNP-type BJT tube are both grounded, and the source of the third NMOS tube is grounded.

[0013] The drain of the third PMOS tube is connected to the gate and the drain of the fourth NMOS tube and the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and the source of the seventh NMOS tube, the drain of the fourth PMOS tube is connected to the gate and the drain of the sixth NMOS tube and the gate of the seventh NMOS tube, the source of the sixth NMOS tube and the drain of the seventh NMOS tube are both connected to the reference voltage VREF output end.

[0014] Further, the operational amplifier circuit further comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube;

[0015] The source electrodes of the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the twelfth PMOS tube are connected to a power supply VDD, the gate electrodes of the sixth PMOS tube and the seventh PMOS tube are connected to a first end of a bandgap reference circuit, the drain electrode of the sixth PMOS tube is connected to the drain electrode of the eighth NMOS tube, the gate electrode of the eighth NMOS tube, the gate electrode of the tenth NMOS tube and the gate electrode of the eleventh NMOS tube, the source electrode of the eighth NMOS tube is connected to the drain electrode of the ninth NMOS tube, the gate electrode of the ninth NMOS tube, the gate electrode of the twelfth NMOS tube, the gate electrode of the thirteenth NMOS tube and the gate electrode of the fourteenth NMOS tube,

[0016] The drain electrode of the seventh PMOS tube is connected to the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube, the gate electrode of the tenth PMOS tube is an in-phase input end of an operational amplifier, the gate electrode of the eleventh PMOS tube is an inverse-phase input end of the operational amplifier, the drain electrode of the tenth PMOS tube is connected to the source electrode of the tenth NMOS tube and the drain electrode of the twelfth NMOS tube, the drain electrode of the eleventh PMOS tube is connected to the source electrode of the eleventh NMOS tube and the drain electrode of the thirteenth NMOS tube, the gate electrode of the eighth PMOS tube is connected to the drain electrode of the eighth PMOS tube, the gate electrode of the ninth PMOS tube and the drain electrode of the tenth NMOS tube, the drain electrode of the ninth PMOS tube is connected to the drain electrode of the eleventh NMOS tube and the gate electrode of the twelfth PMOS tube, the drain electrode of the twelfth PMOS tube and the drain electrode of the fourteenth NMOS tube are connected and are an output voltage VOUT end, and the source electrode of the ninth NMOS tube, the drain electrode of the twelfth NMOS tube, the drain electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are grounded.

[0017] Further, the feedback circuit further comprises a plurality of diode-connected PMOS tubes connected in parallel to the two ends of the thirteenth PMOS tube, for changing the voltage division value of each PMOS tube by changing the number of the parallel PMOS tubes, to obtain different output voltages.

[0018] The present application has the following beneficial effects:

[0019] The present application replaces the resistance feedback used by the traditional LDO, and uses diode-connected MOS tube voltage division feedback. The structure has the characteristics of ultra-low power consumption and small area. Meanwhile, the size of the output voltage VOUT can be adjusted by adjusting the number of feedback MOS tubes. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 For the traditional LDO circuit diagram structure;

[0021] Figure 2 For the low dropout linear regulator circuit provided by the application;

[0022] Figure 3 For the diode connection voltage division structure. DETAILED DESCRIPTION

[0023] The technical solutions of the application will be described below in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0024] Reference Figures 1-3 The application provides a technical solution:

[0025] A low dropout linear regulator circuit, as shown in Figure 2 The bandgap reference circuit is used to generate a reference voltage VREF, the feedback circuit is used to generate different feedback voltages FB, and the operational amplifier circuit is used to generate a stable output voltage VOUT according to the reference voltage VREF and the feedback voltage FB.

[0026] The operational amplifier circuit includes an operational amplifier, the reference voltage VREF output end of the bandgap reference circuit is connected to the non-inverting input end of the operational amplifier, the feedback voltage FB output end of the feedback circuit is connected to the inverting input end of the operational amplifier, and the output end of the operational amplifier outputs the voltage VOUT.

[0027] The feedback circuit includes a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14 and a diode connection structure in series; the diode connection structure includes a plurality of PMOS tubes connected in series in diode mode, which is used to change the voltage division value of each PMOS tube by changing the number of PMOS tubes connected in series, and the diode mode of the PMOS tube is to short the base and the drain of the PMOS tube; the source of the thirteenth PMOS tube is connected to the output voltage VOUT end of the operational amplifier circuit, the gate and the drain of the thirteenth PMOS tube MP13 are both connected to the feedback voltage FB output end, the source of the fourteenth PMOS tube MP14 is connected to the drain of the thirteenth PMOS tube MP13, the gate and the drain of the fourteenth PMOS tube MP14 are both connected to the first end of the diode connection structure, and the second end of the diode connection structure is grounded.

[0028] In the embodiment, the bandgap reference circuit comprises a PNP type BJT tube Q1, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6 and a seventh NMOS tube MN7.

[0029] The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected to a power supply VDD, the drain of the first PMOS tube is connected to the emitter of the PNP type BJT tube, the gate of the first NMOS tube and the gate of the second NMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube, the drain of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the drain of the first NMOS tube are connected, the source of the first NMOS tube is connected to the drain of the second NMOS tube and the source of the fifth NMOS tube, the source and the drain of the second NMOS tube are connected, the base and the collector of the PNP type BJT tube are grounded, and the source of the third NMOS tube is grounded.

[0030] The drain of the third PMOS tube is connected to the gate and the drain of the fourth NMOS tube and the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and the source of the seventh NMOS tube, the drain of the fourth PMOS tube is connected to the gate and the drain of the sixth NMOS tube and the gate of the seventh NMOS tube, and the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected to a reference voltage VREF output terminal.

[0031] In the bandgap reference circuit, the positive temperature coefficient voltage formed by the negative temperature coefficient voltage and the two self-bias structures is added in proportion to obtain a temperature-independent voltage VREF, and the circuit principle analysis is as follows: the BJT tube Q1 generates a temperature-negative current, the size of the current is the same as the current flowing through MN1, the gate of MN1 is connected to the gate of MN2 to make MN1 and MN2 in a mirror relationship, MN2 can copy the current size of MN1, MN4 and MN5 form a self-bias structure to generate a temperature-positive voltage at the drain of MN5. The sources and gates of MP2, MP3 and MP4 are connected together, so the current flowing through MP3 and MP4 is equal to MP2; MN6 and MN7 form a self-bias structure to generate a temperature-positive voltage at the drain of MN7.

[0032] The emitter voltage of the BJT tube Q1 is the sum of the gate-source voltage of MN3 and the gate-source voltage of MN2, if the width-length ratios of MN2 and MN3 are the same, then The current flowing through MN3 is the sum of the currents flowing through MP4, MP3 and MP2. Since MP1 and MP2 are current mirror structures, the currents are proportional to each other Therefore .

[0033] The drain of MN2 generates a negative temperature coefficient voltage. MN4 and MN5 form a self-bias structure, MN6 and MN7 form a self-bias structure, the drain of MN5 generates a positive temperature coefficient voltage, and the drain of MN7 generates a positive temperature coefficient voltage. Therefore, the drain of MN2 is the sum of the negative temperature coefficient voltage and the positive temperature coefficient voltage generated by the self-bias structure in proportion. A temperature-independent voltage VREF is obtained at the drain of MN7.

[0034] In the embodiment, the operational amplifier circuit further comprises a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14.

[0035] The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the twelfth PMOS transistor are connected to the power supply VDD. The gates of the sixth PMOS transistor and the seventh PMOS transistor are connected to the first end of the bandgap reference circuit. The drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor. The source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor.

[0036] The drain of the seventh PMOS tube is connected with the source of the tenth PMOS tube and the source of the eleventh PMOS tube, the gate of the tenth PMOS tube is the non-inverting input terminal of the operational amplifier, the gate of the eleventh PMOS tube is the inverting input terminal of the operational amplifier, the drain of the tenth PMOS tube is connected with the source of the tenth NMOS tube and the drain of the twelfth NMOS tube, the drain of the eleventh PMOS tube is connected with the source of the eleventh NMOS tube and the drain of the thirteenth NMOS tube; the gate of the eighth PMOS tube is connected with the drain of the eighth PMOS tube, the gate of the ninth PMOS tube and the drain of the tenth NMOS tube, the drain of the ninth PMOS tube is connected with the drain of the eleventh NMOS tube and the gate of the twelfth PMOS tube, the drain of the twelfth PMOS tube and the drain of the fourteenth NMOS tube are connected and are the output voltage VOUT terminal, the source of the ninth NMOS tube, the drain of the twelfth NMOS tube, the drain of the thirteenth NMOS tube and the source of the fourteenth NMOS tube are all grounded.

[0037] The reference voltage VREF generated by the bandgap reference circuit is provided to the operational amplifier OPA in the subsequent circuit, and the reference voltage VREF generated by the operational amplifier OPA is provided to MP10. The source of MP6 is connected with VDD, the drain of MN8 is connected with the drain of MP6, and the gate and the drain of MP8 are connected, thereby providing bias voltage for MN10 and MN11; the source of MN8 is connected with the drain of MN9, and the gate and the drain of MN9 are connected, thereby providing bias voltage for MN12 and MN13 and providing bias current for MN14. The source of MP7 is connected with VDD, and the gate of MP7 is connected with the gate of MP2, thereby flowing through MP7 the current mirrored from MP2, MP7 to MP11, and MP12 to MN14 as the first stage of the operational amplifier, thereby providing higher gain, and MN10 and MN13 as the second stage of the operational amplifier, thereby providing a larger bandwidth.

[0038] In the embodiment, as shown in Figure 3 The feedback circuit further comprises a plurality of PMOS tubes connected in parallel across the thirteenth PMOS tube in diode connection, for changing the output voltage by changing the number of the parallel PMOS tubes and the voltage division value of each PMOS tube.

[0039] The voltage feedback circuit is composed of MP13, MP14 and MPn. The source of MP13 is connected with the drain of MP12, and the gate and the drain of MP13 are connected in diode connection, and the feedback is provided to the negative input terminal FB of the operational amplifier. The source of MP14 is connected with the drain of MP13, and the gate and the drain of MP14 are connected, and the gate of MP14 is connected with the gate of MP11. MPn is a plurality of MOS tubes in diode connection, and the gate and the source of the last MOS tube are grounded.

[0040] The aforementioned reference voltage VREF is provided to MP10. MP7 to MP11 and MN10 to MN13 form the first stage of the op-amp. MP6, MN8, and MN9 provide bias voltage and current to the op-amp. MP6 and MP7 mirror the current of MP2. MN8 provides bias voltage to the gate voltages of MN10 and MN11. MP10 is connected to VREF. MP11 serves as the feedback input terminal FB. MP10 and MP11 form the input pair of the op-amp. MP12 and MN14 form the second stage of the op-amp. The gate of MP12 serves as the input terminal of the second stage. The gate of MN14 is connected to the gate of MN9. The current is proportional to MP6. The drain of MP12 serves as the output terminal of the op-amp, with an output voltage VOUT. The output terminal of the op-amp is connected to a diode-connected PMOS transistor. The gate of the PMOS transistor is connected from the feedback terminal FB to the input terminal MP11 of the op-amp. The diode connection is equivalent to a resistor, with a value approximately equal to... Therefore, to change the value of this resistor, it is necessary to change the transconductance of the MOSFET. Due to the voltage clamping relationship between the op-amp inputs, the voltage of MP11 is equal to the voltage of MP10. Since MP11 serves as the FB feedback terminal, then... The voltage at the output terminal FB It equals VREF because the MOSFETs connected to each diode have the same width and length, so the output voltage VOUT can be obtained proportionally. According to... Figure 3 Assuming a PMOS transistor with n diodes connected in series below the FB terminal, the voltage can be obtained. As long as the number of MOSFETs below the FB terminal remains constant, the output voltage will not change.

[0041] If you want to change the voltage without changing the number of MOSFETs connected in series below the FB terminal, you need to change the number of MOSFETs on the FB terminal. Since the MOSFETs connected to diodes are used as resistors, PMOS circuits with different numbers of diodes connected in parallel can change their equivalent resistance, and different output voltages VOUT can be obtained in this way.

[0042] This invention replaces the resistive feedback used in traditional LDOs with voltage divider feedback via diode-connected MOSFETs. This structure features ultra-low power consumption and a small area. Furthermore, the output voltage VOUT can be adjusted by changing the number of feedback MOSFETs.

[0043] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all such variations are intended to be included within the scope of the present application as defined in the claims below and their equivalents.

Claims

1. An ultra-low power low-dropout linear voltage regulator circuit, characterized by: The band gap reference circuit, the operational amplifier circuit, and the feedback circuit are included; the band gap reference circuit is used to generate a reference voltage VREF, the feedback circuit is used to generate different feedback voltages FB, and the operational amplifier circuit is used to generate a stable output voltage VOUT according to the reference voltage VREF and the feedback voltages FB; The operational amplifier circuit includes an operational amplifier, the reference voltage VREF output end of the band gap reference circuit is connected to the non-inverting input end of the operational amplifier, the feedback voltage FB output end of the feedback circuit is connected to the inverting input end of the operational amplifier, and the output end of the operational amplifier outputs the voltage VOUT; The feedback circuit includes a thirteenth PMOS tube, a fourteenth PMOS tube, and a diode connection structure in series; the diode connection structure includes a plurality of diode-connected PMOS tubes in series, which are used to change the voltage division value of each PMOS tube by changing the number of series PMOS tubes; the gate and the drain of the diode-connected PMOS tube are short-circuited; the source of the thirteenth PMOS tube is connected to the output voltage VOUT end of the operational amplifier circuit, the gate and the drain of the thirteenth PMOS tube are connected to the feedback voltage FB output end, the source of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, the gate and the drain of the fourteenth PMOS tube are connected to the first end of the diode connection structure, and the second end of the diode connection structure is grounded; The band gap reference circuit includes a PNP-type BJT tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube; The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are connected to the power supply VDD, the drain of the first PMOS tube is connected to the emitter of the PNP-type BJT tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube, the drain of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube, and the drain of the first NMOS tube are connected, the source of the first NMOS tube is connected to the drain of the second NMOS tube and the source of the fifth NMOS tube, the source of the second NMOS tube is connected to the drain and the gate of the third NMOS tube, the base and the collector of the PNP-type BJT tube are grounded, and the source of the third NMOS tube is grounded; The drain of the third PMOS tube is connected to the gate and the drain of the fourth NMOS tube and the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and the source of the seventh NMOS tube, the drain of the fourth PMOS tube is connected to the gate and the drain of the sixth NMOS tube and the gate of the seventh NMOS tube, the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected to the reference voltage VREF output end. The operational amplifier circuit further comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor and a fourteenth NMOS transistor; The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor and the twelfth PMOS transistor are connected to a power supply VDD, the gates of the sixth PMOS transistor and the seventh PMOS transistor are connected to a first end of the bandgap reference circuit, the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor and the gate of the eleventh NMOS transistor, the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor; The drain of the seventh PMOS transistor is connected to the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor, the gate of the tenth PMOS transistor is an in-phase input end of the operational amplifier, the gate of the eleventh PMOS transistor is an inverse-phase input end of the operational amplifier, the drain of the tenth PMOS transistor is connected to the source of the tenth NMOS transistor and the drain of the twelfth NMOS transistor, the drain of the eleventh PMOS transistor is connected to the source of the eleventh NMOS transistor and the drain of the thirteenth NMOS transistor, the gate of the eighth PMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the ninth PMOS transistor and the drain of the tenth NMOS transistor, the drain of the ninth PMOS transistor is connected to the drain of the eleventh NMOS transistor and the gate of the twelfth PMOS transistor, the drain of the twelfth PMOS transistor and the drain of the fourteenth NMOS transistor are connected and are an output voltage VOUT end, and the source of the ninth NMOS transistor, the drain of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor are grounded.

2. The ultra-low power low-dropout linear voltage regulator circuit according to claim 1, wherein: The feedback circuit further comprises a plurality of diode-connected PMOS transistors connected in parallel across the thirteenth PMOS transistor, for changing the voltage division value of each PMOS transistor by changing the number of parallel PMOS transistors, to obtain different output voltages.

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