Memory chip defect processing method and memory chip

Abstract

Embodiments of the present application provide a memory chip defect processing method and a memory chip, and belong to the technical field of semiconductor memories. The memory chip defect processing method comprises the following steps: testing a plurality of dies in a memory chip to obtain a physical address of a faulty unit with a defect in each die; encoding the physical address of each faulty unit and obtaining an encoded physical address of each faulty unit, so as to mark the faulty unit as unusable. The memory chip defect processing method and the memory chip can flexibly mark complex defect information, and improve the repair efficiency of the memory chip and the die yield of the memory chip.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor memory, and in particular to a method for handling defects in memory chips and a memory chip. Background Technology

[0002] In the field of semiconductor memory technology, dynamic random access memory (DRAM), such as LPDDR and DDR, inevitably produces memory cell defects during the manufacturing process. To improve chip yield, post-packaging repair mechanisms (such as Hard Post-Package Repair, hPPR) are commonly used. This type of repair mechanism utilizes pre-designed redundant resources (i.e., PPR resources) within the chip to remap the access path of faulty memory cells (such as the faulty row address) to redundant cells after packaging using an external testing machine.

[0003] A typical PPR resource allocation pattern is as follows: a die contains multiple memory banks (memory blocks, e.g., 8 memory blocks), and each memory block is typically equipped with an independent PPR repair resource. For a packaged chip containing multiple die stacks, the total number of PPR resources is the product of the number of dies and the number of memory blocks in each die (e.g., 8 dies × 8 memory blocks = 64 PPR resources). However, existing repair mechanisms have the following drawbacks:

[0004] Addressing resource bottlenecks: When more than one (or two) faults occur within the same memory block, the block has only one PPR resource, preventing the additional faults from being repaired. This leads to the failure or degradation of the entire memory chip, severely restricting the yield improvement of high-density memory chips. The time and economic costs of testing and repair also need to be considered.

[0005] Rigid repair process: Traditional hPPR repair heavily relies on external test machines, repair information databases, and rigid analysis processes. It lacks flexible resource management and dynamic allocation strategies for complex fault distributions (such as multiple storage blocks or multiple dies failing at the same time), resulting in decreased repair efficiency and success rate.

[0006] Poor portability of defect information: Even after a chip meets factory standards, a small number of unrepaired defects may still exist within it. These defect address information are typically stored in an external database. Applications must retrieve this defect information from the external database through a complex query process, which is cumbersome, inefficient, and inconvenient for system integration and real-time management.

[0007] In view of this, a novel method for handling memory chip defects and a memory chip are proposed to solve the above problems in whole or in part. Summary of the Invention

[0008] To address at least one of the aforementioned problems and deficiencies in the existing technology, embodiments of the present invention provide a memory chip defect handling method and a memory chip. By introducing encoded physical addresses, status registers, and fuse arrays using multiple encoding rules, it can flexibly handle the marking of complex memory chip defect information such as multiple row faults and multiple column faults, thereby improving memory chip repair efficiency and chip yield, and reducing the overall cost of chip manufacturing and testing. The technical solution is as follows:

[0009] According to one aspect of the present invention, a method for handling defects in a memory chip is provided. The method includes the following steps:

[0010] Test multiple bare dies in the memory chip to obtain the physical address of the faulty cell with defects in each die;

[0011] The physical address of each faulty unit is encoded, and the encoded physical address of each faulty unit is obtained, which is used to mark the faulty unit as unavailable.

[0012] Specifically, the faulty unit is a faulty unit that cannot be repaired and / or a faulty unit that cannot be relocated.

[0013] Further, the physical address of each faulty unit is encoded, and the encoded physical address of each faulty unit is obtained for marking the faulty unit as unavailable, including the following steps:

[0014] Configure the encoded physical address in the register;

[0015] The encoded physical address is burned into the fuse array on the bare die.

[0016] Specifically, the physical address written to the fuse array is a binary physical address. Each die is equipped with a fuse array, which includes multiple fuse units or multiple anti-fuse units. The fuse array blows a specified fuse or anti-fuse through the programming controller to write the encoded physical address into the memory chip.

[0017] Preferably, the register is a mode register for recording the usage status of PPR repair resources, and the fuse array is a fuse array for recording the usage status of PPR repair resources.

[0018] More preferably, based on the encoded physical address, the corresponding status bit of the PPR repair resource usage status in the mode register of each die is modified; based on the data formed by the combination of status bits in each die to express the physical address of the fault unit, the fuse array of the corresponding die is programmed.

[0019] Furthermore, the encoded physical address includes the encoding of the encoding rules and the encoding of the defect address information. The encoding of the encoding rules is used to provide the encoding rules for recording the physical address of the faulty unit, and the encoding of the defect address information is used to record the encoding of the physical address formed according to the encoding rules.

[0020] Specifically, memory chip defects include repairable defects, unrepairable row defects, and unrepairable column defects.

[0021] When an irreparable row defect exists, the defect address information encoding includes the die ID where the irreparable defect is located, the physical address of the storage block group, the physical address of the storage block, and the physical address of the row fault;

[0022] When an unrepairable column defect exists, the defect address information encoding includes the die ID where the unrepairable defect is located, the physical address of the storage block group, the physical address of the storage block, and the physical address of the column fault.

[0023] Furthermore, at least one set of bits is set in the encoded physical address to record the area of ​​row fault physical address and / or at least one set of bits is set to record the area of ​​column fault physical address.

[0024] Furthermore, redundant bits are set in the encoded physical address. These redundant bits are used to record encrypted information, extend storage, or retrieve database information recording memory chip defects, or any combination thereof.

[0025] Specifically, during the application phase, the faulty unit corresponding to the physical address is marked as unavailable through the system memory mapping table.

[0026] Specifically, marking the faulty unit corresponding to the physical address as unavailable through the system memory mapping table includes the following steps:

[0027] Decode the encoded physical address to obtain the decoded physical address;

[0028] Based on the decoded physical address, the corresponding block is marked as unavailable in the system memory mapping table.

[0029] Furthermore, the fault unit is a faulty row or faulty column on a storage block in the die of the memory chip.

[0030] When multiple fault behaviors are consecutive or multiple fault columns are consecutive, the corresponding block is an area formed by a combination of consecutive fault rows or a combination of consecutive fault columns.

[0031] When multiple fault rows or multiple fault columns are not contiguous, the corresponding block is an area formed by combining multiple non-contiguous fault rows located in the same memory block in the die with non-fault rows located between the multiple fault rows; or the corresponding block is an area formed by combining multiple non-contiguous fault columns located in the same memory block in the die with non-fault columns located between the multiple fault columns.

[0032] Furthermore, during the testing phase, the physical address of each faulty unit is obtained and recorded in the memory chip error address database, which is set in an external testing device.

[0033] Furthermore, during the testing phase, the encoded physical address is recorded in the memory chip error address encoding database, which is set in an external testing device; both the memory chip error address database and the memory chip error address encoding database use the die ID as an index.

[0034] According to another aspect of the present invention, a memory chip is provided. The memory chip includes a plurality of dies and a fault address storage unit for recording the physical address of a faulty cell, wherein each of the plurality of dies is provided with a fault address storage unit.

[0035] The memory chip performs memory chip defect processing using the memory chip defect processing method described above, and configures the physical address of the faulty unit in each die obtained through memory chip defect processing in the fault address storage unit. The physical address is the encoded physical address.

[0036] Furthermore, the fault address storage unit includes a register, a programming controller, and a fuse array. The encoded physical address is configured in the register, and the programming controller programs the fuse array based on the physical address configured in the register, so as to program the physical address of the fault unit into the memory chip.

[0037] Specifically, the register is a mode register, and the fuse array includes fuse units or antifuse units. By blowing the corresponding fuse unit or antifuse unit through the programming controller, the physical address of the faulty unit can be programmed into the memory chip.

[0038] The memory chip defect handling method and memory chip provided by the embodiments of the present invention have at least one or a portion of the following advantages:

[0039] (1) By introducing fault units with different encoding modes, the physical address and fault address storage unit (including registers and fuse array) after encoding can flexibly deal with the marking of complex memory chip defect information such as row faults and column faults, thereby improving the memory chip repair efficiency and chip yield in the memory chip.

[0040] (2) By using different encoding modes of fault units, the physical address, register and fuse array are encoded, even after the repair resources or relocation resources of some memory blocks are exhausted, the unrepaired defects can still be recorded by the encoded physical address and fault address storage unit, so that the memory chip can still meet the factory standard and be delivered for use even if there are a small number of unrepaired defects, which effectively improves the production yield of memory chips and reduces production costs.

[0041] (3) By storing the encoding information of unrepaired defects directly in the memory chip and delivering it to the application side along with the memory chip, the application side can directly read and decode the memory chip defect address information when the system starts up, without relying on complex external database queries, which greatly improves the ease of use and reliability of the application side.

[0042] (4) By storing the encoding information of unrepaired defects directly in the register and delivering it with the chip, the application can quickly and accurately mark the address of the unrepaired defect after the memory chip leaves the factory through a simple physical address to logical address mapping operation, which greatly improves the efficiency and reliability of the application system initialization.

[0043] (5) By compressing and redefining each bit, more memory chip defect address information can be efficiently recorded within a limited register bit width, thus optimizing repair resource management, improving testing and repair efficiency, and reducing the overall cost of chip testing.

[0044] (6) By using compression encoding and redundant bit settings, it provides scalable space within a limited bit width, providing a scalable solution for handling extreme failure situations (such as needing to switch to a cloud database to query repair information);

[0045] (7) By providing the application with encoded physical address and fault address storage units, the dependence on external test resources and database queries is effectively reduced, the process flow from production test to application use is simplified, thereby reducing the overall test cost and time cost.

[0046] (8) By establishing a memory chip defect record coding table in the cloud or on the server, it also helps to provide basic data to assist in optimizing the design and production process of memory chips, such as manufacturing process analysis, yield model training and AI learning. Attached Figure Description

[0047] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0048] Figure 1This is a schematic diagram of the overall steps of a memory chip defect handling method according to an embodiment of the present invention;

[0049] Figure 2 This is a flowchart illustrating the steps of implementing a memory chip defect handling method in the memory chip delivery and application stage according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram illustrating the process of decoding and marking the encoded physical address on the application side according to an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of the structure of a multi-die stacked register chip according to an embodiment of the present invention;

[0052] Figure 5 In order to be in Figure 4 A schematic diagram illustrating the principle of the encoded physical address formed in the mode register of one embodiment;

[0053] Figure 6 This is a flowchart illustrating the steps of implementing a memory chip defect handling method in the memory chip manufacturing process according to an embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram of a memory chip according to an embodiment of the present invention. Detailed Implementation

[0055] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0056] Embodiments of this invention provide a method for handling memory chip defects and a memory chip itself. By introducing encoded physical address and fault address storage units with different encoding modes or rules, it can flexibly handle the marking of complex memory chip defect information (physical addresses of fault units) such as centralized (multiple faults in the same memory block) and distributed (faults in different memory blocks), thus integrating the defect recording function. It is particularly suitable for defect management in the post-packaging repair process (e.g., based on the hPPR repair mechanism) of high-density memory chip modules (such as LPDDR and DDRDRAM), thereby improving the chip repair efficiency and chip yield, and reducing the overall cost of chip manufacturing and testing.

[0057] During the chip production and testing phase, external testing equipment inspects the memory chip modules to identify faulty cells (such as row and / or column faults in the memory blocks of the die). For memory chip defects that cannot be repaired by mechanisms such as hPPR, the physical address of the faulty cell is encoded and burned into the fuse array mode register of each die. Because this encoded faulty cell is burned / programmed into the fuse array, it can be delivered to the application with the chip without being written into transient volatile registers or memory, preventing unrepeatable access. Furthermore, by blowing or de-fusing the fuse, the physical address of the faulty cell cannot be tampered with for any reason. At startup, the application reads the encoded physical address, decodes it to obtain the memory chip defect address, and marks the block corresponding to the memory chip defect address as unusable using the system memory mapping table, thereby avoiding the use of locations in the memory chip that still contain defects.

[0058] The mode register is a programmable register in SDRAM used to configure the operating mode of the memory chip, typically programmed via commands such as `LOAD MODE REGISTER`. In embodiments of this invention, the mode register, originally used to record the usage status of PPR (Proof of Repair) resources, is repurposed to configure the encoded physical address of the faulty cell. Furthermore, the fuse array in the original die, originally used to record the PPR resource usage status, is also used to write the encoded physical address of the faulty cell. This repurposing eliminates the need for new registers or fuse units, thus preserving the original memory chip size and storage space. In one example, the bit width of the fuse array in the memory chip can be customized according to the memory chip structure. For instance, a memory chip may have eight dies, and each die may have an 8-bit fuse array to store information about the faulty cells within that die, resulting in a total of 64 fuse units in the memory chip. The physical address of the faulty cell supports multiple recording modes, allowing those skilled in the art to encode it based on different recording modes to adapt to different fault distribution scenarios.

[0059] Of course, those skilled in the art will understand that a memory chip can also contain 4 dies, 16 dies, etc., and the number of dies can be designed according to the actual needs of those skilled in the art. Those skilled in the art will also understand that multiple dies in a memory chip can be stacked on top of each other or arranged in parallel. Preferably, multiple dies are stacked. This example is merely an illustrative example and should not be construed as a limitation of the present invention.

[0060] See Figure 1 This document illustrates the overall step flow of a memory chip defect handling method according to an embodiment of the present invention. The memory chip defect handling method includes:

[0061] Step S100: Test multiple dies in the memory chip to obtain the physical address of the faulty cell with defects in each die;

[0062] Step S200: Encode the physical address of each faulty unit and obtain the encoded physical address of each faulty unit for marking the faulty unit as unavailable.

[0063] In one example, the implementation of this memory chip defect handling method mainly includes two stages: the chip production testing stage (testing stage) and the application stage (application stage).

[0064] In one example, specifically during the testing phase, the memory chip is tested using external testing equipment (e.g., an AOI-based automated optical inspection system). The testing process includes functional testing and defect scanning to identify the physical addresses of faulty cells (e.g., the row and / or column where the fault is located). Physical addresses typically include the die ID, block group address, bank address, row address, and / or column address.

[0065] The aforementioned testing phase also includes an encoding stage for the address location of the faulty unit. The physical address of the faulty unit is compressed and encoded to save storage space. The encoding method uses binary bit mapping. For example, if a total of 8 dies are used in the mode register, 3 bits can be used to mark all die IDs, i.e., 2 bits... 3 =8. Similarly, binary bit-mapped encoding can be performed on a number of memory blocks, fault rows, and fault columns. The encoded physical address is stored in a specified location in the mode register.

[0066] In one example, specifically during the application phase, the block corresponding to the physical address of the faulty unit is marked as unavailable using the system memory mapping table. This includes decoding the encoded physical address to obtain the decoded physical address; and marking the corresponding block as unavailable in the system memory mapping table based on the decoded physical address.

[0067] See Figure 2 This illustrates the steps involved in decoding the encoded physical address burned into the fuse array mode register of the chip by the application.

[0068] See Figure 3 This illustrates an example of an application decoding the encoded physical address mode register of a chip.

[0069] Combination Figure 2 and Figure 3As shown, when the application system starts, the CPU sends a command such as LOAD MODE REGISTER to read the physical address encoded in the fuse array from the memory chip mode register.

[0070] Decode the encoded physical address, parse the bit fields according to the table type, and restore the physical address of the faulty unit (e.g., die ID, address of storage block group and / or storage block, address of row and / or column).

[0071] Memory mapping is performed, mapping physical addresses to system linear logical addresses, and the corresponding blocks are marked as "unavailable" in the system memory mapping table. After marking, the system can mask and skip these faulty blocks when allocating memory chips.

[0072] In one example, specifically, the faulty unit is an unrepairable faulty unit and / or an unrelocatable faulty unit.

[0073] During testing, hPPR repair resources are limited (e.g., each storage block typically has only one repair resource). When multiple failures occur in the same storage block, some failures cannot be repaired or relocated. These unrepairable faulty cells will be preferentially programmed / written into the fuse array.

[0074] In one example, relocation technology establishes a correspondence between the program logic address space and the physical memory chip address space through an address mapping mechanism. Relocation is typically used to relocate faulty rows and columns in the memory chip to redundant rows and columns reserved in the memory chip, so as to convert the data that needs to be stored in the faulty rows and columns to the corresponding redundant rows and columns for storage.

[0075] In one example, encoding the physical address of each faulty unit and obtaining the encoded physical address of each faulty unit for marking the faulty unit as unavailable includes the following steps:

[0076] Configure the encoded physical address in the register;

[0077] The encoded physical address is burned into the fuse array on the bare die.

[0078] In one example, the register is used to test communication between the device (not shown) and the memory chip. Preferably, the register is a mode register (i.e., an MR register).

[0079] During use, the MR register receives the encoded physical address sent by the test device, which is represented in binary. Simultaneously, the MR register receives either a programming instruction or a write instruction from the test device. Based on the programming instruction and the encoded physical address, the programming controller generates or releases high voltage or high current at the corresponding bit in the fuse array to blow the fuse or anti-fuse at that bit, thereby writing the encoded physical address into the corresponding die of the memory chip.

[0080] In one example, a blown fuse in a fuse cell represents a binary value of 1 for that bit, while a non-blown fuse represents a binary value of 0. When the fuse array contains either or all antifuse cells, a fuse cell with a non-blown antifuse represents a binary value of 1 for that bit, while a fuse cell with a blown antifuse represents a binary value of 0 for that bit.

[0081] In one example, it is more preferable to configure the MR register as a register for recording the usage status of PPR repair resources, and the fuse array as a fuse array for recording the usage status of PPR repair resources. In use, since the encoded physical address is represented in binary, and the recorded usage status of the PPR repair resources is also represented in binary, the encoded physical address can be characterized by changing the binary value of the status bit in the MR register representing the usage status of the PPR repair resources.

[0082] Specifically, based on the encoded physical address, the corresponding status bit of the PPR repair resource usage status in the MR register of each die is modified;

[0083] The fuse array of the corresponding die is programmed based on the data formed by the combination of status bits in each die to express the physical address of the fault cell.

[0084] For example, when the encoded physical address is 10010011, the corresponding 8 status bits in the MR register, which records the usage status of PPR repair resources, are all 1, and the combination of the 8 status bits (also called a bit sequence or bit string) is 11111111. When the MR register receives the encoded physical address and the burning instruction sent by the test device, based on the encoded physical address 10010011, the MR register consumes the PPR resources corresponding to the 3rd, 4th, 6th, and 7th bits of its own status bits 11111111, which represent the usage status of PPR repair resources, so that the usage status of the PPR repair resources corresponding to that bit is updated to 0. Thus, the usage status of PPR resources in the MR register is modified to the combination or bit sequence 10010011.

[0085] Next, the programming controller reads the status bit of the PPR repair resource in the MR register, obtaining a status bit content of 10010011, and programs the fuse array corresponding to the PPR resource usage status on the die based on this status bit data. A large voltage or current is applied to the bit corresponding to the binary value "1" in the fuse array to blow the fuse of that fuse unit, or a large voltage or current is applied to the bit corresponding to the binary value "0" in the fuse array to blow the anti-fuse of that fuse unit. This achieves the programming of the encoded physical address into the fuse array of the corresponding die, ensuring that each memory chip, when delivered to the user, has the physical address of the faulty unit, and that this physical address is non-volatile and non-transiently recorded in the memory chip.

[0086] In one example, the encoded physical address includes the encoding of the encoding rules and the encoding of the defect address information. The encoding of the encoding rules is used to provide the encoding rules for recording the physical address of the faulty unit, and the encoding of the defect address information is used to record the encoded physical address formed according to the encoding rules.

[0087] In one example, when the MR register stores the encoded physical address of a faulty cell, the data in this encoded physical address includes the encoding rule, the die physical address, the memory group physical address, the memory block physical address, and the memory row (or memory column) physical address. The data structure of the decoded physical address can be set as follows: {Rule, die, Group, Bank, Row1, Row2}, {Rule, die, Group, Bank, Row1:Row3}, {Rule, die, Group, Bank, Column1, Column3}, {Rule, die, Group, Bank, Column1:Column2}. The encoded physical address of the faulty cell is obtained by encoding the contents of the above data structures.

[0088] See Figure 4 The diagram illustrates the structure of a chip with a mode register in one embodiment.

[0089] See Figure 5 The diagram illustrates the principle of encoded physical address in one embodiment.

[0090] Combination Figure 4 and Figure 5As shown, the mode register stacks a total of 8 dies and marks them with die ID (marked as die0-die7). At the same time, each die has 8 memory blocks (marked as bank0-bank7), thus forming a 64-bit (marked as bit0-bit63) MR register based on an 8 die × 8 memory block architecture. Each bit initially corresponds to a PPR repair resource.

[0091] In one example, the fault unit is either a fault row or a fault column, and the block marking method is adjusted according to the continuity of the fault.

[0092] In one example, the faulty unit is a continuous fault, where multiple faulty rows are consecutive (e.g., rows 100-105). These rows are then grouped into a continuous area and marked as unavailable.

[0093] In one example, the faulty unit is a discontinuous fault, where the faulty rows are not consecutive (e.g., rows 100, 150, 200). These faulty rows are then combined with the non-faulty rows in between and marked as an unavailable area. This marking principle reduces the amount of mapping information. For example, rows 100-200 can be marked as a whole to simplify management.

[0094] Similar to the marking principles for consecutive or non-consecutive fault rows mentioned above, the same marking principles or coding strategies can be adopted and selected for fault columns, which will not be elaborated here.

[0095] In one example, the encoded physical address is structured as a bit field and stored in the MR register. In another example, the encoding rule is defined by the high-order bits, while the defect address information is encoded by occupying the remaining bits.

[0096] In one example, specifically, the encoding rule can typically be preset to one encoding rule, or multiple encoding rules, and can also be customized according to the needs of those skilled in the art. This encoding rule usually occupies the highest few bits of the mode register, for example... Figure 5 The schematic diagram uses bits 63-60 for identification, with encoding rules of tabel 0000, tabel 0001, and tabel 0010 respectively.

[0097] tabel 0000 indicates the standard recording mode, meaning the chip follows the JEDEC standard without specific exclusions. It usually indicates that all PPR resources are available or that recording is done according to the default rules.

[0098] tabel 0001 indicates a centralized defect recording mode, which is suitable for recording the defect address information (i.e., the physical address of the faulty cell) or defect address information encoding (i.e., the encoding of the physical address of the faulty cell) of multiple unrepaired memory chips within the same storage block.

[0099] tabel 0010 indicates a distributed defect recording mode, which is suitable for recording unrepaired memory chip defect address information (i.e., the physical address of the faulty cell) or defect address information encoding (i.e., the encoding of the physical address of the faulty cell) scattered in different storage blocks.

[0100] Other table types can also be identified, such as table 1111, indicating that the register space is insufficient to record all unrepaired memory chip defect address information (i.e., the physical address of the faulty cell) or defect address information encoding (i.e., the encoding of the physical address of the faulty cell), requiring additional queries to a database recording chip repair information and error information. These are merely illustrative examples and should not be construed as limiting the invention.

[0101] In one example, specifically, the types of memory chip defects include repairable defects, unrepairable row defects, and unrepairable column defects. Defect address information includes die ID, group ID, bank address, and row or column address. Preferably, the encoded physical address includes a region for recording the physical address of the row / column fault. When the faulty cell is in the same bank, its row address is recorded; when the faulty cells are distributed across different banks on the same die, its column address is recorded. The defect address information encoding includes: encoding rules, die ID, group ID, bank address, and row or column address encoding.

[0102] The application determines which encoding rule is currently being used by reading the values ​​of bits 63-60 (table T3 T2 T1 T0), and then calls the corresponding decoding algorithm to decode and map the encoded physical address.

[0103] In one example, further, to Figure 5 Taking table 0001, which represents the centralized defect record mode, as an example, we can illustrate its corresponding encoding method or encoding rule.

[0104] Tabel 0001 is an encoding rule for a centralized defect recording pattern. To clearly and explicitly record the defect address information of memory chips, i.e., the physical address of the faulty cell, the memory chip defect recording pattern uses a centralized defect recording pattern. This pattern is used to record the encoding of multiple defect address information within the same memory block of the chip. This centralized defect recording pattern is generally suitable when the memory chip has few defects at the time of factory delivery, clearly marking the physical address of each faulty cell in the memory chip through a layer-by-layer, line-by-line recording method.

[0105] Tabel 0001 includes, in sequence, the defective die ID (die7-die0), the defective storage block group ID (Group1-Group0), the defective storage block address (bank3-bank0), and a number of row fault addresses (row1-row3) (3 in tabel 0001).

[0106] For example, in the row containing the defective die ID, D2, D1, and D0 indicate that all 8 die IDs can be marked by binary encoding every 3 bits, i.e., 2 3 =8.

[0107] Similarly, the row containing the defective block group ID, with G1 and G0 filled in, indicates that all four defective block group IDs can be marked by binary encoding using every two bits. The row containing the defective block address, with B3, B2, B1, and B0 filled in, indicates that all 16 block addresses for each defective block group ID can be marked by binary encoding using every four bits.

[0108] For example, if we need to record the three row fault addresses (row1, row2, row3) in bank1 (binary code B=0001) under Group1 (binary code G=01) of die5 (binary code D=101), then the encoding rule using table 0001 is as follows:

[0109] bit63-bit60 (T3-T0): Set to 0001, indicating that this is the tab 0001 of the centralized defect recording mode.

[0110] bit59-bit57 (D2-D0): Setting this to 101 indicates that the defective die ID is die5.

[0111] bit56-bit55 (G1-G0): Setting this to 01 indicates that the defective storage block group ID is Group1.

[0112] bit54-bit51 (B3-B0): Setting it to 0001 indicates that the defective storage block is bank1.

[0113] Subsequent bits are divided into multiple row encoding segments:

[0114] bit50-bit34: Used to record the first row fault address row1 (R16-R0, a total of 17 bits, the actual number of bits can be adjusted according to the row address width).

[0115] bit33-bit17: Used to record the second row fault address, row2.

[0116] bit16-bit0: Used to record the third row fault address row3.

[0117] When the application decodes, after recognizing the encoding rule as table 0001, it extracts the encoding of die, group, bank and each row corresponding to the fault unit in sequence according to the bit allocation rule mentioned above, combines them into a complete physical address and then maps it to a linear logical address to mark the unusable blocks of the memory chip.

[0118] Similarly, centralized defect record encoding of fault addresses can be performed, which will not be elaborated here.

[0119] In one example, similarly, with Figure 5 Taking table 0010, which represents the distributed defect record pattern, as an example, we can illustrate its corresponding encoding method or encoding rule.

[0120] Tabel 0010 is an encoding rule for a distributed defect recording pattern. To record a larger number of memory chip defect address information, i.e., the physical addresses of faulty cells, the distributed defect recording pattern is used. This pattern is used to encode defect address information in different memory blocks within the chip. This distributed defect recording pattern is actually a compressed writing pattern, generally used when the chip has many defects at the time of factory delivery (but meets chip delivery requirements). Compression allows for the marking of more physical addresses of faulty cells within the memory chip.

[0121] The binary encoding principle is the same as that of table 0001 in the centralized defect recording mode, so it will not be repeated here. The difference is that by grouping the storage block address encoding and the row fault address encoding together, compressed recording of defects in different storage blocks is achieved, which improves the utilization rate of the bits in the mode register.

[0122] For example, if we need to record the row fault addresses of three different banks in Group 1 (binary G=00) of die2 (binary code D=010): row A of bank3 (binary code B=0100), row B of bank2 (binary code B=0010), and row C of bank0 (binary code B=0000), then the encoding rule for table 0010 is as follows:

[0123] bit63-bit60 (T3-T0): Set to 0010, indicating that this is the tab 0010 of the distributed defect recording mode.

[0124] bit59-bit57 (D2-D0): Setting this to 010 indicates that the defective die ID is die2.

[0125] bit56-bit55 (G1-G0): Setting this to 00 indicates that the defective storage block group ID is Group0.

[0126] Subsequent bits are divided into multiple bank-row combined encoding segments:

[0127] The first group (bit54-bit37) contains the storage block code (B3-B0, for example, binary code 0100 represents bank3) and the corresponding row fault address code (R16-R3, a total of 14 bits, representing row A).

[0128] The second group (bit36-bit19) contains the storage block code (B3-B0, for example, binary code 0010 represents bank2) and the corresponding row fault address code (R16-R3, representing row B).

[0129] The third group (bit18-bit1) contains the storage block code (B3-B0, for example, binary code 0000 represents bank0) and the corresponding row fault address code (R16-R3, representing row C).

[0130] Similarly, centralized defect record encoding of fault addresses can be performed, which will not be elaborated here.

[0131] In one example, preferably, the encoded physical address also includes redundant bits. These redundant bits are used to record encrypted information, extend storage, or invoke defect repair record database information, or any combination thereof.

[0132] by Figure 5 For example, in the tabel 0010 of the distributed defect recording mode, the remaining bit 0 can be used as a redundant bit or a reserved bit.

[0133] Furthermore, depending on the amount of recorded memory chip defect address information encoded, some bits can be reserved as redundant or reserved bits in any of the above encoding rules. These redundant or reserved bits can be used for, for example: encryption, storing simple checksums and / or keys to ensure the integrity and security of defect record information; extended storage, using redundant bits to store additional address information bits when the main recording area is insufficient; and external chip testing and repair database call indication, where redundant bits can store an index number or hash value, allowing the application to query the cloud database for more detailed repair solutions or defect information, etc.

[0134] In one example, to further improve fault tolerance and encoding efficiency, the encoded bit sequence can be shuffled before writing the encoded physical address to the register. After reading the bit sequence, the application must rearrange it according to a preset reversal rule to decode it correctly. This method can mitigate the impact of consecutive failures and enhance the information's resistance to interference to some extent.

[0135] In one example, when the memory chip has insufficient storage cells for recording defects, the encoded physical addresses are stored in the database. If the number of defects exceeds the fuse array capacity (e.g., the redundant bit encoding information in table 1111 indicates insufficient defect record resources), a database query is triggered. The external testing equipment uploads the defect addresses to a cloud database, and the application accesses this cloud database via the network to obtain a complete list of defect information. Furthermore, this database can also analyze historical data on chip testing and memory chip defect handling based on AI models to optimize processes and repair strategies.

[0136] For example, the bit allocation and encoding length (such as row address being 17 bits or 14 bits) listed in the above embodiments are merely examples. In actual applications, adjustments need to be made based on the specific chip architecture (such as the number of dies, the number of memory blocks, the address width of the row, etc.). These are only illustrative examples and should not be construed as limiting the present invention.

[0137] See Figure 6 This illustrates the steps of implementing a memory chip defect handling method during the production testing phase (testing stage) of a chip according to one embodiment.

[0138] In one example, specifically during the testing phase, the faulty physical address is obtained and recorded in the memory chip error address database; the database is set up in an external testing device; the encoded physical address is recorded in the memory chip error address encoding database; both databases are indexed by the die ID, which facilitates quick retrieval and tracing of chip production batches and obtaining corresponding memory defect information, error addresses, error address codes, etc.

[0139] In one example, the encoded physical address stored in the memory chip error address encoding database can be binary, or in other bases (such as hexadecimal, octal, etc.), or in a form compiled into a programming language. When configured into a register, the encoded physical address in other bases or expressed in a programming language is assembled into binary form and configured into the status bits of, for example, a mode register (i.e., the MR register) used to record the usage status of PPR repair resources. This allows the encoded physical address to be expressed in binary form at registers and fuse arrays.

[0140] In other words, regardless of the form in which the encoded physical address is expressed in the database, local device, or cloud, it has been converted into a binary encoding form when configured into a register. That is, when configured into a register, the encoding of the encoding rules and the encoding of the defect address information are both converted into binary form, and the binary encoded physical address is burned or recorded in the fuse array.

[0141] In one example, the overall testing process includes: AOI inspection and 5DP testing to identify the physical address of the defect and store it in the memory chip error address database. The encoder compresses the physical address into a bit sequence or bit string format and stores it in the memory chip error address encoding database. The testing equipment writes the data into the MR register according to the encoding table.

[0142] In one example, specifically during the chip production and testing phase, the chip undergoes memory chip testing by an external testing machine, and defects and faults present in the memory chip are repaired after packaging (e.g., using the hPPR repair mechanism). Simultaneously, any remaining memory chip defects after packaging and repair are first stored in an external database for storing chip error address information. Then, the information in the database is written into the chip's mode register using different encoding methods, thereby encoding the physical address information of the memory chip defects according to different predetermined rules to form different encoded physical addresses.

[0143] Theoretically, repeated packaging and repair can improve the repair rate of memory chips, meaning more and more memory chip defects can be repaired. However, chip testing and repair incur time and economic costs. Therefore, considering the control of overall manufacturing costs, the number of tests and repairs, the repair rate, and chip qualification standards need to be adjusted while adhering to industry standards. In other words, a certain number of unrepaired or unrepairable memory chip defects are allowed after the chip leaves the factory and has undergone testing and repair. The design of the MR register, fuse array, and binary encoded physical address is to mark the physical addresses of these unrepaired or unrepairable faulty units and simultaneously provide corresponding encoding rules, which are delivered to the application for reading and processing along with the chip. This ensures the accuracy and convenience of the physical addresses of the decoded faulty units obtained later.

[0144] See Figure 7 The diagram illustrates the principle structure of a memory chip according to one embodiment. The memory chip 100 includes a die 110 and a fault address storage unit 120. The memory chip 100 processes memory chip defects using the memory chip defect handling methods described in the above embodiments, and stores the physical address of the faulty unit in the memory chip 100 in the fault address storage unit 120. The fault address storage unit 120 is configured with a fuse array 123, which has multiple rows of fuse units for recording row / column fault physical addresses.

[0145] For example, the memory chip 100 includes a stacked plurality of dies 110 and a fault address storage unit 120. Each die 110 contains a plurality of memory blocks. The fault address storage unit 120 includes a register 121, a programming controller 122, and a fuse array 123. The encoded physical address is configured in the register 121, and the programming controller 122 programs the fuse array 123 based on the physical address configured in the register 121, thereby programming the physical address of the faulty unit into the memory chip 100.

[0146] In one example, register 121 is a mode register, preferably an MR register that records the usage status of PPR repair resources. Each die 110 is matched with a fuse array 123, and each fuse array 123 includes multiple fuse units (not shown) or antifuse units (not shown). By blowing the corresponding fuse unit or antifuse unit through the programming controller 122, the physical address of the faulty unit is programmed into the memory chip 100.

[0147] In one example, the fuse array 123 has a total bit width of 64 bits (taking 8 dies × 8 bits as an example). The fuse array 123 can be partitioned into bit fields according to the binary rules of the above embodiments, for example, using... Figure 5The table shown is 0001 or 0010, and other encoding rules based on similar principles are used.

[0148] In one example, specifically, during the testing phase, the physical addresses of memory chip defects (physical addresses of faulty cells) detected by external testing equipment and not repaired are used to generate encoded physical addresses. These encoded physical addresses are then programmed / encoded into fuse array 123 and delivered to the application along with memory chip 100. The application reads the encoded physical addresses of the faulty cells programmed into fuse array 123 and decodes them to obtain the physical addresses of faulty cells in memory chip 100 that have defects, faults, or errors. These faulty cell physical addresses are then marked as unavailable in the application's system memory mapping table for masking purposes.

[0149] The memory chip defect handling method and memory chip provided by the embodiments of the present invention have at least one or a portion of the following advantages:

[0150] (1) By introducing fault units with different encoding modes, the physical address and fault address storage unit (including registers and fuse array) after encoding can flexibly deal with the marking of complex memory chip defect information such as row faults and column faults, thereby improving the memory chip repair efficiency and chip yield in the memory chip.

[0151] (2) By using different encoding modes of fault units, the physical address, register and fuse array are encoded, even after the repair resources or relocation resources of some memory blocks are exhausted, the unrepaired defects can still be recorded by the encoded physical address and fault address storage unit, so that the memory chip can still meet the factory standard and be delivered for use even if there are a small number of unrepaired defects, which effectively improves the production yield of memory chips and reduces production costs.

[0152] (3) By storing the encoding information of unrepaired defects directly in the memory chip and delivering it to the application side along with the memory chip, the application side can directly read and decode the memory chip defect address information when the system starts up, without relying on complex external database queries, which greatly improves the ease of use and reliability of the application side.

[0153] (4) By storing the encoding information of unrepaired defects directly in the register and delivering it with the chip, the application can quickly and accurately mark the address of the unrepaired defect after the memory chip leaves the factory through a simple physical address to logical address mapping operation, which greatly improves the efficiency and reliability of the application system initialization.

[0154] (5) By compressing and redefining each bit, more memory chip defect address information can be efficiently recorded within a limited register bit width, thus optimizing repair resource management, improving testing and repair efficiency, and reducing the overall cost of chip testing.

[0155] (6) By using compression encoding and redundant bit settings, it provides scalable space within a limited bit width, providing a scalable solution for handling extreme failure situations (such as needing to switch to a cloud database to query repair information);

[0156] (7) By providing the application with encoded physical address and fault address storage units, the dependence on external test resources and database queries is effectively reduced, the process flow from production test to application use is simplified, thereby reducing the overall test cost and time cost.

[0157] (8) By establishing a memory chip defect record coding table in the cloud or on the server, it also helps to provide basic data to assist in optimizing the design and production process of memory chips, such as manufacturing process analysis, yield model training and AI learning.

[0158] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for handling defects in a memory chip, characterized in that, The method for handling memory chip defects includes the following steps: Test multiple bare dies in the memory chip to obtain the physical address of the faulty cell with defects in each die; The physical address of each faulty unit is encoded to obtain the encoded physical address of each faulty unit, which is used to mark the faulty unit as unavailable. The encoded physical address includes the encoding of the encoding rule and the encoding of the defect address information. The encoding of the encoding rule is used to provide the encoding rule for recording the physical address of the faulty unit, and the encoding of the defect address information is used to record the encoding of the encoded physical address formed according to the encoding rule. The defect address information encoding includes one or any combination of the following: die ID, memory block group ID, memory block address, row address, and column address encoding.

2. The memory chip defect handling method according to claim 1, characterized in that, The faulty unit is an unrepairable faulty unit and / or an unrelocatable faulty unit.

3. The memory chip defect handling method according to claim 1, characterized in that, Encoding the physical address of each faulty unit and obtaining the encoded physical address of each faulty unit for marking the faulty unit as unavailable includes the following steps: Configure the encoded physical address in the register; The encoded physical address is burned into the fuse array in the bare die.

4. The memory chip defect handling method according to claim 3, characterized in that, The physical address written to the fuse array is a binary physical address. Each die contains the aforementioned fuse array. The fuse array includes multiple fuse units or multiple anti-fuse units. The fuse array melts a specified fuse or anti-fuse through a programming controller to write the encoded physical address into the memory chip.

5. The memory chip defect handling method according to claim 3 or 4, characterized in that, The register is a mode register used to record the usage status of PPR repair resources. The fuse array is used to record the usage status of PPR repair resources.

6. The memory chip defect handling method according to claim 5, characterized in that, Based on the encoded physical address, modify the corresponding status bit of the PPR repair resource usage status in the mode register of each die; The fuse array of the corresponding die is programmed based on the data formed by combining the status bits in each die to express the physical address of the fault unit.

7. The memory chip defect handling method according to claim 6, characterized in that, Memory chip defects include repairable defects, unrepairable row defects, and unrepairable column defects. When an irreparable row defect exists, the defect address information encoding includes the die ID where the irreparable defect exists, the physical address of the memory block group, the physical address of the memory block, and the physical address of the row fault. When an unrepairable column defect exists, the defect address information encoding includes the die ID where the unrepairable defect is located, the physical address of the storage block group, the physical address of the storage block, and the physical address of the column fault.

8. The memory chip defect handling method according to claim 5, characterized in that, In the encoded physical address, at least one set of bits is set for the area to record the physical address of a row failure and / or at least one set of bits is set for the area to record the physical address of a column failure.

9. The memory chip defect handling method according to claim 5, characterized in that, The encoded physical address also includes redundant bits, which are used to record encrypted information, extend storage, or retrieve database information recording memory chip defects, or any combination thereof.

10. The method for handling memory chip defects according to any one of claims 1-4, characterized in that, During the application phase, the faulty unit corresponding to the physical address is marked as unavailable through the system memory mapping table.

11. The memory chip defect handling method according to claim 10, characterized in that, Marking the faulty unit corresponding to the physical address as unavailable through the system memory mapping table includes the following steps: Decode the encoded physical address to obtain the decoded physical address; Based on the decoded physical address, the corresponding block is marked as unavailable in the system memory mapping table.

12. The memory chip defect handling method according to claim 11, characterized in that, The fault unit is a faulty row or faulty column on a storage block in the die of the memory chip. When multiple fault behaviors are consecutive or multiple fault columns are consecutive, the block is a region formed by a combination of consecutive fault rows or a region formed by a combination of consecutive fault columns. When multiple fault rows or multiple fault columns are not contiguous, the block is an area formed by combining multiple non-contiguous fault rows located in the same memory block in the die and non-fault rows located between the multiple fault rows, or The block is a region formed by combining multiple non-contiguous fault columns located in the same memory block in the die and non-fault columns located between the multiple fault columns.

13. The memory chip defect handling method according to claim 5, characterized in that, During the testing phase, the physical address of each faulty unit is obtained and recorded in the memory chip error address database. The memory chip error address database is set in an external testing device.

14. The memory chip defect handling method according to claim 13, characterized in that, During the testing phase, the encoded physical address is recorded in the memory chip error address encoding database. The memory chip error address encoding database is set in the external testing equipment. Both the memory chip error address database and the memory chip error address encoding database use the die ID as an index.

15. A memory chip, characterized in that, The memory chip includes multiple dies and a fault address storage unit for recording the physical address of faulty units. Each of the multiple dies is equipped with the fault address storage unit. The memory chip undergoes memory chip defect processing using the memory chip defect processing method described in any one of claims 1-14, and the physical address of the faulty cell in each die obtained through the memory chip defect processing is configured in the fault address storage unit. The physical address is the encoded physical address.

16. The memory chip according to claim 15, characterized in that, The fault address storage unit includes a register, a programming controller, and a fuse array. The encoded physical address is configured in the register, and the programming controller programs the fuse array based on the physical address configured in the register, so as to program the physical address of the fault unit into the memory chip.

17. The memory chip according to claim 16, characterized in that, The register is a mode register, and the fuse array includes fuse units or antifuse units. The physical address of the faulty unit is written into the memory chip by blowing the corresponding fuse unit or anti-fuse unit through the programming controller.

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