Flip chip device and method of flip chip device packaging

Abstract

The application provides a device flip-chip soldering packaging method and a flip-chip soldering device, and belongs to the technical field of semiconductor device packaging. The device flip-chip soldering packaging method comprises the following steps: providing a flip-chip with a first on-chip metal and a substrate chip with a second on-chip metal, the first on-chip metal is provided with an interconnection metal array and a first spacer which are spatially isolated away from one side of the flip-chip, and the second on-chip metal is provided with a solder metal array and a second spacer which are spatially isolated away from one side of the substrate chip; turning over the flip-chip and aligning it with the substrate chip, wherein the first spacer is nested in the second spacer by turning over the flip-chip, and the alignment of the interconnection metal array and the solder metal array is realized by external correction; heating the aligned flip-chip and substrate chip in a reducing gas atmosphere to melt the solder metal, realize the welding of the interconnection metal array and the solder metal array, and thus obtain a flip-chip soldering device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device packaging technology, specifically relating to a flip-chip packaging method and a flip-chip device. Background Technology

[0002] Flip-chip bonding is an advanced semiconductor packaging process that stacks multiple chips vertically or horizontally to redistribute metal electrodes on the chip surface and modularly integrate chips with different functions. Since its inception, flip-chip bonding has undergone continuous evolution in structure and process. Early 2D packaging used solder ball arrays to electrically interconnect the chip and fan out signals from the packaging substrate. Subsequent 2.5D and 3D packaging technologies further introduced redistribution layers (RDLs) and through-silicon vias (TSVs) to achieve finer arrangement and electrical isolation of metal electrodes. Overall, flip-chip bonding technology has consistently developed towards two core directions: increasing the density of interlayer electrode interconnections and optimizing the performance of interlayer electrical connections.

[0003] In practical application, the mechanical and electrical connections between flip chips and substrate chips are achieved through solder bumps. Therefore, miniaturizing bump size and reducing pitch are crucial for improving flip-chip bonding performance. Traditional solder bump bonding processes are limited by the inherent properties of the materials themselves, facing constraints in processing accuracy, mechanical stability, and electrical performance. Solder bump sizes are typically in the tens of micrometers range, and pitches are often greater than fifty micrometers. To overcome these limitations, the industry has developed direct bonding processes such as dielectric-dielectric bonding and copper-copper bonding, successfully compressing solder bump sizes to the micrometer level and reducing pitches to around ten micrometers. However, direct bonding processes are extremely demanding, requiring bonding temperatures of several hundred degrees Celsius and high bonding pressures, while also demanding extremely clean solder bump surfaces and an unrepairable connection interface. These requirements limit the application of this technology in many device systems, such as quantum computing, where the core chips typically cannot withstand the high temperatures and pressures required for direct bonding (typically 300-800°C and 0.1-10 MPa). On the other hand, quantum chips also require the integration of a large number of qubits and the interconnection between upper and lower chips, while traditional solder bump bonding is difficult to meet the requirements of high-density interconnection and electrical performance.

[0004] Furthermore, another key factor in achieving higher interconnect density and better electrical performance with flip-chip bonding technology is alignment accuracy. In current processes, alignment primarily relies on a high-precision optical vision system and a multi-axis displacement platform. Motor-driven and guide rail-mounted upper and lower die stages are used to precisely position the patterned structure between the upper and lower chips. However, high-precision equipment is often expensive. Although self-alignment solutions that do not rely on high-precision equipment have been proposed, these methods are typically complex and still suffer from low alignment accuracy, insufficient soldering reliability, and difficulty in meeting the electrical performance requirements of high-density interconnects. Summary of the Invention

[0005] This invention provides a flip-chip bonding packaging method and a flip-chip bonding device, aiming to at least partially solve the above-mentioned technical problems. The specific technical solution provided by this invention is as follows.

[0006] As a first aspect of the present invention, a flip-chip bonding packaging method is provided, comprising: providing a flip chip and a substrate chip, wherein a first on-chip metal is deposited on the surface of the flip chip, and an interconnect metal array and a first limiter spatially isolated from each other are deposited on the side of the first on-chip metal opposite to the flip chip; a second on-chip metal is deposited on the surface of the substrate chip, and a solder metal array and a second limiter spatially isolated from each other are deposited on the side of the second on-chip metal opposite to the substrate chip; flipping the flip chip and aligning it with the substrate chip, wherein the interconnect metal array and the solder metal array are aligned by external correction, wherein the external correction is to apply momentum to the substrate chip to adjust the position of the flip chip relative to the substrate chip; and heating the aligned flip chip and the substrate chip in a reducing gas atmosphere to melt the solder metal, thereby bonding the interconnect metal array to the solder metal array to obtain a flip-chip bonded device.

[0007] As a second aspect of the present invention, a flip-chip bonding device is provided, which is prepared by the above-described flip-chip bonding packaging method.

[0008] In this embodiment of the invention, a first limiter and a second limiter are deposited on the on-chip metal of the flip chip and the substrate chip, respectively. The movement of the flip chip is restricted by the first and second limiters, aligning the interconnect metal array on the flip chip and the solder metal array on the substrate chip, followed by soldering to obtain a flip-chip bonded device. This invention provides a high-precision and easily implemented flip-chip bonding packaging method, reducing the difficulty of implementing higher-precision flip-chip bonding. It achieves micron or even sub-micron error control in both horizontal and vertical directions, while eliminating the need for complex flip-chip alignment equipment, thus reducing manufacturing costs. This invention provides a new approach for implementing higher-precision aligned classical semiconductor chips and quantum chips, and brings new ideas to the design of flip-chip bonding equipment. Attached Figure Description

[0009] Figure 1 This is a flowchart of the device flip-chip packaging method in an embodiment of the present invention;

[0010] Figure 2 This is a top view of the substrate chip in an embodiment of the present invention;

[0011] Figure 3 This is a top view of the flip chip structure in an embodiment of the present invention;

[0012] Figure 4 This is a top view of the flip-chip bonding device in an embodiment of the present invention;

[0013] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the AA direction;

[0014] Figure 6 This is a schematic cross-sectional view of the interconnect metal and solder metal when aligned in an embodiment of the present invention.

[0015] Figure 7 This is a schematic diagram of the structure of the first alignment mark in an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of the structure of the second alignment mark in an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of the structure after the first alignment mark and the second alignment mark are aligned in an embodiment of the present invention;

[0018] Figure 10 This is a schematic diagram of the structure of the chip and the external auxiliary welding system during the external correction process in an embodiment of the present invention;

[0019] Figure 11 This is a flowchart of the device flip-chip bonding and packaging method in Embodiment 1 of the present invention;

[0020] Figure 12 This is a schematic diagram of the momentum application and the relative displacement of the chip during the external correction process in Embodiment 1 of the present invention;

[0021] Figure 13 This is a time flow chart of welding process Q3 in Embodiment 1 of the present invention;

[0022] Figure 14 This refers to the chip spacing of the flip-chip device after pressure bonding in Embodiment 1 of the present invention;

[0023] Figure 15 This is a graph showing the microwave signal measurement results of the flip-chip device in Embodiment 1 of the present invention, with and without the interconnect metal via electrodes.

[0024] Figure 16 for Figure 15 A comparison of microwave signal quantities between metals interconnected by electrodes and metals not interconnected by electrodes.

[0025] Symbol explanation:

[0026] 100 - Substrate chip; 101 - Second on-chip metal; 111 - Solder metal; 121 - Second alignment mark;

[0027] 200 - Flip chip; 201 - First on-chip metal; 211 - Aluminum layer; 212 - Titanium layer; 213 - Gold layer; 221 - First alignment mark;

[0028] 300 - Electrical connection metal area; 301 - Substrate chip metal electrode; 302 - Flip chip metal electrode; 303 - On-chip metal etching area; 311 - Electrode interconnect metal; 312 - Ground plane interconnect metal;

[0029] 400 - Support metal area; 401 - Support interconnect metal;

[0030] 500 - Limiting metal area; 501 - Second limiter; 502 - First limiter;

[0031] 600-Stage;

[0032] 700-microscope;

[0033] 800-Desktop;

[0034] 911 - Direction of translational motion applied; 912 - Direction of rotational momentum applied; 921 - Translational displacement; 922 - Rotational displacement. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0036] This invention provides a flip-chip bonding packaging method and a flip-chip bonding device. This flip-chip bonding packaging method combines the high packaging performance of direct bonding technology with the low process complexity of solder bump bonding technology, and has a semi-self-alignment function during implementation. It can be applied to various scenarios such as the development and manufacturing of classical semiconductor devices and quantum devices.

[0037] Figure 1 This is a flowchart of the device flip-chip packaging method in an embodiment of the present invention; Figure 2 This is a top view of the substrate chip in an embodiment of the present invention; Figure 3 This is a top view of the flip chip structure in an embodiment of the present invention; Figure 4This is a top view of the flip-chip bonding device in an embodiment of the present invention; Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the AA direction. Figure 4 and Figure 5 In the diagram, the interconnect metal and solder metal have been soldered together, so the overlap is indicated by "&".

[0038] Specifically, as a first aspect of the present invention, a device flip-chip packaging method is provided, such as... Figure 1 As shown, it includes steps S1-S3.

[0039] In step S1: A flip chip 200 and a substrate chip 100 are provided, wherein a first on-chip metal 201 is deposited on the surface of the flip chip 200, and an interconnect metal array and a first limiter 502 that are spatially isolated from each other are deposited on the side of the first on-chip metal 201 opposite to the flip chip 200; a second on-chip metal 101 is deposited on the surface of the substrate chip 100, and a solder metal array and a second limiter 501 that are spatially isolated from each other are deposited on the side of the second on-chip metal 101 opposite to the substrate chip 100.

[0040] In step S2: The flip chip 200 is flipped and aligned with the substrate chip 100, wherein the interconnect metal array and solder metal array are aligned by external correction, by flipping the flip chip 200 so that the first limiter 502 is nested within the second limiter 501. The external correction is to apply momentum to the substrate chip to adjust the position of the flip chip relative to the substrate chip.

[0041] In step S3: Under a reducing gas atmosphere, the aligned flip chip 200 and substrate chip 100 are heated to melt the solder metal 111, thereby achieving the welding of the interconnect metal array and the solder metal array, thus obtaining a flip-chip device.

[0042] In this embodiment of the invention, a first limiter 502 and a second limiter 501 are deposited on the on-chip metal of the flip chip 200 and the substrate chip 100, respectively. The first limiter 502 and the second limiter 501 restrict the movement of the flip chip 200, aligning the interconnect metal array on the flip chip 200 and the solder metal array on the substrate chip 100, followed by soldering to obtain a flip-chip bonded device. This invention provides a high-precision and easily implemented flip-chip bonding packaging method, reducing the difficulty of implementing higher-precision flip-chip bonding. It can achieve micron or even sub-micron error control in both horizontal and vertical directions, while eliminating the need for complex flip-chip bonding alignment equipment, thus reducing manufacturing costs.

[0043] According to an embodiment of the present invention, the first limiter 502 is a prism structure; the second limiter 501 is an inverted V-shaped columnar structure with its sides perpendicular to its bottom surface. When the first limiter 502 is nested within the second limiter 501, the second limiter 501 restricts the movement or rotation of the first limiter 502 to achieve precise alignment of the interconnect metal array on the flip chip 200 and the solder metal array on the substrate chip 100, with an alignment error between micrometers and even submicrometers. The design of the first limiter 502 nested within the second limiter 501 can reduce the displacement or rotation angle generated by each momentum by limiting the relative movement / rotation of the chip or increasing the relative movement / rotation resistance, thereby improving the final alignment accuracy.

[0044] In this embodiment of the invention, the patterns on the flip chip 200 and the substrate chip 100, as well as the first limiter 502 and the second limiter 501, have good alignment. When the patterns on the flip chip 200 and the substrate chip 100 are aligned, the first limiter 502 on the flip chip 200 and the second limiter 501 on the substrate chip 100 fit together perfectly. Preferably, the first limiter 502 and the second limiter 501 are overlaid and positioned based on the pattern on the chip using a high-precision laser direct writing process to fabricate the device structure. The overlay accuracy needs to be higher than the alignment accuracy to ensure that patterns or structures at different levels on the chip can be accurately superimposed during soldering.

[0045] Figure 6 This is a schematic cross-sectional view of the interconnect metal and solder metal when aligned in an embodiment of the present invention.

[0046] According to an embodiment of the present invention, the first limiter 502, the second limiter 501, and the interconnecting metal array have the same height. Figure 6 As shown, the first limiter 502, the second limiter 501, and the interconnect metal array are all three-layer cylindrical structures consisting of an aluminum layer 211, a titanium layer 212, and a gold layer 213. In this three-layer cylindrical structure, the aluminum layer 211 has a thickness of 1 μm, the titanium layer 212 has a thickness of 10 nm, and the gold layer 213 has a thickness of 70 nm; the diameter of the three-layer cylindrical structure is 4-40 μm. The average spacing of the interconnect metal array is 20-80 μm. The solder metal 111 is made of indium; the height of the solder metal 111 is 100-500 nm; preferably, the solder metal 111 is a cylindrical structure with a diameter slightly larger than that of the interconnect metal.

[0047] In this embodiment of the invention, the first limiter 502, the second limiter 501, and the interconnect metal array are all directly deposited on the side of the on-chip metal phase opposite to the flip chip 200 or the substrate chip 100. Since the first limiter 502, the second limiter 501, and the interconnect metal array have the same structure (e.g., height), they can be deposited simultaneously. The on-chip metal of the chip is patterned to form on-chip devices and implement other functions. In the interconnect metal array, an aluminum layer 211 is deposited on the surface of the metal 201 on the first wafer of the flip chip 200. It possesses excellent mechanical strength and conductivity, providing mechanical support and electrical connections between the chips. A titanium layer 212 is deposited on top of the aluminum layer 211 and completely covers it. It enables electrical connections between the chips, prevents oxidation of the aluminum layer 211, and bonds the aluminum layer 211 to the gold layer 213. A gold layer 213 is deposited on top of the titanium layer 212 and completely covers it. It also provides electrical connections between the chips. The gold layer 213 itself has anti-oxidation properties, helping to reduce electrical connection losses and allowing for good wetting of the molten solder metal 111 to form a reliable solder interface. The solder metal 111 is deposited on the surface of the metal 101 on the second wafer of the substrate chip 100. It has a low melting point and good conductivity, and melts during the soldering process to achieve a stable connection. Both the interconnect metal and the solder metal 111 have a columnar structure, and the size of the solder metal 111 is slightly larger than or equal to the size of the interconnect metal to ensure maximum soldering contact area. Without departing from generality, the solder metal 111 and the interconnect metal on the substrate chip 100 and the flip chip 200 can be interchanged.

[0048] According to an embodiment of the present invention, micro-nano fabrication precision is used to replace the alignment precision requirements of general flip-chip bonding equipment, requiring the preparation error of the exposed pattern and the alignment error of the pattern overlay to be controlled within half of the flip-chip bonding alignment error; preferably, the preparation error and alignment error are not greater than 0.25 μm.

[0049] Figure 7 This is a schematic diagram of the structure of the first alignment mark in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the second alignment mark in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the first alignment mark and the second alignment mark are aligned in an embodiment of the present invention.

[0050] According to embodiments of the present invention, such as Figures 7-9As shown, a first alignment mark 221 is etched on the first metal plate 201, and a second alignment mark 121 is etched on the second metal plate 101. The readout principle of the first alignment mark 221 and the second alignment mark 121 is based on a vernier caliper mechanism. The tooth pitch of the first alignment mark 221 is 3 μm, and the tooth pitch of the second alignment mark 121 is 2.8 μm. This alignment mark structure allows for preliminary assessment of alignment deviation using only an optical microscope without the need for additional measuring equipment. From a top-down view, each division of relative misalignment between the first alignment mark 221 and the second alignment mark 121 corresponds to an alignment deviation on the order of 0.2 μm.

[0051] According to an embodiment of the present invention, the interconnect metal array includes an electrode interconnect metal array, a ground plane interconnect metal array, and a support interconnect metal array. The electrode interconnect metal array and the corresponding solder metal array in the vertical direction are used to achieve electrical connection between the flip chip 200 and the substrate chip 100; the ground plane interconnect metal array and the corresponding solder metal array in the vertical direction are used to ensure that the electrode interconnect metal array has a good reference ground plane; the support interconnect metal array and the corresponding solder metal array in the vertical direction are used to provide sufficient and consistent support force during the soldering process and to ensure that the first on-chip metal 201 and the second on-chip metal 101 are at the same potential.

[0052] In this embodiment of the invention, the chip can be divided into different regions to meet different functional requirements, including: an electrical connection metal region 300, a support metal region 400, and a limiting metal region 500. The electrical connection metal region 300 includes a substrate chip metal electrode 301, a flip chip metal electrode 302, an on-chip metal etching region 303, an electrode interconnect metal array, and a ground plane interconnect metal array. These metal electrode regions, disposed on the surfaces of the flip chip 200 and the substrate chip 100, are used to achieve high-density electrical interconnection between the chips. The interconnect metals in this region have small dimensions and short pitch to meet the requirements of high connection density. After flip-chip bonding alignment, the interconnect metals and solder metals 111 should be aligned and overlapped in the horizontal direction. When the electrodes need to transmit microwave signals, the ground plane interconnect metal 312 disposed near the ground plane ensures that the electrode interconnect metal 311 has a good reference ground plane. The support metal region 400 includes a support interconnect metal array disposed on the ground plane region of the flip chip 200 surface. The support interconnect metals 401 are widely and uniformly distributed on the chip, providing mechanical connection and equipotential connection between the flip chip 200 and the substrate chip 100. The interconnect metals in this region have a large size and pitch to provide sufficient mechanical support and bonding strength. After flip chip alignment is completed, the interconnect metals and solder metals 111 should be aligned and overlapped in the horizontal direction. The limiting metal region 500 includes a first limiter 502 and a second limiter 501 disposed on the ground plane region or dielectric layer region of the flip chip 200 or the substrate chip 100 surface. It is used to achieve semi-self-alignment between chips and provide additional physical support. The interconnect metals in this region have a very large size and pitch to provide mechanical limiting and support in the horizontal direction. After flip chip alignment is completed, the first limiter 502 and the second limiter 501 do not overlap in the horizontal direction but are tightly fitted, thereby achieving the mechanical limiting function. The limit switch structure must not interfere with the supporting structure, and should have sufficient size and quantity to ensure that its limiting function is reliably realized.

[0053] As an embodiment of the present invention, the interconnecting metal diameter of the electrical connection metal region 300 is 4 μm and the pitch is 10 μm; the interconnecting metal diameter of the supporting metal region 400 is 10 μm and the pitch is 40 μm; the limiter structure of the limiting metal region 500 has a size on the order of hundreds of micrometers.

[0054] Figure 10 This is a schematic diagram of the structure of the chip and the external auxiliary welding system during the external correction process in an embodiment of the present invention.

[0055] According to an embodiment of the present invention, aligning the interconnect metal array and the solder metal array through external correction includes: applying momentum to the substrate chip 100, and using the frictional force between the first limiter 502 and the second limiter 501 and the inertia of the flip chip 200 to move or rotate relative to the substrate chip 100, thereby aligning the interconnect metal array and the solder metal array. Before soldering, the flip chip 200 and the substrate chip 100 are brought into contact through the first limiter 502 and the second limiter 501, and momentum is applied to the substrate chip 100. At this time, due to the frictional force between the first limiter 502 and the second limiter 501 and the inertia of the flip chip 200, the flip chip 200 moves horizontally relative to the substrate chip 100 by a specific distance or a specific angle, thereby aligning the interconnect metal array and the solder metal array.

[0056] According to an embodiment of the present invention, the heating temperature is higher than the melting point of the solder metal 111 but lower than the melting point of the interconnect metal. During the heating process, the solder metal 111 melts and expands, contacting the interconnect metal to complete the welding, while the first limiter 502, the second limiter 501, and the interconnect metal array remain unchanged during this process. The welding is performed in a reducing gas atmosphere, wherein the reducing gas is formic acid, maintaining a suitable heating temperature and heating time to ensure that the metal oxide layer on the surface of the solder metal 111 and the interconnect metal is fully reduced, thereby achieving a good mechanical and electrical connection.

[0057] According to some embodiments of the present invention, high-precision, low-cost semi-automatic alignment of the flip chip 200 and the substrate chip 100 can be achieved by the following method: The method includes fixing the substrate chip 100 on a stage 600 of suitable shape and mass, placing the stage 600 on a tabletop 800, and placing the flip chip 200 on the substrate chip 100 with low precision. The edges of the first limiter 502 and the second limiter 501 are observed through a microscope 700 to estimate the directional and angular deviation of the coarse placement. A momentum of a certain magnitude and direction is applied to the stage 600 in the opposite direction of the deviation. Movement in the specified direction is achieved by utilizing the friction between the first limiter 502 and the second limiter 501 and the inertia of the flip chip 200. By controlling the magnitude and direction of the momentum, displacement and angle adjustments of the flip chip 200 within a small range can be achieved. Due to the presence of the first limiter 502 and the second limiter 501, the displacement and rotation of the flip chip 200 are restricted when the first limiter 502 and the second limiter 501 are close together. By continuously repeating the process of applying momentum to adjust the position and angle of the flip chip 200, the alignment accuracy between the flip chip 200 and the substrate chip 100 can be continuously improved. The alignment marks are continuously monitored by the microscope 700. When the predetermined alignment accuracy is reached, the alignment of the flip chip 200 and the substrate chip 100 is completed.

[0058] In this embodiment of the invention, the substrate chip 100 is mounted on the stage 600 by an adhesive or a fixing clamp; the stage 600 is used to provide a point of application for applying momentum and to reduce the displacement caused by a unit momentum by its own mass; the tabletop 800 provides frictional resistance for braking the movement of the stage 600; and the microscope 700 is used to monitor the alignment status in real time.

[0059] According to some embodiments of the present invention, the microscope 700 can be an optical microscope. Furthermore, in order to observe the positions of the first limiter 502 and the second limiter 501 after inversion, a flip-chip with a transparent substrate, such as a sapphire substrate, is required. Further, according to some examples of the present invention, the stage can be a glass slide, and momentum can be applied manually.

[0060] According to some embodiments of the present invention, after flip-chip alignment is completed, the interconnect metal and solder metal 111 on the flip chip 200 and the substrate chip 100 coincide in the vertical direction; the first limiter 502 and the second limiter 501 are in contact with each other in the horizontal direction; the height of the interconnect metal is slightly less than the design spacing between the substrate chip 100 and the flip chip 200, and the final soldering spacing after flip-chip bonding is completed is determined by the interconnect metal and the solder metal 111.

[0061] According to some embodiments of the present invention, after the flip chip 200 and the substrate chip 100 are aligned, they are heated for welding. Specifically, this includes: placing the aligned flip chip 200 and substrate chip 100 together with the stage 600 in a reducing gas atmosphere to isolate them from air and prevent oxidation. Heating the stage 600 raises the temperature above the melting point of the solder metal 111 but below the melting point of the interconnect metal, while simultaneously enhancing the reducing power of the reducing gas to reduce the oxide layer on the surface of the solder metal 111. A predetermined pressure is applied to the chip assembly and maintained for a predetermined duration to ensure sufficient contact between the molten solder metal 111 and the interconnect metal, while preventing plastic deformation or damage to the interconnect metal. Heating is then stopped, the pressure is released, and the reducing gas atmosphere is removed sequentially to complete the pressure welding process. For example, the reducing gas is formic acid, the heating temperature is 220°C, and the maximum pressure between the chips is 20N, thus achieving the welding of the flip chip 200 and the substrate chip 100. The external pressure needs to be sufficient to break through the oxide layer of the solder metal 111 so that the molten solder metal 111 can come into contact with the interconnect metal, while avoiding excessive deformation of the interconnect metal.

[0062] In this embodiment of the invention, after the pressure bonding process is completed, the interconnect metal and its paired solder metal 111 form a tightly bonded structure, wherein the thickness of the interconnect metal determines the inter-chip spacing. Since the solder metal 111 does not completely collapse or become zero-thickness after bonding, the final inter-chip spacing will be slightly higher than the thickness of the interconnect metal.

[0063] This invention provides a flip-chip bonding packaging method that combines the high electrical connectivity of direct bonding with the low process complexity of solder bump bonding, while also possessing semi-self-alignment capabilities. This provides a new path for high-precision semiconductor flip-chip packaging, and is particularly suitable for the research and application of flip-chip bonding technology in quantum devices. Its core implementation steps include: first, fabricating interconnect metal and solder metal structures on a substrate chip and a flip chip, achieving electrical connectivity and mechanical support between them through the design of different interconnect metal structures; second, achieving on-chip sub-micron precision semi-self-alignment through constraint structure design and external momentum application; and finally, using thermoforming to enhance the connection stability and strength.

[0064] The flip-chip bonding packaging method provided by this invention has many significant advantages and beneficial effects: In terms of interconnect density, by replacing traditional solder bumps with interconnect metal structures, micro-bumps with micrometer-level dimensions and tens of micrometer pitches are achieved, significantly improving the interconnect density per unit area, with pin spacing reaching the ten-micrometer level; In terms of spacing and alignment accuracy control, it can not only effectively support and maintain micrometer-level chip spacing between chips, facilitating ultra-fine pitch interconnects to reduce inter-chip capacitance and parasitic capacitance, but also achieve sub-micrometer-level horizontal alignment accuracy and excellent vertical spacing control capability; In terms of process and reliability, the interconnect metal has high hardness, melting point, and good machinability, supporting thermoforming under relatively higher temperature and pressure conditions, effectively suppressing the problems of poor soldering and increased signal transmission loss caused by the reduction of solder metal size, improving the electrical reliability of the solder interface, and the required temperature and pressure are still lower than those of direct bonding processes, making it compatible with most device processes; At the same time, this method transfers the alignment accuracy requirements to the overlay process of the processing steps, replacing the stringent accuracy requirements of high-precision flip-chip bonding equipment with micro-nano processing accuracy, significantly reducing the difficulty of process implementation and the complexity of equipment alignment, making process implementation simpler.

[0065] As a second aspect of the present invention, a flip-chip bonding device is provided, which is prepared by the above-described flip-chip bonding packaging method.

[0066] The present invention will be further illustrated below through embodiments and related test experiments. In the following detailed description, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Moreover, the details in the following embodiments can be arbitrarily combined to form other feasible embodiments without conflict. All instruments, consumables, and reagents used in the following embodiments are commercially available unless otherwise specified.

[0067] Example 1

[0068] This embodiment 1 exemplarily illustrates the fabrication of a flip-chip device using the flip-chip packaging method provided by the present invention.

[0069] Figure 11 The flowchart of the device flip-chip bonding packaging method in Embodiment 1 of the present invention includes steps Q1-Q3.

[0070] Step Q1: Design and fabricate the device structure on the substrate chip 100 and the flip chip 200, specifically including the following sub-steps.

[0071] Step Q1-1: Establish a global positioning coordinate system on the substrate chip 100 and the flip chip 200, and prepare alignment marks for coordinate system establishment and to assist in subsequent flip alignment.

[0072] Step Q1-2: Fabricate non-flip-chip bonding structures (such as metal electrodes) on the substrate chip 100 and flip chip 200 to realize device functions.

[0073] Steps Q1-3 involve using photolithography to define the layout and shape of interconnect metals on the substrate chip 100 and flip chip 200, and then depositing multiple layers of interconnect metals in a single step in a high vacuum environment to avoid interlayer oxidation.

[0074] Steps Q1-4 involve using photolithography to define the layout and structure of the solder metal on the substrate chip 100 and the flip chip 200, and then completing the deposition of the solder metal.

[0075] In step Q1, compared to the non-flip-chip packaging process, only two additional coating steps are added, and the metal structure does not require a special morphology; the required columnar structure can be formed through a peeling process. Consistent with traditional flip-chip designs, the distribution and shape of the on-chip metal need to be defined through precise overlay and exposure, and this precision directly determines the final packaging performance.

[0076] Step Q2: Perform flip-chip alignment on the substrate chip 100 and the flip chip 200, which includes the following sub-steps.

[0077] Step Q2-1: Fix the substrate chip 100 onto the stage 600 with a suitable shape and mass, and perform coarse alignment and fastening with the flip chip 200. At this time, the first limiter 502 of the limiting metal area 500 is near the second limiter 501, and the alignment deviation is in the range of hundreds of micrometers to millimeters.

[0078] Step Q2-2: By observing the relative positions of the alignment marks on the substrate chip 100 and the flip chip 200, the direction of deviation is estimated. A certain magnitude and direction of momentum is applied to the stage 600 along the opposite deviation direction, so that the flip chip 200 is displaced or deflected at an angle relative to the substrate chip 100. Repeat this process to reduce the alignment deviation to the order of several micrometers to tens of micrometers.

[0079] Step Q2-3: Continue to apply momentum in the opposite direction of the deviation, and gradually reduce the momentum to reduce the single movement step. When nearing complete alignment, the first limiter 502 and the second limiter 501 can limit the relative movement and rotation of the flip chip 200, or increase its resistance, thereby suppressing excessive displacement or deflection and further improving alignment accuracy.

[0080] Step Q2-4: Repeat the above fine-tuning steps and continue to observe the alignment mark. When the mark reaches the expected overlap state, the alignment is completed. The final accuracy can reach the sub-micron level.

[0081] In step Q2, submicron-level alignment can be achieved simply by observing with an external optical microscope, without relying on high-precision dedicated equipment. Since the flip chip 200 is aligned on top of the substrate chip 100, there is no issue of parallelism alignment between the upper and lower chips in the traditional flip-chip bonding process. This alignment method is an optional step, and this flip-chip bonding packaging solution is also compatible with the equipment used in the traditional flip-chip process for alignment.

[0082] Step Q3: Perform thermoforming welding on the substrate chip 100 and the flip chip 200, which includes the following sub-steps.

[0083] Step Q3-1: Place the aligned chipset in a reducing gas environment to isolate it from air and prevent oxidation.

[0084] Step Q3-2: Heat the chipset and apply appropriate pressure to make its temperature higher than the melting point of the solder metal but much lower than the melting point of the interconnect metal, so as to avoid excessive deformation of the interconnect metal structure; at the same time, heating enhances the reducing power of the reducing gas to further remove the oxide layer on the surface of the solder metal.

[0085] Step Q3-3: Maintain the soldering temperature and pressure for a sufficiently long duration to ensure that the molten solder and interconnect metal are in full contact.

[0086] Steps Q3-4: Stop heating, remove pressure and reducing gas in sequence to complete welding.

[0087] In step Q3, the welding temperature exceeds the melting point of the solder metal, which helps to achieve a denser bond between the solder and the interconnect metal. At the same time, because there is an oxide layer on the surface of the solder metal, external pressure still needs to be applied to promote welding. Since the interconnect metal has high strength and melting point, the pressure used can exceed the welding pressure of conventional thermocompression welding processes. In addition, the reduction in the amount of solder metal can prevent solder overflow at high temperatures, thereby supporting the realization of smaller interconnect pitch.

[0088] The flip-chip bonding device in this embodiment 1 includes a flip chip 200 and a substrate chip 100. The flip chip 200 is approximately 400 μm thick, 4.7 mm long, and 3.7 mm wide, and is made of double-polished sapphire. The substrate chip 100 is approximately 400 μm thick, 8.2 mm long, and 7.2 mm wide, and is also made of double-polished sapphire. The on-chip metal on both the flip chip 200 and the substrate chip 100 is made of titanium nitride, which exhibits superconductivity at low temperatures (5-6 K) and can achieve good bonding with the aluminum layer and solder metal. The thickness of the on-chip metal is 10 nm. The first limiter 502 on the flip chip 200 is a regular triangular prism with a side length of 300 μm. The second limiter 501 on the substrate chip 100 is an inverted V-shaped columnar structure with a length of 300 μm and a width of 80 μm. The first limiter 502 on the flip chip 200, the interconnect metal, and the second limiter 501 on the substrate chip 100 all have a three-layer structure of aluminum layer 211-titanium layer 212-gold layer 213; wherein, the thickness of aluminum layer 211 is 1μm, the thickness of titanium layer 212 is 10nm, and the thickness of gold layer 213 is 70nm. The solder metal 111 on the substrate chip 100 is cylindrical in shape, with a diameter of 32μm and a height of approximately 300nm, and is made of indium.

[0089] After soldering, the first limiter 502 on the flip chip 200 and the second limiter 501 on the substrate chip 100 have no overlap and their edges are completely aligned. The interconnect metal on the flip chip 200 and the solder metal 111 on the substrate chip 100 are completely aligned.

[0090] The method for fabricating the first limiter 502, the second limiter 501, and the interconnect metal includes: uniformly coating a 5-10 μm thick photoresist on the flip chip 200 and the substrate chip 100; using laser direct writing to perform high-precision overlay exposure using existing patterns on the chip; precisely depositing a 1 μm thick layer of aluminum, a 10 nm thick layer of titanium, and a 70 nm thick layer of gold using electron beam evaporation deposition; and finally peeling off the photoresist on the flip chip 200 and the substrate chip 100.

[0091] The method for preparing solder metal 111 includes: uniformly coating a 1-2 μm thick photoresist on a substrate chip 100, performing high-precision overlay using laser direct writing to utilize existing patterns on the chip, depositing a 300 nm thick indium using thermal evaporation deposition, and finally stripping the photoresist on the substrate chip 100.

[0092] Figure 12 This is a schematic diagram of the momentum application and the relative displacement of the chip during the external correction process in Embodiment 1 of the present invention, including the translational momentum application direction 911 and the resulting translational displacement 921, and the rotational momentum application direction 912 and the resulting rotational displacement 922.

[0093] like Figure 12As shown, external correction is performed on the stage 600. The basic structure includes: a flip chip 200, which is rectangular in shape; a substrate chip 100, which is rectangular in shape; and a stage 600, which is rectangular in shape. Momentum is applied to the stage 600 to complete the external correction and achieve alignment. Specifically, momentum is applied along the 911 direction to control the movement of the flip chip 200 along the 921 direction; momentum is applied along the 921 direction to control the counterclockwise rotation of the flip chip 200 along the 922 direction. The substrate chip 100 is fixed on the stage 600. When the flip chip 200 moves, the direction of momentum application passes through the center of mass of the flip chip 200, while when the flip chip 200 rotates, the direction of momentum application does not pass through the center of mass of the flip chip 200.

[0094] Assume the mass of flip chip 200 is The frictional force between the substrate chip 100 and the substrate chip 100 is The combined mass of the substrate chip 100 and the stage 600 is The friction force with the desktop is 800. Each time, a force of size 600 can be applied to the stage. The momentum along direction 911 can be used to determine the displacement of both relative to the tabletop reference frame according to basic Newtonian mechanics. Specifically, the stage 600 and the substrate chip 100 undergo joint displacement. The specific calculation method is shown in equation (1).

[0095] (1).

[0096] The displacement of the flip chip 200 relative to the desktop reference frame is... The specific calculation method is shown in equation (2).

[0097] (2).

[0098] This refers to the displacement of the flip chip 200 relative to the substrate chip 100. Generally, the parameter range needs to be set to... ,at this time , This refers to the magnitude of the translational displacement 921. The rotational momentum can be set as a couple composed of a pair of momentum 912 whose centers of mass coincide with the center of mass of the stage 600 and the substrate chip 100. The control principle and parameter range are the same as those described above, and the rotational displacement 922 can be achieved in the end.

[0099] The stage 600 can use a glass slide, and a larger size can be achieved by attaching the substrate chip 100 to the glass slide. The relative positions of the first limiter 502 and the second limiter 501 are observed using a microscope, which can be an optical microscope. To facilitate observation of the positions of the first limiter 502 on the flip chip 200 and the second limiter 501 on the substrate chip 100, a flip chip 200 with a transparent substrate, such as a double-polished sapphire substrate in this embodiment, is required. By continuously correcting the position and angle of the flip chip 200, when the first limiter 502 and the second limiter 501 are close together, the relative displacement between the flip chip 200 and the substrate chip 100 will further decrease, reaching the sub-micron level, thereby achieving high-precision alignment.

[0100] Figure 13 This is a time flow diagram of welding process Q3 in Embodiment 1 of the present invention, which includes pressure, temperature and gas on / off status changing over time.

[0101] The aligned flip chip 200 and substrate chip 100, along with the stage 600, are placed in a reducing atmosphere. The stage 600 is heated, and a predetermined pressure is applied to the chip assembly and maintained for a predetermined duration. This melts and expands the solder metal 111, bringing it into contact with the interconnect metals, thus achieving bonding and obtaining a flip-chip device. The reducing gas is formic acid, the heating temperature is 220°C, the heating time is 30 minutes, and the maximum bonding pressure between the chips is 20 N.

[0102] Figure 14 This refers to the chip spacing of the flip-chip bonding device after pressure bonding in Embodiment 1 of the present invention.

[0103] like Figure 14 As shown, the actual measured height of the interconnect metal is 1.14 μm, and the inter-chip pitches measured at the four corners are 1.23 μm, 1.00 μm, 1.29 μm, and 1.42 μm, respectively. Compared to the designed inter-chip pitch parameter of 1.2 μm, the average pitch on the chip is 1.24 μm, the average deviation is 0.04 μm, and the maximum deviation is 0.22 μm. The difference in inter-chip pitch at different locations is related to the chip's stress distribution, the non-uniformity of the interconnect metal support force, and the warping of the chip after being subjected to force.

[0104] Figure 15 This is a graph showing the microwave signal measurement results of the flip-chip device in Embodiment 1 of the present invention, with and without the interconnect metal via electrodes. Figure 16 for Figure 15 A comparison of microwave signal quantities between metals interconnected by electrodes and metals not interconnected by electrodes.

[0105] from Figure 15 and Figure 16It can be seen that in the 0-8.5GHz frequency band, the microwave signal transmitted through the electrode interconnect metal 311 deviates from the microwave transmission signal transmitted without the electrode interconnect metal 311 by less than 3dB.

[0106] In summary, by designing suitable limiters and combining them with solder metal, the flip-chip packaging method proposed in this invention can achieve high-precision and easily implemented flip-chip bonding. The flip-chip packaging method can be further expanded to achieve 3D or 2.5D packaging by soldering more chips.

[0107] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for flip-chip bonding and packaging of a device, characterized in that, include: A flip chip and a substrate chip are provided, wherein a first on-chip metal is deposited on the surface of the flip chip, and an interconnect metal array and a first limiter are deposited on the side of the first on-chip metal opposite to the flip chip, which are spatially isolated from each other; and a second on-chip metal is deposited on the surface of the substrate chip, and a solder metal array and a second limiter are deposited on the side of the second on-chip metal opposite to the substrate chip, which are spatially isolated from each other. The flip chip is flipped and aligned with the substrate chip. By flipping the flip chip so that the first limiter is nested within the second limiter, the edges of the first and second limiters are observed using an optical microscope to estimate the directional and angular deviations. Momentum is applied to the substrate chip in the opposite direction of the deviation. By utilizing the friction between the first and second limiters and the inertia of the flip chip, the flip chip is moved or rotated relative to the substrate chip, thereby aligning the interconnect metal array and the solder metal array. In a reducing gas atmosphere, the aligned flip chip and substrate chip are heated to melt the solder metal, thereby achieving the welding of the interconnect metal array and the solder metal array, thus obtaining a flip-chip device. The first limiter is a prism structure; The second limiter is an inverted V-shaped columnar structure with its side surface perpendicular to its bottom surface.

2. The device flip-chip packaging method according to claim 1, characterized in that, The first limiter, the second limiter, and the interconnected metal array have the same height.

3. The device flip-chip packaging method according to claim 2, characterized in that, The first limiter, the second limiter, and the interconnecting metal array are all three-layer cylindrical structures consisting of an aluminum layer, a titanium layer, and a gold layer. The aluminum layer in the three-layer cylindrical structure has a thickness of 1 μm, the titanium layer has a thickness of 10 nm, and the gold layer has a thickness of 70 nm.

4. The device flip-chip packaging method according to claim 3, characterized in that, The solder metal is made of indium. The height of the solder metal is 100-500 nm.

5. The device flip-chip packaging method according to claim 1, characterized in that, A first alignment mark is etched on the metal of the first wafer, and a second alignment mark is etched on the metal of the second wafer; The reading principle of the first alignment mark and the second alignment mark is based on the vernier caliper mechanism. The tooth pitch of the first alignment mark is 3μm and the tooth pitch of the second alignment mark is 2.8μm.

6. The device flip-chip packaging method according to claim 1, characterized in that, The interconnect metal array includes an electrode interconnect metal array, a ground plane interconnect metal array, and a support interconnect metal array; The electrode interconnect metal array and the corresponding solder metal array in the vertical direction are used to realize the electrical connection between the flip chip and the substrate chip. The ground plane interconnect metal array and the corresponding solder metal array in the vertical direction are used to ensure that the electrode interconnect metal array has a good reference ground plane; The supporting interconnect metal array and the corresponding solder metal array in the vertical direction are used to provide support force during the welding process and to ensure that the first on-chip metal and the second on-chip metal are at the same potential.

7. The device flip-chip packaging method according to claim 1, characterized in that, The heating temperature is higher than the melting point of the solder metal and lower than the melting point of the interconnect metal; The reducing gas is formic acid.

8. A flip-chip bonding device, prepared by the flip-chip bonding packaging method according to any one of claims 1-7.

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