Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure. The method comprises the following steps: providing a substrate, and sequentially forming an epitaxial layer and an active layer on the top surface of the substrate; forming a first well region and a second well region arranged along the parallel substrate direction in the active layer; forming a first source electrode and a second source electrode, the first source electrode being located in the first well region, and the second source electrode being located in the second well region; forming a target doped region in the active layer, the target doped region also being located between the first well region and the second well region; and forming a gate structure on the top surface of the target doped region, the width of the gate structure being greater than the interval between the opposite side walls of the first well region and the second well region and smaller than the interval between the opposite side walls of the first source electrode and the second source electrode. The semiconductor structure preparation method has a simple process flow, can improve the short-circuit resistance time of the semiconductor device without increasing the process cost and greatly affecting the conduction performance of the device, and thus improves the robustness of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] As semiconductor device manufacturing processes continue to iterate, the cell size of semiconductor devices becomes smaller and smaller, and the current density of semiconductor devices increases rapidly.

[0003] In application scenarios, semiconductor devices face various extreme overcurrent and overvoltage conditions due to parasitic inductance and capacitance in the circuit, which can easily lead to thermal failure and compromise the reliability of end products. Therefore, improving the robustness of devices is extremely important. Summary of the Invention

[0004] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0005] According to some embodiments, this application provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A substrate is provided, and an epitaxial layer and an active layer are sequentially formed on the top surface of the substrate;

[0007] A first well region and a second well region are formed in the active layer, arranged parallel to the substrate direction;

[0008] A first source and a second source are formed, with the first source located in the first well region and the second source located in the second well region;

[0009] A target doped region is formed within the active layer, and the target doped region is also located between the first well region and the second well region;

[0010] A gate structure is formed on the top surface of the target doped region. The width of the gate structure is greater than the distance between the opposite sidewalls of the first well region and the second well region, and less than the distance between the opposite sidewalls of the first source and the second source.

[0011] In the semiconductor structure fabrication method of the above embodiments, by forming a target doped region located between the first well region and the second well region within the active layer, the current path size can be controlled through the depletion effect between the target doped region and the active layer, effectively reducing the cross-sectional area of ​​the current path. This prevents the semiconductor device from burning out due to thermal failure caused by excessive current under extreme operating conditions, thus improving the short-circuit withstand performance of the semiconductor device. Furthermore, forming a gate structure on the top surface of the target doped region allows the target doped region to withstand most of the electric field under reverse high voltage, thereby reducing the field strength experienced by the gate structure and increasing protection of the gate structure under reverse high voltage, which helps to increase the robustness of the semiconductor device's reliability. The above method has a simple process flow, and without increasing process costs or significantly affecting the device's conduction performance, it can improve the short-circuit withstand time of the semiconductor device, thereby improving its robustness.

[0012] In some embodiments, before forming the first source and the second source, the method further includes: forming a first doped region and a second doped region, wherein the first doped region is located within a first well region and outside the first source, and the second doped region is located within a second well region and outside the second source.

[0013] In some embodiments, forming a first well region and a second well region arranged in a direction parallel to the substrate within an epitaxial layer includes: forming a first mask layer on the top surface of an active layer; and forming the first well region and the second well region arranged in a direction parallel to the substrate within an epitaxial layer based on the first mask layer.

[0014] Forming a first source and a second source includes: removing a first mask layer; forming a second mask layer on the top surface of the active layer; forming a first source and a second source based on the second mask layer; and removing the second mask layer.

[0015] In some embodiments, forming a first doped region and a second doped region includes: forming a first sidewall structure on the sidewall of a first mask layer along a direction parallel to the substrate; forming a first initial doped region and a second initial doped region based on the first mask layer and the first sidewall structure; and removing the first sidewall structure.

[0016] Based on the second mask layer, forming a first source and a second source includes: forming a first initial source and a second initial source based on the second mask layer, wherein the first initial source at least partially replaces the first initial doped region, and the remaining first initial doped region constitutes the first doped region; and the second initial source at least partially replaces the second initial doped region, and the remaining second initial doped region constitutes the second doped region; and forming the first source and the second source based on the first initial source and the second initial source.

[0017] In some embodiments, forming a target doped region within an active layer includes: forming a third mask layer having an opening pattern, the width of which is equal to the distance between the opposite sidewalls of the first well region and the second well region; forming a second sidewall structure on the sidewall of the opening pattern; and forming the target doped region based on the third mask pattern and the second sidewall structure.

[0018] In some embodiments, the method further includes: forming a first source contact layer and a second source contact layer located on both sides of the target doped region, wherein the first source contact layer is located in a first well region and the second source contact layer is located in a second well region.

[0019] In some embodiments, the target doped region is formed with the first source contact layer and the second source contact layer using a one-time implantation process;

[0020] Forming a target doped region within the active layer, and forming a first source contact layer and a second source contact layer on both sides of the target doped region, includes: forming a first source contact layer, a target doped region, and a second source contact layer arranged sequentially along the direction parallel to the substrate, based on a third mask pattern and a second sidewall structure.

[0021] In some embodiments, after forming a gate structure on the top surface of the target doped region, the method further includes:

[0022] An interlayer dielectric layer is formed, which at least covers the exposed surface of the gate structure;

[0023] A first source contact electrode and a second source contact electrode are formed, wherein the first source contact electrode is located at least on the top surface of the first source contact layer, and the second source contact electrode is located at least on the top surface of the second source contact layer;

[0024] A barrier layer and a metal layer are formed. The barrier layer covers the outer surface of the interlayer dielectric layer, the top surface of the first source contact electrode, and the top surface of the second source contact electrode. The metal layer covers the outer surface of the barrier layer.

[0025] A drain contact layer and a drain electrode are sequentially formed on the bottom surface of the substrate.

[0026] In some embodiments, the doping element of the target doped region includes aluminum.

[0027] In some embodiments, the thickness of the target doped region ranges from 0.4 μm to 1 μm;

[0028] In some embodiments, the target doped region is formed using an ion implantation process with a dose range of 1E14 to 1E15.

[0029] According to some embodiments, this application also provides a semiconductor structure, the semiconductor structure including a substrate, an epitaxial layer, an active layer, a first well region and a second well region, a first source and a second source, a target doped region and a gate structure; the epitaxial layer and the active layer are located on the top surface of the substrate, the first well region and the second well region are located within the active layer and are arranged along a direction parallel to the substrate, the first source is located within the first well region and the second source is located within the second well region; the target doped region is located within the active layer and is also located between the first well region and the second well region; the gate structure is located on the top surface of the target doped region, and the width of the gate structure is greater than the distance between the opposite sidewalls of the first well region and the second well region and less than the distance between the opposite sidewalls of the first source and the second source.

[0030] In the semiconductor structure of the above embodiment, the target doped region is located within the active layer and between the first and second well regions. The depletion effect between the target doped region and the active layer can control the current path size, effectively reducing the cross-sectional area of ​​the current path. This prevents the semiconductor device from burning out due to excessive current under extreme operating conditions, thus improving its short-circuit withstand capability. Furthermore, the gate structure is located on the top surface of the target doped region. Since the target doped region can withstand most of the electric field under reverse high voltage, the field strength experienced by the gate structure is reduced, increasing protection for the gate structure under reverse high voltage and enhancing the robustness of the semiconductor device's reliability. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0032] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S10 of a semiconductor structure fabrication method according to an embodiment of this application;

[0033] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S30 of a semiconductor structure fabrication method according to an embodiment of this application;

[0034] Figure 4 This is a schematic cross-sectional view of the structure obtained in steps S41 and S42 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0035] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S531 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0036] Figure 6 This is a schematic cross-sectional view of the structure obtained in steps S532 and S70 of a semiconductor structure fabrication method provided in an embodiment of this application;

[0037] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S90 of a semiconductor structure fabrication method according to an embodiment of this application;

[0038] Figure 8 for Figure 7 A top view of the structure shown;

[0039] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S91 of a semiconductor structure fabrication method according to an embodiment of this application;

[0040] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S92 of a semiconductor structure fabrication method according to an embodiment of this application;

[0041] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S93 of a semiconductor structure fabrication method according to an embodiment of this application;

[0042] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S94 of a semiconductor structure fabrication method provided in an embodiment of this application.

[0043] Explanation of reference numerals in the attached figures: 10, Substrate; 11, Epitaxial layer; 12, Active layer; 21, First well region; 22, Second well region; 23, First mask layer; 24, First sidewall structure; 31, First doped region; 311, First initial doped region; 32, Second doped region; 321, Second initial doped region; 41, First source; 411, First initial source; 42, Second source; 421, Second initial source; 43, Second mask layer; 51, Target doped region; 52, Third mask layer; 53, Second sidewall structure; 54, First source contact layer; 55, Second source contact layer; 60, Gate structure; 601, Gate oxide layer; 602, Gate layer; 61, Interlayer dielectric layer; 62, First source contact electrode; 63, Second source contact electrode; 64, Barrier layer; 65, Metal layer; 66, Drain contact layer; 67, Drain electrode. Detailed Implementation

[0044] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0047] Furthermore, to clearly illustrate the multiple layers and regions in the accompanying drawings, the thickness of each layer and each region has been enlarged to clearly demonstrate the relative positions of the layers and the distribution of the regions. When a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, this description includes not only the case where it is "directly" above the other portion, but also the case where other layers are present in between. Moreover, it is understood that when a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, it generally refers to the side directly above the other portion.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0051] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0052] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, which includes the following steps.

[0053] Step S10: Provide a substrate, and sequentially form an epitaxial layer and an active layer on the top surface of the substrate;

[0054] Step S30: Form a first well region and a second well region arranged in parallel with the substrate direction within the active layer;

[0055] Step S50: Form a first source and a second source, wherein the first source is located in the first well region and the second source is located in the second well region;

[0056] Step S70: Form a target doped region located within the active layer, wherein the target doped region is also located between the first well region and the second well region;

[0057] Step S90: A gate structure is formed on the top surface of the target doped region. The width of the gate structure is greater than the distance between the opposite sidewalls of the first well region and the second well region, and less than the distance between the opposite sidewalls of the first source and the second source.

[0058] In the semiconductor structure fabrication method of the above embodiments, by forming a target doped region located between the first well region and the second well region within the active layer, the current path size can be controlled through the depletion effect between the target doped region and the active layer, effectively reducing the cross-sectional area of ​​the current path. This prevents the semiconductor device from burning out due to thermal failure caused by excessive current under extreme operating conditions, thus improving the short-circuit withstand performance of the semiconductor device. Furthermore, forming a gate structure on the top surface of the target doped region allows the target doped region to withstand most of the electric field under reverse high voltage, thereby reducing the field strength experienced by the gate structure and increasing protection of the gate structure under reverse high voltage, which helps to increase the robustness of the semiconductor device's reliability. The above method has a simple process flow and can improve the short-circuit withstand time (SCWT) of the semiconductor device without increasing process costs or significantly affecting the device's conduction performance, thereby improving the robustness of the semiconductor device.

[0059] In the embodiments disclosed above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0060] To more clearly illustrate the semiconductor structure fabrication method provided in the above embodiments, the following is combined with... Figures 2 to 12 The method is described in detail.

[0061] like Figure 2As shown, as an example, in step S10, the substrate 10 in this embodiment of the present disclosure can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon-germanium (SiGe) substrate 10, a silicon-germanium-carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistors formed on the substrate 10; therefore, the type of substrate 10 should not limit the scope of protection of this disclosure.

[0062] like Figure 2 As shown, in step S10, an epitaxial layer 11 and an active layer 12 are sequentially formed on the top surface of the substrate 10; in an embodiment where the substrate 10 is a silicon carbide (SiC) substrate 10, the active layer 12 can be formed by an ion implantation process.

[0063] In some embodiments, the doping elements of the active layer 12 include nitrogen or phosphorus, etc.

[0064] In some embodiments, the thickness of the active layer 12 ranges from 0.5 μm to 1.5 μm. For example, the thickness of the active layer 12 is 0.5 μm, 1 μm, or 1.5 μm, etc. It should be noted that the thickness here refers to the thickness of the active layer 12 along the direction perpendicular to the substrate 10, i.e. Figure 2 The thickness in the z-direction shown is the same as the thickness of the film layer mentioned below, and will not be repeated here.

[0065] In some embodiments, the dose range of the ion implantation process for the active layer 12 is 4E11 to 4E12. For example, the dose of the ion implantation process for the active layer 12 is 4E11 or 4E12, etc.

[0066] like Figure 3 As shown, in some embodiments, step S30, forming a first well region 21 and a second well region 22 arranged in the epitaxial layer 11 along the direction parallel to the substrate 10, includes:

[0067] Step S31: Form a first mask layer 23 on the top surface of the active layer 12;

[0068] Step S32: Based on the first mask layer 23, a first well region 21 and a second well region 22 are formed in the epitaxial layer 11 along the direction parallel to the substrate 10.

[0069] In some embodiments, in step S31, forming a first well region 21 and a second well region 22 arranged in the direction parallel to the substrate 10 in the active layer 12 may also include forming a mask material layer (not shown) and coating a photoresist material layer (not shown) on the top surface of the active layer 12. The photoresist material layer undergoes a series of steps such as exposure and development to form a patterned photoresist layer (not shown). Based on the patterned photoresist layer, a portion of the mask material layer is removed using a dry etching process to obtain a patterned first mask layer 23.

[0070] In some embodiments, in step S32, an ion implantation process can be performed based on the first mask layer 23 to obtain the first well region 21 and the second well region 22.

[0071] For example, the first well region 21 and / or the second well region 22 are P-type doped, that is, the first well region 21 and / or the second well region 22 are P-type well regions.

[0072] In some embodiments, the doping elements of the first well region 21 and / or the second well region 22 include aluminum and the like.

[0073] In some embodiments, the thickness of the first well region 21 and / or the second well region 22 ranges from 0.5 μm to 1 μm. For example, the thickness of the active layer 12 is 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm, etc.

[0074] In some embodiments, the dose range of the ion implantation process for the first well region 21 and / or the second well region 22 is 1E12 to 1E14. For example, the dose of the ion implantation process for the active layer 12 is 1E12, 1E13, or 1E14, etc.

[0075] Please combine Figure 4 and Figure 5 It is understood that, in some embodiments, before step S50, forming the first source 41 and the second source 42, the method further includes:

[0076] Step S40: Form a first doped region 31 and a second doped region 32. The first doped region 31 is located inside the first well region 21 and outside the first source 41. The second doped region 32 is located inside the second well region 22 and outside the second source 42.

[0077] In the semiconductor structure fabrication method of the above embodiment, by forming the first doped region 31 and the second doped region 32, the short-channel effect of the semiconductor under high voltage can be improved without sacrificing the performance of the semiconductor device, and the current path resistance can be optimized to further improve the short-circuit withstand time of the semiconductor device.

[0078] For example, the first doped region 31 and / or the second doped region 32 are N-type doped. For instance, the first doped region 31 and / or the second doped region 32 can be a film layer implanted with a shallow concentration of N-type ions.

[0079] In some embodiments, the doping elements of the first doped region 31 and / or the second doped region 32 include nitrogen and the like.

[0080] In some embodiments, the thickness of the first doped region 31 and / or the second doped region 32 ranges from 0.1 μm to 0.2 μm. For example, the thickness of the active layer 12 is 0.1 μm, 0.15 μm, or 0.2 μm, etc.

[0081] For example, an ion implantation process can be used to form the first doped region 31 and the second doped region 32.

[0082] In some embodiments, the dose range of the ion implantation process for the first doped region 31 and / or the second doped region 32 is 3E13 to 7E14. For example, the dose of the ion implantation process for the active layer 12 is 3E13 or 7E14, etc.

[0083] In some embodiments, step S40, forming the first doped region 31 and the second doped region 32, includes:

[0084] Step S41, as follows Figure 4 As shown, a first sidewall structure 24 is formed on the sidewall of the first mask layer 23 along the direction parallel to the substrate 10;

[0085] Step S42, as Figure 4 As shown, a first initial doped region 311 and a second initial doped region 321 are formed based on the first mask layer 23 and the first sidewall structure 24.

[0086] Step S42: Remove the first side wall structure 24.

[0087] For example, in step S41, a sputtering process can be used to form a first sidewall structure 24 on the sidewall of the first mask layer 23 along the direction parallel to the substrate 10.

[0088] Please combine Figures 5 to 6 Understandably, in step S50, a first source 41 and a second source 42 are formed, with the first source 41 located in the first well region 21 and the second source 42 located in the second well region 22.

[0089] In some embodiments, step S50, forming the first source 41 and the second source 42, includes:

[0090] Step S51: Remove the first mask layer 23;

[0091] Step S52: Form a second mask layer 43 on the top surface of the active layer 12;

[0092] Step S53: Based on the second mask layer 43, form the first source 41 and the second source 42;

[0093] Step S54: Remove the second mask layer 43.

[0094] Please combine Figures 4 to 6 Understandably, in some embodiments, step S53, forming the first source 41 and the second source 42 based on the second mask layer 43, includes:

[0095] Step S531, as follows Figure 4 and 5 As shown, based on the second mask layer 43, a first initial source 411 and a second initial source 421 are formed. The first initial source 411 at least partially replaces the first initial doped region 311, and the remaining first initial doped region 311 constitutes the first doped region 31. The second initial source 421 at least partially replaces the second initial doped region 321, and the remaining second initial doped region 321 constitutes the second doped region 32.

[0096] Step S532, as follows Figure 6 As shown, a first source 41 and a second source 42 are formed based on a first initial source 411 and a second initial source 421.

[0097] Please see Figure 6 In step S70, a target doped region 51 is formed within the active layer 12, and the target doped region 51 is also located between the first well region 21 and the second well region 22.

[0098] For example, the target doped region 51 is P-type. For instance, the target doped region 51 can be a film layer with a high concentration of P-type ions implanted.

[0099] In some embodiments, the doping element of the target doped region 51 includes aluminum.

[0100] In some embodiments, the thickness of the target doped region 51 ranges from 0.4 μm to 1 μm;

[0101] In some embodiments, the target doped region 51 is formed using an ion implantation process with a dose range of 1E14 to 1E15.

[0102] like Figure 6 As shown, in some embodiments, step S70, forming the target doped region 51 located within the active layer 12, includes:

[0103] Step S71: Form a third mask layer 52. The third mask layer 52 has an opening pattern. The width of the opening pattern is equal to the distance between the opposite sidewalls of the first well region 21 and the second well region 22.

[0104] Step S72: Form a second sidewall structure 53 on the sidewall of the opening pattern; form the target doped region 51 based on the third mask pattern and the second sidewall structure 53.

[0105] like Figure 6 As shown, in some embodiments, the method further includes:

[0106] Step S73: Form a first source contact layer 54 and a second source contact layer 55 located on both sides of the target doped region 51. The first source contact layer 54 is located in the first well region 21, and the second source contact layer 55 is located in the second well region 22.

[0107] Step S74: Remove the third mask layer 52 and the second sidewall structure 53.

[0108] In some embodiments, the target doped region 51, the first source contact layer 54, and the second source contact layer 55 are formed by a one-time implantation process.

[0109] It is understandable that semiconductor devices with small cell sizes have high current densities. In practical applications, due to parasitic inductance and capacitance in the circuit, semiconductor devices face various extreme overcurrent and overvoltage conditions, which can easily lead to thermal failure and negatively impact the reliability of end products. In the semiconductor structure fabrication method of the above embodiment, by forming a first doped region 31 and a second doped region 32 with N-type low-concentration ion implantation, a low-doped region is introduced into the current path to increase the path resistance. Based on this, a target doped region 51 with P-type high-concentration ion implantation is formed within the active layer 12. The target doped region 51 with P-type high-concentration ion implantation and the first doped region 31 and the second doped region 32 with N-type low-concentration ion implantation can form a PN junction depletion region, thereby reducing the cross-sectional area of ​​the current path. Under high current conditions, this effectively reduces the pressure of current overshoot and improves the short-circuit withstand capability of the device.

[0110] In some embodiments, step S70, forming a target doped region 51 within the active layer 12, and step S73, forming a first source contact layer 54 and a second source contact layer 55 on both sides of the target doped region 51, include:

[0111] Step a: Based on the third mask pattern and the second sidewall structure 53, a first source contact layer 54, a target doped region 51 and a second source contact layer 55 are formed sequentially along the direction parallel to the substrate 10.

[0112] like Figure 7 As shown, in step S90, a gate structure 60 is formed on the top surface of the target doped region 51. The width of the gate structure 60 is greater than the distance between the opposite sidewalls of the first well region 21 and the second well region 22, and less than the distance between the opposite sidewalls of the first source 41 and the second source 42.

[0113] In some embodiments, the gate structure 60 includes a gate oxide layer 601 and a gate layer 602 sequentially stacked along the direction perpendicular to the substrate 10.

[0114] For example, the gate layer 602 may be made of polysilicon. For instance, the gate layer 602 may be a polysilicon layer containing P-type ion implantation.

[0115] In some embodiments, the thickness of the gate oxide layer 601 ranges from 300 Å to 500 Å; for example, the thickness of the gate oxide layer 601 ranges from 300 Å, 400 Å, or 500 Å, etc.

[0116] In some embodiments, the thickness of the gate layer 602 ranges from 3000 Å to 5000 Å; for example, the thickness of the gate layer 602 ranges from 3000 Å, 4000 Å, or 5000 Å, etc.

[0117] For example, in step S90, a diffusion process can be used to form a gate oxide material layer (not shown) and a gate material layer (not shown) on the top surface of the target doped region 51. Then, a photolithography process is used to expose and develop the gate oxide material layer and the gate material layer, and a dry etching process is performed on the gate oxide material layer and the gate material layer to obtain the gate oxide layer 601 and the gate layer 602.

[0118] For example, in step S90, before forming the gate structure 60, a step may also be included whereby Chen uses a field oxide process to define the active region.

[0119] It is understandable that during the iteration process of semiconductor devices, the thickness of the gate oxide layer 601 is further reduced to improve conduction characteristics. However, as the thickness of the gate oxide layer 601 decreases, the reliability failure rate increases. The electric field strength is highest in the middle region of the active layer 12, making it a weak point for gate oxide layer 601 failure. In the semiconductor structure fabrication method of the above embodiment, a target doped region 51 is formed within the active layer 12. The target doped region 51 can withstand most of the electric field, reducing the field strength experienced by the gate oxide layer 601. This helps to increase the protection of the gate oxide structure under reverse high voltage and reduces the possibility of semiconductor device failure at the gate oxide layer 601.

[0120] like Figure 8 As shown, in some embodiments, the gate layer 602 extends along a first direction, which is parallel to the substrate 10, i.e., the Y direction as shown in Figure 8.

[0121] like Figure 8 As shown, in some embodiments, the target doped region 51 extends along a first direction.

[0122] like Figure 8As shown, in some embodiments, the orthographic projection of the first source contact layer 54 and the second source contact layer 55 is rectangular.

[0123] Please combine Figures 9 to 12 It is understood that in some embodiments, after step S90, forming the gate structure 60 on the top surface of the target doped region 51, the method further includes steps S91 to S94.

[0124] Step S91, as follows Figure 9 As shown, an interlayer dielectric layer 61 is formed, which at least covers the exposed surface of the gate structure 60.

[0125] In some embodiments, an interlayer dielectric layer 61 may be formed using a deposition process. For example, the interlayer dielectric layer 61 may be a single-layer structure or a multilayer structure. In an embodiment where the interlayer dielectric layer 61 is a multilayer structure, in step S91, a chemical vapor deposition process may be used to form a 3kA thick tetraethoxysilicon (TEOS) and a 7kA thick borosilicate glass (BPSG) as the interlayer dielectric layer 61.

[0126] Step S92, as follows Figure 10 As shown, a first source contact electrode 62 and a second source contact electrode 63 are formed. The first source contact electrode 62 is located at least on the top surface of the first source contact layer 54, and the second source contact electrode 63 is located at least on the top surface of the second source contact layer 55.

[0127] In some embodiments, step S92 may include obtaining a source via (not shown) by dry etching. A first source contact electrode 62 and a second source contact electrode 63 are located within the source via. For example, step S92 may also include steps such as performing two consecutive annealing processes via sputtering to form a low-resistivity silicide to reduce the contact resistance between the source electrode and the implanted material; and obtaining a gate via (not shown) by dry etching after exposure and development via photolithography.

[0128] Step S93, as follows Figure 11 As shown, a barrier layer 64 and a metal layer 65 are formed. The barrier layer 64 covers the outer surface of the interlayer dielectric layer 61, the top surface of the first source contact electrode 62 and the top surface of the second source contact electrode 63, and the metal layer 65 covers the outer surface of the barrier layer 64.

[0129] For example, in step S93, a physical deposition process can be used to form a barrier layer 64 and a metal layer 65. The barrier layer 64 can increase the adhesion of the metal layer 65 and prevent the diffusion of metal elements in the metal layer 65.

[0130] In some embodiments, the barrier layer 64 may be a titanium layer, a titanium nitride layer, or a combination thereof.

[0131] In some embodiments, the metal layer 65 is an aluminum layer.

[0132] Step S94, as follows Figure 12 As shown, a drain contact layer 66 and a drain electrode 67 are sequentially formed on the bottom surface of the substrate 10.

[0133] For example, in step S94, before the drain contact layer 66 and drain electrode 67 are sequentially formed on the bottom surface of the substrate 10, a step of thinning the back side of the substrate 10 is also included. For example, the drain contact layer 66 can be formed by sputtering and laser annealing processes, and the drain electrode 67 can be formed by metal evaporation.

[0134] In some embodiments, the drain electrode 67 is made of a metallic material. For example, the metallic material may be one or more of titanium, nickel, and silver.

[0135] It is understood that the parasitic capacitance of a semiconductor device itself has a significant impact on its switching characteristics. The overlap area between the gate layer 602 and the drain terminal is a key process parameter for the transfer capacitance Cgd. In the semiconductor structure fabrication method of the above embodiment, in terms of dynamic characteristics, the target doped region 51 and the PN junction depletion region of the first doped region 31 / second doped region 32 reduce the effective width of the active layer 12, i.e., reduce the overlap area between the gate layer 602 and the drain terminal, thereby reducing the device's transfer capacitance and improving the device's switching speed to reduce switching losses.

[0136] Please see Figure 12 According to some embodiments, this application also provides a semiconductor structure, which includes a substrate 10, an epitaxial layer 11, an active layer 12, a first well region 21 and a second well region 22, a first source 41 and a second source 42, a target doped region 51, and a gate structure 60; the epitaxial layer 11 and the active layer 12 are located on the top surface of the substrate 10, the first well region 21 and the second well region 22 are located within the active layer 12, and the first well region 21 and the second well region 22 are arranged along a direction parallel to the substrate 10, the first source 41 is located within the first well region 21, and the second source 42 is located within the second well region 22; the target doped region 51 is located within the active layer 12, and the target doped region 51 is also located between the first well region 21 and the second well region 22; the gate structure 60 is located on the top surface of the target doped region 51, and the width of the gate structure 60 is greater than the distance between the opposite sidewalls of the first well region 21 and the second well region 22, and less than the distance between the opposite sidewalls of the first source 41 and the second source 42.

[0137] In the semiconductor structure of the above embodiment, the target doped region 51 is located within the active layer 12 and between the first well region 21 and the second well region 22. The depletion effect between the target doped region 51 and the active layer 12 can control the current path size, effectively reducing the cross-sectional area of ​​the current path. This prevents the semiconductor device from burning out due to excessive current under extreme operating conditions, thus improving the short-circuit withstand capability. Furthermore, the gate structure 60 is located on the top surface of the target doped region 51. Since the target doped region 51 can withstand most of the electric field under reverse high voltage, the field strength experienced by the gate structure 60 is reduced, increasing protection for the gate structure 60 under reverse high voltage and enhancing the robustness of the semiconductor device's reliability.

[0138] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and an epitaxial layer and an active layer are sequentially formed on the top surface of the substrate; A first well region and a second well region are formed within the active layer, arranged parallel to the substrate direction; The first doped region and the second doped region are formed; A first source and a second source are formed; the first source is located within the first well region, and the second source is located within the second well region; A target doped region is formed within the active layer, and the target doped region is also located between the first well region and the second well region; A first source contact layer and a second source contact layer are formed on both sides of the target doped region, wherein the first source contact layer is located in the first well region and the second source contact layer is located in the second well region; A gate structure is formed on the top surface of the target doped region. The width of the gate structure is greater than the distance between the opposite sidewalls of the first well region and the second well region, and less than the distance between the opposite sidewalls of the first source and the second source. The first doped region is located within the first well region and on the side of the first source electrode closer to the target doped region; the second doped region is located within the second well region and on the side of the second source electrode closer to the target doped region; the target doped region is formed in conjunction with the first source electrode contact layer and the second source electrode contact layer using a one-time implantation process. The formation of the target doped region located within the active layer includes: A third mask layer is formed, the third mask layer having an opening pattern, the width of the opening pattern being equal to the distance between the opposite sidewalls of the first well region and the second well region; A second sidewall structure is formed on the sidewall of the opening pattern; The target doped region is formed based on the third mask layer and the second sidewall structure; The formation of the target doped region located within the active layer, and the formation of the first source contact layer and the second source contact layer located on both sides of the target doped region, include: Based on the third mask layer and the second sidewall structure, the first source contact layer, the target doped region and the second source contact layer are formed in sequence along the direction parallel to the substrate. The target doped region is a high-concentration P-type ion implanted film; the first doped region and / or the second doped region is a low-concentration N-type ion implanted film.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first well region and a second well region within the epitaxial layer, arranged parallel to the substrate direction, includes: A first mask layer is formed on the top surface of the active layer; Based on the first mask layer, a first well region and a second well region are formed in the epitaxial layer along a direction parallel to the substrate; The formation of the first source and the second source includes: Remove the first mask layer; A second mask layer is formed on the top surface of the active layer; The first source and the second source are formed based on the second mask layer; Remove the second mask layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The formation of the first doped region and the second doped region includes: A first sidewall structure is formed on the sidewall of the first mask layer along the direction parallel to the substrate; Based on the first mask layer and the first sidewall structure, a first initial doped region and a second initial doped region are formed; Remove the first sidewall structure; The formation of the first source and the second source based on the second mask layer includes: Based on the second mask layer, a first initial source and a second initial source are formed. The first initial source at least partially replaces the first initial doped region, and the remaining first initial doped region constitutes the first doped region. The second initial source at least partially replaces the second initial doped region, and the remaining second initial doped region constitutes the second doped region. Based on the first initial source and the second initial source, the first source and the second source are formed.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After forming a gate structure on the top surface of the target doped region, the method further includes: An interlayer dielectric layer is formed, which at least covers the exposed surface of the gate structure; A first source contact electrode and a second source contact electrode are formed, wherein the first source contact electrode is at least located on the top surface of the first source contact layer, and the second source contact electrode is at least located on the top surface of the second source contact layer. A barrier layer and a metal layer are formed, wherein the barrier layer covers the outer surface of the interlayer dielectric layer, the top surface of the first source contact electrode and the top surface of the second source contact electrode, and the metal layer covers the outer surface of the barrier layer; A drain contact layer and a drain electrode are sequentially formed on the bottom surface of the substrate.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Includes at least one of the following features: The doping element in the target doped region includes aluminum. The thickness of the target doped region ranges from 0.4 μm to 1 μm; The target doped region is formed using an ion implantation process, wherein the dose range of the ion implantation process is 1E14 to 1E15.

6. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 5, comprising: Substrate, and an epitaxial layer and an active layer located on the top surface of the substrate; A first well region and a second well region are located within the active layer, and the first well region and the second well region are arranged along a direction parallel to the substrate. A first source and a second source, wherein the first source is located within the first well region and the second source is located within the second well region; The target doped region is located within the active layer, and the target doped region is also located between the first well region and the second well region; A gate structure is located on the top surface of the target doped region. The width of the gate structure is greater than the distance between the opposite sidewalls of the first well region and the second well region and less than the distance between the opposite sidewalls of the first source and the second source. The doping type of the target doped region is a high-concentration P-type ion implantation film.

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