Method for improving performance of metal-oxide-semiconductor transistor
By adjusting the ratio of the channel length to the stress metal gate thickness (Lg/TMG) of the MOS transistor, the problem of unclear performance mechanism of the stress metal gate on NMOS and PMOS was solved, realizing synergistic optimization of transistor performance and process simplification, and reducing costs.
Patent Information
- Application Number
- CN202511140714.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-12-09
AI Technical Summary
In the prior art, the mechanism by which stress metal gates, especially tensile stress metal gates, affect the performance of NMOS and PMOS transistors is unclear, making it difficult to accurately and synergistically optimize the performance of both, and hindering advanced manufacturing solutions that simplify processes and reduce costs.
By determining the ratio of the channel length to the stress metal gate thickness (Lg/TMG) of a MOS transistor, and adjusting this ratio to generate a target stress type in the channel, transistor performance can be improved.
This achieves synergistic optimization of NMOS and PMOS transistors, simplifying the manufacturing process, reducing costs, and improving product yield and performance.
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Figure CN121099673A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving the performance of a metal-oxide-semiconductor transistor. BACKGROUND
[0002] With the continuous shrinkage of semiconductor process nodes, in order to continuously improve the drive current and switching performance of MOS transistors, strain engineering technology is widely used in semiconductor manufacturing. The core idea of strain engineering is to change the crystal lattice structure of silicon (Si) by introducing a specific stress in the channel region of the transistor, thereby improving the mobility of carriers (electrons and holes). Generally, introducing tensile stress in the channel of an NMOS transistor can effectively improve the electron mobility; and introducing compressive stress in the channel of a PMOS transistor can effectively improve the hole mobility.
[0003] Stressed metal gate technology is an important means to realize strain engineering, especially in advanced gate-last processes. By depositing a metal material with internal stress when forming the gate, the metal gate exerts stress on the underlying channel. According to the inherent properties of the metal material, the stressed metal gate can be divided into tensile stress metal gate and compressive stress metal gate.
[0004] In the prior art, for the compressive stress metal gate, it is generally believed that it mainly introduces tensile stress in the channel, so it is often used to improve the performance of NMOS transistors. For the tensile stress metal gate, its influence mechanism on the channel stress is more complex. The prior art generally lacks systematic analysis and quantitative research on how it affects the performance of NMOS and PMOS transistors. Specifically, the prior art fails to clearly reveal the interaction relationship between the geometric parameters (such as thickness) of the stressed metal gate and the geometric parameters (such as channel length) of the transistor, and how this relationship ultimately determines the type (tensile or compressive) and size of the stress generated in the channel.
[0005] This lack of understanding leads to difficulties in accurately and synergistically optimizing the performance of NMOS and PMOS transistors when designing devices. For example, one direct solution is to use compressive stress gates for NMOS and tensile stress gates for PMOS at the same process node, but this requires integrating two different metal gate processes, increasing process complexity and cost. Another more desirable simplified solution is to use only a single type of stress metal gate (e.g., only tensile stress metal gates) to simultaneously meet the stress requirements of NMOS and PMOS. However, in the prior art, how to introduce tensile stress for NMOS and compressive stress for PMOS by regulating a single type of tensile stress metal gate remains a technical problem to be solved.
[0006] Therefore, there is an urgent need in the industry for a method that can reveal the interaction mechanism between stress metal gates (particularly tensile stress metal gates) and channel size, and can synergistically optimize NMOS and PMOS transistors based on this mechanism, and propose a feasible implementation scheme that takes into account performance and process complexity. SUMMARY
[0007] The technical problem to be solved by the present application is that the prior art lacks a quantitative regulation method for how stress metal gates (particularly tensile stress metal gates) affect channel stress, which leads to difficulties in accurately and synergistically optimizing the performance of NMOS and PMOS transistors when designing devices, and hinders the development of advanced manufacturing solutions that can simplify processes and reduce costs, such as using a single type of stress metal to simultaneously meet the tensile stress requirements of NMOS and the compressive stress requirements of PMOS.
[0008] To achieve the above object and other related objects, the present application provides a method for improving the performance of a metal-oxide-semiconductor transistor, comprising:
[0009] Step one, determining the ratio of the channel length (Lg) of the MOS transistor to the thickness (TMG) of the stress metal gate of the MOS transistor, i.e., the Lg / TMG ratio;
[0010] Step two, adjusting the Lg / TMG ratio according to the type of the MOS transistor to generate a target type of stress in the channel of the MOS transistor, thereby improving the performance of the MOS transistor.
[0011] Preferably, the stress metal gate is a tensile stress metal gate.
[0012] Preferably, in step two, the stress type applied to the channel by the tensile stress metal gate depends on the characteristics of the Lg / TMG ratio, and the adjusting the Lg / TMG ratio includes: when the MOS transistor is a PMOS transistor, adjusting the Lg / TMG ratio to a first predetermined range to generate compressive stress in the channel; and / or when the MOS transistor is an NMOS transistor, adjusting the Lg / TMG ratio to a second predetermined range to generate tensile stress in the channel.
[0013] Preferably, the first predetermined range is that the Lg / TMG ratio is greater than a preset threshold value.
[0014] Preferably, the second predetermined range is that the Lg / TMG ratio is less than a preset threshold value.
[0015] Preferably, the method is applied to device manufacturing for different process nodes, and by adjusting the Lg / TMG ratio in step two, optimal stress is applied to the NMOS transistor and / or the PMOS transistor under the different process nodes.
[0016] Preferably, the method is applied to manufacturing semiconductor devices integrated in the same process node, and the semiconductor devices include an NMOS transistor and a PMOS transistor, and the method includes: forming a compressive stress metal gate for the NMOS transistor; and forming a tensile stress metal gate for the PMOS transistor.
[0017] Preferably, the method is applied to manufacturing semiconductor devices integrated in the same process node, and the semiconductor devices include an NMOS transistor and a PMOS transistor, and the method includes: forming a tensile stress metal gate on both the NMOS transistor and the PMOS transistor; setting the thickness of the tensile stress metal gate on the NMOS transistor to a first thickness, and setting the thickness of the tensile stress metal gate on the PMOS transistor to a second thickness, wherein the first thickness is greater than the second thickness.
[0018] Preferably, by setting the first thickness to be greater than the second thickness, and in combination with the channel length of the NMOS transistor and the PMOS transistor respectively, the Lg / TMG ratio of the NMOS transistor is in a second predetermined range to generate tensile stress, and the Lg / TMG ratio of the PMOS transistor is in a first predetermined range to generate compressive stress.
[0019] Preferably, the method is applied in a gate-last process flow, and the stress metal gate is formed by a replacement metal gate technology.
[0020] As described above, the method for improving the performance of metal-oxide-semiconductor transistor of the present application has the following beneficial effects:
[0021] The present application explicitly and quantitatively determines that the ratio of MOS transistor channel length (Lg) to tensile stress metal gate thickness (TMG) (Lg / TMG ratio) is a key factor determining the channel stress type (tensile or compressive). This discovery promotes the device design from qualitative cognition to quantitative regulation, enabling the accurate application of optimal stress to NMOS and PMOS as needed; based on the above mechanism, the present application can simultaneously introduce tensile stress to NMOS channel and compressive stress to PMOS channel by simply adjusting the geometric parameters using a single type of tensile stress metal gate, thereby synergistically and effectively improving the carrier mobility and driving capability of both types of transistors, ultimately achieving higher overall device performance; the scheme of using the same type of tensile stress metal gate with different thicknesses proposed by the present application avoids the complex process of integrating two different stress materials on the same chip, significantly simplifying the manufacturing process, reducing the photolithography, deposition, and etching processes, thereby greatly reducing manufacturing costs, shortening research and production cycles, and improving product yield. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 A schematic diagram showing the generation of compressive stress in the channel of a long-channel device using a tensile stress metal gate in an embodiment of the present application;
[0023] Figure 2 A schematic diagram showing the generation of tensile stress in the channel of a short-channel device using a tensile stress metal gate in an embodiment of the present application;
[0024] Figure 3 A schematic diagram showing the generation of compressive stress in the channel when using a thin tensile stress metal gate in an embodiment of the present application;
[0025] Figure 4 A schematic diagram showing the generation of tensile stress in the channel when using a thick tensile stress metal gate in an embodiment of the present application;
[0026] Figure 5 A schematic diagram showing the relationship between the ratio of channel length to stress metal gate thickness (Lg / TMG) and the channel stress type disclosed by the present application;
[0027] Figure 6 A schematic diagram showing the generation of tensile stress in the channel using a compressive stress metal gate in an embodiment of the present application;
[0028] Figure 7 A schematic diagram showing an integrated scheme in which a compressive stress metal gate is used for NMOS and a tensile stress metal gate is used for PMOS in an embodiment of the present application;
[0029] Figure 8 A process flow diagram showing another preferred embodiment of the present application, in which performance co-optimization is achieved by forming different thickness of the same tensile stress metal gate on NMOS and PMOS;
[0030] Figure 9 A method diagram showing the present application for improving the performance of metal-oxide-semiconductor (MOS) transistors. DETAILED DESCRIPTION
[0031] The present application can be further understood by the following specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. The present application can also be implemented or applied by other different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications without departing from the spirit of the present application.
[0032] Referring to Figure 9 The present embodiment provides a method for improving the performance of metal-oxide-semiconductor (MOS) transistors, comprising the following steps:
[0033] Step one, determining the ratio of the channel length (Lg) of the MOS transistor to the thickness (TMG) of the stress metal gate of the MOS transistor, i.e. the Lg / TMG ratio.
[0034] Step two, adjusting the Lg / TMG ratio according to the type of the MOS transistor to generate a target type of stress in the channel of the MOS transistor, thereby improving the performance of the MOS transistor. This method utilizes the quantitative relationship between the geometric size of the stress metal gate and its effect on the stress applied to the channel, and by actively regulating a geometric ratio that is easy to control in design and manufacturing, the channel stress can be precisely managed, thereby obtaining predictable and optimized transistor performance improvement.
[0035] In some embodiments, the stress metal gate is a tensile stress metal gate. By using a tensile stress metal gate as a stress source, its unique physical properties can be utilized to achieve performance co-optimization of NMOS and PMOS transistors through a single type of metal material, providing a new technical path for simplifying the semiconductor manufacturing process.
[0036] In some embodiments, the type of stress applied to the channel by the tensile stress metal gate in step ii depends on the characteristics of the Lg / TMG ratio, and adjusting the Lg / TMG ratio includes: when the MOS transistor is a PMOS transistor, adjusting the Lg / TMG ratio to a first predetermined range to generate compressive stress in the channel; and / or when the MOS transistor is an NMOS transistor, adjusting the Lg / TMG ratio to a second predetermined range to generate tensile stress in the channel. One key finding of the present disclosure is that a tensile stress metal gate does not always apply tensile stress to the channel, and the final effect is strongly related to the Lg / TMG ratio.
[0037] Specifically, as shown in Figure 1 and Figure 2 , for devices using the same tensile stress metal gate, the channel of a long channel device will be subjected to compressive stress, while the channel of a short channel device will be subjected to tensile stress. Similarly, as shown in Figure 3 and Figure 4 , using a thin tensile stress metal gate will cause the channel to be subjected to compressive stress, while using a thick tensile stress metal gate will cause the channel to be subjected to tensile stress. Therefore, the present disclosure discloses that this effect can be uniformly described by the Lg / TMG ratio, as shown in Figure 5 , when the ratio is large, the overall effect of the gate on the channel is to introduce compressive stress in the channel, which is exactly what is needed to improve the performance of PMOS transistors, effectively increasing the hole mobility and enhancing the driving ability of PMOS; on the contrary, when the ratio is small, the desired tensile stress is introduced in the channel, thereby effectively increasing the electron mobility and enhancing the driving ability of NMOS. Using this mechanism, designers can flexibly design the gate size according to the type of transistor to obtain the best performance gain.
[0038] In some embodiments, the first predetermined range is that the Lg / TMG ratio is greater than a certain preset threshold. The preset threshold represents the critical point at which the type of stress changes, and when the ratio is higher than this threshold, effective compressive stress can be stably obtained in the PMOS channel.
[0039] In some embodiments, the second predetermined range is that the Lg / TMG ratio is less than a certain preset threshold. Accordingly, when the ratio is lower than this threshold, effective tensile stress can be stably obtained in the NMOS channel. By defining this threshold, clear guidance can be provided for device design, ensuring that different types of transistors can be applied with the correct type of stress.
[0040] In some embodiments, the method is applied to fabricate devices for different process nodes, by adjusting the Lg / TMG ratio in step two, to apply optimized stress to NMOS transistors and / or PMOS transistors for different process nodes. As semiconductor processes evolve to more advanced nodes, the channel length Lg keeps shrinking. At this time, the thickness TMG of the stress metal gate can be adjusted accordingly to maintain or re-optimize the Lg / TMG ratio, to ensure that NMOS and PMOS can still obtain optimal stress regulation at the new process node, to continuously improve device performance.
[0041] In some embodiments, the method is applied to fabricate semiconductor devices integrated in the same process node, including NMOS transistors and PMOS transistors, the method including: forming a compressive stress metal gate for the NMOS transistors; and forming a tensile stress metal gate for the PMOS transistors. This is an implementation that directly utilizes the traditional advantages of different types of stress gates, and can reliably improve the performance of both types of transistors. As shown in FIG. 1, the compressive stress metal gate can stably provide tensile stress to the channel, making it an ideal choice to improve the performance of NMOS transistors. Figure 6 Figure 7 This integrated solution of using a compressive stress metal gate for NMOS and a tensile stress metal gate for PMOS is schematically shown in FIG. 2.
[0042] In some embodiments, the method is applied to fabricate semiconductor devices integrated in the same process node, including NMOS transistors and PMOS transistors, the method including: forming a tensile stress metal gate on both the NMOS transistors and the PMOS transistors; setting the thickness of the tensile stress metal gate on the NMOS transistors to a first thickness, and setting the thickness of the tensile stress metal gate on the PMOS transistors to a second thickness, wherein the first thickness is greater than the second thickness. As shown in FIG. 3, the tensile stress metal gate can stably provide compressive stress to the channel, making it an ideal choice to improve the performance of PMOS transistors. Figure 8 As shown, the scheme provides a specific implementation for simplifying the process flow. For example, a layer of tensile stress metal with a first thickness (thicker) can be first deposited on the entire wafer including NMOS (NFET) and PMOS (PFET) devices. Then, a photoresist (PR) mask is formed by a photolithography process to protect the NMOS region, and a partial removal of the tensile stress metal layer in the PMOS region not protected by the mask is performed by an etching process to reduce its thickness to a second thickness (thinner). Finally, the photoresist is removed. In this way, the same set of metal deposition and etching processes can be used to efficiently manufacture CMOS devices with stress gates of different thicknesses. By setting the first thickness to be greater than the second thickness and combining the channel lengths of the NMOS and PMOS transistors, the Lg / TMG ratio of the NMOS transistor is in a second predetermined range (smaller value range) to generate tensile stress, and the Lg / TMG ratio of the PMOS transistor is in a first predetermined range (larger value range) to generate compressive stress.
[0043] Specifically, for NMOS, a thicker tensile stress metal gate (first thickness) is used to make its Lg / TMG ratio smaller, thereby generating tensile stress in its channel; for PMOS, a thinner tensile stress metal gate (second thickness) is used to make its Lg / TMG ratio larger, thereby generating compressive stress in its channel. The greatest advantage of this scheme is that only one type of stress metal material (tensile stress metal) is used for the entire CMOS device, and its thickness in the NMOS and PMOS regions is controlled by photolithography and different depth deposition or etching processes. This greatly simplifies the manufacturing process, avoids the complex process of integrating two different stress metals, thereby significantly reducing production costs, shortening manufacturing cycles and improving product yield, providing a solution for high-performance, low-cost advanced semiconductor device manufacturing.
[0044] In some embodiments, the method is applied in a gate-last process flow to form a stress metal gate by replacing the metal gate (RMG) technology. Since the stress metal gate is deposited after all high-temperature annealing processes, its inherent stress will not be released or changed by subsequent high-temperature steps, thereby ensuring that the preset stress can be transmitted to the channel to the greatest extent and most stably. This ensures that the stress effect designed by adjusting the Lg / TMG ratio can be accurately achieved, ensuring the reliability and effectiveness of the present technical solution.
[0045] It is to be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.
[0046] The above-described embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method for improving the performance of a metal-oxide-semiconductor transistor, characterized in that, At least including: Step 1: Determine the ratio of the channel length (Lg) of the MOS transistor to the thickness (TMG) of the stressed metal gate of the MOS transistor, i.e., the Lg / TMG ratio. Step 2: Adjust the Lg / TMG ratio according to the type of the MOS transistor to generate the target type of stress in the channel of the MOS transistor, thereby improving the performance of the MOS transistor.
2. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 1, characterized in that: The stress metal grid is a tensile stress metal grid.
3. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 2, characterized in that: In step two, taking advantage of the characteristic that the type of stress applied to the channel by the tensile stress metal gate depends on the Lg / TMG ratio, adjusting the Lg / TMG ratio includes: when the MOS transistor is a PMOS transistor, adjusting the Lg / TMG ratio to a first predetermined range to generate compressive stress in the channel; and / or when the MOS transistor is an NMOS transistor, adjusting the Lg / TMG ratio to a second predetermined range to generate tensile stress in the channel.
4. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 3, characterized in that: The first predetermined range is when the Lg / TMG ratio is greater than a certain preset threshold.
5. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 3, characterized in that: The second predetermined range is when the Lg / TMG ratio is less than a certain preset threshold.
6. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 1, characterized in that: The method is applied to the fabrication of devices at different process nodes. By adjusting the Lg / TMG ratio in step two, optimal stress is applied to NMOS transistors and / or PMOS transistors at the different process nodes.
7. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 1, characterized in that: The method is applied to the manufacture of semiconductor devices integrated at the same process node, the semiconductor devices including NMOS transistors and PMOS transistors, the method comprising: forming a compressive stress metal gate for the NMOS transistor; and forming a tensile stress metal gate for the PMOS transistor.
8. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 2, characterized in that: The method is applied to the manufacture of semiconductor devices integrated at the same process node, the semiconductor devices including NMOS transistors and PMOS transistors, the method comprising: forming tensile stress metal gates on both the NMOS transistors and the PMOS transistors; setting the thickness of the tensile stress metal gate on the NMOS transistor to a first thickness, and setting the thickness of the tensile stress metal gate on the PMOS transistor to a second thickness, wherein the first thickness is greater than the second thickness.
9. The method for improving the performance of a metal-oxide-semiconductor transistor according to claim 1, characterized in that: By setting the first thickness to be greater than the second thickness, and combining the respective channel lengths of the NMOS transistor and the PMOS transistor, the Lg / TMG ratio of the NMOS transistor is placed within a second predetermined range to generate tensile stress, and the Lg / TMG ratio of the PMOS transistor is placed within a first predetermined range to generate compressive stress.
10. The method for improving the performance of a metal-oxide-semiconductor transistor according to any one of claims 1 to 9, characterized in that: The method is applied in the post-gate process flow to form the stress metal gate by replacing the metal gate technology.