Semiconductor structure, method of manufacturing the same, and semiconductor device

Abstract

The application relates to a semiconductor structure and a preparation method thereof and a semiconductor device, comprising: a substrate; and interlayer dielectric layers and gate trenches alternately arranged along a first direction parallel to a first surface of the substrate on the first surface of the substrate; the gate trench comprises, in sequence along a second direction away from the substrate, a dielectric stack, a target work function layer, a protective layer, a barrier layer and a metal conductive layer; the dielectric stack is located on an inner surface of the gate trench; the longitudinal section of the target work function layer is in a concave shape, and the top surface is lower than a plane where a gate trench opening is located; the protective layer is located on the upper surface of the target work function layer and the inner wall of the dielectric stack, and the top surface is flush with the top surfaces of the barrier layer, the metal conductive layer and the interlayer dielectric layer. In the above structure, the work function layer surface and the sidewall are both protected by the protective layer, and the work function layer is not directly exposed on the gate surface, so that the bottom work function layer is not damaged by Wet HF in the subsequent process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, its fabrication method, and a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase their speed. High-K metal gate (HK-MG) technology is widely used in advanced chip manufacturing to improve chip performance, where the metal gate can be selected from various work function metals to adjust the threshold voltage.

[0003] However, during the formation of the metal gate, due to the soft hardness and active properties of the gate material, defects such as particle residue, scratches, and corrosion are easily generated during chemical mechanical polishing (CMP). These defects can damage the original morphology of the gate in subsequent processes, thereby affecting the performance of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method, as well as a semiconductor device, to address the technical problems in the prior art, so as to at least maintain the morphology of the gate in the subsequent grinding process.

[0005] In a first aspect, this application provides a semiconductor structure, including: a substrate; and an interlayer dielectric layer and a gate trench arranged alternately on a first surface of the substrate along a first direction parallel to the first surface;

[0006] The gate trench includes a dielectric stack, a target work function layer, a protective layer, a barrier layer, and a metal conductive layer arranged sequentially along a second direction away from the substrate; wherein, the dielectric stack is located on the inner surface of the gate trench; the longitudinal section of the target work function layer is U-shaped, and the top surface is lower than the plane where the gate trench opening is located; the protective layer is located on the upper surface of the target work function layer and the inner wall of the dielectric stack, and the top surface is flush with the top surfaces of the barrier layer, the metal conductive layer, and the interlayer dielectric layer.

[0007] In the semiconductor structure described above, the longitudinal section of the target work function layer is U-shaped, with its sidewalls lower than the sidewalls of the gate trench. The U-shaped structure of the work function is covered by a protective layer that extends to the interface between the dielectric stack and the barrier layer. This effectively avoids direct contact between the etching solution and the target work function layer when the etching solution penetrates along the defects or damage on the surface of the cover layer during subsequent grinding processes, thus ensuring the integrity of the morphology of the target work function layer.

[0008] In some embodiments, the dielectric stack includes: a first dielectric layer and a second dielectric layer;

[0009] The first dielectric layer is located at the bottom of the gate trench;

[0010] The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench.

[0011] In some embodiments, the inner wall of the second dielectric layer is in contact with the outer wall of the target work function layer and the outer wall of the protective layer.

[0012] In some embodiments, the substrate includes a first active region and a second active region arranged along a first direction;

[0013] The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

[0014] In a second aspect, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate, wherein a first surface of the substrate includes an interlayer dielectric layer and a gate trench arranged alternately along a first direction parallel to the first surface;

[0015] After forming a dielectric stack in the gate trench, a covering dielectric stack is formed, and an initial work function layer with a predetermined excess thickness is deposited; the thickness is used to characterize the size along a second direction away from the substrate;

[0016] The initial work function layer of the gate trench is partially removed by using a target gas, exposing the inner wall of the gate trench and obtaining a target work function layer with a concave cross-section.

[0017] A protective layer is formed that at least covers the upper surface of the target work function layer and the exposed inner wall.

[0018] In the fabrication method described in the above embodiments, a portion of the initial work function layer sidewalls is removed by selective etching with a target gas to form a U-shaped structure, ensuring that the top surface of the target work function layer is lower than the plane where the gate trench opening is located. During the etching process, the dielectric stack acts as an etching stop layer, effectively protecting the gate trench from damage.

[0019] The protective layer has excellent step coverage capability, completely encapsulating the concave structure, thereby blocking the penetration path of the subsequent etching solution and ensuring the integrity of the target work function layer structure.

[0020] In some embodiments, the removal of a portion of the initial work function layer using a target gas includes:

[0021] The target gas, including hydrogen fluoride and ammonia, is used to remove the initial work function layer of the target thickness in the gate trench.

[0022] In some embodiments, an excess positive correlation with the target thickness is preset.

[0023] In some embodiments, the dielectric stack includes: a first dielectric layer and a second dielectric layer;

[0024] The first dielectric layer is located at the bottom of the gate trench;

[0025] The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench;

[0026] The substrate includes a first active region and a second active region arranged along a first direction;

[0027] The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

[0028] In some embodiments, a barrier layer is formed that at least covers the inner surface of the protective layer, and a metallic conductive layer is formed that fills the remaining gaps in the gate trench.

[0029] Chemical mechanical polishing is performed on the semiconductor structure to form a metal gate.

[0030] Thirdly, this application also provides a semiconductor device, including the semiconductor structure as described in any of the above embodiments; or the semiconductor structure formed by the preparation method as described in any of the above embodiments.

[0031] In the semiconductor devices described above, key failure issues such as threshold voltage drift and gate leakage caused by physical damage or chemical corrosion of the target work function layer can be effectively avoided, reducing chip manufacturing defects from the source and providing a reliable guarantee for improving chip yield.

[0032] The semiconductor structure, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0033] During the process, anisotropic etching is used to precisely shape the concave target work function layer. At the same time, conformal coating technology is used to form a continuous and sealed protective layer on the surface and sidewalls of the target work function layer, which isolates the erosion of etching solutions in subsequent CMP, wet cleaning and other processes, effectively ensuring the integrity of the target work function layer and thus significantly improving the chip yield. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1a This is a schematic diagram of the fabrication process of a semiconductor structure in related technologies;

[0036] Figure 1b for Figure 1a A schematic diagram of a partial cross-sectional electron microstructure of the middle gate;

[0037] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure provided in one embodiment of this application;

[0038] Figure 3 This is a flowchart of a semiconductor structure fabrication method provided in one embodiment of this application;

[0039] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming a gate trench in step S102 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0040] Figure 5a This is a schematic cross-sectional view of the structure obtained after forming a dielectric stack in step S502 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0041] Figure 5b for Figure 5a Enlarged structural diagram of the dashed box;

[0042] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the initial work function layer in step S504 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0043] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a partially removed target work function layer in step S106 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0044] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming a protective layer in step S108 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0045] Figure 9 for Figure 8 A cross-sectional schematic diagram of the structure obtained after the formation of the barrier layer and the conductive metal layer;

[0046] Figure 10 This is a comparative schematic diagram of the semiconductor structure provided in this application and the semiconductor structures provided in related technologies.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10. Substrate; 11. Interlayer dielectric layer; 12. Gate trench; 21. First dielectric layer; 22. Second dielectric layer; 201. First dielectric material layer; 202. Second dielectric material layer; 203. Third dielectric material layer; 204. Fourth dielectric material layer; 205. Fifth dielectric material layer; 301. Initial work function layer; 30. Target work function layer; 40. Protective layer; 50. Barrier layer; 60. Metal conductive layer. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0055] For example, the process flow is as follows Figure 1aAs shown, during the gate structure formation process of the polishing process, polishing particles and polishing slurry residues easily adhere to and accumulate on the top surface of the gate, forming particulate contaminants. In the dry etching step of the high resistivity (HiR) process, the capping layer surface experiences localized stress concentration or uneven etching due to particle residues, leading to defects such as pinholes and cracks in the capping layer, disrupting its continuity and directly exposing the underlying work function layer. When the subsequent wet etching process begins, although the gate metal layers are filled normally, the etching solution can penetrate into the work function layer along the channels formed by the capping layer defects. Because the etching rate of the work function layer material is significantly higher than that of the metal layer, the solution will continuously corrode along the sidewalls of the work function layer, ultimately causing a localized absence of the bottom work function layer, forming a void, as shown in the specific structure. Figure 1b As shown, this directly leads to electrical performance failures such as threshold voltage drift and gate leakage in the device, seriously affecting chip yield and reliability.

[0056] Based on this, please refer to Figure 2 This application provides a semiconductor structure. In this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. In this embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.

[0057] The semiconductor structure includes: a substrate 10; and an interlayer dielectric layer 11 and a gate trench 12 arranged alternately along the OY direction on the first surface 10a of the substrate 10.

[0058] The gate trench 12 includes a dielectric stack, a target work function layer 30, a protective layer 40, a barrier layer 50, and a metal conductive layer 60 arranged sequentially along the OZ direction. The dielectric stack is located on the inner surface of the gate trench 12. The longitudinal section of the target work function layer 30 is U-shaped, and its top surface is lower than the plane where the opening of the gate trench 12 is located. The protective layer 40 is located on the upper surface of the target work function layer 30 and the inner wall of the dielectric stack, and its top surface is flush with the top surfaces of the barrier layer 50, the metal conductive layer 60, and the interlayer dielectric layer 11.

[0059] For example, the substrate 10 includes a first active region A and a second active region B arranged along the OY direction.

[0060] In this embodiment, the first active region A is a P-type active region and the second active region B is an N-type active region. Of course, the active regions may also include other electrical or isolation structures. This is a well-known technology of metal gate process, and the specific structure will not be described in detail.

[0061] Furthermore, in some embodiments, the dielectric stack includes a first dielectric layer 21 and a second dielectric layer 22; the first dielectric layer 21 is located on the bottom surface of the gate trench 12; the second dielectric layer 22 is located on the top surface of the first dielectric layer 21 and on the inner wall of the gate trench 12;

[0062] For example, the inner wall of the first dielectric layer 21 is in contact with the outer wall of the target work function layer 30 and the outer wall of the protective layer 40.

[0063] For example, the second dielectric layer 22 in the first active region A may be the same as or different from the second dielectric layer 22 in the second active region B.

[0064] The semiconductor structure in the above embodiments and Figure 1a When comparing semiconductor structures in related technologies, it can be found that in the semiconductor structure provided in this application, the protective layer completely covers the top surface of the target work function layer, embedding the target work function layer into the metal gate. During subsequent wet etching processes, even if defects appear in the gate top surface capping layer, the etching solution, when penetrating along the defect channel to the surface of the protective layer, will be unable to continue eroding downwards due to the physical barrier and chemical inertness of the protective layer, thus ensuring the structural integrity of the target work function layer inside the gate. Compared with the structure in the prior art where the target work function layer is partially exposed, this effectively blocks the penetration path of the etching solution, effectively reduces the risk of missing target work function layers, and improves the reliability of the semiconductor structure.

[0065] Please see Figures 3-9 On the other hand, this application provides a method for preparing a semiconductor structure, used to prepare such a semiconductor structure. Figure 2 The semiconductor structure shown includes steps S102-S108.

[0066] Step S102: Provide a substrate 10, the first surface 10a of the substrate 10 including an interlayer dielectric layer 11 and a gate trench 12 arranged alternately along the OY direction.

[0067] Step S104: After forming a dielectric stack in the gate trench 12, a cover dielectric stack is formed, and an initial work function layer 301 with a preset excess thickness is deposited; the thickness is used to characterize the size along the OZ direction.

[0068] Step S106: Use the target gas to remove part of the initial work function layer 301 of the gate trench, so that part of the sidewall of the gate trench 12 is exposed, and a target work function layer 30 with a concave cross section is obtained.

[0069] Step S108: Form a protective layer 40 that at least covers the upper surface of the target work function layer 30 and the exposed inner wall.

[0070] The semiconductor structure obtained after steps S102-S108 can be found in [reference]. Figure 9For ease of understanding this application, Figures 4 to 9 This is a schematic diagram illustrating the steps of an exemplary semiconductor structure fabrication method provided in this application embodiment, wherein, Figure 9 This application provides an example of a semiconductor structure prepared using the method described herein. Other suitable examples of semiconductor structures prepared using this application are also possible, and no limitations are imposed herein.

[0071] The following is combined with Figures 4 to 9 The semiconductor structures provided in the embodiments of this application will be described in detail.

[0072] Please see Figure 4 Step S102 further includes: forming an interlayer dielectric layer 11 on the top surface of the substrate 10 using a deposition process, and then performing photolithography and etching processes to form gate trenches 12 spaced apart along the OY direction in the interlayer dielectric layer 11.

[0073] For example, the substrate 10 includes a P-type first active region A and an N-type second active region B arranged along the OY direction.

[0074] For example, substrate 10 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1). x As, Ga x Al 1-x N、In x Ga 1-x As, etc.) or combinations thereof. The substrate 10 may include other device structures (not shown), such as isolation trench structures. Those skilled in the art can select the substrate specifically according to the transistor type, therefore the type of substrate should not limit the scope of protection of this application.

[0075] For example, the interlayer dielectric layer 11 is typically a dielectric material, including but not limited to silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiO2). x N y )wait.

[0076] Please see Figure 5a and Figure 5b Step S104 further includes:

[0077] Step S502: A first dielectric material layer 201 located at the bottom of the gate trench 12 is sequentially formed within the gate trench 12 by a deposition process. A second dielectric material layer 202 and a third dielectric material layer 203 are then stacked on top of the first dielectric material layer 201, and a fourth dielectric material layer 204 covers the remaining inner wall of the gate trench 12 and the top surface of the third dielectric material layer 203. Next, a fifth dielectric material layer 205 is further formed within the gate trench 12 corresponding to the first active region A, resulting in... Figure 5a The structure shown.

[0078] Specifically, such as Figure 5a As shown, the first dielectric material layer 201, the second dielectric material layer 202, and the third dielectric material layer 203 together constitute the first dielectric layer 21; in the first active region A, the fourth dielectric material layer 204 and the fifth dielectric material layer 205 together constitute the second dielectric layer 22; while in the second active region B, the second dielectric layer 22 is constituted solely by the fourth dielectric material layer 204.

[0079] For example, the material of the first dielectric material layer 201 includes, but is not limited to, silicon oxide (SiO2) and silicon oxynitride (SiO2). x N y (or hafnium-based oxides such as HfSiO)

[0080] For example, the material of the second dielectric material layer 202 includes, but is not limited to, materials with a high k dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), titanium oxide (TiO2), or silicon oxide (SiO2); the material of the barrier layer 50 includes, but is not limited to, silicon oxide (SiO2), doped oxides (such as silicon phosphosilicate glass (PSG), borosilicate glass (BPSG)), or silicon nitride (SiN), etc., mainly used to improve the capacitance value of the device and reduce power consumption. The specific physical thickness can be determined by the performance requirements of the device.

[0081] For example, the materials of the third dielectric material layer 203, the fourth dielectric material layer 204 and the fifth dielectric material layer 205 include, but are not limited to, metal nitrides, such as titanium nitride (TiN) or tantalum nitride (TaN).

[0082] The first dielectric layer 21 is composed of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203, as shown in the figure. Figure 5b As shown.

[0083] In the above embodiments, TiN is used as the third dielectric material layer 203, and TaN is used as the fourth dielectric material layer 204. Together, they form a double diffusion barrier structure to prevent the work function layer material from diffusing in. TiN is used as the fifth dielectric material layer 205 to increase the work function of the first active region A of the P-type, adjust the threshold voltage, and improve the electrical characteristics of the device. The first dielectric layer 21 and the second dielectric layer 22 together constitute a dielectric stack.

[0084] Please see Figure 6 Step S504: By deposition method, an excessive initial work function layer 301 is deposited in the gate trench 12 to obtain the following... Figure 6 The structure shown.

[0085] For example, the preset excess is positively correlated with the target thickness. The more target thickness is removed, the larger the preset excess. In this embodiment, the preset excess range is 1nm-2nm, for example, 1nm, 1.5nm or 2nm, etc.

[0086] In this embodiment, TiAl (titanium aluminum compound) is selected as the initial work function layer 301, which has a suitable work function value and can effectively regulate the threshold voltage of the device. Of course, the choice of material for the initial work function layer is not limited to this; other materials can also be selected. The key is that when etching with the target gas, the etching rate of the initial work function layer material must be significantly higher than that of the fourth dielectric material layer 204 and the fifth dielectric material layer 205 to form a sufficient etching selectivity. This effectively protects the underlying and lateral barrier layer structures when removing part of the initial work function layer material, avoiding adverse effects on device performance. This matching design of material selection and etching process provides a flexible process window for device manufacturing.

[0087] Please see Figure 7 Step S106 further includes: using a target gas including hydrogen fluoride and ammonia to remove the initial work function layer 301 of the target thickness within the gate trench 12, to obtain... Figure 7 The target work function layer 30 is then annealed onto the substrate 10 to remove reaction byproducts and repair interface defects.

[0088] Thickness is used to characterize the dimension along the ZO direction (the opposite direction of OZ).

[0089] For example, at radio frequency (RF) power, a mixture of hydrogen fluoride (HF) and ammonia (NH3) dissociates to form NH4F, containing F. -The etching rate of the group on the initial work function layer (such as TiAl) is significantly higher than that on the fourth dielectric material layer 204 (such as TaN) and the fifth dielectric material layer 205 (such as TiN), so it is possible to selectively remove the portion of the initial work function layer 301 with a sidewall height of more than 40nm of the gate trench 12.

[0090] In the above embodiments, the annealing process for removing byproducts can be completed in the same process chamber as the above process, reducing process costs. The excessive initial work function layer deposited in step S504 ensures that a sufficiently thick target work function layer remains at the bottom after etching to maintain electrical performance.

[0091] Please see Figure 8 Step S108 further includes: forming a protective layer 40 using an atomic layer deposition (ALD) process.

[0092] For example, the material of the protective layer 40 includes, but is not limited to, metal nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), or niobium nitride (NbN). In this embodiment, TiN is used as the protective layer 40.

[0093] In the above embodiments, the protective layer prepared by atomic layer deposition (ALD) has excellent conformability and good step coverage. It can completely wrap the surface and sidewalls of the target work function layer, and no surface is exposed on the gate surface. Therefore, in the subsequent wet etching process, the etching solution cannot come into contact with the target work function layer, which fundamentally avoids the risk of the bottom target work function layer being corroded.

[0094] Meanwhile, the concave cross-section of the target work function layer design increases the opening size during the deposition of the metal conductive layer compared to the unetched structure, which is more conducive to the subsequent filling of the gate metal, reduces filling defects such as voids and gaps caused by high aspect ratio, and improves the quality of the metal gate.

[0095] Please see Figure 9 In some embodiments, after step S108, the method further includes:

[0096] A barrier layer 50 is formed that at least covers the inner surface of the protective layer 40, and a metal conductive layer 60 is formed that fills the remaining gaps in the gate trench 12; the above structure is subjected to chemical mechanical polishing to form a metal gate.

[0097] For example, the barrier layer 50 is made of a composite layer of titanium nitride and titanium (TTN), which is mainly used to improve the capacitance of the transistor and enhance its ability to drive current. It can also be used as a diffusion barrier layer to prevent the material forming the metal conductive layer 60 from diffusing into the underlying dielectric layer.

[0098] For example, the material of the metal conductive layer 60 includes, but is not limited to, at least one of aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), and platinum (Pt). In this embodiment, the material of the metal conductive layer 60 is Al.

[0099] In some embodiments, this application also provides a semiconductor device, including the semiconductor structure described in the above embodiments; or including a semiconductor structure prepared by the preparation method mentioned in the above embodiments. Since the semiconductor devices of the above embodiments and the semiconductor structures and preparation methods provided in this application are based on the same inventive concept, the semiconductor devices employing such semiconductor structures and preparation methods have all the advantages of the semiconductor structures and preparation methods provided in this application, which will not be elaborated upon here.

[0100] In the above embodiments, the unexpected technical effect of this application is:

[0101] Figure 10 A comparative schematic diagram of the semiconductor structure provided in this application and the semiconductor structures provided in related technologies, wherein, Figure 10 Figure (a) shows the semiconductor structure provided in this application. Figure 10 Figure (b) shows the semiconductor structure provided by the related technology. By selecting suitable materials such as TiAl as the initial work function layer and dielectric stack, the etching rate of the initial work function layer material is ensured to be significantly higher than that of the fourth and fifth dielectric material layers, forming a sufficient etching selectivity. When selectively removing part of the initial work function layer, the barrier layer structure on the side and below is effectively protected, avoiding performance degradation. The protective layer prepared by atomic layer deposition (ALD) has excellent conformability and good step coverage, which can completely wrap the surface and sidewalls of the target work function layer, so that the target work function layer is embedded in the metal gate. In the subsequent wet etching process, the contact path between the etching solution and the target work function layer is blocked, thus avoiding the corrosion risk of the bottom target work function layer from the root and ensuring the integrity of its structure and electrical performance.

[0102] In addition, the concave design of the longitudinal section of the target work function layer increases the opening size during the deposition of the metal conductive layer compared to the original unetched structure. This effectively reduces the high aspect ratio limitation during the filling process, reduces defects such as voids and gaps, improves the filling quality and conductivity continuity of the metal gate, and achieves a dual improvement in device reliability and fabrication stability.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; And interlayer dielectric layers and gate trenches are alternately arranged on the first surface of the substrate along a first direction parallel to the first surface; The gate trench includes a dielectric stack, a target work function layer, a protective layer, a barrier layer, and a metal conductive layer arranged sequentially along a second direction away from the substrate; wherein, the dielectric stack is located on the inner surface of the gate trench; the longitudinal section of the target work function layer is U-shaped, and its top surface is lower than the plane where the gate trench opening is located; the protective layer is located on the upper surface of the target work function layer and the inner wall of the dielectric stack, and its top surface is flush with the top surfaces of the barrier layer, the metal conductive layer, and the interlayer dielectric layer; the protective layer completely covers the surface and sidewalls of the target work function; the material of the protective layer includes a metal nitride layer, which is partially the same as the material of the dielectric stack; The protective layer and the metallic conductive layer are formed sequentially using a deposition process after the target work function layer is formed.

2. The semiconductor structure according to claim 1, characterized in that, The dielectric stack includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is located on the bottom surface of the gate trench; The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench.

3. The semiconductor structure according to claim 2, characterized in that, The inner wall of the second dielectric layer is in contact with the outer wall of the target work function layer and the outer wall of the protective layer.

4. The semiconductor structure according to claim 2, characterized in that, The substrate includes a first active region and a second active region arranged along the first direction; The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a first surface of the substrate includes an interlayer dielectric layer and gate trenches arranged alternately along a first direction parallel to the first surface; After forming a dielectric stack in the gate trench, an initial work function layer covering the dielectric stack is formed and deposited having a predetermined excess thickness; the thickness is used to characterize the dimension along a second direction away from the substrate; The initial work function layer of the gate trench is partially removed by using a target gas, exposing the inner wall of the gate trench and obtaining a target work function layer with a concave cross-section. A protective layer is formed that at least covers the upper surface of the target work function layer and the exposed inner wall; the protective layer completely encloses the surface and sidewalls of the target work function; the material of the protective layer includes a metal nitride layer, which is partially the same as the material of the dielectric stack.

6. The preparation method according to claim 5, characterized in that, Removing a portion of the initial work function layer using a target gas includes: The initial work function layer of the target thickness in the gate trench is removed using a target gas including hydrogen fluoride and ammonia.

7. The preparation method according to claim 6, characterized in that, The preset excess positive correlation is related to the target thickness.

8. The preparation method according to claim 5, characterized in that, The dielectric stack includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is located on the bottom surface of the gate trench; The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench; The substrate includes a first active region and a second active region arranged along the first direction; The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

9. The preparation method according to any one of claims 5-8, characterized in that, Also includes: A barrier layer is formed that at least covers the inner surface of the protective layer, and a metallic conductive layer is formed that fills the remaining gaps in the gate trench; The semiconductor structure is subjected to chemical mechanical polishing to form a metal gate.

10. A semiconductor device, characterized in that, include: The semiconductor structure as described in any one of claims 1-4; or The semiconductor structure prepared by the preparation method according to any one of claims 5-9.

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