Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. A gate is cut into multiple sections in a gate extension direction, and a gate isolation structure is formed between adjacent section gates. By introducing water vapor on the sidewall silicon nitride and on the exposed substrate, a protection layer is formed on the top of the gate and the top of the gate isolation structure by using a self-alignment process based on the hydrophobic principle. In a back etching process, the top of the gate isolation structure is protected by the protection layer, and only the sidewall silicon nitride is etched, so that the trench between the adjacent gates in the gate width direction meets a preset depth-width ratio. The unexpected effect of the application is that the local protection layer and the etching of the sidewall silicon nitride of the partial gate can be formed in a specific area without using a photolithography process, which is beneficial to avoid the formation of a depression on the top of the gate isolation structure between the adjacent section gates, and further solves the short circuit problem.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the process of manufacturing integrated circuits, a trench filled with silicon oxide is widely used as an electrical isolation structure between transistors. In order to increase the filling window of the electrical isolation structure to avoid the occurrence of holes in the electrical isolation structure, a pull back process is often used to reduce the aspect ratio of the trench between transistors, for example, a silicon nitride pull back process is used before filling the trench with an inter-layer dielectric (ILD).

[0003] However, research has found that the silicon nitride pull back process can cause a recess at the poly cut position of the gate. Figure 1 is a SEM image of a recess at the poly cut position of the gate. Figure 2 is a schematic diagram of the gate profile along the AA' line in Figure 1 Specifically as shown in Figure 1 and Figure 2 , a gate 130 is formed on a substrate 100, and after the silicon nitride pull back process, a silicon nitride recess occurs at the poly cut position of the gate 130 in the extension direction of the gate, that is, a recess 150a occurs in the gate isolation structure 150, causing metal of the metal gate to remain at the recess position of the poly cut, thereby causing a short circuit problem. SUMMARY

[0004] The present application aims to provide a semiconductor structure and a forming method thereof to solve the problem of the recess at the poly cut position of the gate caused by the silicon nitride pull back process, thereby causing a short circuit problem.

[0005] To solve the above technical problems, the present application provides a forming method of a semiconductor structure, comprising:

[0006] providing a substrate, the substrate having a gate and a sidewall silicon nitride covering the gate formed thereon, the gate being cut into multiple segments in the extension direction of the gate, and a gate isolation structure being formed between adjacent segments of the gate;

[0007] introducing water vapor, the water vapor covering the top of the gate, the sidewall silicon nitride, the top of the gate isolation structure, and the surface of the substrate exposed;

[0008] removing part of the water vapor to expose the top of the gate and the top of the gate isolation structure, and retaining the water vapor on the sidewall silicon nitride and the substrate;

[0009] The protection layer is formed by a self-alignment process, and the protection layer is located on top of the gate and on top of the gate isolation structure;

[0010] A back-etching process is performed to etch part of the sidewall silicon nitride, so that the trench between adjacent gates in the gate width direction meets a preset aspect ratio, and in the back-etching process, the protection layer is used to protect the gate isolation structure.

[0011] Optionally, the water vapor is introduced by a wet process.

[0012] Optionally, the wet process includes an immersion process or a spraying process.

[0013] Optionally, part of the water vapor is removed by a non-rotating planar drying process.

[0014] Optionally, the process temperature of the non-rotating planar drying process is 10-100℃, the process time of the non-rotating planar drying process is 10-180 seconds, the process gas of the non-rotating planar drying process is nitrogen, and the flow rate of the nitrogen is 20-150 L / min.

[0015] Optionally, the self-alignment process is a SACVD process or a HARP process, the gas in the SACVD process or the HARP process includes ozone and TEOS, the TEOS has hydrophobicity, and a hydrophobic precursor is formed in the SACVD process or the HARP process to ensure that the protection layer is only formed on top of the gate and on top of the gate isolation structure.

[0016] Optionally, after the protection layer is formed and before the back-etching process, a high-temperature baking process is used to remove the remaining water vapor.

[0017] Optionally, the sidewall silicon nitride on the gate is a gate sidewall or a silicide barrier layer.

[0018] Optionally, after the back-etching process, the protection layer on top of the gate and on top of the gate isolation structure is removed.

[0019] Based on the same concept, the application further provides a semiconductor structure prepared by the forming method of any one of the above semiconductor structures.

[0020] In the method for forming the semiconductor structure, a gate and a sidewall silicon nitride covering the gate are formed on a substrate, the gate is cut into multiple sections in a gate extension direction, and a gate isolation structure is formed between adjacent sections of the gate; then water vapor is introduced, covering the top of the gate, the sidewall silicon nitride, the top of the gate isolation structure, and the surface of the substrate exposed; then part of the water vapor is removed to expose the top of the gate and the top of the gate isolation structure, and to retain the water vapor on the sidewall silicon nitride and the substrate; then a protective layer is formed by a self-alignment process, covering the top of the gate and the top of the gate isolation structure; and then a back-etching process is performed to etch part of the sidewall silicon nitride, so that the trench between adjacent gates in the gate width direction meets a preset aspect ratio, and the protective layer protects the top of the gate isolation structure in the back-etching process. The unexpected effect of the present application is that, by introducing water vapor first and then removing part of the water vapor to expose the top of the gate and the top of the gate isolation structure, and to retain the water vapor on the sidewall silicon nitride and the substrate, and by using the hydrophobic principle, the protective layer is formed on the top of the gate and the top of the gate isolation structure by the self-alignment process. In the back-etching process, the top of the gate isolation structure is protected by the protective layer and is not etched, and only the sidewall silicon nitride of the gate is etched, so that the trench between adjacent gates in the gate width direction meets the preset aspect ratio. The local protective layer and the etched part of the sidewall silicon nitride are formed in a specific area without using a photolithography process, avoiding the problem of recess of the top of the gate isolation structure and short circuit. BRIEF DESCRIPTION OF DRAWINGS

[0021] Those skilled in the art will understand that the drawings provided are for a better understanding of the present application, and do not constitute any limitation on the scope of the present application.

[0022] Figure 1 is a SEM diagram of a gate cutting position recess.

[0023] Figure 2 is a schematic diagram of the gate profile along the AA' line in Figure 1

[0024] Figure 3 is a flow chart of the method for forming the semiconductor structure according to the embodiment of the present application.

[0025] Figure 4 is a schematic diagram of the definition of the X direction and the Y direction in the semiconductor structure according to the embodiment of the present application.

[0026] Figure 5 is a schematic diagram of the X direction structure profile of the semiconductor structure after the water vapor is introduced according to the embodiment of the present application.

[0027] Figure 6 is a schematic diagram of the Y direction structure profile of the semiconductor structure after the water vapor is introduced according to the embodiment of the present application. ​

[0028] Figure 7 is a schematic view of an X-direction structure profile of the semiconductor structure after removing part of the water vapor according to an embodiment of the present application.

[0029] Figure 8 is a schematic view of a Y-direction structure profile of the semiconductor structure after removing part of the water vapor according to an embodiment of the present application.

[0030] Figure 9 is a schematic view of an X-direction structure profile of the semiconductor structure after forming the protective layer according to an embodiment of the present application.

[0031] Figure 10 is a schematic view of a Y-direction structure profile of the semiconductor structure after forming the protective layer according to an embodiment of the present application.

[0032] Figure 11 is a schematic view of an X-direction structure profile of the semiconductor structure after removing the water vapor in the trench according to an embodiment of the present application.

[0033] Figure 12 is a schematic view of an X-direction structure profile of the semiconductor structure after the etch-back process according to an embodiment of the present application.

[0034] Figure 13 is a schematic view of an X-direction structure profile of the semiconductor structure after removing the protective layer according to an embodiment of the present application.

[0035] Figure 14 is a schematic view of a Y-direction structure profile of the semiconductor structure after removing the protective layer according to an embodiment of the present application.

[0036] Figure 1 shows a schematic view of a semiconductor structure according to an embodiment of the present application. Figures 1-2 Figure 1 shows a schematic view of a semiconductor structure according to an embodiment of the present application.

[0037] Figure 1 shows a schematic view of a semiconductor structure according to an embodiment of the present application. Figures 3-14 Figure 1 shows a schematic view of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objects, advantages and features of the present application clearer, the following will further describe the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, different scales are sometimes used in the drawings to show different focuses.

[0039] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense including "and / or" unless the context clearly dictates otherwise. The term "plurality" is generally employed in its sense including "at least one" unless the context clearly dictates otherwise. The term "at least two" is generally employed in its sense including "two or more" unless the context clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only to describe a particular feature, and do not imply relative importance or a number of the indicated features. Thus, features defined with "first," "second," "third," etc. can explicitly or implicitly include one or at least two of the features. In addition, as used in the present application, a component is disposed on another component generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two components, and the two components can be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate component, and cannot be understood as indicating or implying a spatial positional relationship between the two components, i.e. one component can be in any orientation inside, outside, above, below or one side of another component, unless the context clearly indicates otherwise. The specific meaning of the above terms in the present application can be understood according to the specific circumstances by those of ordinary skill in the art.

[0040] Figure 3 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present application. As shown in Figure 3 the present embodiment provides a method for forming a semiconductor structure, comprising:

[0041] Step S10, providing a substrate, a gate and a sidewall silicon nitride covering the gate are formed on the substrate, the gate is cut into multiple segments in the gate extension direction, and a gate isolation structure is formed between adjacent segments of the gate;

[0042] Step S20, introducing water vapor, the water vapor covers the top of the gate, the sidewall silicon nitride, the top of the gate isolation structure and the surface of the substrate exposed;

[0043] Step S30, removing part of the water vapor to expose the top of the gate and the top of the gate isolation structure, and retaining the water vapor on the sidewall silicon nitride and the substrate;

[0044] Step S40, forming a protection layer using a self-alignment process, the protection layer is located on the top of the gate and the top of the gate isolation structure;

[0045] Step S50, performing an etch-back process to etch part of the sidewall silicon nitride, so that the trench between adjacent gates in the gate width direction satisfies a preset aspect ratio, wherein in the etch-back process, the protection layer is used to protect the gate isolation structure.

[0046] Figure 4 is a schematic diagram of the definition of the X direction and the Y direction in the semiconductor structure of an embodiment of the present application. Figure 5 is a schematic diagram of the X direction structure profile of the semiconductor structure after introducing water vapor in an embodiment of the present application. Figure 6 is a schematic diagram of the Y direction structure profile of the semiconductor structure after introducing water vapor in an embodiment of the present application. Figure 7 is a schematic diagram of the X direction structure profile of the semiconductor structure after removing part of the water vapor in an embodiment of the present application. Figure 8 is a schematic diagram of the Y direction structure profile of the semiconductor structure after removing part of the water vapor in an embodiment of the present application. Figure 9 is a schematic diagram of the X direction structure profile of the semiconductor structure after forming a protective layer in an embodiment of the present application. Figure 10 is a schematic diagram of the Y direction structure profile of the semiconductor structure after forming a protective layer in an embodiment of the present application. Figure 11 is a schematic diagram of the X direction structure profile of the semiconductor structure after removing the water vapor in the trench in an embodiment of the present application. Figure 12 is a schematic diagram of the X direction structure profile of the semiconductor structure after an etch-back process in an embodiment of the present application. Figure 13 is a schematic diagram of the X direction structure profile of the semiconductor structure after removing the protective layer in an embodiment of the present application. Figure 14 is a schematic diagram of the Y direction structure profile of the semiconductor structure after removing the protective layer in an embodiment of the present application. In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the following will combine the drawings of the specification Figures 4-14 to make a detailed description of the specific embodiments of the present application.

[0047] As shown in Figure 4 , first define the directions, the X direction is the width direction of the gate 13, also called the first direction. The Y direction is the direction of the extension of the gate 13, also called the second direction. The first direction is perpendicular to the second direction, and the following will respectively along the X direction and the Y direction to the semiconductor structure profile to show the forming steps of the semiconductor structure.

[0048] As shown in Figure 5 and Figure 6As shown, a substrate 10 is provided. In some embodiments, the substrate 10 can be a semiconductor substrate made of any semiconductor material suitable for semiconductor devices, such as Si, SiC, SiGe, etc. In other embodiments, the substrate 10 can also be a silicon-on-insulator (SOI), a silicon-germanium-on-insulator, or other composite substrate. Those skilled in the art understand that the substrate is not limited and can be selected according to the actual application. Various device (not limited to semiconductor devices) components can be formed in the substrate 10. The substrate 10 can also have other layers or components formed therein, such as gate structures, contact holes, dielectric layers, metal wires and vias, etc. In the present embodiment, well regions 12 are formed in the substrate 10, and shallow trench isolation structures 11 are formed between adjacent well regions 12 to isolate the adjacent well regions 12. A gate 13 is formed on the well regions 12, and a sidewall silicon nitride 14 is formed on the sidewall of the gate 13. The sidewall silicon nitride 14 is, for example, a gate sidewall or a silicide barrier (SAB). In the present embodiment, the sidewall silicon nitride 14 is, for example, a gate sidewall. In other embodiments, the sidewall silicon nitride 14 is a silicide barrier (SAB). As shown in FIG. 1A, the gate 13 is cut into multiple segments in the gate extension direction, and a gate isolation structure 15 is formed between adjacent segments of the gate 13. The gate isolation structure 15 has a height that is substantially the same as that of the gate 13, and the gate isolation structure 15 is made of silicon nitride. Thus, the gate isolation structure 15 can be etched when the sidewall silicon nitride 14 is etched back. Figure 6 As shown in FIG. 1A, the gate 13 is cut into multiple segments in the gate extension direction, and a gate isolation structure 15 is formed between adjacent segments of the gate 13. The gate isolation structure 15 has a height that is substantially the same as that of the gate 13, and the gate isolation structure 15 is made of silicon nitride. Thus, the gate isolation structure 15 can be etched when the sidewall silicon nitride 14 is etched back.

[0049] Please refer to Figure 5 and Figure 6 , water vapor 16 is introduced to cover the top of the gate 13, the sidewall silicon nitride 14, the top of the gate isolation structure 15, and the surface of the substrate 10 exposed between the gates 13 in the gate width direction. The water vapor 16 fills the trench formed between the gates 13 in the gate width direction due to the height of the gate 13 being higher than that of the substrate 10. The water vapor 16 can be introduced by a wet process. Specifically, the wet process includes a dipping process or a spraying process.

[0050] As shown in FIG. 1A, the gate 13 is cut into multiple segments in the gate extension direction, and a gate isolation structure 15 is formed between adjacent segments of the gate 13. The gate isolation structure 15 has a height that is substantially the same as that of the gate 13, and the gate isolation structure 15 is made of silicon nitride. Thus, the gate isolation structure 15 can be etched when the sidewall silicon nitride 14 is etched back. Figure 7 and Figure 8As shown, some moisture 16 is removed to expose the top of the gate 13 and the top of the gate isolation structure 15, while retaining moisture on the sidewall silicon nitride 14 and the substrate 10 adjacent to the gate 13 in the width direction. A non-rotating planar drying process can be used to remove some of the moisture 16. The process temperature of the non-rotating planar drying process is 10°C to 100°C, and the process time is 10 seconds to 180 seconds. The process gas for the non-rotating planar drying process is nitrogen, and the nitrogen flow rate is 20 liters / minute to 150 liters / minute. The nitrogen is blown in vertically, for example, to remove moisture only from the top of the gate 13 and the top of the gate isolation structure 15.

[0051] like Figure 9 and Figure 10 As shown, a self-aligned protective layer 17 is formed, located on top of the gate 13 and the gate isolation structure 15. The protective layer 17 is formed using a SACVD (Sub-Atmospheric Chemical Vapor Deposition) or HARP (High Aspect Ratio Process) self-aligned process. The gases in the SACVD or HARP process include ozone and TEOS. TEOS is hydrophobic, and a hydrophobic precursor is formed in the SACVD or HARP process. Due to the hydrophobic nature of the TEOS precursor and the formed hydrophobic precursor, TEOS cannot be effectively adsorbed in the trench containing water vapor to form silicon oxide. Therefore, the protective layer 17 can only be formed on top of the gate 13 and the gate isolation structure 15. The material of the protective layer 17 is silicon oxide.

[0052] An experiment was also conducted to investigate the effect of water vapor retention in the trenches between transistors, specifically the influence of water vapor retention in the trenches between adjacent gates 13 along the width direction on silicon oxide formation. The experiment was divided into three groups: the first group had no water vapor in the trenches, the second group had a small amount of water vapor in the trenches, and the third group had a sufficient amount of water vapor in the trenches. The results showed that the trenches in the first group were filled with silicon oxide, the trenches in the second group had partial silicon oxide formation, and the trenches in the third group did not form silicon oxide. The results indicate that by introducing water vapor, and utilizing the hydrophobicity of the precursor TEOS and the formed hydrophobic precursor, TEOS cannot be effectively adsorbed in the trenches containing water vapor to form silicon oxide.

[0053] like Figure 11 As shown, after the protective layer 17 is formed and before the re-etching process, a high-temperature baking process is used to remove the remaining moisture 16.

[0054] like Figure 12 As shown, during the etch-back process, the protective layer 17 protects the gate isolation structure 15 from etching, and only a portion of the sidewall silicon nitride 14 is etched, so that the trenches between adjacent gates 13 in the gate width direction meet a preset aspect ratio. The trenches between adjacent gates 13 meet the preset aspect ratio to avoid voids during subsequent ILD dielectric layer filling. The preset aspect ratio requirement for the trenches is set by those skilled in the art based on the ILD deposition process, and this embodiment does not limit this. The etch-back process is, for example, dry etching. This embodiment utilizes the principle of hydrophobicity, introducing water vapor and removing some of it, retaining water vapor in the trenches, ensuring no water vapor on the top of the gate isolation structure 15, and self-aligning to form the protective layer 17 on the top of the gates 13 and the top of the gate isolation structure 15. In the etch-back process, the protective layer 17 protects the top of the gate isolation structure 15 from etching, and only the sidewall silicon nitride 14 is etched, ensuring that the trenches between adjacent gates 13 in the gate width direction meet the preset aspect ratio. This embodiment can form a local protective layer 17 and etch part of the sidewall silicon nitride 14 in a specific area without using photolithography, thus avoiding the problem of a short circuit caused by a depression forming on the top of the gate isolation structure 15.

[0055] like Figure 13 and Figure 14 As shown, in some embodiments, if the aspect ratio of the trench between adjacent gates 13 in the width direction of gate 13 is taken into account, after the etch-back process, the protective layer 17 on the top of the gate 13 and the top of the gate isolation structure 15 is removed.

[0056] In some embodiments, if the aspect ratio of the trench between adjacent gates 13 in the width direction of gate 13 is not considered, the protective layer 17 does not need to be removed. This is because the material of the subsequently formed ILD dielectric layer is the same as that of the protective layer 17, and the filling height of the ILD dielectric layer is also higher than the top of the gate 13. Then, a chemical mechanical polishing process is performed to polish to the top of the gate 13.

[0057] like Figure 13 and Figure 14As shown, the embodiment also provides a semiconductor structure prepared by the forming method of the semiconductor structure according to any one of the above embodiments, which comprises a substrate 10, wherein a well region 12 is formed in the substrate 10, a shallow trench isolation structure 11 is formed between adjacent well regions 12, and the shallow trench isolation structure 11 is used to isolate the adjacent well regions 12. A gate 13 is formed on the well region 12, and a sidewall nitride 14 is further formed on the sidewall of the gate 13. The sidewall nitride 14 is, for example, a side wall of the gate or a silicide barrier layer. The gate 13 is cut into multiple segments in the gate extension direction, and a gate isolation structure 15 is formed between adjacent segments of the gate 13, the gate isolation structure 15 has the same height as the gate 13, and the material of the gate isolation structure 15 is also nitride. The depth-width ratio of the trench between adjacent gates 13 in the gate width direction meets the preset requirement, and the preset requirement of the depth-width ratio of the trench is set by a person skilled in the art according to the ILD deposition process, which is not limited in the embodiment.

[0058] As can be seen from the above, in the forming method of the semiconductor structure provided by the embodiment, the substrate is formed with a gate and a sidewall nitride covering the gate, the gate is cut into multiple segments in the gate extension direction, and a gate isolation structure is formed between adjacent segments of the gate; then water vapor is introduced, the water vapor covers the top of the gate, the sidewall nitride, the top of the gate isolation structure and the surface of the substrate exposed; then part of the water vapor is removed to expose the top of the gate and the top of the gate isolation structure, and the water vapor on the sidewall nitride and the substrate is retained; then a protection layer is formed by a self-alignment process, the protection layer is located on the top of the gate and the top of the gate isolation structure; and then a back etching process is performed to etch part of the sidewall nitride, so that the trench between adjacent gates in the gate width direction meets the preset depth-width ratio, and the protection layer is used to protect the top of the gate isolation structure in the back etching process. The unexpected effect of the present application is that, by first introducing water vapor and then removing part of the water vapor to expose the top of the gate and the top of the gate isolation structure, and retaining the water vapor on the sidewall nitride and the substrate, and then using the hydrophobic principle to form a protection layer on the top of the gate and the top of the gate isolation structure by a self-alignment process. In the back etching process, the protection layer protects the top of the gate isolation structure from being etched, and only the sidewall nitride of the gate is etched, so that the trench between adjacent gates in the gate width direction meets the preset depth-width ratio. Without using a photolithography process, the forming of a local protection layer and the etching of part of the sidewall nitride can be realized in a specific area, and the problem of recessing of the top of the gate isolation structure and causing short circuit is avoided.

[0059] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other, and the different parts of each embodiment can also be used with each other. The present application is not limited in this regard.

[0060] It should also be appreciated that, although the present application has been disclosed in the context of preferred embodiments, the embodiments disclosed are not intended to limit the present application. Any modifications of the above-described embodiments made by one skilled in the art to adapt the present application for use in other aspects are considered within the scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate and a sidewall silicon nitride covering the gate are formed. The gate is cut into multiple segments in the gate extension direction, and a gate isolation structure is formed between adjacent segments of the gate. Moisture is introduced to cover the top of the gate, the sidewall silicon nitride, the top of the gate isolation structure, and the exposed surface of the substrate, wherein the moisture is introduced using a wet process, which includes an immersion process or a spray process. Some moisture is removed to expose the top of the gate and the top of the gate isolation structure, while retaining moisture on the sidewall silicon nitride and the substrate, wherein a non-rotational planar drying process is used to remove some of the moisture; A protective layer is formed using a self-aligned process, the protective layer being located on top of the gate and on top of the gate isolation structure. The self-aligned process is either SACVD or HARP, the gas in the SACVD or HARP process includes ozone and TEOS, the TEOS being hydrophobic, and a hydrophobic precursor is formed in the SACVD or HARP process to ensure that the protective layer is formed only on top of the gate and on top of the gate isolation structure. A reverse etching process is performed to etch a portion of the sidewall silicon nitride so that the trenches between adjacent gates in the gate width direction meet a preset aspect ratio, wherein the protective layer is used to protect the gate isolation structure during the reverse etching process.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The process temperature of the non-rotating flat drying process is 10℃ to 100℃, the process time is 10 seconds to 180 seconds, the process gas is nitrogen, and the flow rate of the nitrogen is 20 liters / minute to 150 liters / minute.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, After the protective layer is formed and before the etching process, a high-temperature baking process is used to remove the remaining moisture.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The sidewall silicon nitride on the gate is either a sidewall of the gate or a silicide barrier layer.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, After the etch-back process, the protective layer on top of the gate and on top of the gate isolation structure is removed.

6. A semiconductor structure, characterized in that, It is prepared by the semiconductor structure formation method as described in any one of claims 1 to 5.

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