Semiconductor devices and their manufacturing methods

Abstract

This application discloses a semiconductor device and a method for manufacturing the same, comprising: detecting a height difference between the gate structures of a first device and a second device; sequentially depositing a polysilicon layer and a sacrificial layer on the surface of the semiconductor structure; thinning the sacrificial layer to expose the upper surface of the polysilicon layer on the gate structure of the second device; etching back the polysilicon layer above the gate structure in the second device, the etching back distance being the height difference; removing the sacrificial layer; and oxidizing the remaining polysilicon layer. The semiconductor device and manufacturing method provided in this application reduce the gate height difference between the first device and the second device by compensating for the gate height of the first device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In the field of semiconductor integrated circuit manufacturing, especially in the fabrication of P-type MOS (PMOS) devices in Complementary Metal Oxide Semiconductor (CMOS), the formation of the silicon-germanium structure is a crucial step. During this process, the problem of exposed PMOS dummy gates is particularly prominent.

[0003] like Figure 1 As shown, substrate 110 is divided into a first region and a second region. A first device (PMOS) is formed in the first region, and a second device (NMOS) is formed in the second region. The first device includes a germanium-silicon structure 150, a dummy gate structure 140, and an isolation structure 120. The second device includes the dummy gate structure 140 and the isolation structure 120. Because the SiO2 film 130 on the PMOS dummy gate thins after the etching process, the overall height of the PMOS dummy gate is lower than that of the NMOS dummy gate. This height difference will cause a series of problems during the subsequent chemical mechanical polishing (CMP) process. Specifically, the first hard mask layer on the PMOS gate may remain after CMP, such as... Figure 2a and Figure 2b As shown, these residues affect the electrical characteristics of subsequent devices, thereby affecting the performance and reliability of the devices.

[0004] In addition, residue removal during the CMP process is also a technical challenge, as the presence of residues can seriously affect the electrical properties and manufacturing process of semiconductor devices, especially the downstream metal interconnect process.

[0005] Therefore, in order to improve the stability and reliability of semiconductor devices, it is necessary to improve existing processes to reduce a series of problems caused by the inconsistency in gate height between PMOS and NMOS devices. Summary of the Invention

[0006] In view of the above problems, this application provides a semiconductor device and a method for manufacturing the same, which reduces the difference in gate height between the first device and the second device by compensating for the gate height of the first device.

[0007] According to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor structure, the semiconductor structure including a substrate and a gate structure, the substrate including a first region for forming at least one first device and a second region for forming at least one second device, the height of the gate structure of the first device being less than the height of the gate structure of the second device; detecting a height difference between the gate structures of the first device and the second device; sequentially depositing a polysilicon layer and a sacrificial layer on the surface of the semiconductor structure; thinning the sacrificial layer to expose the upper surface of the polysilicon layer on the gate structure of the second device; etching back the polysilicon layer above the gate structure in the second device to a distance equal to the height difference; removing the sacrificial layer and oxidizing the remaining polysilicon layer.

[0008] Optionally, the height difference of the gate structures of the first device and the second device can be measured using a scanning electron microscope and / or an optical profilometer.

[0009] Optionally, the thickness of the polycrystalline silicon layer is equal to the height difference.

[0010] Optionally, in the step of sequentially depositing a polysilicon layer and a sacrificial layer on the surface of the semiconductor structure, the step of depositing the sacrificial layer includes: depositing a first sacrificial layer using a chemical vapor deposition method or a physical vapor deposition method, wherein the first sacrificial layer fills the groove between adjacent gate structures; and depositing a second sacrificial layer on the first sacrificial layer using a spin coating method, wherein the sacrificial layer includes the first sacrificial layer and the second sacrificial layer.

[0011] Optionally, the sacrificial layer may be thinned using a chemical mechanical polishing process.

[0012] Optionally, the polysilicon layer above the gate structure in the second device may be etched back.

[0013] Optionally, the step of removing the sacrificial layer may employ a wet etching process with a high selectivity.

[0014] Optionally, in the step of oxidizing the remaining polycrystalline silicon layer, a process such as a diffusion furnace tube or a rapid thermal process is used to oxidize the polycrystalline silicon layer into a silicon dioxide layer.

[0015] Optionally, the first device is either an NMOS or a PMOS, and the second device is either an NMOS or a PMOS.

[0016] According to another aspect of the present invention, a semiconductor device is provided, wherein the semiconductor device is manufactured by the semiconductor device manufacturing method described above, and the gate structures of the first device and the second device are at the same height.

[0017] The unexpected technical effect of this application is:

[0018] According to the semiconductor device and manufacturing method of the present application, after a height difference occurs between the gate structure of the first device and the gate structure of the second device, a polysilicon layer is formed on the gate of the first device with a lower height, and then the polysilicon layer is oxidized to form a silicon dioxide layer, thereby compensating for the gate height of the first device and reducing the height difference between the gate structures of the first device and the second device.

[0019] Furthermore, during the compensation process, after obtaining the height difference between the gate structure of the first device and the gate structure of the second device, a polysilicon layer and a sacrificial layer are deposited sequentially. The polysilicon layer on the surface of the gate structure of the second device is exposed by chemical mechanical polishing. The gate structure of the second device is etched back using the sacrificial layer as a mask layer. The etched back height is, for example, the difference value. After removing the sacrificial layer, the polysilicon layer is oxidized. This yields a first device and a second device with consistent gate structure heights, thereby reducing the device yield and reliability issues caused by the gate height difference between the first device and the second device. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 A structural diagram of a semiconductor device with a height difference in the gate structure in the prior art is shown;

[0022] Figure 2a and Figure 2b Electron micrographs of the gate structures of the first and second devices in a semiconductor device with a height difference in the gate structure in the prior art are shown.

[0023] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0024] Figures 4a to 4h Cross-sectional views of each stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention are shown. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0027] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0028] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the terms “and / or” include any and all combinations of the associated listed items.

[0029] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0030] This application provides a semiconductor structure and a method for manufacturing the same, which compensates for the height of the gate structure of the first device when the gate structure heights of the first device and the second device are inconsistent, thereby improving the performance of the semiconductor structure.

[0031] This application may be presented in various forms, some of which will be described below.

[0032] Figure 3A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figures 4a to 4h Cross-sectional views of each stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention are shown.

[0033] The manufacturing process of semiconductor devices begins with the formation of semiconductor structures, such as... Figure 4a As shown, the semiconductor structure includes a substrate 210, an isolation structure 220 located in the substrate 210, a germanium-silicon structure 221, and a gate structure 240 located on the substrate 210.

[0034] The substrate 210 includes a first region and a second region distributed along a first direction. The first region is used to form at least one first device, and the second region is used to form at least one second device. Specifically, the first device is either an NMOS or a PMOS, and the second device is either an NMOS or a PMOS. In embodiments of this application, the first device is, for example, a PMOS device, and the second device is, for example, an NMOS device. Figure 4a Only one embodiment with a first device and a second device is shown.

[0035] An isolation structure 220 is located in the substrate 210 at the boundary between the first and second regions, and is used to isolate the first device and the second device. The dimension of the isolation structure 220 in the substrate along the third direction is larger than the dimensions of the first and second devices in the substrate along the second direction. The isolation structure 220 is, for example, a shallow trench isolation structure (STI). The first direction, the second direction, and the third direction are mutually perpendicular, for example, represented by the X-axis, Y-axis, and Z-axis, respectively.

[0036] The gate structure 240, from bottom to top, includes: a first dielectric layer 241, an interface layer 242, a high-k dielectric layer 243, a gate conductor 245, an etch stop layer 246, and the first dielectric layer 241 and the first sidewall 244 surrounding the gate structure 240. Specifically, the first dielectric layer 241 includes multiple portions, including a first portion located between the interface layer 242 and the substrate 210, a second portion surrounding the side surface and top surface of the interface layer 242, the high-k dielectric layer 243, the gate conductor 245, and the etch stop layer 246, a third portion located outside the first sidewall 244, and a fourth portion located on the surface of the substrate 210. The first sidewall 244 is surrounded by the second and third portions of the first dielectric layer 241.

[0037] What is known is that Figure 4a The semiconductor structure shown has been formed after several steps, and the first dielectric layer 241 has also been formed after multiple depositions of dielectric material. However, for ease of description, the dielectric layers formed by multiple depositions are uniformly referred to as the first dielectric layer 241 in this application.

[0038] In addition, although Figure 4a Although not shown, it is understood that active regions, drain regions, bulk regions, contact regions, etc. are also formed in the substrate 210.

[0039] In this semiconductor structure, the material of the first dielectric layer 241 is, for example, silicon dioxide (SiO2), and the first dielectric layer 241 serves as an insulating layer; the material of the interface layer 242 is, for example, silicon oxynitride (SiON), and the interface layer 242 helps to reduce interface defects and carrier scattering; the material of the high-k dielectric layer 243 is, for example, hafnium dioxide (HfO2) and / or zirconium dioxide (ZrO2), used to reduce gate leakage current and increase the physical thickness of the first portion of the first dielectric layer 241, thereby reducing the direct tunneling effect; the material of the gate conductor 245 is, for example, polysilicon (Poly Si); and the materials of the etch stop layer 246 and the first sidewall 244 are, for example, silicon nitride (SiN).

[0040] exist Figure 4a In the semiconductor structure shown, it can be clearly seen that the thickness of the first dielectric layer 241 on the top surface of the gate structure 240 in the first device is less than the thickness of the first dielectric layer 241 on the top surface of the gate structure 240 in the second device. This will result in the upper surface height of the gate structure in the first device and the second device being inconsistent after chemical polishing, which will affect the performance and yield of the device.

[0041] The following will combine Figure 3 , Figures 4a to 4h The method for manufacturing the semiconductor device of this application is described in detail.

[0042] Step S201: Detect the height difference between the gate structures of the first device and the second device, and deposit a polysilicon layer on the surface of the semiconductor structure.

[0043] In this step, such as Figure 4a As shown, the height difference D1 of the gate structures of the first device and the second device is measured by methods such as scanning electron microscopy (SEM) and / or optical profilometry. For example, the height of the gate structure of the first device is smaller than the height of the gate structure of the second device. This height difference has a certain error range, but is within the error tolerance.

[0044] Then, refer to Figure 4b A polysilicon layer 230 is deposited on the surface of a semiconductor structure using deposition processes such as physical vapor deposition and chemical vapor deposition. The polysilicon layer 230 covers the surface of the gate structure 240 and the surface of the first dielectric layer 241 on the substrate 210.

[0045] In a subsequent step, the polysilicon layer 230 is oxidized to compensate for the height of the gate structure of the first device. Therefore, the thickness of the polysilicon layer 230 is the height to be compensated for in the gate structure of the first device, and this thickness can be greater than or less than the height difference D1. Preferably, the thickness of the polysilicon layer 230 is the height difference D1.

[0046] Step S202: Form a sacrificial layer on the polysilicon layer and thin the sacrificial layer down to the surface of the polysilicon layer on the gate structure of the second device.

[0047] In this step, such as Figure 4c As shown, a first sacrificial layer is deposited on the upper surface of the polysilicon layer 230 using deposition processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). Then, a second sacrificial layer is deposited on the first sacrificial layer using spin coating. The first sacrificial layer is primarily used to quickly fill the grooves between adjacent gate structures 240, while the second sacrificial layer utilizes the flow characteristics of spin coating to ensure a flush surface. For ease of description, both the first and second sacrificial layers are collectively referred to as sacrificial layer 250.

[0048] Furthermore, such as Figure 4d As shown, the sacrificial layer 250 is thinned using a chemical mechanical polishing (CMP) process until the surface of the polysilicon layer 230 on the gate structure 240 in the second device is exposed.

[0049] Step S203: Etch back the polysilicon layer above the gate structure in the second device to reduce the height difference of the gate structure in the second device.

[0050] In this step, such as Figure 4e As shown, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor phase etching, is used to etch back the polysilicon layer 230 above the gate structure 240 of the first device through the sacrificial layer 250. The height of the back etching is the height difference D1 between the gate structures of the first device and the second device obtained in the aforementioned steps.

[0051] In the etch-back process, the polysilicon layer 230 is first etched back. If the thickness of the polysilicon layer 230 is greater than the height difference D1, then some polysilicon layer 230 on the gate structure 240 of the first device will remain after the etch-back process. If the thickness of the polysilicon layer 230 is less than or equal to the height difference D1, then the polysilicon layer 230 on the gate structure 240 of the first device will be completely etched back, and the first dielectric layer 241 above the gate structure 240 will also be partially etched back, so that the etch-back height satisfies the height difference D1.

[0052] During the etching process, if dry etching is used, the energy and incident angle of the laser beam or ion beam can be controlled according to the density of the material being etched, so as to adjust the etching rate and obtain the required etching height. If wet etching or vapor phase etching is used, the concentration of etching material in the etching solution or etching gas can be controlled according to the density and etching selectivity of the material being etched, so as to adjust the etching rate and obtain the required etching height.

[0053] Step S204: Remove the sacrificial layer and oxidize the remaining polysilicon layer.

[0054] In this step, such as Figure 4f As shown, the sacrificial layer 250 is removed using an etching process, such as dry etching, including ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor phase etching. Specifically, for example, a wet etching process with a high selectivity can be used to remove the sacrificial layer 250.

[0055] At this time, since a portion of the polysilicon layer 230 above the gate structure 240 of the second device is removed, the height of the gate structure 240 and the polysilicon layer 230 in the first device is basically the same as the height of the gate structure 240 in the second device.

[0056] Furthermore, the polysilicon layer 230 is oxidized using processes such as diffusion furnace tubes or rapid thermal processing (RTP), turning it into silicon dioxide (SiO2), which becomes part of the first dielectric layer 241 in the gate structure 240, thus compensating for the thickness of the first dielectric layer 241 in the first device. Simultaneously, since the height of the gate structure 240 and the polysilicon layer 230 in the first device before oxidation is essentially the same as the height of the gate structure 240 in the second device, the heights of the gate structures 240 in the first and second devices are consistent after the first dielectric layer 241 is compensated. Figure 4g As shown.

[0057] Step S205: The second sidewall, the second medium layer, the third sidewall, and the third medium layer are formed sequentially.

[0058] In this step, refer to Figure 4h A deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit a second sidewall 261, a second dielectric layer 262, a third sidewall 263, and a third dielectric layer 264 sequentially on a first device and a second device having a highly consistent gate structure.

[0059] In the process of forming the sidewalls, sidewall material needs to be deposited first, and then the sidewall material is etched back to retain only the sidewall material located on the side of the gate structure 240. Furthermore, during the multiple material layer deposition process, the final dielectric layer fills the grooves between adjacent gate structures 240.

[0060] In addition, this application also provides a semiconductor device formed using the manufacturing method described above, wherein the gate structures of the first device and the second device are at the same height.

[0061] According to the semiconductor device and manufacturing method of the present application, after a height difference occurs between the gate structure of the first device and the gate structure of the second device, a polysilicon layer is formed on the gate of the first device with a lower height, and then the polysilicon layer is oxidized to form a silicon dioxide layer, thereby compensating for the gate height of the first device and reducing the height difference between the gate structures of the first device and the second device.

[0062] Furthermore, during the compensation process, after obtaining the height difference between the gate structure of the first device and the gate structure of the second device, a polysilicon layer and a sacrificial layer are deposited sequentially. The polysilicon layer on the surface of the gate structure of the second device is exposed by chemical mechanical polishing. The gate structure of the second device is etched back using the sacrificial layer as a mask layer. The etched back height is, for example, the difference value. After removing the sacrificial layer, the polysilicon layer is oxidized. This yields a first device and a second device with consistent gate structure heights, thereby reducing the device yield and reliability issues caused by the gate height difference between the first device and the second device.

[0063] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure comprising a substrate and gate structures, the substrate comprising a first region for forming at least one first device and a second region for forming at least one second device, a height of the gate structure of the first device being less than a height of the gate structure of the second device; detecting a height difference between the gate structures of the first device and the second device; sequentially depositing a polysilicon layer and a sacrificial layer on a surface of the semiconductor structure; thinning the sacrificial layer to expose an upper surface of the polysilicon layer on the gate structure of the second device; etching back the polysilicon layer above the gate structure in the second device by a distance of the height difference; removing the sacrificial layer and oxidizing the remaining polysilicon layer. The height difference of the gate structures of the first device and the second device is measured by a scanning electron microscope and / or an optical profiler. The thickness of the polysilicon layer is equal to the height difference. In the step of sequentially depositing a polysilicon layer and a sacrificial layer on a surface of the semiconductor structure, the step of depositing the sacrificial layer comprises: depositing a first sacrificial layer by a chemical vapor deposition method or a physical vapor deposition method, the first sacrificial layer filling a groove between adjacent gate structures; depositing a second sacrificial layer on the first sacrificial layer by a spin coating method. The sacrificial layer comprises the first sacrificial layer and the second sacrificial layer. The sacrificial layer is thinned by a chemical mechanical polishing process. The polysilicon layer above the gate structure in the second device is etched back.

2. The manufacturing method according to claim 1, wherein, In the step of removing the sacrificial layer, a wet etching process with a high selectivity ratio is used.

3. The manufacturing method according to claim 2, wherein, In the step of oxidizing the remaining polysilicon layer, the polysilicon layer is oxidized into a silicon dioxide layer by a diffusion furnace tube or a rapid thermal process.

4. The manufacturing method according to claim 3, wherein, The first device is one of an NMOS or a PMOS, and the second device is the other of the NMOS or the PMOS. The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, and in the semiconductor device, the heights of the gate structures of the first device and the second device are consistent. ​ ​ 5. The manufacturing method according to claim 2, wherein, ​ 6. The manufacturing method according to claim 5, wherein, ​ 7. The production method according to claim 1, wherein ​ 8. The manufacturing method according to claim 7, wherein ​ 9. The production method according to claim 1, wherein ​ 10. A semiconductor device, wherein, ​

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