Manufacturing method of backside illuminated image sensor and backside illuminated image sensor

Abstract

The embodiment of the invention discloses a manufacturing method of a back-illuminated image sensor and the back-illuminated image sensor, and the method comprises the steps: providing a device wafer which comprises a functional region and a welding pad region, and exposing a welding pad from a welding pad window at the back surface of the device wafer in the welding pad region; sequentially depositing a first dielectric layer and an etching stop layer on the back surface of the device wafer, wherein the first dielectric layer and the etching stop layer cover the back surface of the device wafer and the side wall and the bottom of the welding pad window; patterning to remove the etching stop layer in the welding pad area; depositing a second dielectric layer on the back surface of the device wafer, wherein the second dielectric layer covers the back surface of the device wafer and overfills the welding pad window; patterning to remove the second dielectric layer in the functional region based on the reserved etching stop layer; and after the etching stop layer is removed through ashing, chemical mechanical grinding is carried out on the welding pad area so as to flatten the back surface of the device wafer. According to the embodiment of the invention, the generation probability of edge cracks of the welding pad in the chemical mechanical polishing process is reduced, so that the device yield and reliability are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a back-illuminated image sensor and the back-illuminated image sensor itself. Background Technology

[0002] Back-illuminated (BSI) image sensors, by placing photodiodes on top of metal interconnect layers, significantly improve the photoelectric conversion efficiency of pixels and have become the mainstream structure for high-pixel-density imaging chips. In a typical BSI image sensor manufacturing process, after the pixel array, multilayer metal interconnects, and top-layer pads (e.g., aluminum pads, AlPADs) are completed on the front side of the device wafer, it needs to be bonded to a blank carrier wafer. Subsequently, the back side of the device wafer is thinned and deep-hole etched to expose the pads, forming pad windows, followed by deep-hole filling and chemical mechanical polishing (CMP). However, with the reduction in pixel size and the increase in the aspect ratio of the pad windows, the pad area after deep-hole etching on the back side of the device wafer forms a steep step approaching 90°. Subsequently, a dielectric layer (e.g., oxide) is used to backfill the deep holes on the back side in one step, followed by surface planarization. Surface planarization is performed in two steps: first, a large area of ​​the dielectric layer in the functional area (also known as the pixel array area) outside the pad area is removed using an etching process; then, the entire back side of the device wafer is planarized using a CMP process. However, over-etching can occur when etching the dielectric layer of functional areas, resulting in sharp corners near steep steps. Stress is highly concentrated at these corners, making CMP processes highly susceptible to inducing pad cracks. These cracks not only propagate further in subsequent high-temperature processes, leading to pad peeling or even open circuits, but also cause probe contact failure during the WAT (Wafer Acceptance Test) stage, reducing product yield and reliability. Summary of the Invention

[0003] In view of the above problems, the purpose of this application is to provide a method for manufacturing a back-illuminated image sensor and a back-illuminated image sensor, which aims to achieve global planarization of the back side of the device wafer without increasing the number of photomask layers, effectively eliminate stress concentration at the sharp corners of the pad area, reduce the probability of pad cracks during chemical mechanical polishing, and thus improve device yield and reliability.

[0004] According to a first aspect of the embodiments of this application, a method for manufacturing a back-illuminated image sensor is provided, comprising:

[0005] A device wafer is provided, the device wafer including a functional region and a pad region, wherein a pad window on the back side of the device wafer exposes the pad in the pad region;

[0006] A first dielectric layer and an etch stop layer are sequentially deposited on the back side of the device wafer, the first dielectric layer and the etch stop layer covering the back side of the device wafer and the sidewalls and bottom of the pad window;

[0007] Graphically remove the etch stop layer in the pad region;

[0008] A second dielectric layer is deposited on the back side of the device wafer, the second dielectric layer covering the back side of the device wafer and overfilling the pad window;

[0009] Based on the retained etch stop layer, the second dielectric layer of the functional region is graphically removed;

[0010] After the etch stop layer is removed by ashing, the pad area is chemically and mechanically polished to planarize the back side of the device wafer.

[0011] Optionally, a pixel array and a metal interconnect structure are stacked sequentially on the front side of the device wafer, the metal interconnect structure covers the pixel array, and the metal interconnect structure in the pad area outside the functional area has the pads disposed on the topmost layer near the back side of the device wafer.

[0012] Optionally, before sequentially depositing a first dielectric layer and an etch stop layer on the back side of the device wafer, the manufacturing method further includes:

[0013] Deposit a bonding layer on the surface of the carrier wafer;

[0014] The carrier wafer and the front side of the device wafer are bonded together through the bonding layer to form a composite wafer;

[0015] The composite wafer is flipped over to thin the back side of the device wafer;

[0016] The backside stack of the device wafer is etched in the pad area to form the pad window.

[0017] Optionally, the graphical removal of the etch stop layer in the pad region includes:

[0018] Photoresist is applied over the etch stop layer on the back side of the device wafer, and exposed and developed to form openings in the photoresist corresponding to the pad regions;

[0019] The photoresist is used as a mask to etch the etch stop layer, retaining only the etch stop layer of the functional area. The etch stop layer directly above the pad area is removed and the etching stops at the first dielectric layer.

[0020] Optionally, the graphical removal of the second dielectric layer of the functional region based on the retained etch stop layer includes:

[0021] Photoresist is coated over the second dielectric layer on the back side of the device wafer, exposed and developed to form an opening in the photoresist corresponding to the functional region;

[0022] Using the photoresist as a mask, the second dielectric layer of the functional area is etched, and the etching stops on the surface of the etching stop layer.

[0023] Optionally, after the ashing process removes the etch stop layer, the pad area is chemically and mechanically polished to planarize the back side of the device wafer, including:

[0024] Ashing removes the etching stop layer in the functional area;

[0025] The second dielectric layer in the pad region is subjected to chemical mechanical polishing, wherein the endpoint of chemical mechanical polishing is detected in real time based on the first dielectric layer of the functional region.

[0026] Optionally, the orthographic projection of the pad region overlaps with the orthographic projection of the pad window.

[0027] Optionally, after flipping the composite wafer and thinning the back side of the device wafer, the manufacturing method further includes:

[0028] A grid structure is formed in the area between pixels on the back side of the device wafer.

[0029] Optionally, the material of the etch stop layer includes amorphous carbon.

[0030] According to a second aspect of the embodiments of this application, a back-illuminated image sensor is provided, manufactured according to the aforementioned manufacturing method.

[0031] The unexpected technical effect of this application is:

[0032] After patterning the removal of the etch stop layer in the pad region, a partitioned structure is formed on the back side of the device wafer. The etch stop layer in the retained functional region not only serves as an end marker for the subsequent second dielectric layer etching, preventing over-etching of the functional region dielectric layer and thus avoiding sharp corners near the steep steps of the pad window, but also forms a virtual polishing stop layer (i.e., the first dielectric layer of the functional region on the back side of the device wafer) in the CMP process of the pad region, preventing pad edge cracks caused by the CMP process. Through the dual functional integration of the etch stop layer, global planarization of the back side of the device wafer is achieved without increasing the number of photomask layers. This effectively eliminates stress concentration at the sharp corners of the pad edges in the pad region, reduces the probability of pad edge cracks during chemical mechanical polishing, and thus improves device yield and reliability. Attached Figure Description

[0033] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1A The diagram illustrates how over-etching of the dielectric layer in the functional area in related technologies can lead to sharp corners near steep steps in the solder pad region.

[0035] Figure 1B The diagram illustrates how over-etching of the dielectric layer in the functional area in related technologies can lead to sharp corners near steep steps in the solder pad region.

[0036] Figure 1C The diagram shows a schematic of cracks at the edge of the solder pad caused by the dielectric layer in the solder pad region during chemical mechanical polishing in related technologies.

[0037] Figure 1D The diagram shows a schematic of cracks at the edge of the solder pad caused by the dielectric layer in the solder pad region during chemical mechanical polishing in related technologies.

[0038] Figure 1E The diagram shows a schematic of cracks at the edge of the solder pad caused by the dielectric layer in the solder pad region during chemical mechanical polishing in related technologies.

[0039] Figure 1F The diagram shows the location of a device with pad edge cracks in a whole device wafer in the related technology;

[0040] Figure 2 The diagram shown is a schematic flowchart of an exemplary method for manufacturing a back-illuminated image sensor according to an embodiment of this application.

[0041] Figures 3A to 3I The diagram shows cross-sectional views of different stages of an exemplary back-illuminated image sensor manufacturing method according to an embodiment of this application.

[0042] Figure 4A The diagram shown is a schematic diagram of the edge of the pad after the dielectric layer in the chemical mechanical polishing of the pad region according to an embodiment of this application;

[0043] Figure 4B The diagram shows the location of a device with a pad edge crack in a whole device wafer according to an embodiment of this application.

[0044] Figure reference numerals: 100 - First back-illuminated image sensor; 110 - First carrier wafer; 120 - First bonding layer; 130 - First device wafer; 140 - First functional area; 150 - First pad area; 131 - First metal interconnect structure; 132 - First support dielectric layer; 133 - First interconnect metal line; 134 - First pad; 135 - First pixel array layer; 136 - First grid structure layer; 137 - Through-fill dielectric layer; 138 - Sharp corner; 139 - Crack; 300 - Second back-illuminated sensor Image sensor; 310-Second carrier wafer; 320-Second bonding layer; 330-Second device wafer; 340-Second functional region; 350-Second pad region; 331-Second metal interconnect structure; 332-Second support dielectric layer; 333-Second interconnect metal line; 334-Second pad; 335-Second pixel array layer; 336-Second grid structure layer; 337-Pad window; 338-First dielectric layer; 339-Etch stop layer; 361-Photoresist; 362-Second dielectric layer. Detailed Implementation

[0045] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0046] This application may be presented in various forms, some of which will be described below.

[0047] Figure 1A and Figure 1B The diagram illustrates how over-etching of the dielectric layer in the functional region in related technologies can lead to sharp corners near steep steps in the solder pad area. For example... Figure 1AAs shown, the first back-illuminated image sensor 100 includes a first device wafer 130 and a first carrier wafer 110, which are bonded together by a first bonding layer 120. A pixel array and a first metal interconnect structure 131 are sequentially stacked on the front side of the first device wafer 130. The first metal interconnect structure 131 includes a first supporting dielectric layer 132 and first interconnect metal lines 133 embedded in the first supporting dielectric layer. The first supporting dielectric layer 132 supports and protects the first interconnect metal lines 133 and prepares for subsequent bonding. The material of the first supporting dielectric layer 132 is, for example, silicon oxide or other low dielectric material layers, and the first supporting dielectric layer 132 can be formed by processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The first interconnect metal lines 133 can be made of metal materials with low resistance, such as aluminum (Al), copper (Cu), tungsten (W), etc. The first interconnect metal lines 133 can be formed, for example, using a damascus damascene process. The first metal interconnect structure 131 can also be formed using other suitable conventional processes in the art, which will not be described in detail here.

[0048] The first device wafer 130 includes a first functional region 140 and a first pad region 150 located outside the first functional region 140. A pixel array in the first pixel array layer 135 is located within the first functional region 140. A first metal interconnect structure 131 covers the pixel array. In the first pad region 150, the first metal interconnect structure 131 has a first pad 134 disposed on the topmost layer near the back surface of the first device wafer 130. Pixels in the pixel array can also be referred to as photosensitive regions, which are used to convert light signals into electrical signals. A photosensitive region is, for example, a photodiode, which is a PN junction composed of different types of semiconductor materials. In some embodiments, a first grid structure layer 136 is formed on the back surface of the first device wafer 130. The grid structure corresponds to the region formed between adjacent pixels, and the grid structure helps to isolate individual pixels, reduce optical crosstalk between pixels, and improve image quality. The pixel array and grid structure can adopt structures conventional in the art. In some embodiments, the back surface of the first device wafer 130 is subsequently thinned and deep-hole etched to expose the first pad 134 to form a pad window. As pixel size shrinks and the aspect ratio of the pad window increases, the pad window of the first pad region 150 will form a steep step of nearly 90° after deep hole etching on the back side of the first device wafer 130. Subsequently, a via-filling dielectric layer 137 is deposited on the back side of the first device wafer 130 to complete deep hole filling and perform surface planarization. Surface planarization is performed in two steps: first, a large area of ​​the via-filling dielectric layer 137 in the first functional region 140 outside the first pad region 150 is removed using an etching process; then, the entire back side of the first device wafer 130 is planarized using a CMP process. However, as... Figure 1A and Figure 1BAs shown, over-etching occurs when etching the via-filling dielectric layer 137 of the first functional region 140, resulting in sharp corners 138 near the steep steps of the pad window.

[0049] Figure 1C , Figure 1D and Figure 1E The diagram illustrates how chemical mechanical polishing (CMP) in the solder pad region can cause cracks at the pad edge. Figure 1C , Figure 1D and Figure 1E As shown, the back side of the first device wafer 130 is planarized by CMP process. The stress is highly concentrated at the sharp corner 138. CMP process can easily induce edge cracks 139 on the first pad 134. Figure 1F The diagram illustrates the location of pad edge cracks on a whole-wafer device in related technologies. For example... Figure 1F As shown, the spatial distribution density of edge cracks 139 on the first pad 134 of the entire first device wafer 130 is clearly presented. It is evident that most devices on the entire first device wafer 130 exhibit edge cracks 139 on the first pad 134. These cracks 139 will not only further propagate during subsequent high-temperature processes, leading to the peeling or even open circuit of the first pad 134, but will also cause probe contact failure during the WAT (Wafer Acceptance Test) stage, reducing product yield and reliability.

[0050] Based on this, this application provides a method for manufacturing a back-illuminated image sensor and a back-illuminated image sensor, which achieves global planarization of the back side of the device wafer without increasing the number of photomask layers, effectively eliminates stress concentration at the sharp corners of the pad area, reduces the probability of pad cracks during chemical mechanical polishing, and thus improves device yield and reliability.

[0051] Figure 2 The diagram shown is a schematic flowchart of an exemplary back-illuminated image sensor manufacturing method according to an embodiment of this application. Figures 3A to 3I The diagram shows cross-sectional views of different stages in an exemplary back-illuminated image sensor manufacturing method according to an embodiment of this application. The following is in conjunction with... Figures 3A to 3I Detailed description Figure 2 The method for manufacturing a back-illuminated image sensor is shown. For example... Figure 2 As shown, the manufacturing method includes: In step S210, a device wafer is provided, the device wafer including a functional region and a pad region, wherein a pad window on the back side of the device wafer exposes the pads in the pad region.

[0052] In some embodiments, such as Figure 3AAs shown, the second back-illuminated image sensor 300 includes a second device wafer 330. The second device wafer 330 can be any material suitable for forming a semiconductor device, such as silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), indium nitride (InN), gallium nitride (GaN), silicon germanium (GeSi), sapphire, or other III / V group compound semiconductor materials. The second device wafer 330 can also be a multilayer structure, such as a silicon / germanium / silicon multilayer. Furthermore, the second device wafer 330 can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The type of the second device wafer 330 can be selected according to actual production needs; it can use a P-type substrate or an N-type substrate. The second device wafer 330 has a front side and a back side arranged opposite to each other along the thickness direction. The front side is used to form a device layer, and the back side is used to form a grid structure, etc.

[0053] In some embodiments, the second device wafer 330 includes a second functional region 340 and a second pad region 350 located outside the second functional region 340. A second pixel array layer 335 and a second metal interconnect structure 331 are formed on the front side of the second device wafer 330. The pixel array in the second pixel array layer 335 is located in the second functional region 340. The pixel array and the second metal interconnect structure 331 are sequentially stacked on the front side of the second device wafer 330. The pixels in the pixel array can also be referred to as photosensitive regions, which are used to convert light signals into electrical signals. The photosensitive region is, for example, a photodiode, which is a PN junction composed of different types of semiconductor materials. In the embodiments of this application, the photosensitive region can be formed by filling different types of semiconductor materials into the trench using epitaxy, or by other suitable conventional processes in the art, without limitation. In some embodiments, the second metal interconnect structure 331 includes a second supporting dielectric layer 332 and a second interconnect metal line 333 embedded in the dielectric layer, wherein the second supporting dielectric layer 332 is used to support and protect the second interconnect metal line 333, and can also prepare for subsequent bonding. The material of the second supporting dielectric layer 332 is, for example, silicon oxide or other low dielectric material layers, and the second supporting dielectric layer 332 can be formed by processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The second interconnect metal line 333 can be made of a metal material with low resistance, such as aluminum (Al), copper (Cu), tungsten (W), etc. The second interconnect metal line 333 can be formed, for example, using a damascus damascene process. The second metal interconnect structure 331 can also be formed using other suitable conventional processes in the art, which will not be described in detail here. In the second pad region 350, the second metal interconnect structure 331 has a second pad 334 on the top layer near the back side of the second device wafer 330.

[0054] In some embodiments, such as Figure 3A As shown, a second grid structure layer 336 is formed on the back side of the second device wafer 330. The grid structure is formed in the region between adjacent pixels, which helps to isolate the pixels, reduce optical crosstalk between pixels, and improve image quality. The pixel array and grid structure can adopt conventional structures in the art. In some embodiments, the second back-illuminated image sensor 300 further includes a second carrier wafer 310. The front side of the second device wafer 330 and the second carrier wafer 310 are bonded together by a second bonding layer 320. In some embodiments, a second bonding layer 320 is deposited on the surface of the second carrier wafer 310, and the second carrier wafer 310 is bonded to the front side of the second device wafer 330 by the second bonding layer 320 to form a composite wafer. The composite wafer is flipped, the back side of the second device wafer 330 is thinned, and the back side stack of the second device wafer 330 is etched in the second pad region 350 to form a pad window 337. The orthographic projection of the pad window 337 overlaps with the orthographic projection of the second pad region 350.

[0055] In step S220, a first dielectric layer and an etch stop layer are sequentially deposited on the back side of the device wafer, the first dielectric layer and the etch stop layer covering the back side of the device wafer and the sidewalls and bottom of the pad window.

[0056] In some embodiments, such as Figure 3B As shown, a first dielectric layer 338 is formed over the back side of a second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The first dielectric layer 338 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the second functional region 340 on the back side of the second device wafer 330. The material of the first dielectric layer 338 is, for example, silicon oxide or other low-dielectric-content material layers. In some embodiments, such as... Figure 3C As shown, an etch stop layer 339 is formed over the first dielectric layer 338 on the back side of the second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The etch stop layer 339 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the first dielectric layer 338 of the second functional region 340 on the back side of the second device wafer 330. The material of the etch stop layer 339 is, for example, amorphous carbon. It should be noted that the etch selectivity ratio of amorphous carbon to the dielectric layer is greater than 30:1, and its Young's modulus is less than 10 GPa, significantly lower than the Young's modulus of conventional oxide dielectric layers (typically greater than 70 GPa). This material characteristic allows the etch stop layer 339 to serve as a self-stopping layer in subsequent dry etching processes.

[0057] In step S230, the etch stop layer in the pad region is graphically removed.

[0058] In some embodiments, such as Figure 3D As shown, photoresist 361 is coated over the etch stop layer 339 on the back side of the second device wafer 330 using processes such as plasma-enhanced chemical vapor deposition (PECVD). Exposure and development are then performed to form an opening in the photoresist 361 corresponding to the second pad region 350, the size of which perfectly matches the orthographic projection of the pad window 337. In some embodiments, such as... Figure 3EAs shown, the etch stop layer 339 is etched using reactive ion etching (RIE) and other processes with photoresist 361 as a mask. Only the etch stop layer 339 of the second functional region 340 is retained, while the etch stop layer 339 directly above the second pad region 350 is removed (including the etch stop layer 339 on the sidewalls and bottom of the pad window 337), and the etching stops at the first dielectric layer 338. The etching endpoint is monitored in real time using optical emission spectroscopy (OES) to ensure precise stopping on the surface of the first dielectric layer 338. Residual photoresist 361 is then removed. It should be noted that after patterning the removal of the etch stop layer 339 of the second pad region 350, a partitioned structure is formed on the back side of the second device wafer 330. The etch stop layer 339 of the retained second functional region 340 not only serves as an etch endpoint marker for the subsequent second dielectric layer 362, but also forms a virtual polishing stop layer (i.e., the first dielectric layer of the functional region on the back side of the device wafer) in the CMP process of the second pad region 350.

[0059] In step S240, a second dielectric layer is deposited on the back side of the device wafer, the second dielectric layer covering the back side of the device wafer and overfilling the pad window.

[0060] In some embodiments, such as Figure 3F As shown, a second dielectric layer 362 is formed over the back side of the second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The second dielectric layer 362 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the second functional region 340, and overfills the pad window 337. The material of the second dielectric layer 362 is, for example, silicon oxide or other low dielectric material layers.

[0061] In step S250, the second dielectric layer of the functional region is graphically removed based on the retained etch stop layer.

[0062] In some embodiments, such as Figure 3G As shown, photoresist (not shown) is coated on the second dielectric layer 362 on the back side of the second device wafer 330 using processes such as plasma-enhanced chemical vapor deposition (PECVD). Exposure and development are then performed to form openings in the photoresist corresponding to the second functional region 340. Reactive ion etching (RIE) is then used to etch the second dielectric layer 362 of the second functional region 340 using the photoresist as a mask, with etching stopping at the surface of the etch stop layer 339. The etching endpoint is monitored in real-time using optical emission spectroscopy (OES) to ensure precise stopping at the surface of the etch stop layer 339. Residual photoresist is then removed.

[0063] In step S260, after the etch stop layer is removed by ashing, the pad area is chemically mechanically polished to planarize the back side of the device wafer.

[0064] In some embodiments, such as Figure 3H As shown, an oxygen plasma ashing process is used to remove the etch stop layer 339 of the second functional region 340 on the back side of the second device wafer 330. This process simultaneously strips away any remaining thin layer of the second dielectric layer 362 in the second functional region 340, exposing the clean surface of the first dielectric layer 338 again. In some embodiments, such as... Figure 3I As shown, a short-term selective chemical mechanical polishing (CMP) is performed on the overfilled second dielectric layer 362 of the second pad region 350 on the back side of the second device wafer 330. Based on the real-time detection of the CMP endpoint of the first dielectric layer 338 of the second functional region 340 on the back side of the second device wafer 330, the CMP is immediately terminated when a zero-loss state of the first dielectric layer 338 is detected.

[0065] Figure 4A The diagram shown is a schematic representation of the pad edge after chemical mechanical polishing of the pad region dielectric layer according to an embodiment of this application. Figure 4A As shown, short-term selective chemical mechanical polishing of the overfilled second dielectric layer 362 of the second pad region 350 on the back side of the second device wafer 330 did not result in pad edge cracks in the pad window. Figure 4B The diagram shows the location of a device with a solder pad edge crack in a whole device wafer according to an embodiment of this application. Figure 4B As shown, the spatial distribution density of edge cracks of the second pad 334 on the surface of the entire second device wafer 330 of this application embodiment is presented intuitively. Obviously, no edge cracks of the pads have occurred in the entire second device wafer 330.

[0066] It should be noted that after the etch stop layer 339 of the second pad region 350 is removed graphically, a structure system with partitioned characteristics is formed on the back side of the second device wafer 330. The etch stop layer 339 of the retained second functional region 340 not only serves as an etch endpoint marker for the subsequent second dielectric layer 362, preventing over-etching of the dielectric layer in the second functional region 340, but also avoids sharp corners near the steep steps of the pad window. At the same time, the etch stop layer 339 of the retained second functional region 340 also forms a virtual polishing stop layer (i.e., the first dielectric layer 338 of the second functional region 340 on the back side of the second device wafer 330) in the CMP process of the second pad region 350, preventing pad edge cracks (PadCrack) from appearing in the pad window due to the CMP process. It should be noted that by integrating the dual functions of the etch stop layer 339, global planarization of the back side of the second device wafer 330 is achieved without increasing the number of photomask layers. This effectively eliminates the stress concentration phenomenon at the sharp corners of the pad edges in the second pad region 350, reduces the probability of pad edge cracks during chemical mechanical polishing, and thus improves device yield and reliability.

[0067] Accordingly, this application also provides a back-illuminated image sensor manufactured according to the aforementioned manufacturing method. Since the process of manufacturing a back-illuminated image sensor using the manufacturing method of this application has been described in detail in the above method embodiments, it will not be repeated here.

[0068] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a back-illuminated image sensor, comprising: A device wafer is provided, the device wafer including a functional region and a pad region, wherein a pad window on the back side of the device wafer exposes the pad in the pad region; A first dielectric layer and an etch stop layer are sequentially deposited on the back side of the device wafer, the first dielectric layer and the etch stop layer covering the back side of the device wafer and the sidewalls and bottom of the pad window; Graphically remove the etch stop layer in the pad region; A second dielectric layer is deposited on the back side of the device wafer, the second dielectric layer covering the back side of the device wafer and overfilling the pad window; Based on the retained etch stop layer, the second dielectric layer of the functional region is graphically removed; After the etch stop layer is removed by ashing, the pad area is chemically and mechanically polished to planarize the back side of the device wafer.

2. The manufacturing method according to claim 1, wherein, The front side of the device wafer has a pixel array and a metal interconnect structure stacked sequentially, the metal interconnect structure covering the pixel array, and the metal interconnect structure having the solder pads on the top layer near the back side of the device wafer in the pad area outside the functional area.

3. The manufacturing method according to claim 2, wherein, Before sequentially depositing a first dielectric layer and an etch stop layer on the back side of the device wafer, the manufacturing method further includes: Deposit a bonding layer on the surface of the carrier wafer; The carrier wafer and the front side of the device wafer are bonded together through the bonding layer to form a composite wafer; The composite wafer is flipped over to thin the back side of the device wafer; The backside stack of the device wafer is etched in the pad area to form the pad window.

4. The manufacturing method according to claim 3, wherein, The patterning removal of the etch stop layer in the solder pad region includes: Photoresist is applied over the etch stop layer on the back side of the device wafer, and exposed and developed to form openings in the photoresist corresponding to the pad regions; The photoresist is used as a mask to etch the etch stop layer, retaining only the etch stop layer of the functional area. The etch stop layer directly above the pad area is removed and the etching stops at the first dielectric layer.

5. The manufacturing method according to claim 3, wherein, The second dielectric layer, based on the retained etch stop layer, is graphically removed from the functional region, including: Photoresist is coated over the second dielectric layer on the back side of the device wafer, exposed and developed to form an opening in the photoresist corresponding to the functional region; Using the photoresist as a mask, the second dielectric layer of the functional area is etched, and the etching stops on the surface of the etching stop layer.

6. The manufacturing method according to claim 3, wherein, After the ashing process removes the etch stop layer, the pad area is subjected to chemical mechanical polishing to planarize the back side of the device wafer, including: Ashing removes the etching stop layer in the functional area; The second dielectric layer in the pad region is subjected to chemical mechanical polishing, wherein the endpoint of chemical mechanical polishing is detected in real time based on the first dielectric layer of the functional region.

7. The manufacturing method according to claim 3, wherein, The orthographic projection of the pad region overlaps with the orthographic projection of the pad window.

8. The manufacturing method according to claim 3, wherein, After flipping the composite wafer and thinning the back side of the device wafer, the manufacturing method further includes: A grid structure is formed in the area between pixels on the back side of the device wafer.

9. The manufacturing method according to claim 1, wherein, The material of the etch stop layer includes amorphous carbon.

10. A back-illuminated image sensor, manufactured according to the manufacturing method of any one of claims 1 to 9.

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