Backside illuminated image sensor and method of making the same

Abstract

The application belongs to the technical field of semiconductors, and discloses a back-illuminated image sensor and a preparation method thereof, the method comprising the following steps: providing a wafer bonding structure; the wafer bonding structure comprising a device wafer; performing co-ion implantation on the back surface of the device wafer, then performing chemical mechanical planarization to thin the device wafer to a set thickness, then forming a substrate oxide layer on the back surface of the device wafer; depositing a high dielectric constant layer on the substrate oxide layer; and performing annealing treatment. The application performs co-ion implantation on the back surface of the device wafer before CMP to change the polishing rate of the back surface, so that the chemical grinding can be more planarized; the H2O2 reacts with damaged Si to generate a sacrificial oxide layer, and the sacrificial oxide layer can be removed by adding HF, so that the EPI damage degree after chemical grinding can be reduced, the SI-H bond generated at the interface can make up for defects while eliminating silicon damage; the application solves the problem of bubbles and improves the terminal performance of products under the premise of ensuring the terminal performance of white spots and dark current.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and more specifically, relates to a back-illuminated image sensor and its fabrication method. Background Technology

[0002] Back-illuminated CMOS image sensors are image sensors that improve light-sensing efficiency by adjusting the structure of the photosensitive layer and the circuit layer. Their core design involves swapping the positions of the photodiode layer and the circuit layer in a traditional front-illuminated structure, allowing light to directly illuminate the photosensitive area from the back. This reduces the obstruction of light by metal circuitry and transistors, significantly improving image quality and signal-to-noise ratio under low-light conditions.

[0003] Please see Figures 1 to 5 As shown, existing BSI (Backside illumination) technology includes the following steps:

[0004] A wafer bonding structure is provided; the wafer bonding structure includes a carrier wafer 10 and a device wafer 20 bonded together.

[0005] Chemical-Mechanical Planarization (CMP) is performed on the back side of device wafer 20 to reduce the thickness of device wafer 20 to a set thickness. The existing chemical-mechanical planarization process itself has an effect that results in poor film thickness uniformity U% of device wafer 20, with thinner edges and thicker centers, and surface damage (Si damage) 21 will be formed on the back side of device wafer 20.

[0006] The substrate damage caused by chemical mechanical planarization was not completely repaired. Then, decoupled plasma oxide was deposited on the back side of device wafer 20 to form substrate oxide layer 30. Due to the large height difference between the edge and center of device wafer 20, the plasma O contact was insufficient, resulting in slow growth of decoupled plasma oxidation at the edge of device wafer 20.

[0007] Then a high dielectric constant layer 40 is deposited on the substrate oxide layer 30;

[0008] After depositing a silicon nitride layer 50 on the device, an annealing process is performed to complete the fabrication of the back-illuminated CMOS image sensor.

[0009] The existing BSI (Backside illumination) process technology requires chemical-mechanical planarization (CMP) of the device wafers after bonding two wafers. After wet etching, decoupled plasma oxidation, and deposition of a high-k film, the wafers are heat-treated and the number of bubbles (bubble 31) is checked. The presence of bubble 31 will affect the performance and reliability testing of the back-illuminated CMOS image sensor.

[0010] The substrate oxide layer 30 of the decoupled plasma oxide is located between the device wafer 20 and the high-k film 40, playing a crucial role in isolation and adhesion. Performance-wise, variations in the decoupled plasma oxide significantly impact white point and dark current termination performance, but the following factors may also cause wafer edge bubble problems after heat treatment:

[0011] 1) When the height difference between the wafer edge and center is large due to chemical mechanical planarization, the contact between plasma and oxygen is insufficient, resulting in slow growth of the decoupled plasma oxide layer at the wafer edge;

[0012] 2) The damage to the EPI substrate caused by chemical mechanical planarization was not completely repaired. Summary of the Invention

[0013] The purpose of this invention is to provide a back-illuminated image sensor and its fabrication method, so as to reduce the technical problem that the large height difference between the wafer edge and the center and / or damage to the EPI substrate caused by chemical mechanical planarization during the fabrication of back-illuminated CMOS image sensors, resulting in a large number of bubbles at the wafer edge and thus affecting product performance.

[0014] To achieve the above objectives, the present invention adopts the following technical solution:

[0015] In a first aspect, the present invention provides a method for fabricating a back-illuminated image sensor, comprising:

[0016] A wafer bonding structure is provided; the wafer bonding structure includes a device wafer;

[0017] The back side of the device wafer is co-ion implanted, and then chemical mechanical planarization is performed to thin the device wafer to a set thickness. Then, a substrate oxide layer is formed on the back side of the device wafer.

[0018] Deposit a high dielectric constant layer on the substrate oxide layer;

[0019] Perform annealing treatment;

[0020] In the step of co-ion implantation on the back side of the device wafer, the implanted ions are neutral ions; the neutral ions are one or both of Si ions and C ions.

[0021] A further improvement of this invention is that the neutral ions are Si ions and C ions; the dose ratio of Si ions to C ions is (2~5):(1~3), the inner ring injection energy is 0.5-5 keV, and the injection dose is 1.0×e 13 -1.0×e 14 Ions / cm²; outer ring implantation energy 5-15 keV, implantation dose 5.0 × e⁻¹ 14 -5.0×e 15 Ions per square centimeter.

[0022] A further improvement of the present invention is that, in the step of co-ion implantation on the back side of the device wafer, the back side is composed of an inner ring located at the center and an outer ring located on the periphery of the inner ring, and the implantation doses of the inner ring and the outer ring are different.

[0023] A further improvement of the present invention is that, in the step of co-ion implantation on the back side of the device wafer, the dose implanted in the inner ring is less than the dose implanted in the outer ring.

[0024] A further improvement of the present invention is that the inner ring occupies 80% to 95% of the overall device wafer surface area, and the outer ring occupies 5% to 20% of the overall device wafer surface area.

[0025] A further improvement of this invention is that the inner ring injection energy is 0.5-5 keV, and the injection dose is 1.0 × e 13 -1.0×e 14 Ions / cm²; outer ring implantation energy 5-15 keV, implantation dose 5.0 × e⁻¹ 14 -5.0×e 15 Ions per square centimeter.

[0026] A further improvement of the present invention is that: after performing chemical mechanical planarization to thin the device wafer to a set thickness, the damaged Si on the back side of the device wafer is oxidized to form a sacrificial oxide layer, the sacrificial oxide layer is removed, and then a substrate oxide layer is formed on the back side of the device wafer.

[0027] A further improvement of the present invention is that: the step of removing the sacrificial oxide layer formed on the damaged Si on the back side of the oxidized device wafer specifically includes:

[0028] A sacrificial oxide layer is formed by oxidizing the damaged Si on the back side of the device wafer with H2O2, and then the sacrificial oxide layer is removed by immersion in HF.

[0029] A further improvement of the present invention is that: after performing chemical mechanical planarization to thin the device wafer to a set thickness, the film thickness uniformity on the back side of the device wafer is detected, and after the film thickness uniformity reaches a preset film thickness uniformity U%, a substrate oxide layer is formed on the back side of the device wafer.

[0030] A further improvement of the present invention is that the preset film thickness uniformity U% is less than or equal to 1%.

[0031] A further improvement of this invention is that the process parameters of the decoupling plasma oxidation process are as follows: oxygen is introduced into a reaction chamber with a temperature of 360℃~380℃, a pressure of 75mT~90mT, and a radio frequency power of 2.2KW~2.4KW, and the oxygen is decoupled by high-energy plasma to form high-energy, highly reactive oxygen free radicals; the back side of the device wafer reacts with the oxygen free radicals to form decoupling plasma oxides; wherein the oxygen flow rate is 240mL / min~300mL / min.

[0032] A further improvement of the present invention is that the material of the high dielectric constant layer 40 is an oxide or nitride of one of hafnium, tantalum, and zirconium.

[0033] A further improvement of the present invention is that the annealing process temperature is 350℃~400℃ and the annealing time is 10 minutes to 2 hours.

[0034] Secondly, this invention provides a back-illuminated image sensor, which is prepared by the method for preparing the back-illuminated image sensor.

[0035] Compared with the prior art, the present invention has the following unexpected technical effects:

[0036] This invention provides a method for fabricating a back-illuminated image sensor, comprising: providing a wafer bonding structure; the wafer bonding structure including a device wafer; performing co-ion implantation on the back side of the device wafer, followed by chemical mechanical planarization to thin the device wafer to a set thickness, and then forming a substrate oxide layer on the back side of the device wafer; depositing a high dielectric constant layer on the substrate oxide layer; and performing annealing. This invention performs co-ion implantation on the back side of the device wafer before chemical mechanical planarization to change the polishing rate of the back side, which can make chemical polishing more planar and improve the U% (unsaturation point). Furthermore, by reacting H2O2 with damaged Si to generate a sacrificial oxide layer, and adding HF to remove the sacrificial oxide layer, the degree of EPI damage after chemical polishing can be reduced. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for defects. This invention solves the bubble problem and improves the final product performance while ensuring good white point and dark current terminal performance. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a wafer bonding structure for bonding a device wafer to a carrier wafer in the prior art.

[0039] Figure 2 This is a schematic diagram of the structure of a device wafer after CMP polishing in the prior art.

[0040] Figure 3 A schematic diagram of the structure of a device wafer after decoupling plasma oxide deposition in the prior art;

[0041] Figure 4 A schematic diagram of the structure of a device wafer in the prior art when a high dielectric constant layer is deposited and covered with a silicon nitride layer and then annealed.

[0042] Figure 5 A schematic diagram of a back-illuminated image sensor structure prepared using the existing BSI process technology;

[0043] Figure 6 A microscopic cross-sectional view of bubbles forming at the edge of a back-illuminated image sensor prepared using the existing BSI process.

[0044] Figure 7 This is a schematic flowchart illustrating a method for fabricating a back-illuminated image sensor according to an embodiment of the present invention.

[0045] Figure 8 This is a schematic diagram of the wafer bonding structure for bonding the device wafer and the carrier wafer according to an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the structure of the device wafer after CMP polishing according to an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of the structure for surface repair of a device wafer according to an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of the structure of a device wafer after decoupling plasma oxide deposition, according to an embodiment of the present invention.

[0049] Figure 12 This is a schematic diagram of the structure of a device wafer during annealing after depositing a high dielectric constant layer and covering it with a silicon nitride layer, according to an embodiment of the present invention.

[0050] Figure 13This is a schematic diagram of the back-illuminated image sensor structure obtained by a method for fabricating a back-illuminated image sensor according to an embodiment of the present invention. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0054] Please see Figures 7-13 As shown, this embodiment of the invention provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0055] S1. A wafer bonding structure is provided; the wafer bonding structure includes a device wafer 20;

[0056] S2. Perform co-ion implantation on the back side of the device wafer, then perform chemical mechanical planarization to thin the device wafer to the set thickness, and then form a substrate oxide layer on the back side of the device wafer.

[0057] S3. Deposit a high dielectric constant layer on the substrate oxide layer;

[0058] S4. Perform annealing treatment.

[0059] In one specific embodiment, the wafer bonding structure provided in step S1 includes a device wafer 20 and a carrier wafer 10 bonded to each other. The device wafer 20 includes a first substrate and a first bonding layer located on the first substrate. The carrier wafer 10 includes a second substrate and a second bonding layer located on the second substrate. The first bonding layer is bonded to the second bonding layer. The first bonding layer and the second bonding layer are bonded to obtain the wafer bonding structure.

[0060] In one embodiment, a first bonding layer is formed on a first substrate, which can be formed by chemical vapor deposition. For example, the first bonding layer can be a high-bonding-strength oxide layer; the thickness of the first bonding layer is 18,000 angstroms to 22,000 angstroms. A second bonding layer is formed on a second substrate, which can also be formed by chemical vapor deposition. For example, the second bonding layer can be a high-bonding-strength oxide layer; the thickness of the second bonding layer is 18,000 angstroms to 22,000 angstroms.

[0061] In one embodiment, the cross-sectional area of ​​the carrier wafer 10 is greater than or equal to the cross-sectional area of ​​the device wafer 20. Exemplarily, the cross-sections of the carrier wafer 10 and the device wafer 20 are square or circular, preferably circular.

[0062] In one specific embodiment, before performing chemical-mechanical planarization (CMP) in step S2, co-implantation is performed on the back side of the device wafer 20 to change the CMP polish rate at the edge of the device wafer 20; then, chemical-mechanical planarization is performed on the back side of the device wafer 20 to thin it to a set thickness, making the back side of the device wafer 20 more flat.

[0063] In one specific embodiment, the ions co-implanted are neutral ions; for example, the implanted neutral ions are one or both of Si ions and C ions. The neutral ions are co-implanted ions, which are positively charged ions themselves, such as silicon ions and / or carbon ions. However, co-implantation does not affect the electrical properties of the device wafer, hence the term neutral ions. This invention utilizes the commonality of neutral ions to amorphize the silicon surface through neutral ion implantation, thus causing changes in the etching rate. For example, the implanted neutral ions are one of Si ions and C ions, or Si ions and C ions; different dosages in different regions achieve the effect of changing the etching rate as described in this invention.

[0064] In one specific implementation, please refer to Figure 8As shown, the back side of the device wafer consists of an inner ring located in the central region and an outer ring located around the periphery of the inner ring. During co-ion implantation, the implanted dose in the central region (inner ring) is less than the implanted dose in the edge region (outer ring) of the device wafer, in order to adjust the polishing rates of the edge region and the central region of the device wafer to make the inner and outer rings more flat after subsequent grinding. For example, the inner ring occupies 80%~95% of the total surface area of ​​the device wafer, and the outer ring occupies 5%~20% of the total surface area of ​​the device wafer. For example, the implantation energy of the inner ring in co-ion implantation is 0.5-5 keV, and the implantation dose is 1.0 × e-1 13 -1.0×e 14 Ions / cm²; outer ring implantation energy 5-15 keV, implantation dose 5.0 × e⁻¹ 14 -5.0×e 15 Ions / cm². For example, both Si and C ions are implanted together, with a Si ion to C ion dose ratio of (2~5):(1~3), an inner-ring implantation energy of 0.5-5 keV, and an implantation dose of 1.0 × e⁻¹. 13 -1.0×e 14 Ions / cm²; outer ring implantation energy 5-15 keV, implantation dose 5.0 × e⁻¹ 14 -5.0×e 15 Ions per square centimeter.

[0065] In one specific embodiment, the back side of the device wafer 20 is thinned to a predetermined thickness using chemical-mechanical planarization (CMP). Since co-ion implantation is performed before CMP, the polishing rate of the inner and outer rings on the back side of the device wafer is improved, resulting in a more flattened back side of the device wafer 20. After detecting that the film thickness uniformity on the back side of the device wafer 20 reaches a predetermined film thickness uniformity U%, a substrate oxide layer 30 is formed on the back side of the device wafer 20. For example, the predetermined film thickness uniformity U% is 0.5% or 1%.

[0066] In one specific implementation, please refer to Figure 9As shown, during the thinning process on the back side of device wafer 20, surface damage 21 is generated on the back side of device wafer 20. Surface damage 21 can cause problems such as dark current and white pixels in the sensor, thus requiring defect repair. In this embodiment, after the chemical mechanical planarization step to thin the device wafer to the set thickness, a sacrificial oxide layer is formed on the damaged Si on the back side of the device wafer, the sacrificial oxide layer is removed, and then a substrate oxide layer is formed on the back side of the device wafer. Specifically, the sacrificial oxide layer is formed by oxidizing the damaged Si on the back side of device wafer 20 with H2O2, and the sacrificial oxide layer is removed by HF immersion. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for defects and improve the performance of subsequent products.

[0067] In one specific implementation, please refer to Figure 10 As shown, the substrate oxide layer 30 is a dense silicon oxide or similar material. The specific fabrication steps include: performing a decoupled plasma oxidation process on the back side of the device wafer 20 to form the substrate oxide layer 30. Specifically, the process parameters for the decoupled plasma oxidation process are as follows: oxygen is introduced into a reaction chamber at a temperature of 360℃~380℃, a pressure of 75mT~90mT, and a radio frequency power of 2.2KW~2.4KW. High-energy plasma decouples the oxygen, forming high-energy, highly reactive oxygen free radicals. The back side of the device wafer 20 reacts with these oxygen free radicals to form a decoupled plasma oxide (the free radicals react with silicon to form a silicon dioxide substrate oxide layer 30), further repairing surface defects caused by the thinning of the back side of the device wafer 20. For example, the oxygen flow rate is 240mL / min~300mL / min. This invention forms a sacrificial oxide layer by oxidizing the damaged Si on the back side of the device wafer 20 with H2O2, and removes the sacrificial oxide layer by immersion in HF. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for the defects. Furthermore, by forming a decoupled plasma oxide layer on the back side of the device wafer 20, the surface defects caused by the thinning of the back side of the device wafer 20 are reduced, solving the problems of dark current and white pixel in the sensor caused by surface defects, and enabling the manufacture of a higher quality back-illuminated CMOS image sensor.

[0068] In one specific implementation, exemplarily, please refer to Figure 11 As shown, in step S3, a high dielectric constant layer 40 is deposited on the surface of the substrate oxide layer 30 using a chemical vapor deposition process; the material of the high dielectric constant layer 40 can be an oxide or oxynitride of one of hafnium (Hf), tantalum (Ta), and zirconium (Zr).

[0069] In one specific implementation, exemplarily, please refer to Figure 12 As shown, during step S4 annealing, a silicon nitride layer is covered on the surface of the high dielectric constant layer of the back-illuminated image sensor for protection. This can protect the underlying thin film layer structure of the back-illuminated image sensor to a certain extent, maintain its stability during the annealing process, and reduce problems such as thin film cracking and deformation.

[0070] In one specific embodiment, for example, the annealing process temperature is 350°C to 400°C, and the annealing time is 10 minutes to 2 hours.

[0071] In this embodiment, the inspection of wafer edge bubbles in a back-illuminated image sensor is performed. The bubble detection method shows a significant improvement over existing BSI (Backside Illumination) technology, meeting the acceptable standards for bubble inspection. The acceptable standards are: bubble size greater than 0.8 mm and zero bubbles. This invention significantly reduces or eliminates wafer edge bubbles.

[0072] Please see Figures 7-13 As shown, this embodiment of the invention provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0073] S1. A wafer bonding structure is provided; the wafer bonding structure includes a carrier wafer 10 and a device wafer 20.

[0074] In one specific embodiment, the cross-sectional area of ​​the carrier wafer 10 is larger than the cross-sectional area of ​​the device wafer 20, and the cross-sections of both the carrier wafer 10 and the device wafer 20 are circular.

[0075] In one specific embodiment, the device wafer 20 includes a first substrate and a first bonding layer located on the first substrate, and the carrier wafer 10 includes a second substrate and a second bonding layer located on the second substrate, wherein the first bonding layer is bonded to the second bonding layer; the first bonding layer and the second bonding layer are bonded to obtain a wafer bonding structure.

[0076] In one specific embodiment, a first bonding layer is formed on a first substrate using chemical vapor deposition. The first bonding layer is a high-bonding-strength oxide layer with a thickness of 18,000 angstroms. A second bonding layer is formed on a second substrate using chemical vapor deposition. The second bonding layer is also a high-bonding-strength oxide layer with a thickness of 18,000 angstroms.

[0077] S2. Perform co-ion implantation on the back side of the device wafer 20, then perform chemical mechanical planarization to thin the device wafer to a set thickness, form a sacrificial oxide layer 22 on the Si damaged on the back side of the device wafer, remove the sacrificial oxide layer 22, and then form a substrate oxide layer on the back side of the device wafer.

[0078] In one specific embodiment, before chemical-mechanical planarization (CMP) in step S2, co-implantation is performed on the back side of device wafer 20 to change the CMP polish rate at the edge of device wafer 20. Then, CMP thinning is performed on the back side of device wafer 20 to a set thickness, making the back side of device wafer 20 more planar. During co-implantation, the implanted neutral ions are Si ions and C ions; the Si ion to C ion dose ratio is 1:1; the inner ring occupies 80% of the total device wafer surface area, and the outer ring occupies 20% of the total device wafer surface area. During co-implantation, the dose implanted in the central region (inner ring) is less than the dose implanted at the edge (outer ring) of the device wafer, to adjust the different polishing rates between the edge and central regions of the device wafer, resulting in a more planar inner and outer ring after subsequent polishing. Specifically, the inner ring implantation energy is 5 keV, and the implantation dose is 1.0 × e 14 Ions / cm²; outer ring implantation energy 15 keV, implantation dose 5.0 × e⁻¹ 15 Ions per square centimeter.

[0079] In one specific embodiment, the back side of the device wafer 20 is thinned to a predetermined thickness using chemical-mechanical planarization (CMP). Since co-ion implantation is performed before CMP, the polishing rate of the inner and outer rings on the back side of the device wafer is improved, resulting in a more flattened back side of device wafer 20. After the film thickness uniformity on the back side of device wafer 20 reaches a predetermined film thickness uniformity U%, a substrate oxide layer 30 is formed on the back side of device wafer 20. Specifically, the predetermined film thickness uniformity U% is 0.5%.

[0080] In one specific implementation, please refer to Figure 9As shown, during the thinning process of the back side of the device wafer 20, surface damage 21 is generated on the back side of the device wafer 20. Surface damage 21 can cause problems such as dark current and white pixel in the sensor, so it is necessary to repair the defects. In this embodiment, after the step of thinning the device wafer to a set thickness by chemical mechanical planarization, the damaged Si on the back side of the device wafer 20 is oxidized by H2O2 with a volume concentration of 10% to form a sacrificial oxide layer 22. The sacrificial oxide layer 22 is removed by immersion in HF with a volume concentration of 40%. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for the defects and improve the performance of subsequent products.

[0081] In one specific implementation, please refer to Figure 10 As shown, the substrate oxide layer 30 is a dense silicon oxide material. The specific fabrication steps include: performing a decoupled plasma oxidation process on the back side of the device wafer 20 to form the substrate oxide layer 30. Specifically, the process parameters for the decoupled plasma oxidation process are: oxygen is introduced into a reaction chamber at a temperature of 360℃, a pressure of 75mT, and a radio frequency power of 2.2KW. High-energy plasma decouples the oxygen, forming high-energy, highly reactive oxygen free radicals. The back side of the device wafer 20 reacts with these oxygen free radicals to form a decoupled plasma oxide (the free radicals react with silicon to form the silicon dioxide substrate oxide layer 30), further repairing surface defects caused by the thinning of the back side of the device wafer 20. Specifically, the oxygen flow rate is 240mL / min. In this embodiment of the invention, a sacrificial oxide layer 22 is formed by oxidizing the damaged Si on the back side of the device wafer 20 with H2O2 at a volume concentration of 10%. The sacrificial oxide layer 22 is removed by immersion in HF at a volume concentration of 40%. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for the defects. Furthermore, by forming a decoupled plasma oxide layer on the back side of the device wafer 20, the surface defects caused by the thinning of the back side of the device wafer 20 are reduced. This solves the problems of dark current and white pixel in the sensor caused by surface defects, and enables the manufacture of a higher quality back-illuminated CMOS image sensor.

[0082] S3. Deposit a high dielectric constant layer on the substrate oxide layer;

[0083] In one specific implementation, please refer to [link / reference]. Figure 11 As shown, in step S3, a high dielectric constant layer 40 is deposited on the surface of the substrate oxide layer 30 using a chemical vapor deposition process; the material of the high dielectric constant layer 40 is an oxide of zirconium (Zr).

[0084] S4. Perform annealing treatment.

[0085] In one specific implementation, please refer to [link / reference]. Figure 12 As shown, during step S4 annealing, a silicon nitride layer 50 is applied to the surface of the high dielectric constant layer 40 of the back-illuminated image sensor for protection. This protects the underlying thin film layers of the back-illuminated image sensor, ensuring their stability during annealing and reducing issues such as film cracking and deformation. Specifically, the annealing temperature is 400℃, and the annealing time is 10 minutes.

[0086] In this embodiment, the inspection of wafer edge bubbles in a back-illuminated image sensor is performed. The bubble detection method shows a significant improvement over existing BSI (Backside Illumination) technology, meeting the acceptable standards for bubble inspection. The acceptable standards are: bubble size greater than 0.8 mm and zero bubbles. This invention significantly reduces or eliminates wafer edge bubbles.

[0087] Please see Figures 7-13 As shown, this embodiment of the invention provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0088] S1. A wafer bonding structure is provided; the wafer bonding structure includes a carrier wafer 10 and a device wafer 20; the device wafer 20 includes a first substrate and a first bonding layer located on the first substrate, the carrier wafer 10 includes a second substrate and a second bonding layer located on the second substrate, the first bonding layer and the second bonding layer are bonded; the first bonding layer and the second bonding layer are bonded to obtain the wafer bonding structure; the first bonding layer is formed on the first substrate by chemical vapor deposition, the first bonding layer is a high-bonding-strength oxide layer with a thickness of 20,000 angstroms. The second bonding layer is formed on the second substrate by chemical vapor deposition, the second bonding layer is a high-bonding-strength oxide layer; the thickness of the second bonding layer is 20,000 angstroms.

[0089] In one specific embodiment, the cross-sectional area of ​​the carrier wafer 10 is equal to the cross-sectional area of ​​the device wafer 20, and both the carrier wafer 10 and the device wafer 20 have circular cross-sections.

[0090] S2. Perform co-ion implantation on the back side of the device wafer 20, then perform chemical mechanical planarization to thin the device wafer to a set thickness, form a sacrificial oxide layer 22 on the Si damaged on the back side of the device wafer, remove the sacrificial oxide layer 22, and then form a substrate oxide layer on the back side of the device wafer.

[0091] In one specific embodiment, before CMP in step S2, co-ion implantation is performed on the back side of device wafer 20; then, chemical mechanical planarization is performed on the back side of device wafer 20 to thin it to a set thickness, making the back side of device wafer 20 more planar. During co-ion implantation, the implanted neutral ions are Si ions and C ions; the dose ratio of Si ions to C ions is 2:3; the inner ring occupies 95% of the total device wafer surface area, and the outer ring occupies 5% of the total device wafer surface area. During co-ion implantation, the dose implanted in the central region (inner ring) is less than the dose implanted at the edge of the device wafer (outer ring) to adjust the polishing rate difference between the edge region and the central region of the device wafer, so that the inner and outer rings are more planar after subsequent polishing. Specifically, the implantation energy of the inner ring is 3 keV, and the implantation dose is 1.0 × e 13 Ions / cm²; outer ring implantation energy 5 keV, implantation dose 5.0 × e⁻¹ 14 Ions per square centimeter.

[0092] In one specific embodiment, the back side of the device wafer 20 is thinned to a predetermined thickness using chemical mechanical planarization. Because co-ion implantation is performed before CMP, the polishing rate of the inner and outer rings on the back side of the device wafer is improved, resulting in a more planar back side of the device wafer 20. After the film thickness uniformity on the back side of the device wafer 20 is detected to reach a predetermined film thickness uniformity U%, a substrate oxide layer 30 is formed on the back side of the device wafer 20. Specifically, the predetermined film thickness uniformity U% is 1%.

[0093] In one specific implementation, please refer to Figure 9 As shown, during the thinning process of the back side of the device wafer 20, surface damage 21 is generated on the back side of the device wafer 20. Surface damage 21 can cause problems such as dark current and white pixel in the sensor, so it is necessary to repair the defects. In this embodiment, after the step of thinning the device wafer to a set thickness by chemical mechanical planarization, the damaged Si on the back side of the device wafer 20 is oxidized by H2O2 with a volume concentration of 10% to form a sacrificial oxide layer 22. The sacrificial oxide layer 22 is removed by immersion in HF with a volume concentration of 40%. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for the defects and improve the performance of subsequent products.

[0094] In one specific implementation, please refer to Figure 10As shown, the substrate oxide layer 30 is a dense silicon oxide material. The specific fabrication steps include: performing a decoupling plasma oxidation process on the back side of the device wafer 20 to form the substrate oxide layer 30. Specifically, the process parameters for the decoupling plasma oxidation process are: oxygen is introduced into a reaction chamber at a temperature of 380℃, a pressure of 90mT, and a radio frequency power of 2.4KW. High-energy plasma decouples the oxygen, forming high-energy, highly reactive oxygen free radicals. The back side of the device wafer 20 reacts with these oxygen free radicals to form a decoupling plasma oxide (the free radicals react with silicon to form the silicon dioxide substrate oxide layer 30), further repairing surface defects caused by the thinning of the back side of the device wafer 20. Specifically, the oxygen flow rate is 300mL / min. In this embodiment of the invention, a sacrificial oxide layer 22 is formed by oxidizing the damaged Si on the back side of the device wafer 20 with H2O2 at a volume concentration of 10%. The sacrificial oxide layer 22 is removed by immersion in HF at a volume concentration of 40%. While eliminating silicon damage, the SI-H bonds generated at the interface can compensate for the defects. Furthermore, by forming a decoupled plasma oxide layer on the back side of the device wafer 20, the surface defects caused by the thinning of the back side of the device wafer 20 are reduced. This solves the problems of dark current and white pixels in the sensor caused by surface defects, and enables the manufacture of a higher quality back-illuminated CMOS image sensor.

[0095] S3. Deposit a high dielectric constant layer on the substrate oxide layer;

[0096] In one specific implementation, please refer to [link / reference]. Figure 11 As shown, in step S3, a high dielectric constant layer 40 is deposited on the surface of the substrate oxide layer 30 using a chemical vapor deposition process; the material of the high dielectric constant layer 40 is an oxide of hafnium (Hf).

[0097] S4. Perform annealing treatment.

[0098] In one specific implementation, please refer to [link / reference]. Figure 12 As shown, during step S4 annealing, a silicon nitride layer 50 is applied to the surface of the high dielectric constant layer 40 of the back-illuminated image sensor for protection. This protects the underlying thin film layers of the back-illuminated image sensor, ensuring their stability during annealing and reducing issues such as film cracking and deformation. Specifically, the annealing temperature is 350℃, and the annealing time is 2 hours.

[0099] In this embodiment, the inspection of wafer edge bubbles in a back-illuminated image sensor is performed. The bubble detection method shows a significant improvement over existing BSI (Backside Illumination) technology, meeting the acceptable standards for bubble inspection. The acceptable standards are: bubble size greater than 0.6 mm and zero bubbles. This invention significantly reduces or eliminates wafer edge bubbles.

[0100] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or equivalent to the scope of this invention are included in this invention.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: Provide a wafer bonding structure; Wafer bonding structures include device wafers; The back side of the device wafer is co-ion implanted, and then chemical mechanical planarization is performed to thin the device wafer to a set thickness. Then, a substrate oxide layer is formed on the back side of the device wafer. Deposit a high dielectric constant layer on the substrate oxide layer; Perform annealing treatment; In the step of co-ion implantation on the back side of the device wafer, the implanted ions are neutral ions; In the step of co-ion implantation on the back side of the device wafer, the back side consists of an inner ring located in the central region and an outer ring located on the outer periphery of the inner ring, and the implantation doses of the inner ring and the outer ring are different. After performing chemical mechanical planarization to thin the device wafer to a set thickness, the damaged Si on the back side of the device wafer is oxidized to form a sacrificial oxide layer. The sacrificial oxide layer is removed, and then a substrate oxide layer is formed on the back side of the device wafer. The step of removing the sacrificial oxide layer formed on the damaged Si on the back side of the oxidized device wafer specifically includes: A sacrificial oxide layer is formed by oxidizing the damaged Si on the back side of the device wafer with H2O2, and then the sacrificial oxide layer is removed by immersion in HF.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The neutral ion is one or both of Si ions and C ions.

3. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, In the step of co-ion implantation on the back side of the device wafer, the implantation dose in the inner ring is less than that in the outer ring.

4. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The inner ring occupies 80% to 95% of the total back surface area of ​​the device wafer, while the outer ring occupies 5% to 20% of the total back surface area of ​​the device wafer.

5. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The inner ring injection energy is 0.5-5 keV, and the injection dose is 1.0 × e 13 -1.0×e 14 Ions / cm²; outer ring implantation energy 5-15 keV, implantation dose 5.0 × e⁻¹ 14 -5.0×e 15 Ions per square centimeter.

6. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, After performing chemical mechanical planarization to thin the device wafer to a set thickness, the film thickness uniformity on the back side of the device wafer is detected. After the film thickness uniformity reaches a preset film thickness uniformity U%, a substrate oxide layer is formed on the back side of the device wafer.

7. A back-illuminated image sensor, characterized in that, It is prepared by the method of any one of claims 1-6 for preparing a back-illuminated image sensor.

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