Method for manufacturing silicon nanowire on (110) type silicon wafer

Abstract

The invention relates to a method for manufacturing a silicon nanowire on a (110) type silicon wafer, and belongs to the technical field of MEMS. The method comprises the following steps: S1, providing a (110) type silicon substrate, and forming a mask layer on the silicon substrate; s2, patterning the mask layer to form a corrosion window; s3, performing anisotropic etching on the silicon substrate through the corrosion window to form a groove and a groove partition wall; s4, oxidizing the trench partition walls to form an oxide layer and a silicon nanowire; and S5, removing the oxide layer to obtain the suspended silicon nanowire. The problems that in the prior art, a silicon nanowire preparation method is complex, high in cost and poor in batch consistency are solved.

Description

TECHNICAL FIELD

[0001] The application relates to a method for manufacturing silicon nanowires on a (110) type silicon wafer and belongs to the technical field of MEMS. BACKGROUND

[0002] The silicon nanowires have significant application value in the fields of nano-electronics, biosensors and energy storage due to the excellent semiconductor characteristics of silicon materials and unique effects under nanometer scale, and controllable preparation technology of the silicon nanowires is a core bottleneck for industrialization in the related fields. 1. The “top-down” method: for example, a photolithography-etching method depends on expensive and precise equipment, has a long process, and is difficult to control the diameter of the nanowires and the roughness of the sidewall; a metal-assisted chemical etching method (MACE) has low equipment requirements, but the distribution of metal particles and the etching rate are easily disturbed, so that the size of the nanowires is uneven and the defect rate is high.

[0003] 2. The “bottom-up” method: for example, a chemical vapor deposition method (CVD) needs high temperature, high vacuum and toxic silicon source, has high process risk, and is difficult to control the growth direction of the nanowires; a thermal evaporation method depends on an ultrahigh vacuum environment, and the distribution of the diameter and length of the nanowires is wide, so that the nanowires are easily aggregated and difficult to be directly used for device integration.

[0004] In summary, the existing silicon nanowire preparation technology generally has problems of difficulty in low-cost mass production, difficulty in structure parameter control and difficulty in compatibility with a mature manufacturing system, so there is an urgent need for a silicon nanowire manufacturing method with simple process and controllable parameters to break through the limitations of the existing technology. SUMMARY

[0005] In view of the deficiencies of the prior art, the application provides a method for manufacturing silicon nanowires on a (110) type silicon wafer, which solves the problems of complex preparation method, high cost and poor batch consistency of the silicon nanowires in the prior art.

[0006] The technical scheme of the application is as follows: A method for manufacturing silicon nanowires on a (110) type silicon wafer, comprising the following steps: S1. providing a (110) type silicon substrate and forming a mask layer on the silicon substrate; S2. patterning the mask layer to form an etching window; S3. performing anisotropic etching on the silicon substrate through the etching window to form a groove and a groove wall; S4. oxidizing the groove wall to form an oxide layer and a silicon nanowire; S5. removing the oxide layer to obtain a suspended silicon nanowire.

[0007] According to a preferred embodiment of the present invention, in step S1, the silicon substrate is a P-type doped silicon wafer.

[0008] According to a preferred embodiment of the present invention, in step S1, the material of the mask layer is silicon nitride, and the thickness is 100~500nm.

[0009] According to a further preferred embodiment of the present invention, the silicon nitride is formed by LPCVD.

[0010] According to a preferred embodiment of the present invention, step S2 specifically includes the following steps: S2-1. Coat the mask layer with photoresist; S2-2. Based on the pre-made photomask, the photoresist is exposed and developed through photolithography to obtain a window pattern; S2-3. Pattern the mask layer through etching process, transfer the window pattern on the photoresist onto the mask layer, and obtain the etched window 21. S2-4, Remove photoresist.

[0011] According to a further preferred embodiment of the present invention, in steps S2-3, the etching process used is RIE, the number of etching windows is at least two, the etching window is a shape that is confined within the boundary L and passes through two opposite vertices, including but not limited to triangles, quadrilaterals, stars or irregular shapes, and the shapes of multiple etching windows are the same or different.

[0012] According to a further preferred embodiment of the present invention, the boundary L is a rhombus with interior angles of 70.53° and 109.47°, and the two opposite vertices are on the same vertical line.

[0013] According to a preferred embodiment of the present invention, in step S3, a KOH solution with a mass fraction of 25% and a temperature of 50°C is used to etch the silicon substrate.

[0014] According to a further preferred embodiment of the present invention, the upper boundary of the groove coincides with the boundary L, and the groove wall is located between two adjacent grooves.

[0015] According to a preferred embodiment of the present invention, in step S5, the oxide layer is removed by wet etching, and the etching solution used is BOE solution.

[0016] The beneficial effects of this invention are as follows: This invention utilizes anisotropic etching technology of silicon, which has the advantages of simple process, controllable parameters, and batch processing capability. It effectively overcomes the problems of complex silicon nanowire preparation methods, high cost, and poor batch consistency in existing technologies, and has high utilization value. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the method flow of the present invention; Figure 2 This is a schematic diagram of the mask layer structure of the present invention; Figure 3 This is a schematic diagram of the product in step S2 of Embodiment 1 of the present invention, wherein, Figure 3 (a) is a plan view of the product; Figure 3 (b) is Figure 3 (a) along AA' Cross-sectional view in the direction; Figure 3 (c) is a schematic diagram of the boundary L; Figure 4 This is a schematic diagram of the product in step S3 of Embodiment 1 of the present invention, wherein, Figure 4 (a) is a plan view of the product; Figure 4 (b) is Figure 4 (a) along AA' Cross-sectional view in the direction; Figure 5 This is a three-dimensional product diagram from step S3 of Embodiment 1 of the present invention, wherein... Figure 5 (a) is a schematic diagram of the three-dimensional structure of the groove; Figure 5 (b) is Figure 5 (a) Sectional view along plane bdfe. Figure 5 (c) is Figure 5 (a) Sectional view along plane acg (where g is the midpoint of line segment ef); Figure 5 (d) is a schematic diagram of the product's three-dimensional structure; Figure 6 This is a schematic diagram of the product in step S4 of Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the product in step S5 of Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the product in step S2 of Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the product in step S3 of Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the product in step S2 of Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of the product in step S3 of embodiment 3 of the present invention; Wherein: 1. Silicon substrate; 2. Mask layer; 11. Groove; 12. Inter-groove wall; 121. Oxide layer; 122. Silicon nanowires; 21. Corrosion window. Detailed Implementation

[0018] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0019] Example 1: like Figures 1-7 As shown, this embodiment provides a method for fabricating silicon nanowires on a (110) type silicon wafer, the steps of which are as follows: S1. Provide a (110) type silicon substrate 1, and form a mask layer 2 on the silicon substrate 1, such as Figure 2 As shown; The silicon substrate 1 is selected as a P-type doped silicon wafer. It should be understood that the P-type doped silicon wafer here is only an example and not a limitation. In fact, other doping types or intrinsic silicon wafers are also applicable.

[0020] In step S1, the material of the mask layer 2 is silicon nitride, which is formed by LPCVD and has a thickness of 100~500nm. It should be understood that the silicon nitride and its thickness here are merely examples and not limitations. In this embodiment, since the silicon substrate 1 is subsequently etched using anisotropic etching, the material of the mask layer 2 does not need to react with the method.

[0021] S2, a patterned mask layer, forming an etch window 21, such as Figure 3 As shown; The specific steps are as follows: S2-1. Coat photoresist on mask layer 2; S2-2. Based on the pre-made photomask, the photoresist is exposed and developed through photolithography to obtain a window pattern; S2-3. Pattern the mask layer 2 through an etching process to transfer the window pattern on the photoresist onto the mask layer 2, thus obtaining the etched window 21. The etching process used is RIE (Re-Etching), and the number of etching windows 21 is at least two. It should be understood that in subsequent operations, a silicon nanowire will be formed between every two etching windows 21. The actual number of etching windows 21 can be set as needed. An etching window is a shape confined within the boundary L (i.e., the boundary composed of vertices a, b, c, and d) and passing through two opposite vertices a and c, including but not limited to triangles, quadrilaterals, stars, or irregular shapes. Multiple etching windows may have the same or different shapes. In this embodiment, the number of etching windows 21 is two, and both are quadrilaterals.

[0022] The boundary L is a rhombus with interior angles of 70.53° and 109.47°, and the two opposite vertices a and c are on the same vertical line.

[0023] S2-4, Remove photoresist.

[0024] S3. Anisotropic etching is performed on the silicon substrate 1 through the etching window to form grooves 11 and inter-groove walls 12, such as... Figure 4 As shown; The silicon substrate was etched using a KOH solution with a mass fraction of 25% and a temperature of 50°C. It should be understood that the KOH solution, mass fraction, and temperature here are only examples and not limitations. In fact, other mass fractions, temperatures, or other anisotropic etching solutions for silicon (such as TMAH solution) are also applicable.

[0025] Specifically, the upper boundary of the groove and Figure 3 The boundary L of (a) coincides. For ease of understanding, the anisotropic etching principle of (110) type silicon wafers will be introduced. Because the atomic arrangement density of silicon differs on different crystal planes, the etching rates of KOH, TMAH, and other etching solutions on different crystal planes vary significantly. Among them, the (111) plane is the slowest, the (100) plane is moderate, and the (110) plane is the fastest. Therefore, for… Figure 3 The corrosion window in (a) will form under anisotropic corrosion. Figure 5 The groove 11 shown in (a) is specifically a heptahedron with vertices a, b, c, d, e, and f, and except for face abcd (i.e., the silicon wafer surface), the other six faces are (111) faces. Figure 3 The two corrosion windows 21 in (a) will form after anisotropic corrosion. Figure 5 In the structure shown in (d), the groove wall 12 is located between two adjacent grooves 11.

[0026] The feature size of the inter-slot wall 12 is 200~500nm.

[0027] S4. Oxidize the walls between the tanks to form an oxide layer 121 and silicon nanowires 122, such as Figure 6 As shown; A high-temperature, moist-oxygen thermal oxidation method is employed because, at the microscale, when the oxide layer grows to its maximum thickness, it hinders oxygen diffusion to the silicon-oxide interface, preventing further oxidation reactions. Therefore, the oxidation reaction "self-stops," leading to the formation of silicon nanowires within the tank walls. It should be understood that this thermal oxidation method is merely an example and not a limitation. Since the maximum thickness of the oxide layer is affected by the oxidation temperature and atmosphere, a low-temperature, dry-oxygen thermal oxidation method can be used when the feature size of the tank walls 12 is small or the feature size of the target silicon nanowires is large.

[0028] S5. The oxide layer 121 was removed by wet etching using a BOE solution to obtain suspended silicon nanowires, such as... Figure 7 As shown.

[0029] Example 2: This embodiment provides a method for fabricating silicon nanowires on a (110) type silicon wafer, with the steps described in Embodiment 1, except that: In step S2, the shape of the erosion window 21 is any shape that passes through vertices a' and c' and is confined to the parallelogram boundary L' (i.e., the boundary formed by vertices a', b', c', and d'). For example... Figure 8 As shown.

[0030] In step S3, after anisotropic etching, a product is formed. Figure 9 The structure shown.

[0031] Example 3: This embodiment provides a method for fabricating silicon nanowires on a (110) type silicon wafer, with the steps described in Embodiment 1, except that: like Figure 10 As shown, in step S2, the shape of the erosion window 21 is a figure passing through vertices a'', b'', c'', and d'', where a'' and c'' are respectively confined to line segments mm' and nn', points m and m' are the intersection points of lines b''k and d''k with the horizontal line M, and points n and n' are the intersection points of lines b''k' and d''k with the horizontal line N. In step S3, after anisotropic etching, a product is formed. Figure 11 The structure shown.

[0032] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating silicon nanowires on a (110) type silicon wafer, characterized in that, The steps are as follows: S1. Provide a (110) type silicon substrate and form a mask layer on the silicon substrate; S2, a patterned mask layer, forms an etch window; S3. Anisotropic etching is performed on the silicon substrate through the etching window to form grooves and trench walls; S4. Oxidize the walls between the tanks to form an oxide layer and silicon nanowires; S5. Remove the oxide layer to obtain suspended silicon nanowires.

2. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 1, characterized in that, In step S1, a P-type doped silicon wafer is selected as the silicon substrate.

3. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 2, characterized in that, In step S1, the mask layer is made of silicon nitride and has a thickness of 100~500nm.

4. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 3, characterized in that, The silicon nitride is formed by LPCVD.

5. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 2, characterized in that, In step S2, the specific steps are as follows: S2-1. Coat the mask layer with photoresist; S2-2. Based on the pre-made photomask, the photoresist is exposed and developed through photolithography to obtain a window pattern; S2-3. Pattern the mask layer through etching process, transfer the window pattern on the photoresist onto the mask layer, and obtain the etched window. S2-4, Remove photoresist.

6. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 5, characterized in that, In steps S2-3, the etching process used is RIE, and the number of etching windows is at least two. The etching window is a shape that is confined within the boundary L and passes through two opposite vertices, including but not limited to triangles, quadrilaterals, stars or irregular shapes. The shapes of multiple etching windows may be the same or different.

7. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 6, characterized in that, The boundary L is a rhombus with interior angles of 70.53° and 109.47°, and the two opposite vertices are on the same vertical line.

8. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 7, characterized in that, In step S3, a KOH solution with a mass fraction of 25% and a temperature of 50°C is used to etch the silicon substrate.

9. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 7, characterized in that, The groove is a heptahedron, with its upper boundary coinciding with boundary L, and the groove wall located between two adjacent grooves.

10. The method for fabricating silicon nanowires on a (110) type silicon wafer as described in claim 7, characterized in that, In step S5, the oxide layer is removed by wet etching, using BOE solution as the etching solution.

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