KGD chip automatic test device and test method

Abstract

The invention relates to the technical field of chip testing, in particular to a KGD chip automatic testing method which comprises the steps that a control unit obtains a chip configuration file and a testing task list sent by a terminal; the control unit conducts a program loading channel based on to-be-tested chip interface information in the chip configuration file, and transmits a test program to the to-be-tested chip through the program loading channel; and the control unit extracts the current test task from the test task list, determines a to-be-tested chip interface matched with the current test task from the chip configuration file, and conducts the signal acquisition channel based on the to-be-tested chip interface. The control unit conducts a corresponding channel based on a chip configuration file, completes program loading, signal acquisition and test task execution, and efficiently processes a detection result through a distributed computing architecture. According to the invention, the test process is optimized by integrating a multifunctional module, automatic test of different types of chips is realized, the test efficiency and precision are improved, and the efficient intelligent test requirements of modern industry are met.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing technology, specifically an automated testing device and method for KGD chips. Background Technology

[0002] With the continuous development of semiconductor technology, KGD (Known Good Die) chip testing is becoming increasingly important in advanced electronic packaging and integrated circuit manufacturing. While existing KGD chip testing solutions meet testing requirements to a certain extent, there is still room for improvement in terms of automation, testing efficiency, and structural design. Adapting to the demands of modern industry for efficient and intelligent testing equipment presents certain challenges.

[0003] A search revealed a test fixture for IGBT & KGD chips, with publication number CN113203943B, published on September 14, 2021. This patent achieves IGBT & KGD chip testing by incorporating components such as heating rods, temperature-sensing couplers, and insulating protective sleeves within the test chamber. However, this technical solution relies on manually tightening the cover plate to secure the chip, lacking automated clamping and testing capabilities, thus impacting testing efficiency. Furthermore, the test chamber involves multiple independent components such as adjusting washers, plastic insulating blocks, and snap-fit ​​springs, resulting in high complexity in assembly and maintenance. While the nitrogen-based gas design provides a certain level of testing environment protection, gas flow and pressure regulation still require manual intervention, and full-process automated control has not yet been achieved, which to some extent limits the improvement of production efficiency.

[0004] A search revealed an interconnect substrate with elastic conductive microbumps and a KGD socket based thereon, with publication number CN112180128B, published on August 1, 2023. This patent achieves high-precision positioning and efficient electrical interconnection by constructing a three-dimensional metal electrical interconnect structure and a coplanar design of conductive elastic microbumps. However, this technical solution primarily focuses on the physical connection performance between the chip and the socket, without addressing the automated control of the testing process. Specifically, chip loading, test signal transmission, and result analysis still require manual intervention; full-process automation is not yet implemented. Furthermore, while this socket design solves the density, accuracy, and coplanarity issues of traditional spring pin arrays, the complex microbump structure places high demands on the manufacturing process, potentially increasing production costs and impacting large-scale applications.

[0005] The aforementioned problems indicate that existing KGD chip testing devices and methods still have room for improvement in terms of automation, testing efficiency, and structural simplification. Therefore, this invention provides an automated KGD chip testing device and method, aiming to optimize the testing process and improve testing efficiency and accuracy by integrating automatic clamping, signal acquisition, and data analysis functions, thereby better meeting the needs of modern industry for efficient and intelligent KGD chip testing equipment. Summary of the Invention

[0006] Given that the existing KGD chip testing devices and methods still have room for improvement in terms of automation, testing efficiency, and structural simplification, an automated KGD chip testing device and method are proposed.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: The first aspect of this invention provides an automated testing method for KGD chips, comprising: a control unit acquiring a chip configuration file and a test task list sent by a terminal; the control unit activating a program loading channel based on the interface information of the chip under test in the chip configuration file, and transmitting a test program to the chip under test through the program loading channel; wherein the test program includes a detection module; the control unit extracting the current test task from the test task list, determining the interface of the chip under test matching the current test task from the chip configuration file, and activating a signal acquisition channel based on the interface of the chip under test; the control unit sending a current test task instruction to the chip under test, and receiving the detection result of the current test task; wherein the detection result is generated by sampling electrical signals through the signal acquisition channel during the process of the chip under test receiving the current test task instruction and running the detection module corresponding to the current test task.

[0008] In a preferred embodiment of the KGD chip automated testing device and testing method described in this invention, the testing program further includes a communication module; the control unit sends a current test task instruction to the chip under test and receives the detection result of the current test task, including: the control unit sending the current test task instruction to the chip under test; the control unit sending a synchronization trigger signal to the chip under test in response to the confirmation instruction returned by the chip under test; wherein, the confirmation instruction is a feedback signal generated by the communication module corresponding to the current test task after the chip under test receives the current test task instruction; the control unit receiving the detection result of the chip under test after running the detection module under the action of the synchronization trigger signal.

[0009] As a preferred embodiment of the KGD chip automated testing device and testing method described in this invention, the device further includes: a control unit that conducts a power supply circuit based on the power interface information of the chip under test in the chip configuration file, so that the power supply device connected to the chip under test provides the required power to the chip under test through the power supply circuit; and a control unit that conducts a clock signal circuit based on the clock interface information of the chip under test in the chip configuration file, so that the clock generator connected to the chip under test provides a reference clock signal to the chip under test through the clock signal circuit.

[0010] As a preferred embodiment of the KGD chip automated testing device and testing method described in this invention, the control unit extracts the environmental parameters required for the chip under test to execute the current testing task from the test task list; the control unit activates the environmental regulation loop based on the functional interface information of the chip under test in the chip configuration file, so that the environmental regulation device provides the chip under test with the required environmental conditions through the environmental regulation loop.

[0011] As a preferred embodiment of the KGD chip automated testing device and testing method described in this invention, in the case of replacing the chip under test, the control unit receives an updated chip configuration file sent by the terminal, and opens a new program loading channel based on the interface information of the chip under test in the updated chip configuration file, and transmits the updated test program to the replaced chip under test through the new program loading channel; wherein, the updated test program includes a detection module and an updated communication module.

[0012] As a preferred embodiment of the KGD chip automated testing device and testing method described in this invention, the chip under test is connected to the measuring instrument through a signal acquisition channel; receiving the detection results of the current testing task includes: the control unit receiving the detection results transmitted by the chip under test and the measuring instrument; the method further includes: the control unit sending the detection results to the terminal for display on the terminal.

[0013] A second aspect of the present invention provides an automated testing system for KGD chips, comprising: a data acquisition module configured to acquire a chip configuration file and a test task list sent by a terminal; a channel switching module configured to enable a program loading channel based on the interface information of the chip under test in the chip configuration file, and to transmit a test program to the chip under test through the program loading channel; wherein the test program includes a detection module; a signal acquisition module configured to enable the control unit to extract the current test task from the test task list, determine the interface of the chip under test matching the current test task from the chip configuration file, and enable a signal acquisition channel based on the interface of the chip under test; and a result receiving module configured to enable the control unit to send the current test task instruction to the chip under test and to receive the detection result of the current test task; wherein the detection result is generated by sampling electrical signals through the signal acquisition channel during the process of the chip under test receiving the current test task instruction and running the detection module corresponding to the current test task.

[0014] A third aspect of the present invention provides a computer program product, including computer-readable instructions, which, when executed on an electronic device, cause the electronic device to perform the KGD chip automated testing method described in the first aspect or any implementation thereof.

[0015] A fourth aspect of the present invention provides an electronic device, including at least one processor and a memory connected to the processor, wherein: the memory is used to store a computer program; the processor is used to execute the computer program to cause the electronic device to perform the KGD chip automated testing method described in the first aspect or any implementation thereof.

[0016] The fifth aspect of the present invention provides a computer storage medium carrying one or more computer programs, which, when executed by an electronic device, cause the electronic device to perform the KGD chip automated testing method described in the first aspect or any implementation thereof.

[0017] The beneficial effects of this invention are as follows: The control unit activates the program loading channel based on the interface information of the chip under test (DUT) in the chip configuration file, and transmits the test program to the DUT through the program loading channel; the control unit extracts the current test task from the test task list, determines the DUT interface matching the current test task from the chip configuration file, and activates the signal acquisition channel based on the DUT interface; the control unit sends the current test task instruction to the DUT and receives the detection result of the current test task. This detection result is generated after sampling the electrical signal through the signal acquisition channel during the process of the DUT receiving the current test task instruction and running the detection module corresponding to the current test task. This invention, based on the chip configuration file and test task list, can activate corresponding channels to test the DUT, thereby generating detection results. It can perform separate tests on different types of chips, improving the efficiency of automated chip testing.

[0018] In terms of automated clamping, this invention achieves rapid fixation and release of the chip under test by combining a robotic arm with a vacuum suction device. The robotic arm has an adjustable gripper at its end, with a vacuum suction cup embedded within. The vacuum level is adjusted via a pneumatic control system to ensure the chip remains stable during testing. Furthermore, the gripper's adjustment range is adaptable to chips of different sizes, avoiding frequent gripper changes due to chip size differences.

[0019] In terms of signal acquisition, this invention employs a design combining a multi-channel signal acquisition card and a high-precision analog-to-digital converter (ADC). The input terminal of the signal acquisition card is electrically connected to the functional interface of the chip under test (DUT), and the output terminal is connected to the ADC. The ADC converts the analog signal into a digital signal and transmits it to the control unit. The signal acquisition card supports simultaneous acquisition of multiple signals, and the isolation between channels is high, reducing the possibility of signal interference. Furthermore, the sampling frequency of the signal acquisition card can be dynamically adjusted according to testing requirements, meeting the requirements of different testing scenarios.

[0020] In terms of environmental regulation, this invention achieves precise control of environmental parameters such as temperature and humidity through the design of a closed-loop control system. The environmental regulation equipment includes a heater, a cooler, a humidifier, and a dehumidifier, whose operating status is adjusted by the control unit according to the environmental parameter settings in the chip configuration file. The control unit collects feedback signals from environmental sensors in real time, compares them with the set values, calculates the deviation, and adjusts the operating power of the environmental regulation equipment using a PID algorithm to ensure that the environmental parameters are always maintained within the target range.

[0021] Regarding program loading, this invention employs a dual-channel design: a program loading channel and a backup loading channel. The program loading channel is used for program transmission under normal testing scenarios, while the backup loading channel is activated when the program loading channel fails, ensuring the continuity of the testing process. Both channels are connected to the chip under test via a high-speed serial interface, achieving a transmission rate of hundreds of megabits per second, significantly reducing program loading time.

[0022] In terms of data analysis, this invention achieves efficient processing of detection results through the design of a distributed computing architecture. The control unit divides the detection results into multiple sub-tasks and distributes them to multiple computing nodes for parallel processing. Each computing node is responsible for completing a specific data analysis task, such as signal waveform analysis and spectrum analysis, and finally, the processing results are aggregated to the master node for comprehensive evaluation. The distributed computing architecture not only improves data processing efficiency but also enhances the system's scalability, enabling it to adapt to the needs of large-scale testing scenarios.

[0023] This invention optimizes the testing process of KGD chips by integrating functional modules such as automatic clamping, signal acquisition, environmental adjustment, program loading, and data analysis, significantly improving testing efficiency and accuracy, and meeting the needs of modern industry for efficient and intelligent testing equipment. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the overall structure of the automated KGD chip testing device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the automatic clamping module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the signal acquisition module in an embodiment of the present invention; Figure 4 This is a schematic diagram of the environmental control module in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the program loading module in an embodiment of the present invention; Figure 6 This is a schematic diagram of the data analysis module in an embodiment of the present invention; Figure 7 This is a logic block diagram of the testing process in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the interaction between the control unit and other modules in an embodiment of the present invention.

[0025] The attached figures are labeled as follows: 1. Automatic clamping module; 2. Signal acquisition module; 3. Environmental control module; 4. Program loading module; 5. Data analysis module; 6. Control unit; 7. Chip under test; 8. Terminal. Detailed Implementation

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0028] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0029] Secondly, the present invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0030] Example This invention provides an automated testing device and method for KGD chips, the specific implementation of which is as follows. (Combined with...) Figures 1 to 8 The accompanying drawings and related descriptions detail the specific implementation process of the present invention.

[0031] like Figure 1 As shown, the device includes an automatic clamping module 1, a signal acquisition module 2, an environmental control module 3, a program loading module 4, a data analysis module 5, and a control unit 6. These modules work together through electrical and mechanical connections to complete the automated testing of the KGD chip 7. The specific structure of each module and their interconnections will be described in detail below.

[0032] Automatic clamping module 1 Figure 2As shown, the device consists of a robotic arm, an adjustable gripper, and vacuum suction cups. The robotic arm is mounted on the base of the device, and its end has an adjustable gripper with multiple vacuum suction cups embedded inside. These suction cups are connected to a pneumatic control system via pneumatic tubing. The pneumatic control system adjusts the vacuum level according to the size and shape of the chip under test (7), ensuring that the chip is firmly attracted without being damaged by excessive suction. The adjustable gripper is designed to extend and retract freely within a certain range to accommodate chips of different sizes. When changing chips, the robotic arm removes the old chip and places the new chip in the test position via a preset path. This layout not only achieves rapid fixation and release but also avoids frequent gripper changes, improving testing efficiency.

[0033] The structure of signal acquisition module 2 is as follows: Figure 3 As shown, this module mainly includes a multi-channel signal acquisition card and a high-precision analog-to-digital converter (ADC). The input terminal of the signal acquisition card is electrically connected to the functional interface of the chip under test (DUT) 7 via wires, while the output terminal is connected to the ADC. The ADC converts the acquired analog signals into digital signals and transmits them to the control unit 6. The signal acquisition card supports simultaneous acquisition of multiple signals, and each signal is processed through an independent isolation circuit, reducing the possibility of interference between signals. Furthermore, the sampling frequency of the signal acquisition card can be dynamically adjusted according to testing requirements, achieved by sending commands through the control unit 6. For example, in high-frequency signal testing scenarios, the sampling frequency can be set to the highest value to capture subtle changes; while in low-frequency signal testing scenarios, the sampling frequency can be appropriately reduced to save resources.

[0034] Environmental control module 3, such as Figure 4 As shown, the test chamber includes heaters, coolers, humidifiers, and dehumidifiers, which are arranged around the chamber and connected to the control unit 6 via cables. The heaters and coolers regulate the temperature within the chamber, while the humidifiers and dehumidifiers control the humidity. The operating status of all devices is controlled by the control unit 6 based on environmental parameter settings in the chip configuration file. The control unit 6 collects feedback signals from environmental sensors in real time, compares them with the set values, and uses a PID algorithm to calculate the deviation and adjust the power of the devices. For example, when the test requires maintaining a constant temperature, the control unit 6 dynamically adjusts the power of the heaters and coolers based on the feedback signals from the temperature sensors, ensuring that the temperature within the test chamber remains within the target range.

[0035] Program loading module 4, such as Figure 5As shown, a dual-channel design is adopted, including a program loading channel and a backup loading channel. Both channels are connected to the chip under test (DUT) 7 via a high-speed serial interface, with a transmission rate of up to hundreds of megabits per second. The program loading channel is used for program transmission under normal testing scenarios, while the backup loading channel is activated when the main channel fails to ensure the continuity of the testing process. The control unit 6 selects the appropriate channel according to the DUT interface information in the chip configuration file and transmits the test program to the DUT 7 through that channel. The test program includes a detection module and a communication module, where the detection module is used to execute specific test tasks, and the communication module is responsible for data interaction with the control unit 6.

[0036] Data Analysis Module 5, such as Figure 6 As shown, a distributed computing architecture is adopted, including a master node and multiple computing nodes. The control unit 6 divides the detection results into multiple sub-tasks and distributes them to various computing nodes for parallel processing. Each computing node is responsible for completing a specific data analysis task, such as signal waveform analysis or spectrum analysis, and finally summarizes the processing results to the master node for comprehensive evaluation. The master node is connected to the computing nodes through a network, using an efficient communication protocol to ensure the real-time performance and accuracy of data transmission. This distributed computing architecture not only improves data processing efficiency but also enhances the system's scalability, enabling it to adapt to the needs of large-scale testing scenarios.

[0037] like Figure 7 As shown, the entire testing process begins with terminal 8 sending the chip configuration file and test task list. Control unit 6 first acquires these files and transmits the test program to the chip under test (DUT) 7 via program loading module 4. Subsequently, control unit 6 extracts the current test task from the test task list and activates the signal acquisition channel according to the interface information in the chip configuration file. During this process, control unit 6 sends the current test task instruction to DUT 7 and receives the test results. The test results are generated after the electrical signals are sampled by signal acquisition module 2 during the operation of the test module on DUT 7. If the chip needs to be replaced during the test, control unit 6 receives the updated chip configuration file sent by terminal 8 and reactivates the program loading channel to transmit the new test program.

[0038] like Figure 8 As shown, control unit 6 plays a core coordinating role throughout the testing process. It maintains real-time communication with other modules via electrical connections and dynamically adjusts the operating status of each module according to testing requirements. For example, when a testing task requires specific environmental conditions, control unit 6 extracts relevant parameters from the chip configuration file and achieves precise control through environmental adjustment module 3. Similarly, when signal acquisition module 2 needs to adjust its sampling frequency, control unit 6 promptly sends instructions to meet the testing requirements.

[0039] In this manner, the present invention optimizes the testing process of KGD chips by integrating functional modules such as automatic clamping, signal acquisition, environmental adjustment, program loading, and data analysis. The modules work together to complete testing tasks through clear connections and collaborative mechanisms, significantly improving testing efficiency and accuracy.

[0040] To enable those skilled in the art to fully understand and implement this invention, the specific implementation principles of this invention are further supplemented below with a specific application scenario.

[0041] During the actual testing process, the chip configuration file and test task list are first sent to the control unit 6 via terminal 8. After receiving these files, the control unit 6 activates the program loading channel of the program loading module 4 according to the interface information of the chip under test in the chip configuration file, and transmits the test program to the chip under test 7. The test program includes a detection module and a communication module, whereby the detection module is used to execute specific test tasks, and the communication module is responsible for data interaction with the control unit 6.

[0042] Subsequently, the control unit 6 retrieves the current test task from the test task list and activates the signal acquisition channel of the signal acquisition module 2 based on the interface information in the chip configuration file. At this time, the control unit 6 sends the current test task command to the chip under test (DUT) 7, which then runs the detection module upon receiving the command. During this process, the signal acquisition module 2 samples the electrical signal through a multi-channel signal acquisition card and transmits the analog signal to a high-precision analog-to-digital converter (ADC). The ADC converts the analog signal into a digital signal and then transmits it to the control unit 6 to generate the detection result.

[0043] When specific conditions are required in the testing environment, the control unit 6 extracts environmental parameters from the chip configuration file and achieves precise control through the environmental adjustment module 3. For example... Figure 4 As shown, heaters, coolers, humidifiers, and dehumidifiers are arranged around the test chamber and connected to control unit 6 via cables. Control unit 6 collects feedback signals from environmental sensors in real time, compares them with set values, and uses a PID algorithm to calculate the deviation and adjust the operating power of the equipment. For example, when the test requires maintaining a constant temperature, control unit 6 dynamically adjusts the power of the heater and cooler based on the feedback signal from the temperature sensor to ensure that the temperature inside the test chamber remains within the target range.

[0044] In the design of program loading module 4, the dual-channel structure ensures the continuity of the testing process. For example... Figure 5As shown, both the program loading channel and the backup loading channel are connected to the chip under test (DUT) 7 via a high-speed serial interface, with a transmission rate of up to several hundred megabits per second. When the main channel fails, the backup loading channel is immediately activated to prevent test failure due to program loading interruption. The control unit 6 selects the appropriate channel based on the interface information in the chip configuration file and transmits the test program to the DUT 7 through that channel.

[0045] In data analysis module 5, the distributed computing architecture significantly improves data processing efficiency. For example... Figure 6 As shown, the control unit 6 divides the detection results into multiple sub-tasks and distributes them to multiple computing nodes for parallel processing. Each computing node is responsible for completing a specific data analysis task, such as signal waveform analysis or spectrum analysis, and finally summarizes the processing results to the master node for comprehensive evaluation. The master node is connected to the computing nodes through a network, using an efficient communication protocol to ensure the real-time performance and accuracy of data transmission. This architecture not only improves data processing speed but also enhances the system's scalability, enabling it to adapt to the needs of large-scale testing scenarios.

[0046] The automatic clamping module 1 played a crucial role throughout the entire testing process. For example... Figure 2 As shown, the robotic arm has an adjustable gripper at its end, with multiple vacuum suction cups embedded inside. These suction cups are connected to a pneumatic control system via pneumatic tubing. The pneumatic control system adjusts the vacuum level according to the size and shape of the chip under test 7, ensuring that the chip is firmly adsorbed without being damaged by excessive suction. When a chip needs to be replaced, the robotic arm removes the old chip and places the new chip in the test position via a preset path, thus achieving rapid fixation and release and avoiding frequent gripper changes.

[0047] In the above manner, this invention completes the automated testing task of KGD chips through the collaborative work of various modules. The automatic clamping module 1 ensures rapid fixation and adaptation of the chip under test 7; the signal acquisition module 2 achieves efficient and accurate signal acquisition and processing; the environmental adjustment module 3 provides a stable testing environment; the program loading module 4 ensures continuous loading of the test program; and the data analysis module 5 improves data processing efficiency through a distributed computing architecture. The modules work together to complete the testing task through clear connections and collaborative mechanisms, significantly improving testing efficiency and accuracy.

[0048] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape, and proportions of various elements, as well as parameter values ​​(e.g., temperature, pressure, etc.), mounting arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of the invention. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and not only structurally equivalent but also equivalent in structure. Other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0049] Furthermore, in order to provide a concise description of exemplary embodiments, not all features of actual embodiments (i.e., those features that are not relevant to the currently considered best mode for carrying out the invention, or those features that are not relevant to implementing the invention) may be omitted.

[0050] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An automated testing method for KGD chips, characterized in that, include: The control unit (6) acquires the chip configuration file and test task list sent by the terminal (8); The control unit (6) connects the program loading channel based on the interface information of the chip under test in the chip configuration file, and transmits the test program to the chip under test (7) through the program loading channel; wherein, the test program includes a detection module; The control unit (6) extracts the current test task from the test task list, determines the chip interface under test that matches the current test task from the chip configuration file, and turns on the signal acquisition channel based on the chip interface under test. The control unit (6) sends a current test task instruction to the chip under test (7) and receives the detection result of the current test task; wherein, the detection result is generated by sampling the electrical signal through the signal acquisition channel during the process when the chip under test (7) receives the current test task instruction and runs the detection module corresponding to the current test task.

2. The automated testing method for KGD chips according to claim 1, characterized in that, The test program also includes a communication module; The control unit (6) sends a current test task instruction to the chip under test (7) and receives the detection result of the current test task, including: The control unit (6) sends the current test task instruction to the chip under test (7); The control unit (6) responds to the confirmation instruction returned by the chip under test (7) and sends a synchronization trigger signal to the chip under test (7); wherein, the confirmation instruction is a feedback signal generated by the communication module corresponding to the current test task after the chip under test (7) receives the current test task instruction; The control unit (6) receives the detection results of the chip under test (7) after the detection module is run under the action of the synchronous trigger signal.

3. The automated testing method for KGD chips according to claim 1, characterized in that, Also includes: The control unit (6) turns on the power supply circuit based on the power interface information of the chip under test in the chip configuration file, so that the power supply device connected to the chip under test (7) can provide the required power to the chip under test (7) through the power supply circuit; The control unit (6) turns on the clock signal loop based on the clock interface information of the chip under test in the chip configuration file, so that the clock generator connected to the chip under test (7) provides a reference clock signal to the chip under test (7) through the clock signal loop.

4. The automated testing method for KGD chips according to claim 1, characterized in that, Also includes: The control unit (6) extracts the environmental parameters required for the chip under test to perform the current test task from the test task list; The control unit (6) activates the environmental regulation loop based on the functional interface information of the chip under test in the chip configuration file, so that the environmental regulation device provides the required environmental conditions to the chip under test (7) through the environmental regulation loop.

5. The automated testing method for KGD chips according to any one of claims 1 to 4, characterized in that, Also includes: When the chip under test (7) is replaced, the control unit (6) receives the updated chip configuration file sent by the terminal (8), opens a new program loading channel based on the interface information of the chip under test in the updated chip configuration file, and transmits the updated test program to the replaced chip under test (7) through the new program loading channel; wherein, the updated test program includes a detection module and an updated communication module.

6. The automated testing method for KGD chips according to any one of claims 1 to 4, characterized in that, The chip under test (7) is connected to the measuring instrument through a signal acquisition channel; Receiving the detection result of the current test task includes: The control unit (6) receives the test results transmitted by the chip under test (7) and the measuring instrument; The method further includes: The control unit (6) sends the detection results to the terminal (8) for display on the terminal.

7. An automated testing system for KGD chips, characterized in that, include: The data acquisition module is configured to allow the control unit (6) to acquire the chip configuration file and test task list sent by the terminal (8); The channel switching module is configured such that the control unit (6) connects the program loading channel based on the interface information of the chip under test in the chip configuration file, and transmits the test program to the chip under test (7) through the program loading channel; wherein the test program includes a detection module; The signal acquisition module is configured such that the control unit (6) extracts the current test task from the test task list, determines the chip interface under test that matches the current test task from the chip configuration file, and turns on the signal acquisition channel based on the chip interface under test; The result receiving module is configured such that the control unit (6) sends a current test task instruction to the chip under test (7) and receives the detection result of the current test task; wherein the detection result is generated by sampling the electrical signal through the signal acquisition channel during the process when the chip under test (7) receives the current test task instruction and runs the detection module corresponding to the current test task.

8. A computer program product, characterized in that, It includes computer-readable instructions that, when executed on an electronic device, cause the electronic device to perform the KGD chip automated testing method as described in any one of claims 1 to 6.

9. An electronic device, characterized in that, It includes at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program to enable the electronic device to implement the KGD chip automated testing method as described in any one of claims 1 to 6.

10. A computer storage medium, characterized in that, The storage medium carries one or more computer programs, which, when executed by an electronic device, enable the electronic device to implement the KGD chip automated testing method as described in any one of claims 1 to 6.

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